Semiconductor device and manufacturing method, power module, power conversion circuit, and vehicle

Abstract

Embodiments of the present application disclose a semiconductor device and a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a silicon carbide semiconductor body comprising a first device region and a second device region; the second device region comprises a first conductive type device region and a second conductive type device region; the silicon carbide semiconductor body comprises an electrode setting surface; at the same preset temperature, the mobility of the semiconductor graphene layer is greater than the mobility of the silicon carbide; the first semiconductor graphene layer is located on the electrode setting surface of the first device region, the second semiconductor graphene layer is located on the electrode setting surface of the first conductive type device region, and the third semiconductor graphene layer is located on the electrode setting surface of the second conductive type device region. The technical scheme provided by the present application improves the electrical performance of the monolithic integrated silicon carbide metal-oxide semiconductor field effect transistor and the silicon carbide complementary metal oxide semiconductor semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] Silicon carbide (SiC) is renowned for its wide bandgap, high thermal conductivity, and high electric field breakdown strength, offering superior performance compared to silicon in applications across a wide temperature range, high power, and high switching frequency. The development of SiC integrated circuits that integrate control systems and power devices onto a single chip is crucial to fully realizing the potential of SiC in applications where system efficiency and power density are critical.

[0003] One of the main challenges of lateral complementary metal-oxide-semiconductor (CMOS) integration is the low channel mobility of NMOS and PMOS devices, as well as the mobility difference between p-type and n-type carriers. These technical issues severely hinder the enormous potential of SiC in improving system power efficiency and switching performance. Furthermore, the different operating voltages of silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) and silicon carbide complementary metal-oxide-semiconductor (SiC CMOS) result in poor electrical performance after monolithic integration. Summary of the Invention

[0004] This invention provides a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle to improve the electrical performance of monolithically integrated silicon carbide metal-oxide-semiconductor field-effect transistors and silicon carbide complementary metal-oxide-semiconductor semiconductor devices.

[0005] According to one aspect of the present invention, a semiconductor device is provided, comprising: a silicon carbide semiconductor body, the silicon carbide semiconductor body including a first device region and a second device region spaced apart along a first direction, the first direction being perpendicular to the thickness direction of the silicon carbide semiconductor body; the second device region including a first conductivity type device region and a second conductivity type device region spaced apart along the first direction; the silicon carbide semiconductor body including an electrode mounting surface;

[0006] A semiconductor graphene layer, comprising a first semiconductor graphene layer, a second semiconductor graphene layer, and a third semiconductor graphene layer, is used to improve the mobility of the semiconductor device; at the same preset temperature, the mobility of the semiconductor graphene layer is greater than that of silicon carbide; the first semiconductor graphene layer is located on the electrode mounting surface of the first device region, the second semiconductor graphene layer is located on the electrode mounting surface of the first conductivity type device region, and the third semiconductor graphene layer is located on the electrode mounting surface of the second conductivity type device region;

[0007] In the semiconductor device, the portion located in the first device region is a silicon carbide metal-oxide-semiconductor field-effect transistor with the current conduction direction in the first direction, and the portion located in the second device region is a silicon carbide complementary metal-oxide-semiconductor. The silicon carbide complementary metal-oxide-semiconductor includes a first conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor located in the first conductivity type device region with the current conduction direction in the first direction and a second conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor located in the second conductivity type device region with the current conduction direction in the first direction. The silicon carbide metal-oxide-semiconductor field-effect transistor and the silicon carbide complementary metal-oxide-semiconductor have different operating voltages.

[0008] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising:

[0009] A silicon carbide semiconductor body is provided, the silicon carbide semiconductor body including a first device region and a second device region spaced apart along a first direction, the first direction being perpendicular to the thickness direction of the silicon carbide semiconductor body; the second device region includes a first conductivity type device region and a second conductivity type device region spaced apart along the first direction; the silicon carbide semiconductor body includes an electrode mounting surface;

[0010] A first semiconductor graphene layer, a second semiconductor graphene layer, and a third semiconductor graphene layer are formed on the electrode mounting surface of a semiconductor graphene layer to improve the mobility of the semiconductor device. At the same preset temperature, the mobility of the semiconductor graphene layer is greater than that of silicon carbide. The first semiconductor graphene layer is located on the electrode mounting surface of the first device region, the second semiconductor graphene layer is located on the electrode mounting surface of the first conductivity type device region, and the third semiconductor graphene layer is located on the electrode mounting surface of the second conductivity type device region.

[0011] In the semiconductor device, the portion located in the first device region is a silicon carbide metal-oxide-semiconductor field-effect transistor with the current conduction direction in the first direction, and the portion located in the second device region is a silicon carbide complementary metal-oxide-semiconductor. The silicon carbide complementary metal-oxide-semiconductor includes a first conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor located in the first conductivity type device region with the current conduction direction in the first direction and a second conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor located in the second conductivity type device region with the current conduction direction in the first direction. The silicon carbide metal-oxide-semiconductor field-effect transistor and the silicon carbide complementary metal-oxide-semiconductor have different operating voltages.

[0012] According to another aspect of the present invention, a power module is provided, including a substrate and a semiconductor device as described in any embodiment of the present invention, wherein the substrate is used to support the semiconductor device.

[0013] According to another aspect of the present invention, a power conversion circuit is provided, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0014] The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the present invention, wherein the semiconductor device is electrically connected to the circuit board.

[0015] According to another aspect of the present invention, a vehicle is provided, including a load and a power conversion circuit as described in any embodiment of the present invention, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0016] The semiconductor devices, manufacturing methods, power modules, power conversion circuits, and vehicles provided in this invention integrate a semiconductor graphene layer into SiC complementary metal-oxide-semiconductor (CMOS) devices and power SiC MOSFET devices with the conduction current direction in the first direction. This is to improve the mobility of the semiconductor devices and aims to create high-performance monolithically manufactured power integrated circuits (ICs) that minimize physical footprint, making them ideal for advanced electronic applications requiring high performance and reliability. Since the conduction current direction of the SiC MOSFET, the first conductivity type SiC MOSFET, and the second conductivity type SiC MOSFET is also in the first direction, and the semiconductor graphene layer is located on the electrode surface of their respective device regions, the conduction current flows from the source to the drain through the semiconductor graphene layer under the control of their respective gates. Because the graphene layer has high strength, high thermal conductivity, and a higher mobility than silicon carbide, and possesses semiconductor properties, it ensures the same hole and electron mobility, effectively solving the problem of uniformity in channel mobility of n-MOS and p-MOS transistors. This improves the uniformity of switching speed between p-channel and n-channel, as well as overall efficiency and thermal management efficiency, thereby significantly improving the carrier mobility and channel mobility of SiC MOSFETs, and the carrier mobility and channel mobility of first-conductivity type SiC MOSFETs and second-conductivity type SiC MOSFETs in CMOS planar devices. It also reduces the difference in mobility between carriers of different conductivity types under their respective operating voltages in different planar devices, thereby improving the electrical performance of monolithically integrated silicon carbide metal-oxide-semiconductor field-effect transistors and silicon carbide complementary metal-oxide-semiconductor semiconductor devices.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0022] Figure 4 This is a flowchart of a semiconductor device manufacturing method provided in an embodiment of the present invention;

[0023] Figure 5 yes Figure 4 A structural diagram of the relevant steps in the process;

[0024] Figure 6 yes Figure 4 A schematic diagram of the process included in S110;

[0025] Figures 7-9 yes Figure 6 A structural diagram of each relevant step in the process;

[0026] Figure 10 This is a schematic flowchart of another semiconductor device manufacturing method provided in an embodiment of the present invention;

[0027] Figure 11 yes Figure 10 A flowchart of the process included in S1201;

[0028] Figure 12 yes Figure 11 A structural diagram of each relevant step in the process. Detailed Implementation

[0029] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] To improve the electrical performance of monolithically integrated silicon carbide metal-oxide-semiconductor field-effect transistors and silicon carbide complementary metal-oxide-semiconductor semiconductor devices, embodiments of the present invention provide the following technical solutions:

[0032] like Figure 1 As shown, Figure 1This is a schematic diagram of a semiconductor device provided in an embodiment of the present invention. The semiconductor device includes: a silicon carbide semiconductor body 100, the silicon carbide semiconductor body 100 including a first device region 001 and a second device region 002 spaced apart along a first direction, the first direction being perpendicular to the thickness direction of the silicon carbide semiconductor body 100; the second device region 002 including a first conductivity type device region 021 and a second conductivity type device region 022 spaced apart along the first direction; the silicon carbide semiconductor body 100 including an electrode mounting surface 101; and a semiconductor graphene layer 200, including a first semiconductor graphene layer 201, a second semiconductor graphene layer 202, and a third... A third semiconductor graphene layer 203 is used to improve the mobility of a semiconductor device. At the same preset temperature, the mobility of the semiconductor graphene layer 200 is greater than that of silicon carbide. A first semiconductor graphene layer 201 is located on the electrode surface 101 of the first device region 001, a second semiconductor graphene layer 202 is located on the electrode surface 101 of the first conductivity type device region 021, and a third semiconductor graphene layer 203 is located on the electrode surface 101 of the second conductivity type device region 022. In the semiconductor device, the portion located in the first device region 001 is a silicon carbide metal-oxide-semiconductor field-effect transistor (SiC) with the current conduction direction in the first direction. The portion located in the second device region 002 is a silicon carbide complementary metal-oxide semiconductor (SiC CMOS). The silicon carbide complementary metal-oxide semiconductor (SiC CMOS) includes a first conductivity type silicon carbide metal-oxide semiconductor field-effect transistor (first conductivity type SiC MOSFET) located in the first conductivity type device region 021 with the conduction current direction in the first direction and a second conductivity type silicon carbide metal-oxide semiconductor field-effect transistor (second conductivity type SiC MOSFET) located in the second conductivity type device region 022 with the conduction current direction in the first direction. The silicon carbide metal-oxide semiconductor field-effect transistor (SiC MOSFET) and the silicon carbide complementary metal-oxide semiconductor (SiC CMOS) have different operating voltages.

[0033] The thickness direction of the silicon carbide semiconductor body 100 is as follows: Figure 1 The Y direction, the first direction and Figure 1 The X-direction is set to be parallel.

[0034] In this embodiment of the invention, the silicon carbide semiconductor body 100 may include a substrate and an epitaxial layer, or it may only include an epitaxial layer. The epitaxial layer is a semiconductor layer formed by a single epitaxial process, including chemical vapor deposition (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0035] It should be noted that the mobility of the same semiconductor material varies with temperature. In this embodiment of the invention, the mobility of the semiconductor graphene layer 200 is greater than that of silicon carbide at the same preset temperature. That is, at the same preset temperature, the resistance to carrier movement in the semiconductor graphene layer 200 is less than that in silicon carbide, and the semiconductor graphene layer 200 is located on the electrode surface 101 of its respective device region. In the first device region 001, in a silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) with the current direction in the first direction, the current flows from the source to the drain through the first semiconductor graphene layer 201 under the control of the gate. In the second device region 002, in a silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) with the current direction in the first direction, the current flows from the source to the drain through the second semiconductor graphene layer 202 under the control of the gate. In the second device region 002, within the second conductivity type silicon carbide metal-oxide semiconductor field-effect transistor (second conductivity type SiC MOSFET) with the conduction current direction in the first direction, under the control of the gate, the conduction current flows from the source to the drain through the third semiconductor graphene layer 203. The provision of the semiconductor graphene layer 200 significantly increases the channel carrier mobility within the semiconductor device, thereby reducing the on-resistance of the semiconductor device.

[0036] The semiconductor device provided in this embodiment integrates a semiconductor graphene layer 200 into a SiC complementary metal-oxide-semiconductor (CMOS) device and a power SiC MOSFET device with the conduction current direction in the first direction. This is to improve the mobility of the semiconductor device and aims to create a high-performance monolithically manufactured power integrated circuit (IC) that minimizes physical footprint, making it ideal for advanced electronic applications requiring high performance and reliability. Since the conduction current direction of the SiC MOSFET, the first conductivity type SiC MOSFET, and the second conductivity type SiC MOSFET is in the first direction, and the semiconductor graphene layer 200 is located on the electrode surface 101 of their respective device regions, the conduction current flows from the source to the drain through the semiconductor graphene layer 200 under the control of their respective gates. Because the graphene layer 200 has high strength, high thermal conductivity, and a mobility greater than that of silicon carbide, and possesses semiconductor properties, it ensures the same hole and electron mobility, effectively solving the problem of uniformity of channel mobility in n-MOS and p-MOS transistors. This improves the uniformity of switching speed between p-channel and n-channel, overall efficiency, and thermal management efficiency, thereby significantly improving the carrier mobility and channel mobility of SiC MOSFETs, as well as the carrier mobility and channel mobility of first-conductivity type SiC MOSFETs and second-conductivity type SiC MOSFETs in CMOS planar devices. It also reduces the difference in mobility between carriers of different conductivity types in different planar devices under their respective operating voltages, thereby improving the electrical performance of monolithically integrated silicon carbide metal-oxide-semiconductor field-effect transistors and silicon carbide complementary metal-oxide-semiconductor semiconductor devices.

[0037] It should be noted that the mobility of the semiconductor graphene layer 200 depends on the growth quality of the material, and can range from tens of cm² / Vs to approximately 5000 cm² / Vs. Preferably, the mobility of the semiconductor graphene layer 200 at room temperature is greater than or equal to 1000 cm² / Vs, and can even reach approximately 5500 cm² / Vs. Room temperature, also known as ambient temperature or general temperature, is generally defined as 25 degrees Celsius, and sometimes as 300K (approximately 27 degrees Celsius). The required mobility for semiconductor devices is only around tens of cm² / Vs. Therefore, the semiconductor graphene layer 200 can significantly improve the mobility of semiconductor devices.

[0038] Optional, such as Figure 1 As shown, the band gap of the semiconductor graphene layer 200 is greater than or equal to 0.4 eV. Preferably, as... Figure 1 As shown, the band gap of the semiconductor graphene layer 200 is greater than or equal to 0.6 eV.

[0039] Specifically, due to the high strength, high thermal conductivity, and greater mobility than silicon carbide of the semiconductor graphene layer 200, and its semiconductor properties, its band gap is greater than or equal to 0.4 eV, preferably greater than or equal to 0.6 eV, and its mobility is preferably greater than or equal to 1000 cm² / Vs, or even up to about 5500 cm² / Vs. This ensures the same hole and electron mobility within the conduction channel, effectively solving the problem of uniformity of channel mobility between the first conductivity type SiC MOSFET and the second conductivity type SiC MOSFET, improving the uniformity of switching speed between the first conductivity type channel and the second conductivity type channel, as well as the overall efficiency and thermal management efficiency, resulting in a faster response speed for the semiconductor device.

[0040] Optionally, based on the above technical solution, the silicon carbide semiconductor body 100 includes a first region 103, a first well region 104, a second region 105, a second well region 106, a third region 107, and a third well region 108 on the side near the electrode surface 101; the first region 103 and the first well region 104 are located in the first device region 001 and have opposite conductivity types, the second region 105 and the second well region 106 are located in the first conductivity type device region 021 and have opposite conductivity types, and the third region 107 and the third well region 108 are located in the second conductivity type device region 022 and have opposite conductivity types; the first semiconductor graphene layer 201 is connected to the two first regions 103; the second semiconductor graphene layer 202 is located and connected to the two second regions 105; and the third semiconductor graphene layer 203 is connected to the two third regions 107.

[0041] Specifically, the above technical solution clearly specifies the exact location of the semiconductor graphene layer 200 in the SiC MOSFET with the conduction current direction in the first direction, the SiC MOSFET of the first conductivity type with the conduction current direction in the first direction in the CMOS planar device, and the SiC MOSFET of the second conductivity type with the conduction current direction in the first direction.

[0042] In the first device region 001, within a silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) with the current conduction direction in the first direction, the current flows from the source to the drain through the first region 103, the first semiconductor graphene layer 201, and the first region 103 under the control of the gate. In the second device region 002, within a first conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor (first conductivity type SiC MOSFET) with the current conduction direction in the first direction, the current flows from the source to the drain through the second region 105, the second semiconductor graphene layer 202, and the second region 105 under the control of the gate. In the second device region 002, within a second conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor (second conductivity type SiC MOSFET) with the current conduction direction in the first direction, the current flows from the source to the drain through the third region 107, the third semiconductor graphene layer 203, and the third region 107 under the control of the gate.

[0043] Optionally, based on the above technical solution, the semiconductor graphene layer 200 and the silicon carbide semiconductor body 100 are connected in an orderly manner by covalent bonds.

[0044] Specifically, a semiconductor graphene layer 200 is grown on a wafer-level SiC semiconductor substrate. The semiconductor graphene layer 200 is covalently bonded to the silicon carbide semiconductor substrate 100. The semiconductor graphene layer 200 has high strength, high thermal conductivity, and semiconductor properties, with a band gap greater than or equal to 0.6 eV. As a channel under the isolation gate, it can improve the channel mobility to, for example, about 5500 cm² / Vs. The semiconductor graphene layer 200 has improved channel mobility. The superior charge mobility and thermal properties of the semiconductor graphene layer 200 are used to enhance the channel mobility and overall efficiency of SiC MOSFETs and SiC CMOS at different operating voltages.

[0045] The semiconductor graphene layer 200 is essentially a single layer of carbon atoms within the silicon carbide semiconductor body 100, with a thickness equivalent to that of a single layer of carbon atoms in the silicon carbide semiconductor body 100. The thickness of the semiconductor graphene layer 200 is greater than or equal to 0.2 nm and less than or equal to 0.3 nm, with an average thickness of approximately 0.25 nm. The bonding between the semiconductor graphene layer 200 and the silicon carbide semiconductor body 100 is ordered and periodically arranged, ensuring that the semiconductor graphene layer 200 is a two-dimensional semiconductor material.

[0046] Optionally, based on the above technical solution, the operating voltage of the silicon carbide metal-oxide-semiconductor field-effect transistor (SiCMOSFET) is greater than the operating voltage of the silicon carbide complementary metal-oxide-semiconductor (SiCCMOS); a first isolation region 003 is provided between the silicon carbide semiconductor body 100 between the first device region 001 and the second device region 002. A second isolation region 004 is provided between the first conductivity type device region 021 and the second conductivity type device region 022.

[0047] Optionally, when the drift layer of the silicon carbide semiconductor body 100 near the electrode surface 101 is of a first conductivity type, the first isolation region 003 and the second isolation region 004 are located in the drift layer of the silicon carbide semiconductor body 100 near the electrode surface 101, and the first isolation region 003 and the second isolation region 004 are of a second conductivity type. The first isolation region 003 is used to isolate low-voltage circuits from high-voltage circuits, highlighting the architecture's suitability for various power applications. The second isolation region 004 is used to isolate p-channel and n-channel MOS devices, facilitating the use of the properties of the semiconductor graphene layer 200 to ensure the same hole and electron mobility, effectively solving the uniformity problem of channel mobility in n-MOS and p-MOS transistors, improving the uniformity of switching speeds between p-channel and n-channel, overall efficiency, and thermal management efficiency. For example, Figure 1 In the silicon carbide semiconductor body 100, a first drift layer 10, a second drift layer 20, and a third drift layer 30 are sequentially stacked. The surface of the third drift layer 30 away from the second drift layer 20 is an electrode surface 101. The first drift layer 10 is configured with a first conductivity type, the second drift layer 20 with a second conductivity type, and the third drift layer 30 with a first conductivity type. A first isolation region 003 and a second isolation region 004 are located in the third drift layer 30. The conductivity types of the first isolation region 003 and the second isolation region 004 are opposite to the conductivity type of the third drift layer 30.

[0048] Optionally, based on the above technical solutions, such as Figure 1As shown, the semiconductor device further includes: a first insulating layer 109 located on the electrode mounting surface 101; a first electrode G1 located on the side of the first insulating layer 109 away from the silicon carbide semiconductor body 100 and located in the first device region 001; a second electrode G2 located on the side of the first insulating layer 109 away from the silicon carbide semiconductor body 100 and located in the first conductivity type device region 021; and a third electrode G3 located on the side of the first insulating layer 109 away from the silicon carbide semiconductor body 100 and located in the second conductivity type device region 022. A fourth electrode S1 and a fifth electrode D1 are located in the first device region 001 and are respectively connected to two first regions 103; a sixth electrode S2 and a seventh electrode D2 are located in the first conductivity type device region 021 and are respectively connected to two second regions 105; and an eighth electrode S3 and a ninth electrode D3 are located in the second conductivity type device region 022 and are respectively connected to two third regions 107.

[0049] Specifically, the first insulating layer 109 is used to insulate the silicon carbide semiconductor body 100 and the first electrode G1, the second electrode G2, and the third electrode G3. For example, the first electrode G1, the second electrode G2, and the third electrode G3 are polysilicon gates. The second insulating layer 110 is used to insulate the gate and the source, as well as the gate and the drain. For example, in the fourth electrode S1 and the fifth electrode D1, the fourth electrode S1 is the source and the fifth electrode D1 is the drain; in the sixth electrode S2 and the seventh electrode D2, the sixth electrode S2 is the source and the seventh electrode D2 is the drain; in the eighth electrode S3 and the ninth electrode D3, the eighth electrode S3 is the source and the ninth electrode D3 is the drain.

[0050] The fourth electrode S1, fifth electrode D1, sixth electrode S2, seventh electrode D2, and eighth electrode S3 and ninth electrode D3 are patterned through a third metal layer M3 and connected to the silicon carbide semiconductor body 100 through a second metal layer M2, a first metal layer M1, and a conductive hole located inside the second insulating layer 110. Optionally, an ohmic contact layer 111 is also provided in the semiconductor device to achieve better ohmic contact between the source and the silicon carbide semiconductor body 100.

[0051] Optionally, based on the above technical solutions, such as Figure 1 As shown, the first region 103 is located on the electrode setting surface 101, and the first well region 104 is located between the two first regions 103; the second region 105 is located on the electrode setting surface 101, and the second well region 106 is located between the two second regions 105; the third region 107 is located on the electrode setting surface 101, and the third well region 108 is located between the two third regions 107.

[0052] Optionally, based on the above technical solution, the number of first device regions 001 includes multiple regions; the number of second device regions 002 includes multiple regions; the first device regions 001 and second device regions 002 are arranged alternately along the first direction; or, along the first direction, at least two first device regions 001 are arranged continuously; at least two second device regions 002 are arranged continuously.

[0053] Specifically, the above technical solution provides an arrangement of multiple first device regions 001 and multiple second device regions 002 in the first direction.

[0054] Optionally, based on the above technical solution, the second device region 002 includes S first conductivity type device regions 021 and Q second conductivity type device regions 022, where S includes an integer greater than or equal to 1 and Q includes an integer greater than or equal to 1; the first conductivity type device regions 021 and the second conductivity type device regions 022 are arranged alternately along the first direction; or, S includes an integer greater than or equal to 2, and at least two first conductivity type device regions 021 are arranged continuously along the first direction; Q includes an integer greater than or equal to 2, and at least two second conductivity type device regions 022 are arranged continuously along the first direction.

[0055] Specifically, the above technical solution provides the arrangement of S first conductivity type device regions 021 and Q second conductivity type device regions 022 in the first direction in the second device region 002.

[0056] Optionally, based on the above technical solutions, such as Figure 2 As shown, Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. The semiconductor graphene layer 200 further includes a fourth semiconductor graphene layer 204; the silicon carbide semiconductor body 100 includes a first silicon carbide semiconductor body 1A and a second silicon carbide semiconductor body 1B; the first silicon carbide semiconductor body 1A is used to support the second silicon carbide semiconductor body 1B; the fourth semiconductor graphene layer 204 is located between the first silicon carbide semiconductor body 1A and the second silicon carbide semiconductor body 1B, and the fourth semiconductor graphene layer 204 and the first silicon carbide semiconductor body 1A are connected in an orderly manner by covalent bonds.

[0057] Specifically, the fourth semiconductor graphene layer 204 is located between the first silicon carbide semiconductor body 1A and the second silicon carbide semiconductor body 1B. The fourth semiconductor graphene layer 204 and the first silicon carbide semiconductor body 1A are orderly connected by covalent bonds, and its mobility is greater than that of silicon carbide. Furthermore, the semiconductor graphene layer 204 is located in the conduction channel below the gate structure, which significantly increases the channel carrier mobility within the semiconductor device, and can increase the channel mobility to, for example, 5500 cm⁻¹. 2 V-1 s -1 The semiconductor graphene layer 200 exhibits improved channel mobility. Utilizing the superior charge mobility and thermal properties of the semiconductor graphene layer 200, the channel mobility and overall efficiency of SiC MOSFETs and SiC CMOS at different operating voltages are enhanced. Furthermore, the properties of the semiconductor graphene layer 200 ensure uniform hole and electron mobility, effectively addressing the uniformity issue of channel mobility in n-MOS and p-MOS transistors, and improving the uniformity of switching speeds between p-channels and n-channels, as well as overall efficiency and thermal management efficiency.

[0058] Optionally, based on the above technical solutions, such as Figure 1 As shown, at the same preset temperature, the mobility of the semiconductor graphene layer 200 is greater than that of silicon. For example, under the same selected room temperature conditions, the room temperature mobility of the semiconductor graphene layer 200 is greater than that of silicon, with a maximum mobility reaching 5500 cm⁻¹. 2 V -1 s -1 The graphene layer 200 exhibits a mobility approximately 10 times that of silicon at room temperature, significantly increasing channel carrier mobility within semiconductor devices. This reduces the on-resistance of the semiconductor devices and enhances the channel mobility and overall efficiency of SiC MOSFETs and SiC CMOS at different operating voltages. Furthermore, the properties of the semiconductor graphene layer 200 ensure uniform hole and electron mobility, effectively addressing the uniformity issue of channel mobility in n-MOS and p-MOS transistors, and improving the uniformity of switching speeds between p-channels and n-channels, as well as overall efficiency and thermal management efficiency.

[0059] Optionally, based on the above technical solutions, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention. The semiconductor device further includes a protective layer 300, which covers a semiconductor graphene layer 200.

[0060] Specifically, the protective layer 300 is a thin film formed by atomic layer deposition (ALD) to protect the semiconductor graphene layer 200, preventing damage to the semiconductor graphene layer 200 during the formation of subsequent film layers. This ensures that the semiconductor graphene layer 200 has high mobility, thereby increasing the structural stability of the semiconductor device. Optionally, the protective layer 300 is relatively thin, with a minimum thickness of 5 nm. While fulfilling its function of protecting the semiconductor graphene layer 200, it has little impact on the on-resistance of the semiconductor device. Optionally, based on the above technical solution, the protective layer 300 may include a gold protective layer or an aluminum oxide protective layer.

[0061] Specifically, the gold or aluminum oxide protective layer has stable physicochemical properties, which can protect the semiconductor graphene layer 200 and prevent damage to the semiconductor graphene layer 200 during the epitaxial formation of subsequent film layers.

[0062] Optionally, based on the above technical solutions, such as Figures 1-3 As shown, the silicon carbide semiconductor body 100 further includes a fourth region 112, a fifth region 113, and a sixth region 114; the fourth region 112 is located on the electrode setting surface 101, connected to the first region 103, and located in the first device region 001; the fifth region 113 is located on the electrode setting surface 101, connected to the second region 105, and located in the first conductivity type device region 021; the sixth region 114 is located on the electrode setting surface 101, connected to the third region 107, and located in the second conductivity type device region 022.

[0063] Specifically, the fourth region 112, the fifth region 113, and the sixth region 114 are used to achieve better ohmic contact between the source and the silicon carbide semiconductor body 100. The conductivity type of the fourth region 112 is the same as that of the first well region 104. The conductivity type of the fifth region 113 is the same as that of the second well region 106. The conductivity type of the sixth region 114 is the same as that of the third well region 108.

[0064] Optionally, based on the above technical solutions, such as Figures 1-3 As shown, the silicon carbide semiconductor body 100 includes a first drift layer 10, a second drift layer 20 and a third drift layer 30 stacked sequentially, and the surface of the third drift layer 30 away from the second drift layer 20 is the electrode setting surface 101; the first drift layer 10 is set to a first conductivity type, the second drift layer 20 is set to a second conductivity type, and the third drift layer 30 is set to a first conductivity type.

[0065] Optionally, based on the above technical solutions, such as Figures 1-3 As shown, the area of ​​the third drift layer 30 near the electrode setting surface 101 is reused as a first well region 104, a second well region 106, and a third well region 108, which is a well region of the first conductivity type. This can simplify the structure of the semiconductor device and reduce the manufacturing cost.

[0066] Optionally, based on the above technical solution, the first semiconductor graphene layer 201 and the first region 103 have the same conductivity type, the second semiconductor graphene layer 202 and the second region 105 have the same conductivity type, and the third semiconductor graphene layer 203 and the third region 107 have the same conductivity type.

[0067] Specifically, the first semiconductor graphene layer 201 and the first region 103 have the same conductivity type, that is, the conductivity type of the first semiconductor graphene layer 201 is the same as the conductivity type of the silicon carbide metal-oxide semiconductor field-effect transistor in the first device region 001 where it is located, which can further increase the carrier concentration of the conduction channel and reduce the conduction resistance.

[0068] The second semiconductor graphene layer 202 has the same conductivity type as the second region 105. That is, the conductivity type of the second semiconductor graphene layer 202 is the same as the conductivity type of the silicon carbide metal-oxide semiconductor field-effect transistor in the second device region 002 where it is located. This can further increase the carrier concentration of the conduction channel and reduce the conduction resistance.

[0069] This invention also provides a method for manufacturing a semiconductor device. For example... Figure 4 As shown, Figure 4 This is a flowchart of a semiconductor device manufacturing method provided in an embodiment of the present invention. The semiconductor device manufacturing method includes the following steps:

[0070] S110. A silicon carbide semiconductor body is provided, the silicon carbide semiconductor body includes a first device region and a second device region spaced apart along a first direction, the first direction being perpendicular to the thickness direction of the silicon carbide semiconductor body; the second device region includes a first conductivity type device region and a second conductivity type device region spaced apart along the first direction; the silicon carbide semiconductor body includes an electrode mounting surface.

[0071] like Figure 5 As shown, a silicon carbide semiconductor body 100 is provided. The silicon carbide semiconductor body 100 includes a first device region 001 and a second device region 002 spaced apart along a first direction, the first direction being perpendicular to the thickness direction of the silicon carbide semiconductor body 100; the second device region 002 includes a first conductivity type device region 021 and a second conductivity type device region 022 spaced apart along the first direction; the silicon carbide semiconductor body 100 includes an electrode mounting surface 101.

[0072] Optionally, the silicon carbide semiconductor body 100 includes a first region 103, a first well region 104, a second region 105, a second well region 106, a third region 107, and a third well region 108 on the side near the electrode placement surface 101. The first region 103 and the first well region 104 are located in the first device region 001 and have opposite conductivity types. The second region 105 and the second well region 106 are located in the first conductivity type device region 021 and have opposite conductivity types. The third region 107 and the third well region 108 are located in the second conductivity type device region 022 and have opposite conductivity types. The first semiconductor graphene layer 201 is connected to the two first regions 103. The second semiconductor graphene layer 202 is located and connected to the two second regions 105. The third semiconductor graphene layer 203 is connected to the two third regions 107.

[0073] Specifically, the above technical solution clearly specifies the exact location of the semiconductor graphene layer 200 in the SiC MOSFET with the conduction current direction in the first direction, the first conductivity type SiC MOSFET in the CMOS planar device, and the second conductivity type SiC MOSFET.

[0074] In the first device region 001, within a planar silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET), under the control of the gate, the conduction current flows from the source to the drain through the first region 103, the first semiconductor graphene layer 201, and the first region 103. In the second device region 002, within a first conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor (first conductivity type SiC MOSFET) with the conduction current direction in the first direction, under the control of the gate, the conduction current flows from the source to the drain through the second region 105, the second semiconductor graphene layer 202, and the second region 105. In the second device region 002, within a second conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor (second conductivity type SiC MOSFET) with the conduction current direction in the first direction, under the control of the gate, the conduction current flows from the source to the drain through the third region 107, the third semiconductor graphene layer 203, and the third region 107.

[0075] S120. A first semiconductor graphene layer, a second semiconductor graphene layer, and a third semiconductor graphene layer are formed on the electrode placement surface of the semiconductor graphene layer to improve the mobility of the semiconductor device. At the same preset temperature, the mobility of the semiconductor graphene layer is greater than that of silicon carbide. The first semiconductor graphene layer is located on the electrode placement surface of the first device region, the second semiconductor graphene layer is located on the electrode placement surface of the first conductivity type device region, and the third semiconductor graphene layer is located on the electrode placement surface of the second conductivity type device region.

[0076] like Figure 1As shown, a first semiconductor graphene layer 201, a second semiconductor graphene layer 202, and a third semiconductor graphene layer 203 are formed on the electrode surface 101. The semiconductor graphene layer 200 includes a first semiconductor graphene layer 201, a second semiconductor graphene layer 202, and a third semiconductor graphene layer 203. At the same preset temperature, the mobility of the semiconductor graphene layer 200 is greater than that of silicon carbide. The first semiconductor graphene layer 201 is located on the electrode surface 101 of the first device region 001, the second semiconductor graphene layer 202 is located on the electrode surface 101 of the first conductivity type device region 021, and the third semiconductor graphene layer 203 is located on the electrode surface 101 of the second conductivity type device region 022. In the semiconductor device, the portion located in the first device region 001 is a silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) with the current conduction direction in the first direction, and the portion located in the second device region 002 is a silicon carbide complementary metal-oxide-semiconductor (SiC CMOS). CMOS includes a first-conductivity silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) located in the first conductivity type device region 021 with the conduction current direction in the first direction, and a second-conductivity silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) located in the second conductivity type device region 022 with the conduction current direction in the first direction. The operating voltages of the silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) and the silicon carbide complementary metal-oxide-semiconductor (SiC CMOS) are different.

[0077] The thickness direction of the silicon carbide semiconductor body 100 is as follows: Figure 1 The Y direction, the first direction and Figure 1 The X-direction is set to be parallel.

[0078] In this embodiment of the invention, the silicon carbide semiconductor body 100 may include a substrate and an epitaxial layer, or it may only include an epitaxial layer. The epitaxial layer is a semiconductor layer formed by a single epitaxial process, including chemical vapor deposition (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0079] It should be noted that the mobility of the same semiconductor material varies with temperature. In this embodiment of the invention, the mobility of the semiconductor graphene layer 200 is greater than that of silicon carbide at the same preset temperature. That is, at the same preset temperature, the resistance to carrier movement in the semiconductor graphene layer 200 is less than that in silicon carbide, and the semiconductor graphene layer 200 is located on the electrode surface 101 of its respective planar structure device region. In the first device region 001, in the silicon carbide metal-oxide-semiconductor field-effect transistor (SiCMOSFET) with the current direction in the first direction, the current flows from the source to the drain through the first semiconductor graphene layer 201 under the control of the gate. In the second device region 002, in the first conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor (SiCMOSFET) with the current direction in the first direction, the current flows from the source to the drain through the second semiconductor graphene layer 202 under the control of the gate. In the second device region 002, within the second conductivity type silicon carbide metal-oxide semiconductor field-effect transistor (second conductivity type SiC MOSFET) with the conduction current direction in the first direction, under the control of the gate, the conduction current flows from the source to the drain through the third semiconductor graphene layer 203. The provision of the semiconductor graphene layer 200 significantly increases the channel carrier mobility within the semiconductor device, thereby reducing the on-resistance of the semiconductor device.

[0080] The semiconductor devices provided in this invention integrate a semiconductor graphene layer 200 into a SiC complementary metal-oxide-semiconductor (CMOS) device and a power SiC MOSFET device with the conduction current direction in the first direction. This helps improve the mobility of the semiconductor devices, aiming to create high-performance monolithically manufactured power integrated circuits (ICs) with minimal physical footprint, making them ideal for advanced electronic applications requiring high performance and reliability. Since the conduction current direction of both the SiC MOSFET, the first conductivity type SiC MOSFET, and the second conductivity type SiC MOSFET is in the first direction, and the semiconductor graphene layer 200 is located on the electrode surface 101 of their respective device regions, the conduction current flows from the source to the drain through the semiconductor graphene layer 200 under the control of their respective gates. Because the graphene layer 200 has high strength, high thermal conductivity, and a higher mobility than silicon carbide, and possesses semiconductor properties, it ensures the same hole and electron mobility, effectively solving the problem of uniformity in channel mobility of n-MOS and p-MOS transistors. This improves the uniformity of switching speed between p-channel and n-channel, overall efficiency, and thermal management efficiency, thereby significantly improving the carrier mobility and channel mobility of SiC MOSFETs, as well as the carrier mobility and channel mobility of first-conductivity type SiC MOSFETs and second-conductivity type SiC MOSFETs in CMOS planar devices. It also reduces the difference in mobility between carriers of different conductivity types under their respective operating voltages in different planar devices, thereby improving the electrical performance of monolithically integrated silicon carbide metal-oxide-semiconductor field-effect transistors and silicon carbide complementary metal-oxide-semiconductor semiconductor devices.

[0081] It should be noted that the mobility of the semiconductor graphene layer 200 depends on the growth quality of the material, and can range from tens of cm² / Vs to approximately 5000 cm² / Vs. Preferably, the mobility of the semiconductor graphene layer 200 at room temperature is greater than or equal to 1000 cm² / Vs, and can even reach approximately 5500 cm² / Vs. Room temperature, also known as ambient temperature or general temperature, is generally defined as 25 degrees Celsius, and sometimes as 300K (approximately 27 degrees Celsius). The required mobility for semiconductor devices is only around tens of cm² / Vs. Therefore, the semiconductor graphene layer 200 can significantly improve the mobility of semiconductor devices.

[0082] Optional, such as Figure 1 As shown, the band gap of the semiconductor graphene layer 200 is greater than or equal to 0.4 eV. Preferably, as... Figure 1 As shown, the band gap of the semiconductor graphene layer 200 is greater than or equal to 0.6 eV.

[0083] Specifically, due to the high strength, high thermal conductivity, and greater mobility than silicon carbide of the semiconductor graphene layer 200, and its semiconductor properties, its bandgap is greater than or equal to 0.4 eV, preferably greater than or equal to 0.6 eV, and its mobility is preferably greater than or equal to 1000 cm² / Vs, even reaching around 5500 cm² / Vs. This ensures the same hole and electron mobility within the conduction channel, effectively solving the uniformity problem of channel mobility between the first and second conductivity type SiC MOSFETs, improving the uniformity of switching speed between the first and second conductivity type channels, overall efficiency, and thermal management efficiency, resulting in a faster response speed for the semiconductor device. Optionally, based on the above technical solution, such as... Figure 6 As shown, Figure 6 yes Figure 4 The process diagram includes S110, which provides the silicon carbide semiconductor body including:

[0084] S1101, Provides a first silicon carbide semiconductor body.

[0085] like Figure 7 As shown, a first silicon carbide semiconductor body 1A is provided.

[0086] S1102, A fourth semiconductor graphene layer is formed on one side of the first silicon carbide semiconductor body, the semiconductor graphene layer further comprising a fourth semiconductor graphene layer.

[0087] like Figure 8 As shown, a fourth semiconductor graphene layer 204 is formed on one side of the first silicon carbide semiconductor body 1A, and the semiconductor graphene layer 200 further includes the fourth semiconductor graphene layer 204.

[0088] S1103, A second silicon carbide semiconductor body is formed on the side of the fourth semiconductor graphene layer away from the first silicon carbide semiconductor body; the silicon carbide semiconductor body includes the first silicon carbide semiconductor body and the second silicon carbide semiconductor body.

[0089] like Figure 9 As shown, a second silicon carbide semiconductor body 1B is formed on the side of the fourth semiconductor graphene layer 204 away from the first silicon carbide semiconductor body 1A by an epitaxial process; the silicon carbide semiconductor body 100 includes the first silicon carbide semiconductor body 1A and the second silicon carbide semiconductor body 1B.

[0090] S1104, a first semiconductor graphene layer, a second semiconductor graphene layer, and a third semiconductor graphene layer are formed on the side of the second silicon carbide semiconductor body away from the fourth semiconductor graphene layer.

[0091] like Figure 9As shown, a first semiconductor graphene layer 201, a second semiconductor graphene layer 202, and a third semiconductor graphene layer 203 are formed on the side of the second silicon carbide semiconductor body 1B away from the fourth semiconductor graphene layer 204.

[0092] Specifically, the fourth semiconductor graphene layer 204 is located between the first silicon carbide semiconductor body 1A and the second silicon carbide semiconductor body 1B. The fourth semiconductor graphene layer 204 and the first silicon carbide semiconductor body 1A are orderly connected by covalent bonds, and its mobility is greater than that of silicon carbide. Furthermore, the semiconductor graphene layer 204 is located in the conduction channel below the gate structure, which significantly increases the channel carrier mobility within the semiconductor device, and can increase the channel mobility to, for example, 5500 cm⁻¹. 2 V -1 s -1 The semiconductor graphene layer 200 exhibits improved channel mobility. Utilizing the superior charge mobility and thermal properties of the semiconductor graphene layer 200, the channel mobility and overall efficiency of SiC MOSFETs and SiC CMOS at different operating voltages are enhanced. Furthermore, the properties of the semiconductor graphene layer 200 ensure uniform hole and electron mobility, effectively addressing the uniformity issue of channel mobility in n-MOS and p-MOS transistors, and improving the uniformity of switching speeds between p-channels and n-channels, as well as overall efficiency and thermal management efficiency.

[0093] Optionally, based on the above technical solutions, such as Figure 10 As shown, Figure 10 This is a schematic flowchart of another semiconductor device manufacturing method provided in an embodiment of the present invention. Figure 10 The semiconductor device manufacturing method shown and Figure 4 The difference in the manufacturing methods of the semiconductor devices shown is that... Figure 10 for Figure 4 S120 is further defined, and the formation of the semiconductor graphene layer by S120 includes:

[0094] S1201. The silicon carbide semiconductor body is heated to a preset temperature, causing the silicon in the silicon carbide semiconductor body to evaporate, thereby forming a semiconductor graphene layer on one side of the silicon carbide semiconductor body.

[0095] like Figure 5 , Figure 8 and Figure 9 As shown, the silicon carbide semiconductor body 100 is heated to a preset temperature, causing the silicon on the surface of the silicon carbide semiconductor body 100 to evaporate, thereby forming a semiconductor graphene layer 200 on one side of the silicon carbide semiconductor body 100. The semiconductor graphene layer 200 and the silicon carbide semiconductor body 100 are connected by covalent bonding.

[0096] Specifically, the semiconductor graphene layer 200 is prepared using a heated silicon carbide semiconductor substrate 100. During heating, silicon evaporates before carbon, resulting in spontaneous crystallization of the semiconductor graphene layer 200 on the surface of the silicon carbide semiconductor substrate 100. The semiconductor graphene layer 200 is covalently bonded to the silicon carbide semiconductor substrate 100 during growth, eliminating the need for an adhesive layer, thus simplifying the fabrication process and reducing costs. The semiconductor graphene layer 200 is a two-dimensional semiconductor material, and the ordered covalent bonding between the semiconductor graphene layer 200 and the silicon carbide semiconductor substrate 100 results in a high mobility.

[0097] Optionally, based on the above technical solutions, such as Figure 11 As shown, Figure 11 yes Figure 10 The process flow diagram included in S1201 shows that S1201 heats the silicon carbide semiconductor body to a preset temperature, causing the silicon in the silicon carbide semiconductor body to evaporate, thereby forming a semiconductor graphene layer on one side of the silicon carbide semiconductor body.

[0098] S1201a, The silicon carbide semiconductor layer and the silicon carbide semiconductor body are arranged opposite each other.

[0099] like Figure 12 As shown, a silicon carbide semiconductor layer 400 is provided, and one side of the silicon carbide semiconductor layer 400 and the silicon carbide semiconductor body 100 are arranged opposite each other.

[0100] S1201b: Heating one side of the silicon carbide semiconductor body and the silicon carbide semiconductor layer to a preset temperature, so that the carbon surface of the silicon carbide semiconductor layer and one side of the silicon carbide semiconductor body provide a quasi-equilibrium condition between the carbon surface and the silicon surface at the preset temperature; wherein, the surface of one side of the silicon carbide semiconductor body is the silicon surface.

[0101] like Figure 12 As shown, one side of the silicon carbide semiconductor body 100 and the silicon carbide semiconductor layer 400 are heated to a preset temperature so that the carbon surface of the silicon carbide semiconductor layer 400 and one side of the silicon carbide semiconductor body 100 provide a quasi-equilibrium condition between the carbon surface and the silicon surface at the preset temperature; wherein, the surface of one side of the silicon carbide semiconductor body 100 is the silicon surface.

[0102] S1201c, silicon evaporates on one side of the silicon carbide semiconductor body, thereby forming a semiconductor graphene layer on one side of the silicon carbide semiconductor body.

[0103] like Figure 12As shown, during the heating process, silicon evaporates before carbon, resulting in the spontaneous crystallization of a semiconductor graphene layer 200 on the surface of the silicon carbide semiconductor body 100. The semiconductor graphene layer 200 is covalently bonded to the silicon carbide semiconductor body 100 during growth, eliminating the need for an adhesive layer, thus simplifying the fabrication process and reducing costs. Because the carbon surface of the silicon carbide semiconductor layer 400 and one side of the silicon carbide semiconductor body 100 provide a quasi-equilibrium condition between the carbon and silicon surfaces at a preset temperature, a semiconductor graphene layer 200 with a thickness equal to that of a single carbon atom can be formed on one side of the silicon carbide semiconductor body 100. In summary, the semiconductor graphene layer 200 is essentially a single layer of carbon atoms in the silicon carbide semiconductor body 100, with a thickness equivalent to that of a single layer of carbon atoms in a silicon carbide epitaxial layer. The thickness of the semiconductor graphene layer 200 is greater than or equal to 0.2 nm and less than or equal to 0.3 nm, with an average thickness of approximately 0.25 nm. The bonding between the semiconductor graphene layer 200 and the silicon carbide semiconductor body 100 is ordered and periodically arranged, ensuring that the semiconductor graphene layer 200 is a two-dimensional semiconductor material. The band gap of the semiconductor graphene layer 200 is smaller than that of silicon, and is greater than or equal to 0.6 eV.

[0104] Optionally, based on the above technical solution, after forming the semiconductor graphene layer in S120, the following steps are also included:

[0105] A protective layer is formed on the side of the semiconductor graphene layer away from the silicon carbide semiconductor body.

[0106] like Figure 3 As shown, a protective layer 300 is formed on the side of the semiconductor graphene layer 200 away from the silicon carbide semiconductor body 100.

[0107] Specifically, the protective layer 300 is a thin film formed by atomic layer deposition (ALD) to protect the semiconductor graphene layer 200 and prevent damage to it during the formation of subsequent film layers. This ensures that the semiconductor graphene layer 200 has high mobility, thereby increasing the structural stability of the semiconductor device. Optionally, the protective layer 300 is relatively thin, with a minimum thickness of 5 nm. While fulfilling its function of protecting the semiconductor graphene layer 200, it has little impact on the on-resistance of the semiconductor device.

[0108] Based on the above technical solution, the protective layer 300 includes a gold protective layer or an aluminum oxide protective layer.

[0109] Specifically, the gold or aluminum oxide protective layer has stable physicochemical properties, which can protect the semiconductor graphene layer 200 and prevent damage to the semiconductor graphene layer 200 during the epitaxial formation of subsequent film layers.

[0110] This invention provides a power module including a substrate and at least one semiconductor device as described in any embodiment of this invention, wherein the substrate is used to support the semiconductor device. Therefore, the beneficial effects of this power module including any semiconductor device as described in any embodiment of this invention will not be elaborated further here.

[0111] This invention provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this invention, with the semiconductor device electrically connected to the circuit board.

[0112] Therefore, this power conversion circuit incorporates the beneficial effects of any semiconductor device described in any embodiment of the present invention, which will not be elaborated further here.

[0113] This invention also provides a vehicle, which includes a load and the aforementioned power conversion circuit. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0114] Therefore, the beneficial effects of the vehicle including any of the power conversion circuit packages described in any embodiment of the present invention will not be repeated here.

[0115] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0116] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A semiconductor device, characterized in that, Includes: a silicon carbide semiconductor body, the silicon carbide semiconductor body including a first device region and a second device region spaced apart along a first direction, the first direction being perpendicular to the thickness direction of the silicon carbide semiconductor body; the second device region including a first conductivity type device region and a second conductivity type device region spaced apart along the first direction; the silicon carbide semiconductor body includes an electrode mounting surface; A semiconductor graphene layer, comprising a first semiconductor graphene layer, a second semiconductor graphene layer, and a third semiconductor graphene layer, is used to improve the mobility of the semiconductor device; at the same preset temperature, the mobility of the semiconductor graphene layer is greater than that of silicon carbide. The first semiconductor graphene layer is located on the electrode surface of the first device region, the second semiconductor graphene layer is located on the electrode surface of the first conductivity type device region, and the third semiconductor graphene layer is located on the electrode surface of the second conductivity type device region. In the semiconductor device, the portion located in the first device region is a silicon carbide metal-oxide-semiconductor field-effect transistor with the current conduction direction in the first direction, and the portion located in the second device region is a silicon carbide complementary metal-oxide-semiconductor. The silicon carbide complementary metal-oxide-semiconductor includes a first conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor located in the first conductivity type device region with the current conduction direction in the first direction and a second conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor located in the second conductivity type device region with the current conduction direction in the first direction. The silicon carbide metal-oxide-semiconductor field-effect transistor and the silicon carbide complementary metal-oxide-semiconductor have different operating voltages.

2. The semiconductor device according to claim 1, characterized in that, The band gap of the semiconductor graphene layer is greater than or equal to 0.4 eV.

3. The semiconductor device according to claim 2, characterized in that, The band gap of the semiconductor graphene layer is greater than or equal to 0.6 eV.

4. The semiconductor device according to claim 1, characterized in that, The silicon carbide semiconductor body includes a first region, a first well region, a second region, a second well region, a third region, and a third well region on the side near the electrode surface; the first region and the first well region are located in the first device region and have opposite conductivity types, the second region and the second well region are located in the first conductivity type device region and have opposite conductivity types, and the third region and the third well region are located in the second conductivity type device region and have opposite conductivity types. The first semiconductor graphene layer is connected to two of the first regions; the second semiconductor graphene layer is located and connected to two of the second regions; the third semiconductor graphene layer is connected to two of the third regions.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor graphene layer and the silicon carbide semiconductor body are connected in an orderly manner by covalent bonds.

6. The semiconductor device according to claim 1, characterized in that, The operating voltage of the silicon carbide metal-oxide-semiconductor field-effect transistor is greater than the operating voltage of the silicon carbide complementary metal-oxide-semiconductor. A first isolation region is provided between the silicon carbide semiconductor bodies between the first device region and the second device region; a second isolation region is provided between the first conductivity type device region and the second conductivity type device region.

7. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes: a first insulating layer located on the electrode placement surface; a first electrode located on the side of the first insulating layer away from the silicon carbide semiconductor body and located in the first device region; a second electrode located on the side of the first insulating layer away from the silicon carbide semiconductor body and located in the first conductivity type device region; and a third electrode located on the side of the first insulating layer away from the silicon carbide semiconductor body and located in the second conductivity type device region. The fourth and fifth electrodes are located in the first device region and are respectively connected to the two first regions; The sixth and seventh electrodes are located in the first conductivity type device region and are respectively connected to the two second regions; The eighth and ninth electrodes are located in the second conductivity type device region and are respectively connected to the two third regions.

8. The semiconductor device according to claim 4, characterized in that, The first region is located on the electrode placement surface, and the first well region is located between the two first regions; The second region is located on the electrode surface, and the second well region is located between the two second regions; The third region is located on the electrode surface, and the third well region is located between the two third regions.

9. The semiconductor device according to claim 1, characterized in that, The number of the first device regions includes multiple regions; the number of the second device regions includes multiple regions. Along the first direction, the first device region and the second device region are spaced apart; Alternatively, along the first direction, at least two of the first device regions are arranged consecutively; at least two of the second device regions are arranged consecutively.

10. The semiconductor device according to claim 9, characterized in that, The second device region includes S first conductivity type device regions and Q second conductivity type device regions, where S includes an integer greater than or equal to 1 and Q includes an integer greater than or equal to 1. Along the first direction, the first conductivity type device region and the second conductivity type device region are spaced apart; Alternatively, S includes an integer greater than or equal to 2, and at least two regions of the first conductivity type are continuously arranged along the first direction; Q includes an integer greater than or equal to 2, and at least two regions of the second conductivity type are continuously arranged along the first direction.

11. The semiconductor device according to claim 1, characterized in that, The semiconductor graphene layer further includes a fourth semiconductor graphene layer; The silicon carbide semiconductor body includes a first silicon carbide semiconductor body and a second silicon carbide semiconductor body; The first silicon carbide semiconductor body is used to support the second silicon carbide semiconductor body; The fourth semiconductor graphene layer is located between the first silicon carbide semiconductor body and the second silicon carbide semiconductor body, and the fourth semiconductor graphene layer and the first silicon carbide semiconductor body are connected in an orderly manner by covalent bonds.

12. The semiconductor device according to claim 1 or 11, characterized in that, The semiconductor device further includes a protective layer that covers the semiconductor graphene layer.

13. The semiconductor device according to claim 12, characterized in that, The protective layer includes a gold protective layer or an aluminum oxide protective layer.

14. The semiconductor device according to claim 4, characterized in that, The silicon carbide semiconductor body further includes a fourth region, a fifth region, and a sixth region; The fourth region is located on the electrode mounting surface, connected to a first region, and located in the first device region; The fifth region is located on the electrode mounting surface, connected to a second region, and located in the first conductivity type device region; The sixth region is located on the electrode mounting surface, connected to the third region, and located in the second conductivity type device region.

15. The semiconductor device according to claim 4, characterized in that, The silicon carbide semiconductor body includes a first drift layer, a second drift layer, and a third drift layer stacked sequentially, wherein the surface of the third drift layer away from the second drift layer is the electrode mounting surface; The first drift layer is set to a first conductivity type, the second drift layer is set to a second conductivity type, and the third drift layer is set to a first conductivity type.

16. The semiconductor device according to claim 15, characterized in that, The region of the third drift layer near the electrode surface is reused as the first well region, the second well region, and the third well region where the conductivity type is the first conductivity type.

17. The semiconductor device according to claim 4, characterized in that, The first semiconductor graphene layer and the first region have the same conductivity type, the second semiconductor graphene layer and the second region have the same conductivity type, and the third semiconductor graphene layer and the third region have the same conductivity type.

18. A method for manufacturing a semiconductor device, characterized in that, include: A silicon carbide semiconductor body is provided, the silicon carbide semiconductor body including a first device region and a second device region spaced apart along a first direction, the first direction being perpendicular to the thickness direction of the silicon carbide semiconductor body; the second device region includes a first conductivity type device region and a second conductivity type device region spaced apart along the first direction; the silicon carbide semiconductor body includes an electrode mounting surface; A first semiconductor graphene layer, a second semiconductor graphene layer, and a third semiconductor graphene layer are formed on the electrode surface to improve the mobility of the semiconductor device. At the same preset temperature, the mobility of the semiconductor graphene layer is greater than that of silicon carbide. The first semiconductor graphene layer is located on the electrode surface of the first device region, the second semiconductor graphene layer is located on the electrode surface of the first conductivity type device region, and the third semiconductor graphene layer is located on the electrode surface of the second conductivity type device region. In the semiconductor device, the portion located in the first device region is a silicon carbide metal-oxide-semiconductor field-effect transistor with the current conduction direction in the first direction, and the portion located in the second device region is a silicon carbide complementary metal-oxide-semiconductor. The silicon carbide complementary metal-oxide-semiconductor includes a first conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor located in the first conductivity type device region with the current conduction direction in the first direction and a second conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor located in the second conductivity type device region with the current conduction direction in the first direction. The silicon carbide metal-oxide-semiconductor field-effect transistor and the silicon carbide complementary metal-oxide-semiconductor have different operating voltages.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that, The band gap of the semiconductor graphene layer is greater than or equal to 0.4 eV.

20. The method for manufacturing a semiconductor device according to claim 19, characterized in that, The band gap of the semiconductor graphene layer is greater than or equal to 0.6 eV.

21. The method for manufacturing a semiconductor device according to claim 18, characterized in that, The silicon carbide semiconductor body includes: Provides the first silicon carbide semiconductor body; A fourth semiconductor graphene layer is formed on one side of the first silicon carbide semiconductor body, and the semiconductor graphene layer further includes the fourth semiconductor graphene layer. A second silicon carbide semiconductor body is formed on the side of the fourth semiconductor graphene layer away from the first silicon carbide semiconductor body; the silicon carbide semiconductor body includes the first silicon carbide semiconductor body and the second silicon carbide semiconductor body.

22. The method for manufacturing a semiconductor device according to claim 18, characterized in that, The formation of the semiconductor graphene layer includes: The silicon carbide semiconductor body is heated to a preset temperature, causing the silicon in the silicon carbide semiconductor body to evaporate, thereby forming a semiconductor graphene layer on one side of the silicon carbide semiconductor body.

23. The method for manufacturing a semiconductor device according to claim 22, characterized in that, Heating the silicon carbide semiconductor body to a preset temperature causes the silicon in the silicon carbide semiconductor body to evaporate, thereby forming a semiconductor graphene layer on one side of the silicon carbide semiconductor body, including: The silicon carbide semiconductor layer and the silicon carbide semiconductor body are arranged opposite each other on one side; One side of the silicon carbide semiconductor body and the silicon carbide semiconductor layer are heated to a preset temperature so that the carbon surface of the silicon carbide semiconductor layer and one side of the silicon carbide semiconductor body provide a quasi-equilibrium condition between the carbon surface and the silicon surface at the preset temperature; wherein, the surface of one side of the silicon carbide semiconductor body is the silicon surface; Silicon evaporates on one side of the silicon carbide semiconductor body, thereby forming the semiconductor graphene layer on one side of the silicon carbide semiconductor body.

24. The method for manufacturing a semiconductor device according to claim 18 or 22, characterized in that, After forming the semiconductor graphene layer, the process further includes: A protective layer is formed on the side of the semiconductor graphene layer away from the silicon carbide semiconductor body.

25. A power module, characterized in that, The device includes a substrate and a semiconductor device as described in any one of claims 1-17, wherein the substrate is used to support the semiconductor device.

26. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-17, the semiconductor device being electrically connected to the circuit board.

27. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 26, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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