Complementary FET device and control method thereof

Abstract

The invention discloses a complementary FET device and a control method thereof. There is provided a transistor device including: a substrate; a lower transistor on the substrate and including a lower channel layer, a lower gate, and a lower source / drain region; an upper transistor on the lower transistor and including an upper channel layer, an upper gate, and an upper source / drain region; and an inner spacer configured to insulate the lower transistor from the upper transistor, the inner spacer may be formed by removing a portion of each of a first sacrificial layer and a second sacrificial layer formed over and under the lower channel layer and the upper channel layer and having different Ge contents to a depth according to the Ge content and then depositing an insulating material.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0162440, filed on November 21, 2023, and Korean Patent Application No. 10-2024-0106019, filed on August 8, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] Various embodiments of the present disclosure relate to a semiconductor manufacturing technology. Background Art

[0003] As electronic devices become smaller and more highly integrated, semiconductor devices mounted on electronic devices are also becoming more highly integrated and ultra-miniaturized. In conventional field effect transistors (FETs) with a gate-all-around (GAA) structure, the FETs are horizontally arranged on a wafer substrate, so the number of transistors that can be applied per unit area of ​​the wafer substrate is limited.

[0004] To solve this problem, a complementary FET (CFET) having a vertically stacked n-metal oxide semiconductor FET (MOSFET) and a p-MOSFET of a GAA structure has been recently proposed. Summary of the invention

[0005] However, because CFET devices are still only an ideal technology, the detailed manufacturing process has not yet been disclosed.

[0006] The present disclosure is directed to providing a complementary transistor device and a control method thereof, which can form an inner spacer using a sacrificial layer having different Ge contents.

[0007] According to one aspect of the present disclosure, a transistor device is provided, comprising: a substrate; a lower transistor located on the substrate and comprising a lower channel layer, a lower gate and a lower source / drain region; an upper transistor located on the lower transistor and comprising an upper channel layer, an upper gate and an upper source / drain region; and an inner spacer, wherein the inner spacer is formed by removing a portion of each of a first sacrificial layer and a second sacrificial layer formed above and below the lower channel layer and the upper channel layer and having different Ge contents to a depth according to the Ge content and then depositing an insulating material.

[0008] According to another aspect of the present disclosure, a method for manufacturing a transistor device is provided, the method comprising: forming a nanosheet stack, wherein the nanosheet stack comprises a lower channel layer, an upper channel layer, and a plurality of first and second sacrificial layers separating the lower channel layer from the upper channel layer, wherein the first sacrificial layers and the second sacrificial layers have different Ge contents; forming an inner spacer in a space provided by removing a portion of the first sacrificial layer and a portion of the second sacrificial layer through an etching process at a rate according to the Ge content; and forming a lower gate around the lower channel layer and an upper gate around the upper channel layer in the provided space, wherein the remaining portion of each of the first sacrificial layer and the second sacrificial layer is removed from the provided space.

[0009] According to another aspect of the present disclosure, a transistor device is provided, comprising: a nanosheet stack, wherein the nanosheet stack comprises a lower channel layer, an upper channel layer, and a plurality of first and second sacrificial layers separating the lower channel layer from the upper channel layer; an inner spacer, wherein the inner spacer is formed on some side surfaces of the first and second sacrificial layers between at least the lower channel layer and the upper channel layer; a lower gate formed around the lower channel layer in a space remaining after removing the first and second sacrificial layers, and an upper gate formed around the upper channel layer, wherein the first and second sacrificial layers have different Ge contents, and the inner spacer is formed by removing a portion of the first and second sacrificial layers at a rate according to the Ge content through an etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 and Figure 2 is a diagram showing a process of forming a nanosheet stack of a semiconductor device according to one embodiment; Figures 3 to 7 is a diagram showing a process of forming a shallow trench isolation (STI) module of a semiconductor device according to one embodiment; Figures 8 to 15 is a diagram showing a process of forming a dummy gate module of a semiconductor device according to one embodiment; Figures 16 to 21 is a diagram showing a process of forming an inner spacer module of a semiconductor device according to an embodiment; Fig. 22 is a diagram for describing an epitaxial growth process for forming a lower source / drain according to one embodiment; Figure 23 to Figure 28is a diagram showing a process of forming and separating an n-metal oxide semiconductor field effect transistor (MOSFET) device and a p-MOSFET device; Figure 29 to Figure 44 is a diagram for describing a process of forming a replacement metal gate (RMG); Figures 45 to 51 is a diagram for describing a process for forming a metal line; Fig.52 is a diagram showing the structure of a complementary transistor device according to one embodiment; and Fig.53 is a flow chart illustrating a method of fabricating a complementary transistor device according to one embodiment.

[0011] In the description of the drawings, the same or similar reference numerals may be used for the same or similar components. DETAILED DESCRIPTION

[0012] Figure 1 and Figure 2 is a diagram illustrating a process of forming a nanosheet stack of a semiconductor device according to one embodiment.

[0013] Reference Figure 1 , a lower isolation layer can be formed on the semiconductor substrate sp.

[0014] The semiconductor substrate sp may include a silicon substrate and a silicon-on-insulator (SOI) substrate. The semiconductor substrate sp may include a p-type, n-type, or intrinsic silicon substrate.

[0015] The lower isolation layer may be formed by forming an insulating material on the semiconductor substrate sp or by performing appropriate ground plane doping on the semiconductor substrate sp. The lower isolation layer of the semiconductor substrate sp may serve to reduce leakage current in an off state of a channel formed in the semiconductor substrate sp.

[0016] In the lower isolation layer, after the SiGe sacrificial layer is selectively etched in the replacement metal gate (RMG) module, a metal gate can be formed around the Si channel layer. Then, the metal gate of the lower isolation layer contacts the semiconductor substrate sp, and the source / drain is formed under the lower isolation layer, and thus the lower isolation layer has a planar field effect transistor (FET) form structure.

[0017] like Figure 2As shown in , a nanosheet stack ns_s can be formed by repeatedly and continuously growing Si epitaxial layers Si and SiGe epitaxial layers (at least one of the first sacrificial layer and multiple second sacrificial layers) SiGe1 and SiGe2 on a semiconductor substrate sp. In this regard, the Si epitaxial layer can constitute the channel layer of a stacked n-metal oxide semiconductor FET (MOSFET) and p-MOSFET device having a complementary FET (CFET) structure. Both the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 can be sacrificial layers that are completely removed by selective etching in subsequent processes. The first sacrificial layer SiGe1 can be formed on the upper and lower portions of each of at least the lower channel layer l_ch and the upper channel layer u_ch. The second sacrificial layer SiGe2 can be formed between the first sacrificial layer SiGe1 present between at least the lower channel layer l_ch and the upper channel layer u_ch.

[0018] Figure 2 , an example of forming two channel layers Si in each of the n-MOSFET and the p-MOSFET is shown. However, the present disclosure is not limited thereto. For example, the number of channel layers Si may be one or three or more, and the number of Si channels may be determined by the repeated growth of the SiGe epitaxial layer and the Si epitaxial layer. Similarly, the number and type of sacrificial layers SiGe1 and SiCe2 are not limited thereto. For example, at least one type of sacrificial layer is also included. As another example, the number of the first sacrificial layer and the second sacrificial layer may be the same as Figure 2 different.

[0019] Since there is a lattice constant difference of about 4.3% between Si and Ge, stress may occur in the film during the repeated growth of SiGe epitaxial layer and Si epitaxial layer. When the thickness of the film exceeds the critical thickness in the state where stress occurs, the stress is reduced by releasing the accumulated stress energy. Then, dislocations are generated at the interface, which may reduce the performance of the device and cause leakage current.

[0020] In order to prevent dislocation, the Si epitaxial layer Si and the SiGe epitaxial layers SiGe1 and SiGe2 can be grown by at least one low vacuum process of remote plasma chemical vapor deposition (RPCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), molecular beam epitaxy (MBE) and atomic layer deposition (ALD) growth methods. Therefore, the crystallinity of the channel layer can be ensured, and the composition and thickness can be precisely controlled.

[0021] The Si epitaxial layer Si (channel layer) may be formed to have a thickness of 5 nm to 30 nm. The SiGe epitaxial layers SiGe1 and SiGe2 (sacrificial layers) may each be formed to have a thickness of 5 nm to 30 nm. Considering the thickness reduction due to subsequent processes, the SiGe epitaxial layer SiGe1 located at the top may be formed to be thicker than other layers. For example, the SiGe epitaxial layer SiGe1 located at the top may be formed to have a thickness of 5 nm to 100 nm.

[0022] According to one embodiment, an epitaxial layer may be formed to prevent an empty space from being formed during the formation of an inner spacer in a subsequent process. For example, epitaxial growth may be performed at a Ge content of 10% to 30% of the SiGe epitaxial layer SiGe1. Epitaxial growth may be performed at a ratio where the Ge content of the SiGe epitaxial layer SiGe2 is at least 20% greater than the Ge content of the SiGe epitaxial layer SiGe1. Specifically, the first sacrificial layer SiGe1 may be a SiGe layer having a Ge content of 10% to 30%. The second sacrificial layer SiGe2 may be a SiGe layer having a Ge content of at least 20% greater than the Ge content of the first sacrificial layer.

[0023] Figures 3 to 7 is a diagram illustrating a process of forming a shallow trench isolation (STI) module of a semiconductor device according to one embodiment.

[0024] like Figure 3 As shown in FIG, an upper portion UP_1 including a nanosheet stack ns_s and a portion of a semiconductor substrate sp is etched in a protruding shape using, for example, a hard mask. The upper portion UP_1 process is a process of forming trench isolation for separation between devices, and may be the same as or similar to a process of forming a fin of a fin-FET.

[0025] like Figure 4 As shown in FIG. 1 , a silicon nitride layer (SixNy) liner layer ln1 is formed on the upper portion UP_1 by a deposition method such as LPCVD, PECVD or ALD. The liner layer ln1 may be formed to have a thickness of 30 nm or less. The liner layer ln1 may prevent oxidation of the Si epitaxial layer and the SiGe epitaxial layers SiGe1 and SiGe2 and diffusion of Ge during a subsequent process of forming trench isolation.

[0026] like Figure 5 As shown in FIG. , the silicon oxide layer sl1 is Figure 4 grows on the entire surface of the semiconductor substrate 4, so Figure 3The etched area in is filled with the silicon oxide layer sl1. Then, a portion of the silicon oxide layer sl1 is planarized by a chemical mechanical polishing (CMP) process. Here, the silicon oxide layer sl1 may be densified by a high heat treatment process before the process of planarizing the silicon oxide layer sl1. Since the heat treatment process is performed at a temperature of 900°C or lower, Ge can be prevented from diffusing from the SiGe layer to the Si channel layer. In this case, the silicon nitride layer liner layer ln1 may be used as an etch stop layer in the planarization process of the silicon oxide layer sl1. Alternatively, a planarization process may be performed before exposing the silicon nitride layer liner layer ln1.

[0027] like Figure 6 As shown in , a portion of the silicon oxide layer sl1 can be etched by an etch-back process. In this case, the etch-back process can be performed to a depth where the silicon nitride layer pad layer ln1 is not etched. In this regard, the etch-back process can be performed using a process that has a higher etching selectivity to the silicon oxide film sl1 than to the silicon nitride layer (SixNy). In this case, an STI module STI corresponding to the remaining silicon oxide layer sl1 can be provided, which is lower than the starting height of the Si epitaxial layer and the SiGe epitaxial layers SiGe1 and SiGe2. Therefore, the Si epitaxial layer and the SiGe epitaxial layers SiGe1 and SiGe2 can be exposed in subsequent processes.

[0028] like Figure 7 As shown in , the silicon nitride layer liner layer ln2 can be grown on the STI module STI to a thickness of 30nm or less. In this case, Figure 6 The liner layer ln1 etched together with the silicon oxide layer sl1 in the process may also be regrown. Figure 7 However, the present disclosure is not limited thereto.

[0029] Figures 8 to 15 is a diagram illustrating a process of forming a dummy gate module of a semiconductor device according to an embodiment.

[0030] like Figure 8 As shown in , a dummy gate Dg can be grown on the entire upper surface of the semiconductor substrate sp. Thereafter, the dummy gate Dg is planarized by a CMP process. The dummy gate Dg can be formed using polycrystalline Si or SiGe, or amorphous Si or SiGe. Alternatively, the dummy gate Dg can be formed using another material having a high etching selectivity relative to the silicon nitride (protective) layers ln1 and ln2. Here, a planarization process of the dummy gate Dg can be performed so as not to expose the liner layers ln1 and ln2. The dummy gate Dg remaining after planarization can be a region where a high-k insulating film and a metal gate are deposited by a subsequent process to form a gate stack.

[0031] like Fig. 9 As shown in , the dummy gate cap Dgc may be deposited on the planarized dummy gate Dg using a silicon nitride layer. The dummy gate cap Dgc may be used as a hard mask during etching of the channel layer Si.

[0032] Reference Fig.10 , a dummy gate cap Dgc as a silicon nitride layer is patterned by, for example, a dry etching process. According to one embodiment, the etching process may be performed by photolithography and dry etching processes according to, for example, a silicon channel length of a semiconductor device (or a gate width of a region where a source / drain is to be formed).

[0033] Reference Fig.11 According to one embodiment, the dummy gate cap Dgc is used as a hard mask to etch the dummy gate Dg according to the silicon channel length of the semiconductor device.

[0034] In the following, reference will be made to Figures 12 to 15 A process of forming an outer spacer on a side surface of the dummy gate Dg is described.

[0035] like Fig.12 As shown in , an outer spacer os1 is formed on the side surface of the dummy gate Dg. When the thermal oxidation process is performed at a temperature of 900° C. or less, the outer spacer os1 is formed as a silicon oxide layer. During the thermal oxidation process, since the silicon oxide layer simultaneously grows from the initial boundary surface in a direction away from the horizontal center of the semiconductor substrate sp, the thickness of the outer spacer os1 can be formed in consideration of the width of the channel layer.

[0036] Alternatively, if Fig.13 and Fig.14 As shown in Fig.12 The outer spacer os2 is formed by a different process. Fig.13 As shown in , the outer spacer os2 can be formed by growing a specified material on the entire surface of the wafer using ALD or CVD. The specified material may include at least one material of a silicon oxide layer, a silicon nitride layer, or a silicon carbide layer, such as SiN, SiO, SiC, SiCO, and SiCN. In addition, as Fig.14 As shown in FIG. 1 , since the upper portion of the grown outer spacer layer os2 is etched by an anisotropic etching process, the outer spacer os2 may leave only the side surface of the upper portion of the dummy gate Dg and the dummy gate cap Dgc. Fig.12 However, the present disclosure is not limited thereto.

[0037] like Fig.15As shown in , wet etching or dry etching of the silicon nitride layer In2 is selectively performed on the silicon nitride layer In2 using a process having a higher etching selectivity for the silicon nitride layer In2 than for the silicon oxide layer In1. When etching the silicon nitride layer In2, the upper portion of the SiGe sacrificial layer SiGe1 may be exposed. In this case, the dummy gate cap Dgc is also etched simultaneously with the silicon nitride layer, but the process is controlled so as not to completely remove the dummy gate cap Dgc.

[0038] In the following, reference will be made to Figures 16 to 21 A process of forming an inner spacer module of a semiconductor device according to one embodiment is described.

[0039] like Fig.16 As shown in , the dummy gate cap Dgc as a silicon nitride layer and the outer spacer os1 are used as a hard mask to etch the Si channel layer Si and some of the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2. Fig.16 In the embodiment of the present invention, by using a process having a high etching selectivity for the silicon oxide layer and the silicon nitride layer, the process can be controlled to selectively etch only the Si channel layer Si, the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2. Fig.16 In the embodiment, etching may be performed to a depth at which the nanosheet stack ep including the Si channel layer Si and the first and second sacrificial layers SiGe1 and SiGe2 is entirely exposed and the trench isolation TI is exposed.

[0040] In such Fig.16 In the structure shown in FIG. 1 , the Si channel layer Si and the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 are exposed. Fig.17 As shown in FIG. 5 , a cavity etching process of the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 is performed to form an inner spacer is1.

[0041] In the cavity etching process, the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 are not completely etched, but the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 can be selectively wet or dry etched as much as the width of the inner spacer. The inner spacer is1 determines the length of the Si channel and is used as a self-aligned mask during source / drain formation, so uniformity is necessary.

[0042] The cavity etching process of the first and second sacrificial layers SiGe1 and SiGe2 should have very high selectivity to the dummy gate cap Dgc, the outer spacer os1 and the Si channel layer Si, and the etching rate should increase according to the Ge content in the first and second sacrificial layers SiGe1 and SiGe2.

[0043] In this way, through the etching process, the etching depth of the second sacrificial layer SiGe2 having a Ge content at least 20% higher than the Ge content of the first sacrificial layer SiGe1 should be greater than the etching depth of the first sacrificial layer SiGe1.

[0044] like Fig.18 As shown in , an inner spacer is1 is deposited on the entire surface where the SiGe cavity etching process is performed using ALD. The inner spacer is1 can be formed using a specified material. The specified material may include at least one of a silicon oxide layer, a silicon nitride layer, or a silicon carbide layer, such as SiN, SiO, SiC, SiCO, and SiCN.

[0045] like Fig.19 As shown in Fig.16 When a designated material is formed on the remaining side surface of each of the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 , the outer side surface of the inner spacer is1 may be gradually flattened.

[0046] Fig. 20 Deposition results of designated materials when only the first sacrificial layer SiGe1 is used according to another embodiment are shown.

[0047] refer to Fig. 20 , unlike one embodiment, when only the SiGe sacrificial layer SiGe1 having the same Ge content is used, it can be seen that no insulating material is deposited on some side surfaces of the first sacrificial layer SiGe1. In this case, the gap between the vertically stacked n-MOSFET and p-MOSFET in the subsequent process is not electrically insulated, and thus a CFET structure cannot be formed. Specifically, in Fig. 20 In the left case, the thickness of the inner spacer formed on the side surface of the first sacrificial layer SiGe1 between the upper Si channel layer and the lower Si channel layer is the same as or similar to the thickness of the inner spacer formed on the side surface of the Si channel layer. Therefore, since etching is performed with the same thickness during etching of the formed inner spacer, an empty space may be generated in the inner spacer. Therefore, a problem of forming a source / drain in an unnecessary portion during subsequent source / drain epitaxial growth may occur.

[0048] Fig.21 is a diagram for describing an inner spacer of a semiconductor device.

[0049] Reference Fig.21, a portion of the inner spacer material deposited on the semiconductor substrate sp is removed by an etching process. In the etching process, the inner spacer material deposited on the side surface of the Si channel layer Si and on the top surface and side surface of the dummy gate Dg and the dummy gate cap Dgc is etched. The inner spacer material is deposited to be thicker on the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 than on the Si channel layer Si. In the etching process, the etching of the inner spacer is1 can be controlled to expose only the side surface of the Si channel layer Si. The etching process can be performed, for example, by a wet or dry etching process or an atomic layer etching (ALE) process. The inner spacer material remaining by the above-mentioned etching process can be formed as follows Fig.21 The inner spacer is1 is shown.

[0050] In the following, reference will be made to Fig. 22 Describes the process of forming the source / drain of n-MOSFET and p-MOSFET.

[0051] Fig. 22 is a diagram for describing an epitaxial growth process for forming a lower source / drain according to one embodiment.

[0052] Reference Fig. 22 , using the Si channel layer Si (wherein the silicon is exposed) and the lower isolation layer of the silicon substrate sp as a seed layer to perform selective epitaxial growth of the source / drain regions p_S0 and p_SD. The selective epitaxial growth is not performed on the silicon oxide layer (e.g., the inner spacer is1), but only on the exposed silicon portion. The lower p-MOSFET of the CFET device according to one embodiment is formed. To this end, a SiGe epitaxial layer doped with a p-type dopant in real time can be selectively grown. Optionally, after the SiGe epitaxial layer is selectively grown, doping can be performed by an ion implantation process of a p-type dopant. In this case, the Ge content in each of the source / drain regions p_S0 and p_SD can be 20% or more.

[0053] exist Fig. 22 In FIG. 1 , it can be seen that unnecessary p-type dummy source / drain regions are formed in the upper Si channel layer together with the p-type source / drain regions p_SD in the lower p-MOSFET. However, due to the structure of the designed CFET device, the dummy source / drain p_S0 on the upper portion is removed by subsequent processes.

[0054] In the following, reference will be made to Figure 23 to Figure 28 The processes for forming and separating n-MOSFET devices and p-MOSFET devices are described.

[0055] Fig.23 is a diagram illustrating a process of covering a semiconductor substrate with an insulator (organic solvent) according to one embodiment.

[0056] Reference Fig.23 , the organic solvent l_de is formed to a height greater than the height of the dummy gate covering the semiconductor substrate. The organic solvent l_de is an organic solvent for semiconductors and may include, for example, propylene glycol methyl ether acetate (PGMEA), propylene glycol propyl ether (PGPE), cyclohexanone, ethyl lactate (EL), γ-butyrolactone (GBL) or N-methylpyridine (NMP). The organic solvent may be used in a photoresist (PR), a bottom anti-reflective coating (BARC) or a spin-on carbon (SoC).

[0057] Fig.24 An organic solvent etch-back process for semiconductors is shown.

[0058] like Fig.24 As shown in , some of the organic solvent l_de for semiconductors can be removed by an etch-back process. As a result, the source / drain region p_S0 formed in the upper n-MOSFET can be fully exposed, and the source / drain region p_SD formed in the lower p-MOSFET can be formed in a form covered with the organic solvent l_de for semiconductors.

[0059] Fig.25 FIG. 1 is a diagram for describing the etching process of the upper source / drain SiGe epitaxial layer.

[0060] like Fig.25 As shown in , the dummy source / drain region p_S0 formed in the upper n-MOSFET is selectively removed by a wet or dry etching process. Since the etching process adopts a process having high selectivity for the Si channel layer Si, the etching process can be accurately performed so as not to affect the Si channel layer Si.

[0061] Fig.26 is a diagram for describing a removal process of an organic solvent l_de for semiconductors.

[0062] like Fig.26 As shown in , the organic solvent l_de for semiconductor formed on the upper portion of the lower p-MOSFET can be removed. For example, the organic solvent l_de for semiconductor can be removed by an etch-back process.

[0063] Fig. 27 is a diagram for describing an insulation process of an n-MOSFET and a P-MOSFET according to one embodiment.

[0064] Reference Fig. 27As in the first process (S27_1), a silicon oxide layer sl2 is formed on the entire surface of the semiconductor substrate (for example, in the space where the dummy source / drain region p_S0 and the organic solvent l_de are removed). Thereafter, as in the second process (S27_2), a portion of the silicon oxide layer sl2 is removed by an etch-back process. As a result, the silicon oxide layer sl2 remains only on the upper portion of the p-MOSFET, and the Si channel layer Si of the upper n-MOSFET device is completely exposed.

[0065] Fig.28 is a diagram for describing a process of forming a source / drain of an upper n-MOSTFET according to one embodiment.

[0066] like Fig.28 As shown in , the source / drain region n_SD of the n-MOSFET is formed on the upper Si channel layer Si where the silicon is exposed. For example, a Si epitaxial layer doped with an n-type dopant in real time may be selectively grown. As another example, the source / drain region n_SD of the n-MOSFET may be formed by selectively growing a Si epitaxial layer and doping the Si epitaxial layer by an ion implantation process of an n-type dopant.

[0067] In the following, reference will be made to Figure 29 to Figure 44 The process of forming RMG is described. This may be a process in which the dummy gate Dg is converted into an actual metal gate region.

[0068] Fig.29 and Fig.30 is a diagram for describing a process of forming an interlayer dielectric (ILD).

[0069] like Fig.29 As shown in FIG. 1 , the ILD as a silicon oxide layer is formed on the entire surface of the semiconductor substrate (eg, the top of the upper source / drain regions n_S / D and the silicon oxide layer s12 having a thickness covering the dummy gate cap Dgc).

[0070] like Fig.30 As shown in , the ILD formed on the semiconductor substrate sp is planarized by a CMP process to expose the dummy gate cap Dgc. In this case, the dummy gate cap Dgc as a silicon nitride layer can be used as a stop layer in the planarization process. After the planarization process, the entire upper surface of the dummy gate cap Dgc can be exposed.

[0071] Fig.31 , Fig.32 and Fig.33 is a diagram for describing a process of exposing the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2.

[0072] like Fig.31As shown in FIG. 4 , the dummy gate cap Dgc is completely removed using a wet or dry etching process having a high etching selectivity to the silicon oxide layer (ILD) ILD1.

[0073] like Fig.32 As shown in , an etching process with high etching selectivity for the silicon oxide layer and the silicon nitride layer is used to completely remove the dummy gate Dg. The silicon nitride protection layer ln2 under the dummy gate Dg completely surrounds the Si channel layer Si. Therefore, the dummy gate Dg can be removed by wet etching.

[0074] like Fig.33 As shown in FIG. 1 , the silicon nitride protection layer In2 is removed using a designated etching process to expose the Si channel layer Si, the inner spacer Is1 , and the first and second sacrificial layers SiGe1 and SiGe2 . Fig.33 The etching process may utilize an etching process having a high etching selectivity with respect to the silicon oxide layer.

[0075] Fig.34 is a diagram for describing a process of etching the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2.

[0076] like Fig.34 As shown in the figure, in a state where the side surfaces of the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 and the Si channel layer Si are exposed, the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 are selectively etched. It is important that the etching process of the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 has high selectivity for the ILD ILD1, the outer spacer os1, the inner spacer is1 and the Si channel layer Si. Both dry etching and wet etching can be used as selective etching of the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2. The first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 are selectively etched on both sides of the width of the silicon channel.

[0077] Fig.35 is a diagram for describing a process of forming a gate dielectric insulating layer.

[0078] like Fig.35 As shown in , a gate dielectric insulating layer sl3 is formed on all surfaces of the Si channel layer Si, two cross sections of the inner spacer is1, and the surface of the exposed semiconductor substrate. The gate dielectric insulating layer sl3 can be formed of silicon oxide, silicon nitride, or a high-k dielectric material. The high-k dielectric material may include Hf, Zr, Al, La, Mg, Ba, Ti, or Pb, or metal oxides and silicates according to a combination of Hf, Zr, Al, La, Mg, Ba, Ti, and Pb. ALD can be used to deposit the gate dielectric insulating layer sl3 with the same thickness on the three-dimensional channel.

[0079] Fig.36 is a diagram for describing a process of forming a p-type work function metal.

[0080] like Fig.36 As shown in , a p-type work function metal is formed on all outer surfaces of the gate dielectric insulating layer sl3. Since the p-type work function metal Wf1 should be formed to be thin with a constant thickness, the p-type work function metal Wf1 may be formed using ALD.

[0081] Fig.37 is a diagram for describing a process of forming a metal gate.

[0082] like Fig.37 As shown in FIG. 1 , the portion remaining after forming the gate dielectric insulating layer S12 and the p-type work function metal Wf1 of the semiconductor substrate is filled with the metal gate L_mg.

[0083] The metal gate L_mg may be formed in the form of at least one layer including at least one material of Ti, Al, Cu, and W. The metal gate L_mg may be formed by ALD in the same manner as the gate dielectric insulating layer sl3 and the p-type work function metal Wf1. Alternatively, the metal gate L_mg may be formed by electroplating or electroless plating.

[0084] Fig.38 It is a diagram used to describe the etch-back process of the metal gate.

[0085] like Fig.38 As shown in , the metal gate L_mg is subjected to an etch-back process. The height LMG of the metal gate is adjusted to a height between the heights of the n-MOSFET and the p-MOSFET (or the height of the region where the p-MOSFET is formed). For the etching process of a three-dimensional complex structure, the metal gate LMG can be etched by wet etching.

[0086] Fig.39 is a diagram for describing a process of etching the p-type work function metal Wf1.

[0087] like Fig.39 As shown in , a portion of the p-type work function metal Wf1 formed around the Si channel layer of the upper n-MOSFET and formed on the sidewall may be selectively etched.

[0088] Fig.40 and Fig.41 is a diagram for describing a process of forming an insulator that separates an n-MOSFET from a p-MOSFET.

[0089] like Fig.40 As shown in , an insulator s_de having a high thickness is formed on the entire surface of the semiconductor substrate (eg, on top of the metal gate L_mg).

[0090] like Fig.41 As shown in FIG. 1 , the insulator s_de is removed by an etch-back process and is formed only to the upper portion of the p-MOSFET metal gate.

[0091] Fig.42 is a diagram for describing a process of forming an n-type work function metal.

[0092] like Fig.42 As shown in , an n-type work function metal Wf2 is formed on all surfaces of the gate dielectric insulating layer of the Si channel layer of the upper n-MOSFET. Since the n-type work function metal Wf2 should be formed to be thin with a constant thickness, the n-type work function metal Wf2 can be formed using ALD.

[0093] Fig.43 and Fig.44 is a diagram for describing a process of forming a metal gate.

[0094] like Fig.43 As shown in , the portion remaining after forming the gate dielectric insulating layer sl3 and the n-type work function metal is filled with the metal gate u_mg. The metal gate u_mg may be formed in the form of at least one layer including at least one material of Ti, Al, Cu, and W. The metal gate u_mg may be formed by at least one of ALD, electroplating, and chemical plating.

[0095] like Fig.44 As shown in FIG. 5 , a metal CMP process may be used to planarize excess portions of the gate dielectric insulating layer sl3 , the n-type work function metal Wf2 , and the metal gate u_mg on the upper portion of the ILD layer.

[0096] In the following, reference will be made to Figures 45 to 51 Describe the process of forming metal lines.

[0097] like Fig.45 As shown in FIG. 1 , a second ILD layer ILD2 is formed on the entire surface of the semiconductor substrate (eg, on top of the metal gate u_mg and the gate dielectric insulating layer sl3).

[0098] like Fig.46 As shown in FIG, a metal contact Mc1 is formed in the source / drain region (hereinafter, referred to as “lower source / drain region”) (p_SD) of the lower p-MOSFET and the metal gate region L_mg. The metal contact Mc1 may be formed by photolithography and dry etching processes on at least a portion of each of the second ILD layer ILD2, the lower source / drain region p_SD, and the lower gate region L_mg.

[0099] Fig.47 and48 A process of forming a metal plug is shown.

[0100] like Fig.47 As shown in FIG. 1 , a first metal plug Mp1 is formed in the upper source / drain region p_SD and the metal contact Mc1 .

[0101] like Fig.48 As shown in FIG. 1 , a portion of the first metal plug Mp1 formed on the upper portion of the second ILD layer ILD2 may be sufficiently planarized using a metal CMP process. Then, a metal wiring process for the first metal plug Mp1 is performed.

[0102] Figures 48 to 51 A process of forming a second metal plug is shown.

[0103] like Fig.48 As shown in FIG. 4 , the metal etch-back process is performed by exposing only the source / drain contacts Mc2 of the first metal plugs Mp1 .

[0104] like Fig.49 As shown in FIG. 4 , an insulating layer De2 is formed on the entire surface of the wafer (eg, at least a portion of the source / drain contacts Mc2 ).

[0105] like Fig.50 As shown in FIG. 4 , an etch-back process is performed on the insulating layer De2 to expose the source / drain regions of the upper n-MOSFET device.

[0106] like Fig.51 As shown in , the second metal plug Mp2 may be formed in the source / drain region of the upper n-MOSFET device. Then, a metal line process may be performed on the second metal plug Mp2.

[0107] In this manner, in the CFET semiconductor device 51 according to one embodiment, source / drain regions of n-MOSFET and p-MOSFET may be formed through a relatively simplified process.

[0108] In addition, according to one embodiment, a CFET semiconductor device 51 can be manufactured so that no voids are generated when an inner spacer is formed by stacking SiGe sacrificial layers with different Ge contents, and repeated stacking of SiGe sacrificial layers allows a gap between n-MOSFET and p-MOSFET to be fully formed as needed.

[0109] Fig.52 is a diagram showing the structure of a complementary transistor device according to one embodiment.

[0110] Reference Fig.52, a complementary transistor device 52 according to an embodiment may include a substrate sp, a lower transistor l_tr, an upper transistor u_tr, and an inner spacer is1. Fig.52 In the embodiment, the complementary transistor device 52 includes an example of two transistors, an upper transistor u_tr and a lower transistor l_tr. However, the present disclosure is not limited thereto.

[0111] The lower transistor l_tr is located over the substrate sp and may include a lower channel layer l_ch, a lower gate l_mg, and a lower source / drain region n_SD.

[0112] The upper transistor u_tr is located above the lower transistor l_tr and may include an upper channel layer u_ch, an upper gate u_mg, and an upper source / drain region p_SD.

[0113] The lower channel layer l_ch and the upper channel layer u_ch are repeatedly grown and formed to include a first sacrificial layer SiGe1 and a second sacrificial layer SiGe2 between the lower channel layer l_ch and the upper channel layer u_ch. Then, the lower channel layer l_ch and the upper channel layer u_ch can be formed to correspond to transistors l_tr and u_tr by etching in the y direction (or x direction) corresponding to the channel length and removing the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2.

[0114] The lower source / drain region n_SD may be formed by selectively growing a Si epitaxial layer on a sidewall of the lower channel layer on the substrate and doping the Si epitaxial layer with a first dopant (eg, a p-type dopant).

[0115] The upper source / drain region p_SD may be formed by removing a dummy source / drain region formed on a sidewall of the upper channel layer together with the lower source / drain region in a state where the lower source / drain region n_SD is covered with an organic solvent l_de and then removing the organic solvent l_de. The upper source / drain region p_SD may be formed by epitaxially growing the upper channel layer in a state where a silicon oxide layer is formed only on an upper portion of the lower transistor from which the organic solvent l_de is removed.

[0116] The inner spacer is1 may be formed by removing a portion of each of the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 formed above and below the lower channel layer l_ch and the upper channel layer and having different Ge contents to a depth according to the Ge content, and then depositing an insulating material. The inner spacer is1 may insulate the upper gate u_mg from the lower source / drain region n_SD, and insulate the upper gate u_mg from the upper source / drain region p_SD. As a result, the inner spacer is1 may serve as a sidewall that prevents the gate length (or channel length) from being reduced to a specific value or less. The inner spacer is1 may also be formed between the lower transistor l_tr and the upper transistor u_tr to separate the lower transistor l_tr from the upper transistor u_tr.

[0117] The inner spacer is1 may be located between the lower channel layer l_ch and the upper channel layer u_ch and configured to insulate the lower transistor l_tr from the upper transistor u_tr. Some sidewalls of the inner spacer is1 may be formed thicker than sidewalls of the lower gate l_mg and the upper gate u_mg formed above and below the lower channel layer l_ch and the upper channel layer u_ch.

[0118] The first sacrificial layer SiGe1 may be a SiGe layer having a Ge content of 10% to 30%. The second sacrificial layer SiGe2 may be a SiGe layer having a Ge content at least 20% greater than that of the first sacrificial layer.

[0119] The inner spacer is1 may be formed by etching the second sacrificial layer SiGe2 deeper than the first sacrificial layer SiGe1 by cavity etching having high selectivity to the channel layers u_ch and l_ch at a rate corresponding to the Ge content and depositing an insulating material on the outer sides of the first and second sacrificial layers SiGe1 and SiGe2 remaining after the cavity etching.

[0120] The first sacrificial layer SiGe1 may be formed on upper and lower portions of each of at least the lower and upper channel layers l_ch and u_ch, and the second sacrificial layer SiGe2 may be formed between the first sacrificial layers SiGe1 present between at least the lower and upper channel layers l_ch and u_ch.

[0121] The complementary transistor device 52 may further include a silicon oxide layer s12. The silicon oxide layer s12 may be formed between the lower source / drain region n_S / D and the upper source / drain region p_S / D to contact the upper surface of the lower source / drain region n_S / D and the lower surface of the upper source / drain region p_S / D. The silicon oxide layer s12 may be configured to insulate the lower source / drain region n_S / D from the upper source / drain region p_S / D.

[0122] A first work function metal WF1 is formed between the lower channel layer l_ch and the lower gate l_mg. A second work function metal WF2 is formed between the upper channel layer u_ch and the upper gate u_mg. The first work function metal WF1 and the second work function metal WF2 have channel characteristics of the lower gate l_mg and the upper gate u_mg, respectively.

[0123] The complementary transistor device 52 may further include an insulator s_de. The insulator s_de may be between the lower gate l_mg and the upper gate u_mg to insulate the lower gate l_mg from the upper gate u_mg.

[0124] Fig.53 is a flow chart illustrating a method of fabricating a complementary transistor device according to one embodiment.

[0125] refer to Fig.53 In operation 5310, a nanosheet stack ns_s including a lower channel layer l_ch, an upper channel layer u_ch, a plurality of first sacrificial layers SiGe1 and second sacrificial layers SiGe2 separating the lower channel layer l_ch from the upper channel layer u_ch may be formed by epitaxial growth. The first sacrificial layers SiGe1 and the second sacrificial layers SiGe2 may have different Ge contents.

[0126] In operation 5320, a portion of each of the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 may be removed by an etching process at a rate according to the Ge content. For example, a portion of each of the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 may be removed as shown in FIG. Fig.17 .

[0127] In operation 5330, an inner spacer is1 may be formed in a space where the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 are partially removed. For example, the inner spacer is1 may be formed as shown in FIG. Fig.18 and Fig.19 In operation 5330, inner spacers is1 may be formed as sidewalls of remaining portions of the first and second sacrificial layers SiGe1 and SiGe2 above and below the upper and lower channel layers u_ch and l_ch.

[0128] In operation 5340, an upper drain / source region n_SD and a lower drain / source region p_SD may be formed. Figure 22 to Figure 28 An upper drain / source region n_SD and a lower drain / source region p_SD are formed as shown.

[0129] In operation 5350, the remaining portions of the first and second sacrificial layers SiGe1 and SiGe2 may be removed. For example, the remaining portions of each of the first and second sacrificial layers SiGe1 and SiGe2 may be removed, such as Fig.34 as shown in .

[0130] In operation 5360, a metal lower gate l_mg and an upper gate u_mg may be formed in the space where the first and second sacrificial layers SiGe1 and SiGe2 are removed. The lower gate l_mg may be formed around the lower channel layer l_ch, and the upper gate u_mg may be formed around the upper channel layer u_ch.

[0131] According to various embodiments disclosed in the present disclosure, an inner spacer may be formed using a sacrificial layer having different Ge contents. In addition, various effects directly or indirectly recognized by the present disclosure may be provided.

[0132] It should be understood that the various embodiments and terms used in this specification are not intended to limit the technical features described herein to specific embodiments, but to cover various modifications, equivalents or substitutes of the embodiments. In the description of the accompanying drawings, similar reference numerals may be used for similar or related components. Unless the context clearly states otherwise, the singular form of the noun corresponding to the project may include one or more of the projects. In this specification, phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C" and "at least one of A, B or C" may each include any one of the projects listed together in the corresponding phrases in the above-mentioned phrases or all possible combinations thereof. The terms "first", "second", "primary" and "secondary" may only be used to distinguish a corresponding component from another corresponding component, and may not limit the corresponding component on the other hand (e.g., importance or order).

[0133] The embodiments described herein will be described with reference to the cross-sectional views, which are idealized schematic views of the present invention. Therefore, the shapes of the exemplary views may be modified by manufacturing techniques and / or tolerances. Therefore, the embodiments of the present invention are not limited to the specific shapes shown in the drawings, and include variations in shapes resulting from manufacturing processes.

[0134] It should be noted that in some optional embodiments, the function / operation described in the flowchart frame of this specification may not be performed in the order described in the flowchart. For example, the two frames shown in succession can actually be performed substantially simultaneously. Optionally, the frame can sometimes be performed in reverse order according to the function / action involved. In addition, the function of a given frame of a flowchart and / or block diagram can be divided into multiple frames, and / or the function of two or more frames of a flowchart and / or block diagram can be integrated at least in part. In addition, without departing from the scope of the technical spirit of the present invention, other frames can be added / inserted between the frames shown, and / or the frame / operation can be omitted.

[0135] Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used with the meaning commonly understood by those skilled in the art to which the present invention belongs. Unless otherwise clearly and specifically defined, terms defined in commonly used dictionaries should be understood not to be ideally or excessively interpreted.

[0136] The terms used herein are for the purpose of describing the embodiments and are not intended to limit this specification. In this specification, unless otherwise specifically stated in the context, the singular includes the plural. In this application, the terms "including", "having", etc. are used to specify the presence of features, numbers, steps, operations, components, elements, or combinations thereof described herein, and they do not exclude the presence or addition of one or more other features, numbers, steps, operations, components, elements, or combinations thereof.

[0137] When a component is referred to as being "coupled," "connected," or "responsive to," or "on" another component, it may be directly coupled, connected, responsive to, or on the other component, or the other component may be interposed therebetween. On the other hand, when a component is "directly coupled," "directly connected," "directly responsive to," or "directly on" another component, there may be no other components intervening therebetween. In this specification, the term "and / or" includes one or more or all combinations of the associated enumerated items. In addition, the symbol " / " (for example, when used in the term "source / drain") will be understood to be the same as the term "and / or."

[0138] The terms "first", "second", etc. can be used to describe various components, but the components are not limited by these terms. These terms are only used to distinguish one component from another component. For example, without departing from the scope of the present invention, a "first component" can be referred to as a "second component".

[0139] As shown in the accompanying drawings, spatially relative terms "below," "under," "down," "above," "on," "on," and the like can be used to easily describe the relationship between one or more elements and another or more elements. In addition to the orientation shown in the accompanying drawings, spatially relative terms should be understood to include terms for different orientations of components when the components are used or operated. For example, when the elements shown in the accompanying drawings are inverted, an element described as being "below or under" another element can be set "above" the other element. Therefore, the exemplary term "below" can include all downward and upward directions. Elements can also be oriented in other directions (e.g., rotated 90 degrees or in other directions), in which case the spatially relative terms can be interpreted based on the orientation.

[0140] In this specification, many different embodiments are disclosed in conjunction with the drawings and the above description. It should be understood that fully describing and illustrating all combinations and sub-combinations of these embodiments may be overly repetitive and confusing. Therefore, it should be interpreted that the detailed description including the drawings is intended to be a complete description of all combinations and sub-combinations of the embodiments described herein and methods and processes for making and using them, and is intended to support claims related to such combinations or sub-combinations.

[0141] The invention disclosed above is considered as an embodiment and should not be interpreted as limiting, and the appended claims should be understood to include modifications, additions and other embodiments according to the spirit of the invention. Therefore, the protection scope of the present invention should be determined to the maximum extent allowed by law through the most comprehensive interpretation of the claims and their equivalents, and should not be limited by the detailed description.

Claims

1. A transistor device, comprising: substrate; a lower transistor located on the substrate and comprising a lower channel layer, a lower gate and a lower source / drain region; an upper transistor located on the lower transistor and comprising an upper channel layer, an upper gate, and an upper source / drain region; as well as an inner spacer located between the lower channel layer and the upper channel layer and configured to insulate the lower transistor from the upper transistor, Some sidewalls of the inner spacer are formed to be thicker than sidewalls of the lower gate and the upper gate formed above and below the lower channel layer and the upper channel layer.

2. The transistor device according to claim 1, wherein: The inner spacer is formed by removing a portion of each of first and second sacrificial layers formed above and below the lower and upper channel layers and having Ge contents different from each other to a depth according to the Ge content and then depositing an insulating material.

3. The transistor device of claim 2, wherein: The first sacrificial layer is a SiGe layer having a Ge content of 10% to 30%; and The second sacrificial layer is a SiGe layer having a Ge content at least 20% greater than the Ge content of the first sacrificial layer.

4. The transistor device according to claim 2, wherein: The inner spacer is formed by etching the second sacrificial layer deeper than the first sacrificial layer through cavity etching with high selectivity to the upper channel layer and the lower channel layer at a rate corresponding to the Ge content, and depositing the insulating material on the outer sides of the first sacrificial layer and the second sacrificial layer remaining after the cavity etching.

5. The transistor device of claim 2, wherein: the first sacrificial layer is formed on at least an upper portion and a lower portion of each of the lower channel layer and the upper channel layer; and The second sacrificial layer is formed between the first sacrificial layers, wherein the first sacrificial layer is between at least the lower channel layer and the upper channel layer.

6. The transistor device of claim 1, further comprising: A silicon oxide layer (s12), which is formed between the lower source / drain region and the upper source / drain region to contact the upper surface of the lower source / drain region and the lower surface of the upper source / drain region, and is configured to insulate the lower source / drain region from the upper source / drain region.

7. The transistor device of claim 1, wherein: A first work function metal is formed between the lower channel layer and the lower gate; A second work function metal is formed between the upper channel layer and the upper gate; and The first work function metal and the second work function metal have channel characteristics of the lower gate and the upper gate, respectively.

8. The transistor device of claim 7, further comprising: An insulator (s_de) is configured to insulate the lower gate from the upper gate between the lower gate and the upper gate.

9. The transistor device of claim 2, wherein: The inner spacer is formed to contact at least some side surfaces of each of the first sacrificial layer and the second sacrificial layer between the lower channel layer and the upper channel layer; as well as The lower gate and the upper gate are formed around the lower channel layer and the upper channel layer at a space remaining by removing the first sacrificial layer and the second sacrificial layer.

10. A method for manufacturing a transistor device, comprising: forming a nanosheet stack, wherein the nanosheet stack includes a lower channel layer, an upper channel layer, and at least one of a first sacrificial layer and a plurality of second sacrificial layers separating the lower channel layer from the upper channel layer, wherein the first sacrificial layer and the second sacrificial layer have different Ge contents; forming an inner spacer in a space provided by removing a portion of the first sacrificial layer and a portion of the second sacrificial layer at a rate according to a Ge content through an etching process; and A lower gate is formed around the lower channel layer and an upper gate is formed around the upper channel layer in a provided space from which a remaining portion of each of the first sacrificial layer and the second sacrificial layer is removed.

11. The method according to claim 10, wherein: Forming the inner spacer comprises: forming the nanosheet stack such that the first sacrificial layer is included between the lower channel layer and the upper channel layer, and the plurality of second sacrificial layers are included between the first sacrificial layers; etching a portion of each of the first sacrificial layer and the second sacrificial layer at an etching rate according to the Ge content, wherein sidewalls of the plurality of second sacrificial layers are etched deeper than sidewalls of the first sacrificial layer; and The inner spacer is formed by depositing an insulating material on a sidewall of each of the first sacrificial layer and the second sacrificial layer.

12. The method according to claim 10, further comprising: After forming the inner spacer and before forming the gate, a lower source / drain region is formed on a sidewall of the lower channel layer using the substrate below the lower channel layer.

13. The method according to claim 12, further comprising: covering the lower source / drain region with an organic solvent, removing the dummy source / drain region while the dummy source / drain region formed on the sidewall of the upper channel layer is exposed together with the lower source / drain region, and then removing the organic solvent; forming a silicon oxide layer on the outer surface of the nanosheet stack from which the organic solvent has been removed; as well as An upper source / drain region is formed on the sidewall of the upper channel layer on the silicon oxide layer.

14. The method according to claim 13, wherein: Forming the inner spacer includes forming an inner spacer that insulates the lower gate from the lower source / drain region and that insulates the upper gate from the upper source / drain region.

15. The method according to claim 10, further comprising: forming a dummy gate on the outer side of the nanosheet stack; as well as forming an outer spacer by depositing a silicon oxide layer on the side surface of the dummy gate by a thermal oxidation process, The outer spacer forms a sidewall of the dummy gate and the space from which the remaining portions of the first sacrificial layer and the second sacrificial layer are removed.

16. The method according to claim 15, wherein: Removing the remaining portions of the first and second sacrificial layers includes removing the remaining portions of the first and second sacrificial layers by an etching process having a high selectivity to the inner spacers, the outer spacers, the upper channel layer, and the lower channel layer.

17. The method according to claim 15, wherein: Forming a dummy gate on the outer side of the nanosheet stack, comprising: forming a liner layer on the outer side of the nanosheet stack; and The dummy gate is formed on an outer side of the liner layer.

18. The method according to claim 15, further comprising: forming a dummy gate cover on the dummy gate; as well as The dummy gate, the upper channel layer, and the lower channel layer are etched according to a designated channel length using the dummy gate cap as a hard mask.

19. The method according to claim 13, further comprising: At least one metal plug is formed, wherein the at least one metal plug is used to connect each of the lower source / drain region and the upper source / drain region to an external circuit on the outside of the space.

20. A transistor device comprising: substrate; a lower transistor located on the substrate and comprising a lower channel layer, a lower gate and a lower source / drain region; as well as an upper transistor located on the lower transistor and comprising an upper channel layer, an upper gate and an upper source / drain region, Wherein, an insulator (s_de) is formed between the upper end of the lower gate and the lower end of the upper gate, When viewed from one side of the transistor device, the width of at least one of the upper end of the lower gate, the insulator (s_de), and the lower end of the upper gate is formed to be thinner than the remaining width of the lower gate and the upper gate respectively formed below the lower channel layer and above the upper channel layer.

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