Integrated circuit device and manufacturing method thereof

Abstract

The integrated circuit device includes first and second bit circuits adjacent to each other in a row direction, third and fourth bit circuits adjacent to each other in the row direction, and first column output pins arranged in a column direction. The first and second bit circuits include first to fourth power rails and first to sixth active regions extending in the row direction, and the third and fourth bit circuits include fourth power rails, fifth to seventh power rails and seventh to twelfth active regions extending in the row direction. The first column of output pins includes first and second output pins adjacent to the second bit circuit connected to the first and second bit circuits, respectively, and third and first output pins adjacent to the fourth bit circuit connected to the third and fourth bit circuits, respectively. The embodiment of the invention also relates to a method for manufacturing the integrated circuit device.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit devices and methods for manufacturing the same. Background Art

[0002] In many applications, an integrated circuit (IC) includes a logic circuit, processor, computing circuit, or other circuit that processes multiple bits of data simultaneously. Multi-bit circuits include multi-bit flip-flop devices, which include multiple single-bit flip-flops, each of which can store one bit of data, where one of the two states represents "one" and the other represents "zero". This data storage can be used to store states, and such circuits can be described as sequential logic in electronics. D-type flip-flops are widely used as the basic building block of random access memory (RAM) and registers. The D-type flip-flop captures the D input value at a specified edge (i.e., rising or falling) of the clock signal. After the rising / falling edge of the clock signal, the captured value is available at the output (e.g., a signal pin). Summary of the invention

[0003] According to one aspect of an embodiment of the present application, an integrated circuit device is provided, comprising: a first circuit and a second circuit, adjacent to each other in a row direction; a third circuit and a fourth circuit, adjacent to each other in a row direction; and a first column of output pins, aligned in a column direction. The first circuit and the second circuit comprise: a first power rail to a fourth power rail, extending in a row direction; and a first active region to a sixth active region, extending in a row direction. The third circuit and the fourth circuit comprise: a fourth power rail and a fifth power rail to a seventh power rail, extending in a row direction; and a seventh active region to a twelfth active region, extending in a row direction. The first column of output pins comprises: a first output pin and a second output pin, adjacent to the second circuit, and coupled to the corresponding first circuit and second circuit; and a third output pin and a fourth output pin, adjacent to the fourth circuit, and coupled to the corresponding third circuit and fourth circuit.

[0004] According to another aspect of the embodiment of the present application, an integrated circuit device is provided, comprising: a first row, comprising adjacent first and second trigger positions; a second row, comprising adjacent third and fourth trigger positions; and a first column of output pins, vertically aligned with the first and second rows. The first trigger position and the second trigger position comprise a first power rail to a fourth power rail and a first active region to a sixth active region extending along the first row, the third trigger position and the fourth trigger position comprise a fourth power rail, a fifth power rail to a seventh power rail and a seventh active region to a twelfth active region extending along the second row, and the first column of output pins comprises: a first output pin, adjacent to the second trigger position and electrically connected to the first trigger position; a second output pin, adjacent to the second trigger position and electrically connected to the second trigger position; a third output pin, adjacent to the fourth trigger position and electrically connected to the third trigger position; and a fourth output pin, adjacent to the fourth trigger position and electrically connected to the fourth trigger position.

[0005] According to another aspect of an embodiment of the present application, a method for manufacturing an integrated circuit device is provided, the method comprising: constructing a plurality of transistors, the constructing the plurality of transistors comprising: forming a first bit circuit and a second bit circuit comprising a first active region to a sixth active region extending along a row direction; and forming a third bit circuit and a fourth bit circuit comprising a seventh active region to a twelfth active region extending along the row direction. The method also includes: forming a plurality of metal segments, the forming of the plurality of metal segments including: forming a first power rail to a seventh power rail extending in a row direction, wherein the first power rail to the third power rail overlie each of the first bit circuit and the second bit circuit, the fourth power rail overlie each of the first bit circuit to the fourth bit circuit, and the fifth power rail to the seventh power rail overlie each of the third bit circuit and the fourth bit circuit; and forming a first output pin to a fourth output pin aligned in a column direction, the forming of the first output pin to the fourth output pin including: forming a first electrical connection from the first bit circuit to a first output pin adjacent to the second bit circuit; forming a second electrical connection from the second bit circuit to a second output pin adjacent to the second bit circuit; forming a third electrical connection from the third bit circuit to a third output pin adjacent to the fourth bit circuit; and forming a fourth electrical connection from the fourth bit circuit to a fourth output pin adjacent to the fourth bit circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A and Figure 1Bis a plan view of a multi-bit device and layout according to some embodiments, Figure 1C It is a side view.

[0008] Figure 2A and Figure 2B is a plan view of a multi-bit device and layout according to some embodiments, Figure 2C It is a side view.

[0009] Figure 3 is a schematic diagram of a multi-bit flip-flop circuit according to some embodiments.

[0010] Figure 4 is a flow chart of a method of manufacturing an IC device according to some embodiments.

[0011] Figure 5 is a flow chart of a method of generating an IC layout diagram according to some embodiments.

[0012] Figure 6 is a block diagram of an IC layout generation system according to some embodiments.

[0013] Figure 7 is a block diagram of an IC manufacturing system and its related IC manufacturing flow according to some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0016] In various embodiments, an integrated circuit (IC) device and corresponding layout diagrams and fabrication methods include bit circuits arranged in rows adjacent to one or more columns of output pins of corresponding bit circuits. In some embodiments, the IC device includes a multi-bit flip-flop circuit.

[0017] By aligning the output pins in columns and increasing the row height from two times the power rail pitch to three times the power rail pitch, the number of vertical metal segments can be reduced and the number of placement options for the horizontal metal segments can be increased compared to other approaches, such as those that do not align the output pins in columns and have a row height of two times the power rail pitch. The increased number of placement options allows the horizontal metal segments to be spaced farther apart than the metal segments in other approaches, thereby reducing capacitance and reducing power (e.g., reducing the power of one or more clock signals) by about 5% or 6% in some embodiments.

[0018] According to various embodiments, Figure 1A-Figure 1C is a view of a multi-bit IC device and a layout diagram 100, Figure 2A-2C is a view of a multi-bit integrated circuit device and layout schematic 200, Figure 3 is a schematic diagram of a multi-bit flip-flop circuit 300 that can be used as a multi-bit IC device 100 or 200, Figure 4 is a flow chart of a method 400 for manufacturing a multi-bit IC device based on one or more corresponding integrated circuit layout diagrams 100 or 200, and the following reference is made to Figure 7 An IC manufacturing system 700 is discussed.

[0019] For the purpose of illustration, each figure (eg Figure 1A-Figure 2C ) are simplified. These figures are views of IC structures, devices, and layout diagrams, including and excluding various features to facilitate the following discussion. In various embodiments, except Figure 1A-Figure 2C In addition to the features shown in , the IC structure, device and / or layout diagram also includes one or more features corresponding to distribution structures, metal interconnects, contacts, through-holes, gate structures, source / drain (S / D) structures, body connections or other transistor elements, isolation structures, etc.

[0020] In each of the IC device / layout diagrams 100 and 200, reference designators represent IC device components and IC layout features used to at least partially define the corresponding IC device components during the manufacturing process, for example, as shown below with respect to Figure 4 Method 400 discussed below and / or with respect to Figure 7 The IC manufacturing flow is discussed in relation to the IC manufacturing system 700. Thus, each of the IC device / layout diagrams 100 and 200 represents a view of an IC layout diagram 100 or 200 and a corresponding IC device 100 or 200.

[0021] Figure 1A and Figure 1B Depicted are plan views of the X and Y directions of a multi-bit IC device / layout 100 in accordance with some embodiments, along with legends corresponding to the features discussed below. Figure 1A is a high-level description of a multi-bit IC device / layout 100, Figure 1B is a more detailed description of a non-limiting example of a multi-bit IC device / layout 100 . Figure 1C Depicted are X-direction and Z-direction side views of a multi-bit IC device / layout 100 in accordance with some embodiments.

[0022] A multi-bit IC device / layout 100, also referred to in some embodiments as an IC device / layout 100 or IC 100, includes four rows R1-R4 of bit circuits Bit1-Bit8 aligned in the X direction, and a column C1 of output pins Q1-Q8 aligned in the Y direction. Row R1 includes bit circuits Bit1 and Bit2 and output pins Q1 and Q2, row R2 includes bit circuits Bit3 and Bit4 and output pins Q3 and Q4, row R3 includes bit circuits Bit 5 and Bit6 and output pins Q5 and Q6, and row R4 includes bit circuits Bit7 and Bit8 and output pins Q7 and Q8, each discussed below.

[0023] Figure 2A and Figure 2B Depicted is a plan view of a multi-bit IC device / layout 200 , X and Y directions, and legend, in accordance with some embodiments. Figure 2A is a high-level description of a multi-bit IC device / layout 200, Figure 2B is a more detailed description of a non-limiting example of a multi-bit IC device / layout 100 . Figure 2C A multi-bit IC device / layout 200 is depicted along with side views in the X and Z directions in accordance with some embodiments.

[0024] The multi-bit IC device / layout 200, also referred to in some embodiments as IC device / layout 200 or IC 200, includes two rows R1-R2 of bit circuits Bit1-Bit8 aligned in the X direction, a column C1 of output pins Q1-Q4 aligned in the Y direction, and a column C2 of output pins Q5-Q8 aligned in the Y direction. In the IC device 200, the row R1 includes bit circuits Bit1, Bit2, Bit7, and Bit8 and output pins Q1, Q2, Q7, and Q8, and the row R2 includes bit circuits Bit3-Bit6 and output pins Q3-Q6.

[0025] Figure 1A-Figure 2C The number of rows, bit circuits, and output pins shown are non-limiting examples provided for illustration purposes. Figure 1A-Figure 2CIC device / layout diagrams 100 and / or 200 having numbers of rows, bit circuits, and / or output pins other than those shown are within the scope of the present disclosure.

[0026] exist Figure 1A and Figure 2A In the embodiment shown, output pin Q1 is coupled to bit circuit Bit2, output pin Q2 is coupled to bit circuit Bit3, output pin Q3 is coupled to bit circuit Bit4, output pin Q4 is coupled to bit circuit Bit 5, output pin Q5 is coupled to bit circuit Bit 6, output pin Q6 is coupled to bit circuit Bit7, and output pins Q7 and Q8 are coupled to bit circuit Bit8. Figure 1A and Figure 2A Output pin / bit circuit configurations other than those shown are also within the scope of the present disclosure.

[0027] Two or more circuit elements are considered coupled based on one or more direct signal connections and / or one or more indirect signal connections, wherein the indirect signal connection includes one or more logic devices (e.g., inverters or logic gates) between the two or more circuit elements. In some embodiments, the signal communication between the two or more coupled circuit elements can be modified, such as inverted or conditional, by one or more sub-logic devices.

[0028] exist Figure 1A and Figure 2A In the illustrated embodiment, each of the bit circuits Bit2-Bit8 includes an input pin DI (labeled as a single instance for clarity), also referred to as a data input pin DI or a signal input pin DI in some embodiments. Each input pin DI is coupled to a corresponding output pin Q1-Q7 through a vertical metal region / segment M1 and a horizontal metal region / segment M0 (labeled as a single instance for clarity). Figure 1A and Figure 2A Input / output pin configurations other than those shown are also within the scope of the present disclosure.

[0029] like Figure 1B and Figure 2B As shown, each row R1-R4 corresponds to a total of four power rails PR (one instance is labeled for clarity) extending in the X direction and spaced apart by a power rail pitch PRP in the Y direction. Thus, each row R1-R4 corresponds to a triple pitch PRP, with adjacent rows in the rows R1-R4 sharing corresponding instances of the power rail PR.

[0030] like Figure 1B and Figure 2B As shown, instances of metal region / section M0 are positioned according to a total of three first metal tracks (not labeled) extending between adjacent instances of power rail PR.

[0031] like Figure 1Band Figure 2B As shown, columns C1 and, if present, C2 include instances of output pins Q1-Q8 (representative instances are labeled output pins Q), including vertical metal regions / segments. Figure 1B and Figure 2B In the illustrated embodiment, instances of output pin Q overlap and are aligned along a single instance of a gate region / structure (not labeled), and are therefore considered aligned in the Y direction. In some embodiments, instances of output pin Q are positioned in other ways, such as overlying or between adjacent instances of a gate region / structure, and are therefore considered aligned in the Y direction.

[0032] In some embodiments, each metal region / segment M0 and power rail PR is a metal region / segment of a first metal layer (also referred to as a metal zero layer in some embodiments) of a design and manufacturing process for manufacturing the IC device 100 or 200 based on the IC layout diagram 100 or 200, and each input pin DI, output pin Q and metal region / segment M1 is a metal region / segment of a second metal layer (also referred to as a metal first layer in some embodiments), as further discussed below.

[0033] A bit circuit, such as bit circuits Bit1-Bit8, is a logic circuit, latch, flip-flop or other circuit configured to operate on a single data bit by including some or all of a plurality of p-type and n-type transistors (e.g., a plurality of transistors TP) arranged accordingly.

[0034] like Figure 1B and Figure 2B As shown, a plurality of transistors TP include an active area / region AA extending in the X direction (a single instance is labeled for clarity). Each row R1-R4 includes a total of six instances of the active area / region AA.

[0035] In some embodiments, alternating instances of the power rail PR are configured to have either the supply voltage VDD or the supply reference voltage VSS, and adjacent instances of the active area / region AA have corresponding p-type or n-type doping, respectively.

[0036] The plurality of transistors TP also include additional components, for example, Figure 1B and Figure 2B The illustrated illustration includes metal-like definition region / segment MD, gate region / structure PO, dummy gate region / structure CPODE, and via region structures VG and VD, but these features are not labeled for clarity.

[0037] like Figure 1C and Figure 2CAs shown, a plurality of transistors TP are located on a substrate SUB, and a plurality of metal regions / segments MS are located on the plurality of transistors TP. The plurality of metal regions / segments MS include a power rail PR, an input pin DI, and Figure 1C and Figure 2C The metal regions / segments M0 and M1 of the bit circuits Bit1-Bit8 and output pins Q1-Q8 are arranged as shown.

[0038] In some embodiments, the plurality of metal regions / segments MS include instances of metal regions / segments and / or via regions / structures in addition to those discussed above, e.g. Figure 1B and Figure 2B The legend shown in FIG. 4 includes metal regions / segments M2 and via regions / structures VIA0 and VIA1 , which are not labeled for clarity.

[0039] In some embodiments, the plurality of regions / metal sections MS include regions / sections arranged as a plurality of signal paths, such as one or more clock signal paths, according to the arrangement of the plurality of transistors TP.

[0040] An active area / region (e.g., active area / region AA) is an area included in an IC layout diagram during manufacturing as part of a semiconductor substrate (e.g., substrate SUB) defining an active area, also referred to as an oxide diffusion or definition (OD), directly in an n-well or p-well region / region or in an n-well or p-well region / region (not shown for clarity) where one or more IC device components (e.g., S / D structures) are formed. In some embodiments, the active area is an n-type or p-type active region of a planar transistor, a FinFET (fin field effect transistor), or a GAA (all-around gate) transistor. In various embodiments, the active area (structure) includes one or more of a semiconductor material (e.g., silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), etc.), a dopant material (e.g., boron (B), phosphorus (P), arsenic (As), gallium (Ga), or another suitable material).

[0041] In some embodiments, the active region is a region in an IC layout included in the manufacturing process as part of a defined nanosheet structure, e.g., a continuous volume having one or more layers of semiconductor material with n-type or p-type doping. In various embodiments, a single nanosheet layer includes a single layer or multiple layers of a given semiconductor material.

[0042] The S / D region / structure is an area in an IC layout diagram included in the manufacturing process as part of defining the S / D structure, also referred to in some embodiments as a semiconductor structure, which is configured to have a doping type opposite to that of the corresponding active region / region. In some embodiments, the S / D region / structure is configured to have a lower resistivity than an adjacent channel component (e.g., a portion of a corresponding active region / region of a planar FET, a fin structure of a FinFET, or a gate structure of a GAA transistor). In some embodiments, the S / D region / structure includes one or more portions having a doping concentration greater than one or more doping concentrations present in the corresponding channel component. In some embodiments, the S / D region / structure includes an epitaxial region of a semiconductor material, such as Si, SiGe, and / or silicon carbide SiC.

[0043] MD (metal diffusion) regions / segments are conductive areas included in the IC layout diagram during the manufacturing process as part of defining an MD segment in and / or on a semiconductor substrate, also referred to as conductive segments or MD wires or traces. In some embodiments, the MD segment includes a portion of at least one metal layer, such as a contact layer, which covers and contacts the substrate and has a sufficiently small thickness to form an insulating layer between the MD segment and the overlying metal layer (e.g., the first metal layer). In various embodiments, the MD segment includes one or more of copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), other metals, or materials suitable for providing low resistance (i.e., resistance levels below a predetermined threshold, which corresponds to one or more tolerance levels of resistance-based effects on circuit performance) electrical connections between IC structural elements.

[0044] In various embodiments, the MD segment includes a portion of the semiconductor substrate and / or an epitaxial layer, whose doping level is sufficient to make the segment have a low resistance level, for example, based on an implantation process. In various embodiments, the doped MD segment includes a doping concentration of about 1*10 16 / cubic centimeter or more of one or more dopant materials.

[0045] In some embodiments, the manufacturing process includes two MDs, and an MD zone / segment (eg, MD zone / segment MD) refers to two MDs in the manufacturing process.

[0046] A gate region / structure is an area in an IC layout diagram that is included in the manufacturing process as part of defining a gate structure. A gate structure is a volume that includes one or more conductive segments (e.g., a gate electrode) that includes one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials, substantially surrounded by one or more insulating materials, whereby the one or more conductive segments are configured to control a voltage supplied to an adjacent gate dielectric layer.

[0047] The gate dielectric layer is a volume comprising one or more insulating materials suitable for providing high resistance (i.e., a resistance level above a predetermined threshold corresponding to one or more tolerance levels based on the effect of resistance on circuit performance) between IC structure elements, such as silicon dioxide, silicon nitride (Si 3 N 4 ) and / or one or more other suitable materials, such as a low-k material with a k value less than 3.8 or a high-k material with a k value greater than 3.8 or 7.0, such as aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), Tantalum pentoxide (Ta 2 O 5 ) or titanium oxide (TiO 2 ).

[0048] A metal line or region (e.g., a power rail PR, an input pin DI, an output pin Q, or a metal region M0 or M1) is a region in an IC layout diagram included in a manufacturing process as part of defining a metal line structure that includes one or more conductive materials in a given metal layer of the manufacturing process, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials. In various embodiments, the metal region / segment corresponds to the first metal layer of the manufacturing process (also referred to as metal zero layer M0 in some embodiments), or a second or higher level metal layer (e.g., metal layer M1).

[0049] A via region / structure is a region in an IC layout that is included in the manufacturing process as part of defining a via structure that includes one or more conductive materials configured to provide an electrical connection between an overlying conductive structure and an underlying conductive structure.

[0050] Through the above configuration, each of the multi-bit IC devices / layouts 100 and 200 includes bit circuits Bit1-Bit8, which are arranged in rows R1-R4 adjacent to one or more columns C1 / C2 of output pins Q1-Q8 of the bit circuits Bit1-Bit8. By including output pins Q1-Q8 aligned in columns and rows R1-R4 having a height of three times the power rail pitch PRP, the number of vertical metal segments M1 can be reduced and the number of placement options for horizontal metal segments M0 can be increased compared to other approaches (e.g., those that do not have output pins aligned in columns and include a row height of two times the power rail pitch). The increased number of placement options allows the horizontal metal segments M0 of the IC devices / layouts 100 and 200 to be spaced farther apart than the metal segments in other approaches, thereby reducing capacitance and achieving power reduction.

[0051] Figure 3 is a schematic diagram of a multi-bit flip-flop circuit 300 that can be used as the IC layout / device 100 or 200 according to some embodiments. In some embodiments, the multi-bit flip-flop circuit 300 is referred to as a multi-bit flip-flop IC 300, a multi-bit D flip-flop circuit 300, a D flip-flop circuit 300, a flip-flop 300, or a D flip-flop 300.

[0052] Flip-flop 300 includes the above-described non-limiting example of a plurality of transistors TP arranged according to a multi-bit flip-flop circuit, wherein individual transistors are not labeled for clarity.

[0053] The flip-flop 300 includes an inverter (not labeled) configured to receive a selection signal SE and output an inverted selection signal seb, and a pair of inverters (not labeled) configured to receive a clock signal CP and output a pair of complementary clock signals clkb and clkbb.

[0054] The flip-flop 300 also includes a plurality of N unit flip-flop circuits B1-BN, also referred to as bit circuits B1-BN in some embodiments, which can be used as the above-mentioned Figure 1A-Figure 2C The corresponding bit circuits in the bit circuits Bit1-Bit8 discussed.

[0055] Each bit circuit B1-BN includes p-type and n-type transistors, which are configured to receive selection signals SE and seb, clock signals clkb and clkbb, and corresponding input data bits D1-DN, and ... clock signals clkbb and clkbb, respectively, and are configured to receive selection signals SE and Figure 3 The MCU is shown configured to latch corresponding input data bits D1-DN and output corresponding output data bits Q1-QN in response to selection signals SE, seb and clock signals clkbb and clkbb in operation.

[0056] Thus, one of the IC devices / layouts 100 or 200 corresponding to the flip-flop 300 is capable of performing multi-bit operations according to the benefits discussed above with respect to the IC devices / layouts 100 or 200 .

[0057] Figure 4 4 is a flow chart of a method 400 for manufacturing a multi-bit IC device according to some embodiments. The method 400 may be operable to form the Figure 1A-Figure 3 The IC device 100 or 200 is discussed.

[0058] In some embodiments, the operations of method 400 are performed by Figure 4 In some embodiments, the operations of method 400 are performed in the order shown. Figure 4 In some embodiments, one or more additional operations are performed before, during, between, and / or after the operations of method 400.

[0059] In some embodiments, one or more operations of method 400 are a subset of operations of a method of forming an IC and / or IC package including one or more multi-bit IC devices.

[0060] At operation 410, a plurality of transistors including a first row and a second row of bit circuits are constructed on a semiconductor substrate. Constructing a plurality of transistors including a first row and a second row of bit circuits includes constructing a plurality of transistors TP on a substrate SUB, the transistors TP including the transistors described above with respect to Figure 1A-Figure 2C The two or more rows R1-R4 are discussed.

[0061] In some embodiments, constructing a plurality of transistors includes: Figure 3 The flip-flop circuit 300 discussed is arranged with a plurality of transistors.

[0062] Building multiple transistors includes forming one or more structures and / or devices according to the IC design, for example, transistor features, including MD segments and / or S / D structures in the active region of the semiconductor substrate, gate structures on and / or within the active region, and electrical connections between devices.

[0063] Constructing the plurality of transistors includes performing a first plurality of fabrication operations, such as one or more of lithography, diffusion, deposition, etching, planarization, or other operations suitable for constructing resistive, magnetic, or other material layers, dielectric layers, and / or active region gate structures adjacent to the S / D structures and overlying or otherwise proximate to the semiconductor substrate, the gate structures.

[0064] At operation 420, a plurality of metal sections including a column of output pins of the bit circuits are formed adjacent to each of the first and second rows of bit circuits. Forming the plurality of metal sections includes forming the plurality of metal sections on the plurality of transistors.

[0065] Forming a plurality of metal sections including an output pin column of a bit circuit includes forming a plurality of metal sections including a power rail PR, metal sections M0 and M1, an input pin DI, and the above Figure 1A-Figure 2C A plurality of metal segments MS in some or all of the columns C1 and / or C2 of the output pins Q1 -Q8 of the bit circuits Bit1 -Bit8 in question.

[0066] In some embodiments, forming the plurality of metal segments includes forming the plurality of metal segments according to the above description. Figure 3 The flip-flop circuit 300 discussed is formed of a plurality of metal segments.

[0067] In some embodiments, forming the plurality of metal segments includes performing one or more front-end-of-line (FEOL) and / or back-end-of-line (BEOL) operations, including performing a second plurality of manufacturing operations, such as one or more of lithography, diffusion, deposition, etching, planarization, or other operations suitable for constructing metal segments, conductive, resistive or other material layers and / or dielectric layers and covering the plurality of transistors.

[0068] At operation 430, in some embodiments, an electrical connection is formed with an output pin of the bit circuit. Forming the electrical connection includes forming a Figure 1A-Figure 3 The electrical connections of some or all of the output pins Q1-Q8 are discussed.

[0069] In some embodiments, forming the electrical connection includes forming Figure 1A-Figure 3 Some of the multiple metal segments MS discussed.

[0070] Forming the electrical connection includes performing one or more etching and deposition processes, thereby configuring one or more metal lines according to one or more masks. Performing the deposition process includes depositing one or more conductive materials, such as Cu, Ag, W, Ti, Ni, Sn, Al or other metals or suitable materials, such as polysilicon.

[0071] By performing some or all of the operations of method 400, an IC device is manufactured that includes a multi-bit IC device that includes bit circuits arranged in rows adjacent to one or more columns of output pins of corresponding bit circuits, thereby achieving the benefits discussed above with respect to multi-bit IC devices 100 and 200.

[0072] Figure 5 is a flowchart of a method 500 for generating an IC layout diagram according to some embodiments, for example, Figure 1A-Figure 3 One or more of the IC layout diagrams 100 or 200 are discussed.

[0073] In some embodiments, generating the IC layout diagram includes generating an IC device (eg, the IC device described above) manufactured based on the generated IC layout diagram. Figure 1A-Figure 3An IC layout diagram corresponding to the IC device 100 or 200 discussed.

[0074] In some embodiments, some or all of method 500 is performed by a processor of a computer, such as described below with reference to Figure 6 The processor 602 of the IC layout generation system 600 is discussed.

[0075] Some or all of the operations of method 500 can be performed as in a design studio (e.g., as described below with respect to Figure 7 It is performed as part of a design process performed in the design studio 720 discussed above.

[0076] In some embodiments, the operations of method 500 are as follows: Figure 5 In some embodiments, the operations of method 500 are performed simultaneously and / or in a sequential order. Figure 5 In some embodiments, one or more operations of method 500 are performed before, between, during, and / or after one or more operations of method 500 are performed.

[0077] At operation 510, first and second rows of bit circuits are arranged, and at least one column of output pins are arranged adjacent to the first and second rows of bit circuits. Arranging the first and second rows of bit circuits and the at least one column of output pins includes arranging Figure 1A-Figure 2C Output pins Q1-Q8 in two or more rows R1-R4 and some or all of columns C1 and / or C2 are discussed.

[0078] Arranging the first and second rows of bit circuits and at least one column of output pins includes arranging the above Figure 1A-Figure 2C A plurality of transistors TP and a plurality of metal regions MS are discussed.

[0079] In some embodiments, arranging the first and second rows of bit circuits and at least one column of output pins includes: Figure 3 The flip-flop circuit 300 discussed arranges a first row, a second row of bit circuits and at least one column of output pins.

[0080] At operation 520, in some embodiments, electrical connections of some or all output pins of at least one column of output pins are configured in the IC layout. In some embodiments, configuring the electrical connections to some or all output pins includes configuring the electrical connections described above with respect to Figure 1A-Figure 2C One or more metal regions among the plurality of metal regions MS in question.

[0081] In some embodiments, configuring electrical connections to some or all of the output pins is part of arranging an IC device including a multi-bit IC device.

[0082] At operation 530, in some embodiments, an IC layout diagram including a first row and a second row of bit circuits and at least one column of output pins is stored in a storage device. In some embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram in the storage device as described above. Figure 1A-Figure 2C One or more of the IC layouts 100 or 200 discussed are stored in a storage device.

[0083] In various embodiments, storing the IC layout in a storage device includes storing the IC layout in a non-volatile, computer-readable memory or a cell library (e.g., a database), and / or includes storing the IC layout via a network. In some embodiments, storing the IC layout in a storage device includes storing the IC layout in a cell library, in the layout 609, and / or via a network 614 of the IC layout generation system 600 discussed below with respect to FIG. 6 .

[0084] At operation 540, in some embodiments, one or more manufacturing operations are performed based on the IC layout diagram. In some embodiments, performing the one or more manufacturing operations includes performing one or more photolithography exposures based on the IC layout diagram. Figure 4 Combined with the following Figure 7 Performing one or more manufacturing operations, such as one or more photolithography exposures, based on the IC layout is discussed.

[0085] By performing some or all of the operations of method 600, an IC layout diagram corresponding to a multi-bit IC device is generated, which includes bit circuits arranged in rows adjacent to one or more columns of output pins of corresponding bit circuits, thereby achieving the benefits discussed above with respect to multi-bit IC devices 100 and 200.

[0086] Figure 6 is a block diagram of an IC layout generation system 600 according to some embodiments. According to one or more embodiments, the method of designing an IC layout described herein may be implemented, for example, using the IC layout generation system 600 according to some embodiments.

[0087] In some embodiments, IC layout generation system 600 is a general purpose computing device including hardware processor 602 and non-transitory computer readable storage medium 604. Storage medium 604 is encoded with, among other things, computer program code 606, i.e., a set of executable instructions. Execution of instructions 606 by hardware processor 602 (at least in part) represents an electronic design automation (EDA) tool that implements part or all of the method, such as described above with respect to Figure 5 A method 500 for generating an IC layout diagram (hereinafter referred to as the process and / or method) is described.

[0088] The processor 602 is electrically coupled to the computer readable storage medium 604 via a bus 608. The processor 602 is also electrically coupled to an I / O interface 610 via the bus 608. A network interface 612 is also electrically connected to the processor 602 via the bus 608. The network interface 612 is connected to a network 614 so that the processor 602 and the computer readable storage medium 604 can be connected to external elements via the network 614. The processor 602 is configured to execute a computer program code 606 encoded in the computer readable storage medium 604 so that the IC layout diagram generation system 600 can be used to perform part or all of the process and / or method. In one or more embodiments, the processor 602 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0089] In one or more embodiments, the computer-readable storage medium 604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 604 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 604 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0090] In one or more embodiments, the computer-readable storage medium 604 stores computer program code 606 configured to enable the IC layout diagram generation system 600 (where such execution (at least in part) represents an EDA tool) to perform some or all of the processes and / or methods. In one or more embodiments, the computer-readable storage medium 604 also stores information that facilitates the execution of some or all of the processes and / or methods.

[0091] In one or more embodiments, the computer readable storage medium 604 stores an IC layout diagram 607 of an IC layout diagram, including such IC layout diagrams disclosed herein, such as those described above with respect to Figure 1A-Figure 5 IC layouts 100 and 200 are discussed.

[0092] IC layout generation system 600 includes an I / O interface 610. I / O interface 610 is coupled to external circuits. In one or more embodiments, I / O interface 610 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor direction keys for transmitting information and commands to processor 602.

[0093] The IC layout diagram generation system 600 also includes a network interface 612 coupled to the processor 602. The network interface 612 allows the system 600 to communicate with a network 614 to which one or more other computer systems are connected. The network interface 612 includes a wireless network interface such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as Ethernet, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more IC layout diagram generation systems 600.

[0094] The IC layout generation system 600 is configured to receive information through the I / O interface 610. The information received through the I / O interface 610 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 602. The information is transmitted to the processor 602 via the bus 608. The IC layout generation system 600 is configured to receive information related to the UI through the I / O interface 610. The information is stored in the computer readable medium 604 as a user interface (UI) 642.

[0095] In some embodiments, part or all of the processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an add-on software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by the IC layout drawing generation system 600. In some embodiments, the IC layout drawing generation system 600 is implemented using a software application such as that available from CADENCE DESIGN SYSTEMS, INC. or another suitable layout generation tool to generate a layout diagram including standard cells.

[0096] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of an optical disk (such as a DVD), a magnetic disk (such as a hard disk), a semiconductor memory (such as a ROM), a RAM, a memory card, etc.

[0097] Figure 7is a block diagram of an IC manufacturing system 700 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on the IC layout diagram, the manufacturing system 700 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0098] exist Figure 7 , the IC manufacturing system 700 includes entities that interact in the design, development and manufacturing cycles and / or services associated with manufacturing IC devices 760, such as a design room 720, a mask room 730, and an IC manufacturing plant / manufacturer ("Fab") 750. The entities in the system 700 are connected via a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or fewer other entities. In some embodiments, two or more of the design room 720, the mask room 730, and the IC manufacturing plant 750 are owned by a single larger company. In some embodiments, two or more of the design room 720, the mask room 730, and the IC manufacturing plant 750 coexist in a common facility and use common resources.

[0099] The design office (or design team) 720 generates an IC design layout 722. The IC design layout 722 includes various geometric patterns, such as Figure 1A-Figure 6 One or more of the IC layout diagrams 100 or 200 discussed. The geometric pattern corresponds to the pattern of the metal, oxide or semiconductor layers of the various components that constitute the IC device 760 to be manufactured. The layers are combined to form various IC components. For example, a portion of the IC design layout diagram 722 includes various IC components, such as active areas, gate electrodes, source and drain electrodes, metal lines or through holes for interlayer interconnection, and openings for pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design room 720 implements an appropriate design program to form the IC design layout diagram 722. The design process includes one or more of a logical design, a physical design, or a location and a route. The IC design layout diagram 722 is presented in the form of one or more data files with geometric pattern information. For example, the IC design layout diagram 722 can be represented in a GDSII file format or a DFII file format.

[0100] The mask chamber 730 includes data preparation 732 and mask manufacturing 744. The mask chamber 730 uses the IC design layout drawing 722 to manufacture one or more masks 745 for manufacturing various layers of the IC device 760 according to the IC design layout drawing 722. The mask chamber 730 performs mask data preparation 732, wherein the IC design layout drawing 722 is converted into a representative data file (RDF). The mask data preparation 732 provides the RDF to the mask manufacturing 744. The mask manufacturing 744 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 745 or a semiconductor wafer 753. The design layout drawing 722 is manipulated by the mask data preparation 732 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturing plant 750. In Figure 7 , mask data preparation 732 and mask manufacturing 744 are shown as separate elements. In some embodiments, mask data preparation 732 and mask manufacturing 744 may be collectively referred to as mask data preparation.

[0101] In some embodiments, mask data preparation 732 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 722. In some embodiments, mask data preparation 732 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, an inverse lithography technique (ILT) is also used, which treats OPC as an inverse imaging problem.

[0102] In some embodiments, mask data preparation 732 includes a mask rule checker (MRC) that checks the IC design layout 722 that has been processed by OPC using a set of mask creation rules that contain certain geometric and / or connection constraints to ensure that there are sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 722 to compensate for the constraints during mask fabrication 744, which may undo some of the modifications performed by OPC to satisfy the mask creation rules.

[0103] In some embodiments, mask data preparation 732 includes a lithography process check (LPC), which simulates a process to be performed by the IC fabrication plant 750 to fabricate the IC device 760. The LPC simulates the process based on the IC design layout diagram 722 to create a simulated fabricated device, such as the IC device 760. The processing parameters in the LPC simulation may include parameters related to various processes of the IC fabrication cycle, parameters related to the tools used to fabricate the IC, and / or other aspects of the fabrication process. The LPC takes into account various factors, such as spatial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or combinations thereof. In some embodiments, after the LPC creates the simulated fabricated device, if the shape of the simulated device is not close enough to meet the design rules, the OPC and / or MRC are repeated to further refine the IC design layout diagram 722.

[0104] It should be understood that the above description of mask data preparation 732 has been simplified for the sake of clarity. In some embodiments, data preparation 732 includes additional features, such as modifying the logic operations (LOPs) of IC design layout diagram 722 according to manufacturing rules. In addition, the processes applied to IC design layout diagram 722 during data preparation 732 can be performed in a variety of different orders.

[0105] After the mask data preparation 732 and during the mask manufacturing 744, a mask 745 or a set of masks 745 is manufactured based on the modified IC design layout 722. In some embodiments, the mask manufacturing 744 includes performing one or more photolithography exposures based on the IC design layout 722. In some embodiments, based on the modified IC design layout 722, a pattern is formed on the mask (photomask or reticle) 745 using an electron beam (e-beam) or a plurality of electron beams. The mask 745 can be formed using various techniques. In some embodiments, the mask 745 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. The radiation beam used to expose the image sensitive material layer (e.g., photoresist) coated on the wafer, such as an ultraviolet (UV) or EUV beam, is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask version of the mask 745 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque area of ​​the binary mask. In another example, a mask 745 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 745, various features in a pattern formed on the phase shift mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask generated by the mask manufacturing 744 is used for various processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 753, the mask is used in an etching process to form various etching regions in the semiconductor wafer 754, and / or used in other suitable processes.

[0106] IC manufacturing plant 750 is an IC manufacturing enterprise, including one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC manufacturing plant 750 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end of line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end of line (BEOL) manufacturing) for interconnection and packaging of IC products, and a third manufacturing facility can provide other services for the foundry business.

[0107] IC fabrication plant 750 includes wafer fabrication tools 752 configured to perform various fabrication operations on semiconductor wafer 753 to fabricate IC devices 760 based on masks (e.g., mask 745). In various embodiments, fabrication tools 752 include one or more of a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or a LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes described herein.

[0108] IC manufacturing plant 750 uses mask 745 manufactured by mask chamber 730 to manufacture IC device 760. Therefore, IC manufacturing plant 750 at least indirectly uses IC design layout 722 to manufacture IC device 760. In some embodiments, semiconductor wafer 753 is manufactured by IC manufacturing plant 750 using mask 745 to form IC device 760. In some embodiments, IC manufacturing includes performing one or more photolithography exposures based on IC design layout 722 at least indirectly. Semiconductor wafer 753 includes a silicon substrate or other suitable substrate with a material layer formed thereon. Semiconductor wafer 753 also includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0109] In some embodiments, the IC device includes: a first bit circuit and a second bit circuit, adjacent to each other in a row direction; a third bit circuit and a fourth bit circuit, adjacent to each other in the row direction; and a first column of output pins aligned in the column direction, wherein the first bit circuit and the second bit circuit include: a first power rail to a fourth power rail, extending in the row direction; and a first active area to a sixth active area, extending in the row direction, the third bit circuit and the fourth bit circuit include: a fourth power rail and a fifth power rail to a seventh power rail, extending in the row direction; and a seventh active area to a twelfth active area, extending in the row direction, and the first column of output pins includes: a first output pin and a second output pin, adjacent to the second bit circuit and coupled to the corresponding first bit circuit and second bit circuit; and a third output pin and a fourth output pin, adjacent to the fourth bit circuit and coupled to the corresponding third bit circuit and fourth bit circuit. In some embodiments, the first to seventh power rails are located in a first metal layer of the IC device, each of the first to fourth bit circuits further comprises a plurality of metal segments located in the first metal layer, and the metal segments of the plurality of metal segments are positioned according to a total of three first metal rails extending between adjacent power rails of the first to seventh power rails. In some embodiments, each of the first to fourth output pins comprises a metal segment extending in a column direction in a second metal layer of the IC device. In some embodiments, each of the first to fourth bit circuits is coupled to the same clock signal path. In some embodiments, the IC device includes: a fifth bit circuit and a sixth bit circuit, which are adjacent to each other in a row direction; and a seventh bit circuit and an eighth bit circuit, which are adjacent to each other in the row direction, wherein the fifth bit circuit and the sixth bit circuit include: a seventh power rail and an eighth power rail to a tenth power rail, extending in the row direction; and a thirteenth active region to an eighteenth active region, extending in the row direction, the seventh bit circuit and the eighth bit circuit include: a tenth power rail and an eleventh power rail to a thirteenth power rail, extending in the row direction; and a nineteenth active region to a twenty-fourth active region, extending in the row direction, and the first column output pin also includes: a fifth output pin and a sixth output pin, which are adjacent to the sixth bit circuit and coupled to the corresponding fifth bit circuit and sixth bit circuit; and a seventh output pin and an eighth output pin, which are adjacent to the eighth bit circuit and coupled to the corresponding seventh bit circuit and eighth bit circuit.In some embodiments, the IC device includes: a second column output pin, adjacent to the first column output pin; a fifth bit circuit and a sixth bit circuit, adjacent to each other in the row direction; and a seventh bit circuit and an eighth bit circuit, adjacent to each other in the row direction, wherein the fifth bit circuit and the sixth bit circuit include the first power rail to the fourth power rail and the first active area to the sixth active area, the seventh bit circuit and the eighth bit circuit include the fourth power rail to the seventh power rail and the seventh active area to the twelfth active area, and the second column output pin includes: a fifth output pin and a sixth output pin, adjacent to the sixth bit circuit, and coupled to the corresponding fifth bit circuit and the sixth bit circuit; and a seventh output pin and an eighth output pin, adjacent to the eighth bit circuit, and coupled to the corresponding seventh bit circuit and the eighth bit circuit. In some embodiments, the IC device includes a multi-bit flip-flop circuit, and each of the first to fourth bit circuits includes a flip-flop bit circuit. In some embodiments, each of the first to fourth bit circuits includes an input pin.

[0110] In some embodiments, the IC device includes: a first row, including adjacent first and second trigger positions; a second row, including adjacent third and fourth trigger positions; and a first column of output pins, vertically aligned with the first and second rows, wherein the first and second trigger positions include first to fourth power rails and first to sixth active regions extending along the first row, the third and fourth trigger positions include fourth power rails, fifth to seventh power rails, and seventh to twelfth active regions extending along the second row, and the first column of output pins includes: a first output pin, adjacent to the second trigger position and electrically connected to the first trigger position; a second output pin, adjacent to the second trigger position and electrically connected to the second trigger position; a third output pin, adjacent to the fourth trigger position and electrically connected to the third trigger position; and a fourth output pin, adjacent to the fourth trigger position and electrically connected to the fourth trigger position. In some embodiments, the first to seventh power rails are located in a first metal layer of the IC device, each of the first to fourth trigger bits further comprises a plurality of metal segments located in the first metal layer, and the metal segments of the plurality of metal segments are positioned according to a total of three first metal rails extending between adjacent power rails of the first to seventh power rails. In some embodiments, each of the first to fourth output pins comprises a metal segment extending perpendicular to the first row and the second row in a second metal layer of the IC device. In some embodiments, the IC device comprises a paired clock path electrically connected to each of the first to fourth bits. In some embodiments, the IC device includes: a third row, including an adjacent fifth trigger bit and a sixth trigger bit; and a fourth row, including an adjacent seventh trigger bit and an eighth trigger bit, wherein the fifth trigger bit and the sixth trigger bit include a seventh power rail, an eighth power rail to a tenth power rail, and a thirteenth active area to an eighteenth active area extending along the third row, the seventh trigger bit and the eighth trigger bit include a tenth power rail, an eleventh power rail to a thirteenth power rail, and a nineteenth active area to a twenty-fourth active area extending along the fourth row, and the first column of output pins also includes: a fifth output pin, adjacent to the sixth trigger bit and electrically connected to the fifth trigger bit; a sixth output pin, adjacent to the sixth trigger bit and electrically connected to the sixth trigger bit; a seventh output pin, adjacent to the eighth trigger bit and electrically connected to the seventh trigger bit; and an eighth output pin, adjacent to the eighth trigger bit and electrically connected to the eighth trigger bit.In some embodiments, the IC device includes: a second column of output pins adjacent to the first column of output pins, wherein the first row also includes adjacent fifth and sixth trigger bits, the second row also includes adjacent seventh and eighth trigger bits, the fifth and sixth trigger bits include first to fourth power rails and first to sixth active areas, the seventh and eighth trigger bits include fourth to seventh power rails and seventh to twelfth active areas, and the second column of output pins includes: a fifth output pin adjacent to the sixth trigger bit and electrically connected to the fifth trigger bit; a sixth output pin adjacent to the sixth trigger bit and electrically connected to the sixth trigger bit; a seventh output pin adjacent to the eighth trigger bit and electrically connected to the seventh trigger bit; and an eighth output pin adjacent to the eighth trigger bit and electrically connected to the eighth trigger bit. In some embodiments, each of the first to fourth trigger bits includes an input pin.

[0111] In some embodiments, a method for manufacturing an IC device includes: constructing a plurality of transistors, the constructing the plurality of transistors includes: forming a first bit circuit including a first active region to a sixth active region extending in a row direction and a second bit circuit; and forming a third bit circuit and a fourth bit circuit including a seventh active region to a twelfth active region extending in a row direction; and forming a plurality of metal segments, the forming the plurality of metal segments includes: forming a first power rail to a seventh power rail extending in the row direction, wherein the first power rail to the third power rail overlie each of the first bit circuit and the second bit circuit, and the fourth power rail overlie the first bit circuit to the fourth bit circuit. each of the first bit circuits, and the fifth power rail to the seventh power rail overlies each of the third bit circuit and the fourth bit circuit; and forming first output pins to fourth output pins aligned in the column direction, forming the first output pins to the fourth output pins includes: forming a first electrical connection from the first bit circuit to the first output pin adjacent to the second bit circuit; forming a second electrical connection from the second bit circuit to the second output pin adjacent to the second bit circuit; forming a third electrical connection from the third bit circuit to the third output pin adjacent to the fourth bit circuit; and forming a fourth electrical connection from the fourth bit circuit to the fourth output pin adjacent to the fourth bit circuit. In some embodiments, forming the first power rail to the seventh power rail includes forming the first power rail to the seventh power rail in a first metal layer of the IC device, forming a plurality of metal segments also includes forming a plurality of first metal segments in the first metal layer, and a first metal segment of the plurality of first metal segments is positioned according to a total of three first metal tracks extending between adjacent power rails of the first power rail to the seventh power rail. In some embodiments, forming the first output pin to the fourth output pin includes forming the first metal segment to the fourth metal segment in a second metal layer of the IC device.In some embodiments, constructing the plurality of transistors further includes: forming a fifth bit circuit and a sixth bit circuit including a thirteenth active region to an eighteenth active region extending in a row direction; and forming a seventh bit circuit and an eighth bit circuit including a nineteenth active region to a twenty-fourth active region extending in a row direction; and forming the plurality of metal segments further includes: forming an eighth power rail to a thirteenth power rail extending in the row direction, wherein the seventh power rail also overlies each of the fifth bit circuit and the sixth bit circuit, the eighth power rail and the ninth power rail overlie each of the fifth bit circuit and the sixth bit circuit, and the tenth power rail overlies the fifth bit circuit to the eighth bit circuit each of the bit circuits, and the eleventh power rail to the thirteenth power rail overlies each of the seventh bit circuit and the eighth bit circuit; and forming the first output pin to the fourth output pin also includes: forming a fifth output pin and a fifth electrical connection from the fifth bit circuit to a fifth output pin adjacent to the sixth bit circuit; forming a sixth output pin and a sixth electrical connection from the sixth bit circuit to a sixth output pin adjacent to the sixth bit circuit; forming a seventh output pin and a seventh electrical connection from the seventh bit circuit to a seventh output pin adjacent to the eighth bit circuit; and forming an eighth output pin and an eighth electrical connection from the eighth bit circuit to an eighth output pin adjacent to the eighth bit circuit. In some embodiments, constructing the plurality of transistors further includes: forming a fifth bit circuit and a sixth bit circuit including the first active region to the sixth active region; and forming a seventh bit circuit and an eighth bit circuit including the seventh active region to the twelfth active region; and forming the plurality of metal segments further includes: forming a first power rail to a third power rail further overlying each of the fifth bit circuit and the sixth bit circuit, forming a fourth power rail further overlying each of the fifth bit circuit to the eighth bit circuit, and forming a fifth power rail to a seventh power rail further overlying each of the seventh bit circuit and the eighth bit circuit; and forming the first The output pin to the fourth output pin is adjacent to the fifth output pin to the eighth output pin aligned in the column direction, and the formation of the fifth output pin to the eighth output pin includes: forming a fifth electrical connection between the fifth output pin and the fifth output pin adjacent to the sixth circuit; forming a sixth electrical connection between the sixth output pin and the sixth output pin adjacent to the sixth circuit; forming a seventh electrical connection between the seventh output pin and the seventh output pin adjacent to the eighth circuit; and forming an eighth electrical connection between the eighth output pin and the eighth output pin adjacent to the eighth circuit.

[0112] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. An integrated circuit device, comprising: The first bit circuit and the second bit circuit are adjacent to each other along the row direction; A third bit circuit and a fourth bit circuit are adjacent to each other along the row direction; as well as The first column of output pins are aligned along the column direction. in, The first bit circuit and the second bit circuit include: A first power rail to a fourth power rail extending in the row direction; and The first active region to the sixth active region extend in the row direction, The third bit circuit and the fourth bit circuit include: The fourth power rail and the fifth to seventh power rails extend in the row direction; and The seventh active region to the twelfth active region extend in the row direction, and The first column of output pins includes: a first output pin and a second output pin adjacent to the second bit circuit and coupled to the respective first bit circuit and the second bit circuit; and A third output pin and a fourth output pin are adjacent to the fourth bit circuit and are coupled to the third bit circuit and the fourth bit circuit respectively.

2. The integrated circuit device according to claim 1, wherein: The first power rail to the seventh power rail are located in a first metal layer of the integrated circuit device, Each of the first to fourth bit circuits further includes a plurality of metal segments located in the first metal layer, and The metal segments of the plurality of metal segments are positioned according to a total of three first metal rails extending between adjacent power rails of the first to seventh power rails.

3. The integrated circuit device according to claim 1, further comprising: a fifth bit circuit and a sixth bit circuit, adjacent to each other along the row direction; as well as The seventh bit circuit and the eighth bit circuit are adjacent to each other along the row direction, in, The fifth bit circuit and the sixth bit circuit include: The seventh power rail and the eighth to tenth power rails extend in the row direction; and The thirteenth active region to the eighteenth active region extend in the row direction, The seventh bit circuit and the eighth bit circuit include: The tenth power rail and the eleventh to thirteenth power rails extend in the row direction; and The nineteenth active region to the twenty-fourth active region extend in the row direction, and the first column output pins further include: a fifth output pin and a sixth output pin adjacent to the sixth bit circuit and coupled to the corresponding fifth bit circuit and the sixth bit circuit; and A seventh output pin and an eighth output pin are adjacent to the eighth bit circuit and are coupled to the corresponding seventh bit circuit and the eighth bit circuit.

4. The integrated circuit device according to claim 1, further comprising: A second column of output pins, adjacent to the first column of output pins; a fifth bit circuit and a sixth bit circuit, adjacent to each other along the row direction; as well as The seventh bit circuit and the eighth bit circuit are adjacent to each other along the row direction, in, The fifth bit circuit and the sixth bit circuit include the first power rail to the fourth power rail and the first active area to the sixth active area, The seventh bit circuit and the eighth bit circuit include the fourth power rail to the seventh power rail and the seventh active area to the twelfth active area, and The second column of output pins includes: a fifth output pin and a sixth output pin adjacent to the sixth bit circuit and coupled to the corresponding fifth bit circuit and the sixth bit circuit; and A seventh output pin and an eighth output pin are adjacent to the eighth bit circuit and are coupled to the corresponding seventh bit circuit and the eighth bit circuit.

5. An integrated circuit device comprising: A first row, including adjacent first and second trigger bits; a second row, including adjacent third flip-flop bits and fourth flip-flop bits; as well as The first column of output pins is vertically aligned with the first and second rows, in, The first trigger bit and the second trigger bit include first to fourth power rails extending along the first row and first to sixth active regions, The third trigger bit and the fourth trigger bit include the fourth power rail, the fifth power rail to the seventh power rail, and the seventh active area to the twelfth active area extending along the second row, and The first column of output pins includes: a first output pin adjacent to the second trigger bit and electrically connected to the first trigger bit; a second output pin adjacent to and electrically connected to the second trigger bit; a third output pin adjacent to the fourth trigger bit and electrically connected to the third trigger bit; and A fourth output pin is adjacent to the fourth trigger position and electrically connected to the fourth trigger position.

6. The integrated circuit device according to claim 5, wherein: The first power rail to the seventh power rail are located in a first metal layer of the integrated circuit device, Each of the first to fourth trigger bits further includes a plurality of metal segments located in the first metal layer, and Metal segments of the plurality of metal segments are positioned according to a total of three first metal rails extending between adjacent ones of the first to seventh power rails.

7. The integrated circuit device according to claim 5, further comprising: A third row, including adjacent fifth flip-flop bit and sixth flip-flop bit; and The fourth row includes the adjacent seventh and eighth flip-flop bits, in, The fifth trigger bit and the sixth trigger bit include the seventh power rail, the eighth power rail to the tenth power rail, and the thirteenth active area to the eighteenth active area extending along the third row, The seventh trigger bit and the eighth trigger bit include the tenth power rail, the eleventh power rail to the thirteenth power rail, and the nineteenth active region to the twenty-fourth active region extending along the fourth row, and The first column of output pins also includes: a fifth output pin, adjacent to the sixth trigger bit and electrically connected to the fifth trigger bit; a sixth output pin, adjacent to the sixth trigger bit and electrically connected to the sixth trigger bit; a seventh output pin adjacent to the eighth flip-flop bit and electrically connected to the seventh flip-flop bit; and An eighth output pin is adjacent to the eighth trigger bit and electrically connected to the eighth trigger bit.

8. The integrated circuit device according to claim 5, further comprising: The second column of output pins is adjacent to the first column of output pins, in, The first row also includes adjacent fifth and sixth flip-flop bits, The second row also includes adjacent seventh and eighth flip-flop bits, The fifth trigger bit and the sixth trigger bit include the first power rail to the fourth power rail and the first active area to the sixth active area, The seventh trigger bit and the eighth trigger bit include the fourth power rail to the seventh power rail and the seventh active area to the twelfth active area, and The second column of output pins includes: a fifth output pin, adjacent to the sixth trigger bit and electrically connected to the fifth trigger bit; a sixth output pin, adjacent to the sixth trigger bit and electrically connected to the sixth trigger bit; a seventh output pin adjacent to the eighth flip-flop bit and electrically connected to the seventh flip-flop bit; and An eighth output pin is adjacent to the eighth trigger bit and electrically connected to the eighth trigger bit.

9. A method for manufacturing an integrated circuit device, the method comprising: constructing a plurality of transistors, the constructing the plurality of transistors comprising: forming a first bit circuit and a second bit circuit including first to sixth active regions extending in a row direction; and forming a third bit circuit and a fourth bit circuit including a seventh active region to a twelfth active region extending along the row direction; and Forming a plurality of metal segments, the forming the plurality of metal segments comprising: A first power rail to a seventh power rail extending in the row direction are formed, wherein The first power rail to the third power rail overlie each of the first bit circuit and the second bit circuit, The fourth power rail overlies each of the first to fourth bit circuits, and The fifth to seventh power rails overlie each of the third bit circuit and the fourth bit circuit; and Forming first to fourth output pins aligned in a column direction, the forming the first to fourth output pins comprising: forming a first electrical connection from the first bit circuit to the first output pin adjacent to the second bit circuit; forming a second electrical connection from the second bit circuit to the second output pin adjacent to the second bit circuit; forming a third electrical connection from the third bit circuit to the third output pin adjacent to the fourth bit circuit; and A fourth electrical connection is formed from the fourth bit circuit to the fourth output pin adjacent to the fourth bit circuit.

10. The method according to claim 9, wherein: Constructing the plurality of transistors further comprises: forming a fifth bit circuit and a sixth bit circuit including a thirteenth active region to an eighteenth active region extending along the row direction; and forming a seventh bit circuit and an eighth bit circuit including a nineteenth active region to a twenty-fourth active region extending along the row direction; and Forming the plurality of metal segments further comprises: Eighth to thirteenth power rails extending in the row direction are formed, wherein The seventh power rail also overlies each of the fifth bit circuit and the sixth bit circuit, The eighth power rail and the ninth power rail overlie each of the fifth bit circuit and the sixth bit circuit, The tenth power rail overlies each of the fifth to eighth bit circuits, and The eleventh to thirteenth power rails overlie each of the seventh bit circuit and the eighth bit circuit; and Forming the first output pin to the fourth output pin further includes: forming a fifth output pin and a fifth electrical connection from said fifth bit circuit to said fifth output pin adjacent to said sixth bit circuit; forming a sixth output pin and a sixth electrical connection from said sixth bit circuit to said sixth output pin adjacent to said sixth bit circuit; forming a seventh output pin and a seventh electrical connection from said seventh bit circuit to said seventh output pin adjacent to said eighth bit circuit; and An eighth output pin is formed and an eighth electrical connection is formed from the eighth bit circuit to the eighth output foot adjacent to the eighth bit circuit.

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