Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the structure comprises a substrate which comprises an insulating layer and a substrate layer located on the insulating layer, and the substrate layer comprises an active region; the gate structure is located on a part of the active region and comprises a plurality of main gates located on the first region and first auxiliary gates located on the second region, the main gates are connected with the first auxiliary gates, the main gates are parallel to the first direction and are arranged in the second direction, and the first auxiliary gates are parallel to the second direction and are arranged in the second direction; the first direction is perpendicular to the second direction; the source regions and the drain regions are respectively positioned in the first region on two sides of each main grid, each drain region is positioned between the adjacent source regions, and the source regions and the drain regions have a first conduction type; the first body region is located in the second region, the first body region and the main grid are located on the two sides of the first auxiliary grid respectively, the first body region has a second conduction type, the first conduction type is different from the second conduction type, and the ESD structure has the bidirectional ESD protection characteristic while the robustness of the ESD structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Electrostatic discharge (ESD) is one of the most common factors that can damage chips during chip manufacturing and use. GGNMOS (gate grounded NMOS) devices have been widely used as ESD protection devices due to their high robustness and low leakage current, and their application areas are mainly in bulk silicon platforms.

[0003] With the development of silicon on insulator (SOI) technology, the development and application of GGNMOS based on SOI technology needs to be further expanded. At present, GGNMOS based on SOI platform is mainly concentrated in low-voltage devices. Its application scope is limited by its shortcomings such as low unit area robustness and high leakage, which also increases the cost of GGNMOS devices.

[0004] Therefore, the existing GGNMOS devices based on SOI platform need to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed electrostatic discharge protection structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising an insulating layer and a substrate layer located on the insulating layer, the substrate layer comprising an active area, the active area comprising a first area and a second area arranged along a first direction, the first area and the second area being adjacent to each other; a gate structure located on part of the active area, the gate structure comprising a plurality of main gates located on the first area and a first auxiliary gate located on the second area, the plurality of main gates being connected to the first auxiliary gate, the plurality of main gates being parallel to the first direction and arranged along a second direction, the first auxiliary gate being parallel to the second direction, the first direction and the second direction being perpendicular to each other; a source region and a drain region in the first area respectively located on both sides of each main gate, each drain region being located between adjacent source regions, the source region and the drain region having a first conductivity type; a first body region located in the second area, the first body region and the main gate being located on both sides of the first auxiliary gate respectively, the first body region having a second conductivity type, and the first conductivity type being different from the second conductivity type.

[0007] Optionally, it also includes: a conductive structure located on the substrate, the conductive structure including a first conductive layer and a second conductive layer electrically isolated from each other, the first conductive layer electrically connecting the plurality of source regions, the first body region and the gate structure, and the second conductive layer electrically connecting the plurality of drain regions.

[0008] Optionally, it also includes: a blocking layer located on the substrate, the blocking layer covering the surfaces of the several main gates; the blocking layer also extends to the surface of the portion of the source region and the surface of the portion of the drain region adjacent to the several main gates, and the surface of the portion of the first auxiliary gate; a contact layer located on the surface of the source region, the drain region, and the first body region exposed by the blocking layer; the first conductive layer is electrically connected to the several source regions, the first body region and the gate structure through the contact layer; and the second conductive layer is electrically connected to the several drain regions through the contact layer.

[0009] Optionally, the conductive structure further includes a first conductive plug structure and a second conductive plug structure, the first conductive plug structure including a plurality of first sub-plugs electrically connecting the first conductive layer to the source regions, a plurality of second sub-plugs electrically connecting the first conductive layer to the first body region, and a third sub-plug electrically connecting the first conductive layer to the gate structure, and the second conductive plug structure including a plurality of fourth sub-plugs electrically connecting the second conductive layer to the drain regions; the plurality of first sub-plugs are located on the surface of the contact layer on the source regions and are arranged along the first direction; the plurality of second sub-plugs are located on the surface of the contact layer on the first body region and are arranged along the second direction; the plurality of third sub-plugs are located on the surface of the first auxiliary gate and are arranged along the second direction; the plurality of fourth sub-plugs are located on the surface of the contact layer on the drain region and are arranged along the first direction.

[0010] Optionally, the distance between the first sub-plug and the contact layer on the source region is a first size, and the first size ranges from 0.1 microns to 1 microns; the contact layer on the source region has a second size in the second direction, and the second size ranges from less than or equal to 2 microns; the contact layer on the drain region has a third size in the second direction, and the third size ranges from 0.2 microns to 4 microns; the distance between the contact layer on the drain region and the fourth sub-plug is a fourth size, and the fourth size ranges from 0.1 microns to 1 micron; each of the main gates has a fifth size in the second direction, and the fifth size ranges from 0.1 microns to 1 micron; each of the main gates located on the first region has a sixth size in the first direction, and the sixth size ranges from 5 microns to 40 microns; the first auxiliary gate has a seventh size in the first direction, and the seventh size ranges from 0.2 microns to 2 microns; the distance between the second sub-plug and the first auxiliary gate is an eighth size, and the eighth size ranges from 0.1 microns to 1 microns; the contact layer on the drain region has a ninth size from the first auxiliary gate, and the ninth size ranges from less than or equal to 2 microns.

[0011] Optionally, the active area also includes a third area adjacent to the first area, and the third area and the second area are respectively located on both sides of the first area; the gate structure also includes a second auxiliary gate located on the third area, the several main gates are connected to the second auxiliary gates, and the second auxiliary gates are parallel to the second direction; the structure also includes: a second body region located in the third area, the second body region and the main gate are respectively located on both sides of the second auxiliary gate, and the second body region has a second conductivity type; the first conductive layer is also electrically connected to the second body region.

[0012] Optionally, it also includes: a well region located in the first region and the second region; the bottom of the well region is in contact with the insulating layer; the source region, the drain region and the first body region are all located in the well region; the bottom of the source region, the drain region and the first body region are all in contact with the insulating layer.

[0013] Optionally, the substrate layer further includes an isolation structure surrounding the active area; the plurality of main gates further extend to a portion of the isolation structure; and the first auxiliary gate further extends to a portion of the isolation structure.

[0014] Optionally, the material of the insulating layer includes silicon oxide; the material of the substrate layer includes a combination of one or more of silicon, silicon germanium and germanium.

[0015] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising an insulating layer and a substrate layer located on the insulating layer, the substrate layer comprising an active area, the active area comprising a first area and a second area arranged along a first direction, the first area and the second area being adjacent to each other; forming a gate structure on part of the active area, the gate structure comprising a plurality of main gates located on the first area and a first auxiliary gate located on the second area, the plurality of main gates being connected to the first auxiliary gate, the plurality of main gates being parallel to the first direction and arranged along a second direction, the first auxiliary gate being parallel to the second direction, the first direction and the second direction being perpendicular to each other; forming a source region and a drain region in the first area on both sides of each main gate, respectively, each drain region being located between adjacent source regions, the source region and the drain region having a first conductivity type; forming a first body region in the second area, the first body region and the main gate being located on both sides of the first auxiliary gate, respectively, the first body region having a second conductivity type, and the first conductivity type being different from the second conductivity type.

[0016] Optionally, after forming the source region, the drain region and the first body region, the method further includes: forming a conductive structure on the substrate, the conductive structure comprising a first conductive layer and a second conductive layer electrically isolated from each other, the first conductive layer electrically connecting several of the source regions, the first body region and the gate structure, and the second conductive layer electrically connecting the several drain regions.

[0017] Optionally, before forming the conductive structure, it also includes: forming a blocking layer on the substrate, the blocking layer covering the surfaces of the several main gates; the blocking layer also extends to the surface of the portion of the source region and the surface of the portion of the drain region adjacent to the several main gates, and the surface of the portion of the first auxiliary gate; forming a contact layer on the surface of the source region, the drain region and the first body region exposed by the blocking layer; the first conductive layer is electrically connected to the several source regions, the first body region and the gate structure through the contact layer; and the second conductive layer is electrically connected to the several drain regions through the contact layer.

[0018] Optionally, the process for forming the contact layer includes a metal silicide treatment process.

[0019] Optionally, the conductive structure further includes a first conductive plug structure and a second conductive plug structure, the first conductive plug structure including a plurality of first sub-plugs electrically connecting the first conductive layer to the source regions, a plurality of second sub-plugs electrically connecting the first conductive layer to the first body region, and a third sub-plug electrically connecting the first conductive layer to the gate structure, and the second conductive plug structure including a plurality of fourth sub-plugs electrically connecting the second conductive layer to the drain regions; the plurality of first sub-plugs are located on the surface of the contact layer on the source regions and are arranged along the first direction; the plurality of second sub-plugs are located on the surface of the contact layer on the first body region and are arranged along the second direction; the plurality of third sub-plugs are located on the surface of the first auxiliary gate and are arranged along the second direction; the plurality of fourth sub-plugs are located on the surface of the contact layer on the drain region and are arranged along the first direction.

[0020] Optionally, the active area also includes a third area adjacent to the first area, and the third area and the second area are respectively located on both sides of the first area; the gate structure also includes a second auxiliary gate located on the third area, the several main gates are connected to the second auxiliary gates, and the second auxiliary gates are parallel to the second direction; the method also includes: forming a second body region in the third area, the second body region and the main gate are respectively located on both sides of the second auxiliary gate, and the second body region has a second conductivity type; the first conductive layer is also electrically connected to the second body region.

[0021] Optionally, before forming the gate structure, it also includes: forming a well region in the first region and the second region; the bottom of the well region is in contact with the insulating layer; the source region, the drain region and the first body region are all located in the well region; the bottom of the source region, the drain region and the first body region are all in contact with the insulating layer.

[0022] Optionally, the formation process of the well region includes a first ion implantation process; the process parameters of the first ion implantation process include: the implanted ions include N-type or P-type conductive ions, the implantation energy range is 10KeV to 100KeV, and the implantation dose range is 1E12atom / cm 2 To 1E13atom / cm 2 .

[0023] Optionally, the substrate layer further includes an isolation region surrounding the active region; before forming the well region, the method further includes: etching the isolation region to form a groove in the substrate, wherein the groove exposes the insulating layer; and forming an isolation structure in the groove.

[0024] Optionally, the method for forming the groove also includes: after exposing the insulating layer, continuing to etch the insulating layer at the bottom of the groove; the groove has a first depth in the insulating layer, and the groove has a second depth in the substrate layer, and the ratio of the first depth to the second depth ranges from 5% to 30%.

[0025] Optionally, the process for forming the source region and the drain region includes a second ion implantation process; the process parameters of the second ion implantation process include: the doped ions include N-type or P-type conductive ions, the implantation energy ranges from 5KeV to 100KeV, and the implantation dose ranges from 1E15atom / cm 2 To 9E15atom / cm 2 .

[0026] Optionally, the formation process of the first body region includes a third ion implantation process; the process parameters of the third ion implantation process include: the doping ions include N-type or P-type conductive ions, the implantation energy range is 5KeV to 100KeV, and the implantation dose range is 1E15atom / cm 2 To 9E15atom / cm 2 .

[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0028] In the semiconductor structure provided by the technical solution of the present invention, the gate structure located on part of the active area, the gate structure includes a plurality of main gates located on the first area and a first auxiliary gate located on the second area, the plurality of main gates are connected to the first auxiliary gate, the source region and the drain region in the first area are respectively located on both sides of each main gate, the first body region is located in the second area, the first body region and the main gate are respectively located on both sides of the first auxiliary gate, the plurality of source regions, the first body region and the gate structure are electrically connected as the cathode end, and the plurality of drain regions are electrically connected as the anode end, which can play a positive ESD protection role. In order to provide a protective effect, the first body region is grounded, so that when the ESD structure is turned on, the charges accumulated in the body can be discharged in time, and the adverse effects of the floating body effect can be weakened, thereby helping to increase the turn-on voltage of the ESD structure, reduce device leakage, reduce static power consumption, improve discharge capacity, improve thermal effect and other performance, and increase the robustness of the ESD structure; in addition, due to the existence of the first auxiliary gate, a parasitic diode structure exists between the first body region and the drain region. Since the first body region is grounded, the structure can be temporarily turned on when a negative signal comes from the drain region end, thereby discharging the ESD current, thereby having a bidirectional ESD protection characteristic.

[0029] Furthermore, the device performance can be precisely adjusted to meet different requirements by adjusting one or more parameters in the first dimension to the ninth dimension.

[0030] Furthermore, the gate structure also includes a second auxiliary gate located on the third region, and the plurality of main gates are connected to the second auxiliary gate to form a second body region in the third region. The second body region is grounded to further overcome the influence of the floating body effect and increase the robustness of the ESD structure.

[0031] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a gate structure is formed on part of the active area, the gate structure includes a plurality of main gates located on the first area and a first auxiliary gate located on the second area, the plurality of main gates are connected to the first auxiliary gate, a source region and a drain region are formed in the first area on both sides of each main gate, a first body region is formed in the second area, the first body region and the main gate are respectively located on both sides of the first auxiliary gate, the plurality of source regions, the first body region and the gate structure are electrically connected as a cathode terminal, and the plurality of drain regions are electrically connected as an anode terminal, which can be used to In order to achieve the forward ESD protection effect, the first body region is grounded, so that when the ESD structure is turned on, the charges accumulated in the body can be discharged in time, and the adverse effects of the floating body effect can be weakened, thereby helping to increase the turn-on voltage of the ESD structure, reduce device leakage, reduce static power consumption, improve discharge capacity, improve thermal effect and other performance; in addition, due to the existence of the first auxiliary gate, a parasitic diode structure exists between the first body region and the drain region. Since the first body region is grounded, the structure can be temporarily turned on when a negative signal comes from the drain region end, thereby discharging the ESD current, thereby having a bidirectional ESD protection characteristic.

[0032] Furthermore, the device performance can be precisely adjusted to meet different requirements by adjusting one or more parameters in the first dimension to the ninth dimension.

[0033] Furthermore, the gate structure also includes a second auxiliary gate located on the third region, the several main gates are connected to the second auxiliary gate, and the third region has a second body region, and the second body region is grounded to further overcome the influence of the floating body effect and increase the robustness of the ESD structure; in addition, in addition to the parasitic diode structure between the first body region and the drain region, there is also a parasitic diode structure between the second body region and the drain region, so that the device has better negative protection characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 and Figure 2 It is a schematic diagram of the structure of an electrostatic discharge protection structure;

[0035] Figures 3 to 17 is a schematic structural diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention;

[0036] Figures 18 to 32 It is a structural schematic diagram of each step in a method for forming a semiconductor structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0037] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0038] As described in the background art, the performance of the existing electrostatic discharge protection structure needs to be improved. Now, an existing electrostatic discharge protection structure is described and analyzed.

[0039] Figure 1 and Figure 2 It is a structural schematic diagram of an electrostatic discharge protection structure.

[0040] Please refer to Figure 1 and Figure 2 , Figure 1 This is a top view of the structure. Figure 2 for Figure 1 The cross-sectional structure schematic diagram along the CC1 direction in FIG. 1 , the electrostatic discharge protection structure comprises: a substrate, the substrate comprises an oxide layer 100, an active area (not shown in the figure) located on the oxide layer 100 and an isolation structure layer 102, the isolation structure layer 102 is also located between adjacent active areas, the active area has a P-type well area 101, and the bottom of the well area 101 is in contact with the oxide layer 100; a gate 103 located on the substrate; an N-type source area 104 and a drain area 105 in the well area 101 located on both sides of the gate 103, the bottoms of the source area 104 and the drain area 105 are in contact with the oxide layer 100, the source area 104 and the gate 103 are electrically connected to each other, and are led out as a cathode terminal (cathode), and the lead-out of the drain area 105 is used as an anode terminal (anode).

[0041] The above GGNMOS structure is used in a SOI-based process, the source region 103 and the gate 102 are grounded, and the drain region 104 is electrically connected to the input / output terminal of the protected circuit, which can play a role in electrostatic discharge protection for the integrated circuit.

[0042] However, the GGNMOS structure based on the SOI process has no body contact, that is, it is impossible to lead out the body current by forming a P+ doped region in the well region 101. Therefore, there will be a floating body effect. Figure 2As shown in the dotted line, when a positive signal comes from the anode end (drain end), a certain amount of positive charge will accumulate in the channel due to the hot carrier effect, thereby increasing the body potential. When the body potential rises to about 0.7V, the parasitic PN junction between the body end and the source end opens, further turning on the channel parasitic BJT, and finally turning on the GGNMOS prematurely, resulting in the GGNMOS trigger voltage being too low, reducing the GGNMOS operating window. In addition, due to the floating body effect, the GGNMOS leakage is high, increasing the static power consumption.

[0043] In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming the same, wherein a gate structure is located on part of the active area, wherein the gate structure includes a plurality of main gates located on the first area and a first auxiliary gate located on the second area, wherein the plurality of main gates are connected to the first auxiliary gate, and a source region and a drain region are located in the first area on both sides of each main gate, respectively, and a first body region is located in the second area, wherein the first body region and the main gate are located on both sides of the first auxiliary gate, respectively, and the plurality of source regions, the first body region and the gate structure are electrically connected as cathode terminals, and the plurality of drain regions are electrically connected as anode terminals, which can play a positive role. In order to realize the ESD protection function in the direction, the first body region is grounded, so that when the ESD structure is turned on, the charges accumulated in the body can be discharged in time, and the adverse effects of the floating body effect can be weakened, thereby helping to increase the turn-on voltage of the ESD structure, reduce device leakage, reduce static power consumption, improve discharge capacity, improve thermal effect and other performance, and increase the robustness of the ESD structure; in addition, due to the existence of the first auxiliary gate, there is a parasitic diode structure between the first body region and the drain region. Since the first body region is grounded, the structure can be temporarily turned on when a negative signal comes from the drain region end, thereby playing a role in discharging the ESD current, thereby having a bidirectional ESD protection characteristic.

[0044] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] Figures 3 to 17 It is a structural schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0046] Please refer to Figure 3 and Figure 4 , Figure 3 This is a top view of the structure. Figure 4 for Figure 3A schematic diagram of the cross-sectional structure along the MM1 direction is provided, wherein a substrate is provided, the substrate comprises an insulating layer 200 and a substrate layer 201 located on the insulating layer 200, the substrate layer 201 comprises an active area, the active area comprises a first area I and a second area II arranged along a first direction X, the first area I and the second area II are adjacent.

[0047] Subsequently, a gate structure is formed on a portion of the active area.

[0048] In this embodiment, before forming the gate structure, a well region 202 is formed in the first region I and the second region II; the bottom of the well region 202 is in contact with the insulating layer 200 .

[0049] In this embodiment, the formation process of the well region 202 includes a first ion implantation process.

[0050] The process parameters of the first ion implantation process include: the implanted ions include N-type or P-type conductive ions, the implantation energy range is 10KeV to 100KeV, and the implantation dose range is 1E12atom / cm 2 to 1E13atom / cm 2 In this embodiment, the implanted ions are P-type conductive ions.

[0051] In this embodiment, the method for forming the well region 202 includes: forming a first mask layer (not shown) on a portion of the substrate, the first mask layer exposing the active region; and injecting first doping ions into the substrate using the first mask layer as a mask.

[0052] In this embodiment, the substrate layer 201 also includes an isolation region (not shown in the figure) surrounding the active region; before forming the well region 202, it also includes: etching the isolation region to form a groove in the substrate (not shown in the figure), the groove exposing the insulating layer 200; and forming an isolation structure 203 in the groove.

[0053] In the process of forming the groove, a certain degree of over-etching can be selected to ensure isolation between different devices and avoid latching effect. Specifically, the method for forming the groove also includes: after exposing the insulating layer 200, continuing to etch the insulating layer 200 at the bottom of the groove; the groove has a first depth in the insulating layer 200, and the groove has a second depth in the substrate layer 201, and the ratio of the first depth to the second depth ranges from 5% to 30%. Here, the ratio of the first depth to the second depth is used to measure the degree of over-etching. In this embodiment, the ratio of the first depth to the second depth is 20%.

[0054] In this embodiment, during the formation of the well region 202, the first mask layer also exposes a portion of the isolation structure 203 adjacent to the active region (see Figure 3 The area indicated by the dotted line A in the middle) is used to avoid problems such as ion implantation position alignment accuracy to improve the process window.

[0055] In this embodiment, the material of the insulating layer 200 includes silicon oxide.

[0056] The material of the substrate layer 201 includes one or more of silicon, silicon germanium and germanium. In this embodiment, the material of the substrate layer 201 includes silicon.

[0057] Please refer to Figures 5 to 7 , Figure 5 This is a top view of the structure. Figure 6 for Figure 5 Schematic diagram of the cross-sectional structure along the MM1 direction, Figure 7 for Figure 5 Schematic diagram of the cross-sectional structure along the NN1 direction, a gate structure is formed on part of the active area, the gate structure includes a plurality of main gates 204 located on the first area I and a first auxiliary gate 205 located on the second area II, the plurality of main gates 204 are connected to the first auxiliary gate 205, the plurality of main gates 204 are parallel to the first direction X and arranged along the second direction Y, the first auxiliary gate 205 is parallel to the second direction Y, and the first direction X and the second direction Y are perpendicular to each other.

[0058] In this embodiment, the main gates 204 also extend onto a portion of the isolation structure 203; the first auxiliary gate 205 also extends onto a portion of the isolation structure 203. The main gates 204 and the first auxiliary gate 205 on the active region are effective devices, and the purpose of forming the main gates 204 and the first auxiliary gate 205 on the isolation structure 203 is to improve the process window, for example, to avoid poor size control due to alignment accuracy during etching.

[0059] It should be noted that the number of the main gates 204 can be one or more, which can be adjusted according to actual needs.

[0060] Please refer to Figures 8 to 10 , Figure 8 This is a top view of the structure. Fig. 9 for Figure 8 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.10 for Figure 8In the schematic diagram of the cross-sectional structure along the NN1 direction, a source region 206 and a drain region 207 are respectively formed in the first region I on both sides of each main gate 204, each drain region 207 is located between adjacent source regions 206, and the source region 206 and the drain region 207 have a first conductivity type; a first body region 208 is formed in the second region II, the first body region 208 and the main gate 204 are respectively located on both sides of the first auxiliary gate 205, the first body region 208 has a second conductivity type, and the first conductivity type is different from the second conductivity type.

[0061] In this embodiment, the source region 206 , the drain region 207 and the first body region 208 are all located in the well region 202 .

[0062] In this embodiment, the bottoms of the source region 206 , the drain region 207 , and the first body region 208 are all in contact with the insulating layer 200 .

[0063] In this embodiment, the process of forming the source region 206 and the drain region 207 includes a second ion implantation process.

[0064] The process parameters of the second ion implantation process include: doping ions include N-type or P-type conductive ions, implantation energy ranges from 5KeV to 100KeV, and implantation dose ranges from 1E15atom / cm 2 To 9E15atom / cm 2 In this embodiment, the doping ions in the source region 206 and the drain region 207 are N-type conductive ions.

[0065] The method for forming the source region 206 and the drain region 207 includes: forming a second mask layer (not shown) on a portion of the substrate, the second mask layer exposing the first region I; and injecting second doping ions into the first region I using the second mask layer as a mask.

[0066] In this embodiment, the second mask layer also exposes a portion of the isolation structure 203 and a portion of the first auxiliary gate 205 adjacent to the first region I (eg, Figure 8 The purpose of this process is to improve the process window.

[0067] In this embodiment, the formation process of the first body region 208 includes a third ion implantation process.

[0068] The process parameters of the third ion implantation process include: doping ions include N-type or P-type conductive ions, implantation energy range is 5KeV to 100KeV, and implantation dose range is 1E15atom / cm 2 To 9E15atom / cm 2In this embodiment, the doping ions in the first body region 208 are P-type conductive ions.

[0069] The method for forming the first body region 208 includes: forming a third mask layer (not shown in the figure) on a portion of the substrate, the third mask layer covering the first region and exposing the second region II on one side of the first auxiliary gate 205; using the second mask layer as a mask, injecting second doping ions into the second region II.

[0070] In this embodiment, the third mask layer further exposes a portion of the first auxiliary gate 205 and a portion of the isolation structure 203 adjacent to the second region II (eg, Figure 8 The region indicated by the dotted line C in the middle region is used to improve the process window and avoid the occurrence of abnormal implantation of doping ions in the first body region 208 into the source region 206 and the drain region 207.

[0071] In this embodiment, the source region 206 and the drain region 207 are formed first, and then the first body region 208 is formed. However, it should be noted that the order of forming the source region 206 (the drain region 207) and the first body region 208 is not limited.

[0072] In this embodiment, after forming the source region 206, the drain region 207 and the first body region 208, a conductive structure is further formed on the substrate, the conductive structure comprising a first conductive layer and a second conductive layer electrically isolated from each other, the first conductive layer electrically connecting the source regions 206, the first body region 208 and the gate structure, and the second conductive layer electrically connecting the drain regions 207. Specifically, before forming the conductive structure, please refer to Figures 11 to 13 .

[0073] Please refer to Figures 11 to 13 , Fig.11 This is a top view of the structure. Fig.12 for Fig.11 Schematic diagram of the cross-sectional structure along the MM1 direction (the barrier layer is omitted), Fig.13 for Fig.11 A schematic diagram of the cross-sectional structure along the NN1 direction (the barrier layer is omitted), a barrier layer 209 is formed on the substrate, and the barrier layer 209 covers the surfaces of the several main gates 204; a contact layer 210 is formed on the surfaces of the source region 206, the drain region 207 and the first body region 208 exposed by the barrier layer 209.

[0074] In this embodiment, the formation process of the contact layer 210 includes a metal silicide treatment process. The contact layer 210 is used to reduce contact resistance; the material of the contact layer 210 includes a metal silicide material.

[0075] The blocking layer 209 is used to prevent metal silicide from being formed on the surfaces of the main gates 204 .

[0076] In this embodiment, the barrier layer 209 also extends to the surface of the part of the source region 206 and the surface of the part of the drain region 207 adjacent to the main gates 204, and the surface of the part of the first auxiliary gate 205; the size of the barrier layer 209 on the first auxiliary gate 205 is greater than or equal to 0.03 microns and less than or equal to the width of the first auxiliary gate 205. The width refers to the size of the first auxiliary gate 205 in the first direction X.

[0077] In this embodiment, the barrier layer 209 is in a “U” shape. In another embodiment, the barrier layer may be in a “II” shape, that is, parallel to the first direction and arranged along the second direction.

[0078] Specifically, in the second direction Y, the first auxiliary gate 205 includes a plurality of lead-out regions (not shown in the figure) and a plurality of main regions (not shown in the figure), each of the lead-out regions is adjacent to the source region 206, and each main region is located between two adjacent lead-out regions, and each main region also includes an adjacent region (not shown in the figure) adjacent to the drain region 207; the barrier layer 209 covers the surface of the adjacent region, and extends to a portion of the surface of the drain region 207 and a portion of the surface of the source region 206 adjacent to the first auxiliary gate 205, and exposes each of the lead-out regions. The lead-out region is used to define the position of the subsequent third sub-plug, and the first conductive layer is electrically connected to the gate structure through the third sub-plug.

[0079] More specifically, the contact layer 210 is also located on the surface of each lead-out region to reduce the contact resistance between the third sub-plug and the gate structure.

[0080] Please refer to Figures 14 to 17 , Fig.14 This is a top view of the structure. Fig.15 for Fig.14 On the basis of the conductive structure, a top view schematic diagram is added. Fig.16 for Fig.15 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.17 for Fig.15 The cross-sectional structure schematic diagram along the NN1 direction in the figure shows a conductive structure formed on the substrate, wherein the conductive structure includes a first conductive layer 211 and a second conductive layer 212 electrically isolated from each other, wherein the first conductive layer 211 electrically connects the plurality of source regions 206, the first body region 208 and the gate structure, and the second conductive layer 212 electrically connects the plurality of drain regions 207.

[0081] Here, the plurality of source regions 206, the first body region 208 and the gate structure are electrically connected as a cathode terminal (cathode), and the plurality of drain regions 207 are electrically connected as an anode terminal (anode), which can play a positive ESD protection role. The first body region 208 is grounded, and when the ESD structure is turned on, the charges accumulated in the body can be discharged in time to weaken the adverse effects of the floating body effect, thereby helping to increase the turn-on voltage of the ESD structure, reduce device leakage, reduce static power consumption, improve discharge capacity, improve thermal effect and other performance; in addition, due to the existence of the first auxiliary gate 205, a parasitic diode structure exists between the first body region 208 and the drain region 207. Since the first body region 208 is grounded, the structure can be temporarily turned on when a negative signal comes from the drain region 207 end, thereby playing a role in discharging ESD current, thereby having a bidirectional ESD protection characteristic.

[0082] Next, we will use the TLP (Transmission Line Pulse) test data to explain, including:

[0083] Test the ESD performance of the above structure under positive signal: Figure 1 and Figure 2 Compared with the traditional ESD structure shown in the figure, the leakage of the above structure is reduced by about 4 orders of magnitude, Vt1 (turn-on voltage) is increased by more than 1V, It2 (secondary breakdown current) per unit area is increased by about 50%, and the performance of the device is significantly improved.

[0084] The ESD performance of the above structure under negative signal was tested: It2 (secondary breakdown current) per unit area reached 1.9mA / um.

[0085] In summary, the above structure improves the forward protection characteristics while also having excellent reverse performance.

[0086] It should be noted here that for the sake of convenience, Fig.16 and Fig.17 The conductive structure is not shown, only the electrical connection relationship is shown.

[0087] Specifically, the first conductive layer 211 is electrically connected to the plurality of source regions 206 , the first body region 208 and the gate structure through the contact layer 210 ; the second conductive layer 212 is electrically connected to the plurality of drain regions 207 through the contact layer 210 .

[0088] In this embodiment, the conductive structure further includes a first conductive plug structure and a second conductive plug structure, the first conductive plug structure includes a plurality of first sub-plugs 213 electrically connecting the first conductive layer 211 to the source regions 206, a plurality of second sub-plugs 214 electrically connecting the first conductive layer 211 to the first body region 208, and a third sub-plug 215 electrically connecting the first conductive layer 211 to the gate structure, and the second conductive plug structure includes a plurality of fourth sub-plugs 216 electrically connecting the second conductive layer 212 to the drain regions 207.

[0089] Specifically, the plurality of first sub-plugs 213 are located on the surface of the contact layer 210 on the source region 206 and are arranged along the first direction X; the plurality of second sub-plugs 214 are located on the surface of the contact layer 210 on the first body region 208 and are arranged along the second direction Y; the plurality of third sub-plugs 215 are located on the surface of the first auxiliary gate 205 and are arranged along the second direction Y; the plurality of fourth sub-plugs 216 are located on the surface of the contact layer 210 on the drain region 207 and are arranged along the first direction X.

[0090] In this embodiment, before forming the conductive structure, an interlayer dielectric layer (not shown in the figure) is further formed on the substrate, and the conductive structure is located in the interlayer dielectric layer.

[0091] The method for forming the conductive structure includes a Damascene process or a dual Damascene process. In this embodiment, the method for forming the conductive structure includes a Damascene process, that is, first forming the first conductive plug structure and the second conductive plug structure, and then forming the first conductive layer 211 and the second conductive layer 212. In another embodiment, the conductive structure may also be formed by a dual Damascene process.

[0092] In this embodiment, the device performance can be accurately adjusted by adjusting various size parameters of the device, and the specific size parameter settings are described as follows.

[0093] Please continue to refer to Fig.14, including: the distance between the first sub-plug 213 and the contact layer 210 on the source region 206 is a first size W1, and the first size W1 ranges from 0.1 microns to 1 micron; the contact layer 210 on the source region 206 has a second size W2 in the second direction Y, and the second size W2 ranges from less than or equal to 2 microns; the contact layer 210 on the drain region 207 has a third size W3 in the second direction Y, and the third size W3 ranges from 0.2 microns to 4 microns; the distance between the contact layer 210 on the drain region 207 and the fourth sub-plug 216 is a fourth size W4, and the fourth size W4 ranges from 0.1 microns to 1 micron; each of the main gates 204 is at the first The first auxiliary gate 205 has a seventh dimension W7 in the first direction X, and the seventh dimension W7 ranges from 0.2 microns to 2 microns; the distance between the second sub-plug 214 and the first auxiliary gate 205 is an eighth dimension W8, and the eighth dimension W8 ranges from 0.1 microns to 1 micron; the contact layer 210 on the drain region 207 has a ninth dimension W9 from the first auxiliary gate 205, and the ninth dimension W9 ranges from less than or equal to 2 microns.

[0094] The device performance can be precisely adjusted by adjusting one or more parameters in the first size W1 to the ninth size W9 to meet different requirements, including:

[0095] Forward characteristics of the device: increasing one or more of W1, W3 and W4 can increase It2; increasing W2 can increase Vt1 and Vt2; increasing W5 can reduce leakage and increase Vt2; increasing W6 is beneficial to reducing It2 per unit area.

[0096] For the reverse characteristics of the device: increasing W7 is beneficial to increasing Vt2; increasing W8 is beneficial to increasing It2.

[0097] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 8 , Figures 14 to 17, comprising: a substrate, the substrate comprising an insulating layer 200 and a substrate layer 201 located on the insulating layer 200, the substrate layer 201 comprising an active region, the active region comprising a first region I and a second region II arranged along a first direction X, the first region I and the second region II being adjacent; a gate structure located on part of the active region, the gate structure comprising a plurality of main gates 204 located on the first region I and a first auxiliary gate 205 located on the second region II, the plurality of main gates 204 being connected to the first auxiliary gate 205, the plurality of main gates 204 being parallel to the first direction X and arranged along a second direction Y , the first auxiliary gate 205 is parallel to the second direction Y, and the first direction X and the second direction Y are perpendicular to each other; the source region 206 and the drain region 207 in the first region I are respectively located on both sides of each main gate 204, each drain region 207 is located between adjacent source regions 206, and the source region 206 and the drain region 207 have a first conductivity type; the first body region 208 is located in the second region II, the first body region 208 and the main gate 204 are respectively located on both sides of the first auxiliary gate 205, the first body region 208 has a second conductivity type, and the first conductivity type is different from the second conductivity type.

[0098] Here, the plurality of source regions 206, the first body region 208 and the gate structure are electrically connected as a cathode terminal (cathode), and the plurality of drain regions 207 are electrically connected as an anode terminal (anode), which can play a positive ESD protection role. The first body region 208 is grounded, so that when the ESD structure is turned on, the charges accumulated in the body can be discharged in time, and the adverse effects of the floating body effect can be weakened, thereby helping to increase the turn-on voltage of the ESD structure, reduce device leakage, reduce static power consumption, improve discharge capacity, improve thermal effects and other performance, and increase the robustness of the ESD structure; in addition, due to the existence of the first auxiliary gate 205, a parasitic diode structure exists between the first body region 208 and the drain region 207. Since the first body region 208 is grounded, the structure can be temporarily turned on when a negative signal comes from the drain region 207 end, thereby playing a role in discharging ESD current, thereby having a bidirectional ESD protection characteristic.

[0099] In this embodiment, the semiconductor structure also includes: a conductive structure located on the substrate, the conductive structure including a first conductive layer 211 and a second conductive layer 212 electrically isolated from each other, the first conductive layer 211 electrically connecting the plurality of source regions 206, the first body region 208 and the gate structure, and the second conductive layer 212 electrically connecting the plurality of drain regions 207.

[0100] In this embodiment, the semiconductor structure also includes: a barrier layer 209 located on the substrate, the barrier layer 209 covers the surfaces of the several main gates 204; the barrier layer also extends to the surfaces of the portions of the source region 206 and the drain region 207 adjacent to the several main gates 204, as well as the surfaces of the portions of the first auxiliary gate 205; a contact layer 210 located on the surfaces of the source region 206, the drain region 207, and the first body region 208 exposed by the barrier layer 209; the first conductive layer 211 is electrically connected to the several source regions 206, the first body region 208 and the gate structure through the contact layer 210; and the second conductive layer 212 is electrically connected to the several drain regions 207 through the contact layer 210.

[0101] In this embodiment, the barrier layer 209 also extends to the surface of the part of the source region 206 and the surface of the part of the drain region 207 adjacent to the main gates 204, and the surface of the part of the first auxiliary gate 205; the size of the barrier layer 209 on the first auxiliary gate 205 is greater than or equal to 0.03 microns and less than or equal to the width of the first auxiliary gate 205. The width refers to the size of the first auxiliary gate 205 in the first direction X.

[0102] In this embodiment, the barrier layer 209 is in a “U” shape. In another embodiment, the barrier layer is in a “II” shape, that is, parallel to the first direction and arranged along the second direction.

[0103] Specifically, in the second direction Y, the first auxiliary gate 205 includes a plurality of lead-out regions (not shown in the figure) and a plurality of main regions (not shown in the figure), each of the lead-out regions is adjacent to the source region 206, and each main region is located between two adjacent lead-out regions, and each main region also includes an adjacent region (not shown in the figure) adjacent to the drain region 207; the barrier layer 209 covers the surface of the adjacent region, and extends to a portion of the surface of the drain region 207 and a portion of the surface of the source region 206 adjacent to the first auxiliary gate 205, and exposes each of the lead-out regions. The lead-out region is used to define the position of the third sub-plug, and the first conductive layer is electrically connected to the gate structure through the third sub-plug. More specifically, the contact layer 210 is also located on the surface of each of the lead-out regions, and is used to reduce the contact resistance between the third sub-plug and the gate structure.

[0104] In this embodiment, the conductive structure further includes a first conductive plug structure and a second conductive plug structure, the first conductive plug structure including a plurality of first sub-plugs 213 electrically connecting the first conductive layer 211 to the source regions 206, a plurality of second conductive plugs 214 electrically connecting the first conductive layer 211 to the first body regions 208, and a third sub-plug 215 electrically connecting the first conductive layer 211 to the gate structure, and the second conductive plug structure including a plurality of fourth sub-plugs 216 electrically connecting the second conductive layer 212 to the drain regions 207.

[0105] Specifically, the plurality of first sub-plugs 213 are located on the surface of the contact layer 210 on the source region 206 and are arranged along the first direction X; the plurality of second sub-plugs 214 are located on the surface of the contact layer 210 on the first body region 208 and are arranged along the second direction Y; the plurality of third sub-plugs 215 are located on the surface of the first auxiliary gate 205 and are arranged along the second direction Y; the plurality of fourth sub-plugs 216 are located on the surface of the contact layer 210 on the drain region 207 and are arranged along the first direction X.

[0106] In this embodiment, the distance between the first sub-plug 213 and the contact layer 210 on the source region 206 is a first size, and the first size ranges from 0.1 microns to 1 micron; the contact layer 210 on the source region 206 has a second size in the second direction Y, and the second size ranges from less than or equal to 2 microns; the contact layer 210 on the drain region 207 has a third size in the second direction, and the third size ranges from 0.2 microns to 4 microns; the distance between the contact layer 210 on the drain region 207 and the fourth sub-plug 216 is a fourth size, and the fourth size ranges from 0.1 microns to 1 micron; each of the main gates 204 has a second size in the second direction Y, and the second size ranges from less than or equal to 2 microns; The second direction Y has a fifth dimension, and the fifth dimension ranges from 0.1 micron to 1 micron; each of the main gates 204 located on the first region I has a sixth dimension in the first direction X, and the sixth dimension ranges from 5 microns to 40 microns; the first auxiliary gate 205 has a seventh dimension in the first direction X, and the seventh dimension ranges from 0.2 microns to 2 microns; the distance between the second sub-plug 214 and the first auxiliary gate 205 is an eighth dimension, and the eighth dimension ranges from 0.1 microns to 1 micron; the contact layer 210 on the drain region 207 has a ninth dimension from the first auxiliary gate 205, and the ninth dimension ranges from less than or equal to 2 microns. The device performance can be precisely adjusted by adjusting one or more parameters from the first dimension W1 to the ninth dimension W9 to meet different requirements.

[0107] In this embodiment, the conductive structure further includes: a well region 202 located in the first region I and the second region II; and the bottom of the well region 202 is in contact with the insulating layer 200 .

[0108] In this embodiment, the source region 206 , the drain region 207 and the first body region 208 are all located in the well region 202 .

[0109] In this embodiment, the bottoms of the source region 206 , the drain region 207 , and the first body region 208 are all in contact with the insulating layer 200 .

[0110] In this embodiment, the substrate layer 201 further includes an isolation structure 203 surrounding the active area.

[0111] In this embodiment, the plurality of main gates 204 further extend onto a portion of the isolation structure 203 ; the first auxiliary gate 205 further extends onto a portion of the isolation structure 203 .

[0112] In this embodiment, the material of the insulating layer 200 includes silicon oxide.

[0113] The material of the substrate layer 201 includes one or more of silicon, silicon germanium and germanium. In this embodiment, the material of the substrate layer 201 includes silicon.

[0114] Figures 18 to 32 It is a structural schematic diagram of each step in a method for forming a semiconductor structure according to another embodiment of the present invention.

[0115] In the previous embodiment, a first auxiliary gate and a first body region are added at one end of the main gate, and the first body region is used to overcome the influence of the floating body effect. However, especially when the length of the main gate (reference Fig.15 When the sixth dimension W6 in the embodiment is large (e.g., greater than 20 microns), the other end away from the first auxiliary gate may still be affected by the floating body effect. For this reason, in this embodiment, a second auxiliary gate and a second body region are also added at the other end of the main gate, and the second body region is grounded to further overcome the influence of the floating body effect and increase the robustness of the ESD structure.

[0116] Please refer to Fig.18 and Fig.19 , Fig.18 This is a top view of the structure. Fig.19 for Fig.18 A schematic diagram of the cross-sectional structure along the EE1 direction is provided, wherein a substrate is provided, the substrate comprises an insulating layer 300 and a substrate layer 301 located on the insulating layer 300, the substrate layer 301 comprises an active area, the active area comprises a first area i and a second area ii arranged along a first direction X, the first area i and the second area ii are adjacent.

[0117] In this embodiment, the active region further includes a third region iii adjacent to the first region i, and the third region iii and the second region ii are respectively located on two sides of the first region i.

[0118] Subsequently, a gate structure is formed on a portion of the active area.

[0119] In this embodiment, before forming the gate structure, a well region 302 is formed in the first region i, the second region ii and the third region iii; the bottom of the well region 302 is in contact with the insulating layer 300 .

[0120] In this embodiment, the substrate layer 301 also includes an isolation region (not shown in the figure) surrounding the active region; before forming the well region 302, it also includes: etching the isolation region to form a groove in the substrate (not shown in the figure), the groove exposing the insulating layer 300; and forming an isolation structure 303 in the groove.

[0121] Please refer to Figure 20 to Figure 22 , Fig. 20 This is a top view of the structure. Fig.21 for Fig. 20 Schematic diagram of the cross-sectional structure along the EE1 direction, Fig. 22 for Fig. 20 , a schematic diagram of a cross-sectional structure along the FF1 direction, wherein a gate structure is formed on part of the active area, the gate structure comprising a plurality of main gates 304 located on the first area i and a first auxiliary gate 305 located on the second area ii, the plurality of main gates 304 are connected to the first auxiliary gate 305, the plurality of main gates 304 are parallel to the first direction X and arranged along the second direction Y, the first auxiliary gate 305 is parallel to the second direction Y, and the first direction X and the second direction Y are perpendicular to each other.

[0122] In this embodiment, the gate structure further includes a second auxiliary gate 306 located on the third region iii. The plurality of main gates 304 are connected to the second auxiliary gate 306 . The second auxiliary gate 306 is parallel to the second direction Y.

[0123] In this embodiment, the plurality of main gates 304 further extend onto a portion of the isolation structure 303 ; the first auxiliary gate 305 further extends onto a portion of the isolation structure 303 ; and the second auxiliary gate 306 further extends onto a portion of the isolation structure 303 .

[0124] Please refer to Figure 23 to Figure 25 , Fig.23 This is a top view of the structure. Fig.24 for Fig.23 Schematic diagram of the cross-sectional structure along the EE1 direction, Fig.25 for Fig.24 In the schematic diagram of the cross-sectional structure along the FF1 direction, a source region 307 and a drain region 308 are respectively formed in the first region i on both sides of each main gate 304, each drain region 308 is located between adjacent source regions 307, and the source region 307 and the drain region 308 have a first conductivity type; a first body region 309 is formed in the second region ii, the first body region 309 and the main gate 304 are respectively located on both sides of the first auxiliary gate 305, the first body region 309 has a second conductivity type, and the first conductivity type is different from the second conductivity type.

[0125] In this embodiment, a second body region 310 is further formed in the third region iii. The second body region 310 and the main gate 304 are respectively located on both sides of the second auxiliary gate 306. The second body region 310 has a second conductivity type.

[0126] In this embodiment, the source region 307 , the drain region 308 , the first body region 309 , and the second body region 310 are all located in the well region 202 .

[0127] In this embodiment, the bottoms of the source region 307 , the drain region 308 , the first body region 309 , and the second body region 310 are all in contact with the insulating layer 200 .

[0128] In this embodiment, after forming the source region 307, the drain region 308, the first body region 309 and the second body region 310, a conductive structure is further formed on the substrate, the conductive structure comprising a first conductive layer and a second conductive layer electrically isolated from each other, the first conductive layer electrically connecting the source regions 307, the first body region 309, the second body region 310 and the gate structure, and the second conductive layer electrically connecting the drain regions 308. Specifically, before forming the conductive structure, please refer to Figure 26 to Figure 28 .

[0129] Please refer to Figure 26 to Figure 28 , Fig.11 This is a top view of the structure. Fig.12 for Fig.11 Schematic diagram of the cross-sectional structure along the MM1 direction (the barrier layer is omitted), Fig.13 for Fig.11 In the schematic diagram of the cross-sectional structure along the NN1 direction (the barrier layer is omitted), a barrier layer 311 is formed on the substrate, and the barrier layer 311 covers the surfaces of the several main gates 304; a contact layer 312 is formed on the surfaces of the source region 307, the drain region 308 and the first body region 309 exposed by the barrier layer 311.

[0130] In this embodiment, the blocking layer 311 also extends to a portion of the surface of the source region 307 adjacent to the plurality of main gates 304 , a portion of the surface of the drain region 308 , a portion of the surface of the first auxiliary gate 305 , and a portion of the surface of the second auxiliary gate 306 .

[0131] Specifically, in the second direction Y, the first auxiliary gate 305 includes a plurality of first lead-out regions (not shown in the figure) and a plurality of first main regions (not shown in the figure), each of the first lead-out regions is adjacent to the source region 307, and each of the first main regions is located between adjacent first lead-out regions, and each of the first main regions also includes a first adjacent region (not shown in the figure) adjacent to the drain region 308; the barrier layer 311 covers the surface of the first adjacent region, and extends to a portion of the surface of the drain region 308 and a portion of the surface of the source region 307 adjacent to the first auxiliary gate 305, and exposes each of the first lead-out regions. region; in the second direction Y, the second auxiliary gate 306 includes a plurality of second lead-out regions (not shown in the figure) and a plurality of second main regions (not shown in the figure), each of the second lead-out regions is adjacent to the source region 307, and each of the second main regions is located between adjacent second lead-out regions, and each of the second main regions also includes a second adjacent region (not shown in the figure) adjacent to the drain region 308; the barrier layer 311 covers the surface of the second adjacent region, and extends to a portion of the surface of the drain region 308 and a portion of the surface of the source region 307 adjacent to the second auxiliary gate 306, and exposes each of the second lead-out regions. The first lead-out region is used to define the position of the subsequent third sub-plug, and the second lead-out region is used to define the position of the subsequent fifth sub-plug, and the first conductive layer is electrically connected to the gate structure through the third sub-plug and the fifth sub-plug.

[0132] More specifically, the contact layer 312 is also located on the surface of each of the first lead-out regions and each of the second lead-out regions, so as to reduce the contact resistance between the third sub-plug and the gate structure, and between the fifth sub-plug and the gate structure.

[0133] Please refer to Figure 29 to Figure 32 , Fig.29 This is a top view of the structure. Fig.30 for Fig.29 On the basis of the conductive structure, a top view schematic diagram is added. Fig.31 for Fig.30 Schematic diagram of the cross-sectional structure along the EE1 direction, Fig.32 for Fig.30The cross-sectional structure schematic diagram along the FF1 direction in the figure, a conductive structure is formed on the substrate, the conductive structure includes a first conductive layer 313 and a second conductive layer 314 electrically isolated from each other, the first conductive layer 313 electrically connects the several source regions 307, the first body region 309 and the gate structure, and the second conductive layer 314 is electrically connected to the several drain regions 308.

[0134] In this embodiment, the first conductive layer 313 is also electrically connected to the second body region 310 .

[0135] When the above structure is used as a forward ESD, the first conductive layer 313 is used as the lead-out of the cathode terminal (cathode), and the second conductive layer 314 is used as the lead-out of the anode terminal (anode). Relative to the previous embodiment, a second auxiliary gate 306 and a second body region 310 are added to the other end of the main gate 304, and the second body region 310 is grounded to further overcome the influence of the floating body effect and increase the robustness of the ESD structure. Specifically, in the TLP test, compared with the structure of the previous embodiment, the It2 per unit area of ​​the structure of this embodiment is increased by about 5 times, and the performance of the device is significantly improved.

[0136] In addition, in addition to the parasitic diode structure between the first body region 309 and the drain region 308 , there is also a parasitic diode structure between the second body region 310 and the drain region 308 , so that the device has better negative protection characteristics.

[0137] It should be noted here that for the sake of convenience, Fig.31 and Fig.32 The conductive structure is not shown, only the electrical connection relationship is shown.

[0138] Specifically, the first conductive layer 313 is electrically connected to the plurality of source regions 307 , the first body region 309 , the gate structure and the second body region 310 through the contact layer 312 ; the second conductive layer 314 is electrically connected to the plurality of drain regions 308 through the contact layer 312 .

[0139] In this embodiment, the conductive structure further includes a first conductive plug structure and a second conductive plug structure, the first conductive plug structure including a plurality of first sub-plugs 315 electrically connecting the first conductive layer 313 to the source regions 307, a plurality of second sub-plugs 316 electrically connecting the first conductive layer 313 to the first body region 309, a third sub-plug 317 electrically connecting the first conductive layer 313 to the first auxiliary gate 305, a fifth sub-plug 318 electrically connecting the first conductive layer 313 to the second auxiliary gate 306, and a sixth sub-plug 319 electrically connecting the first conductive layer 313 to the second body region 310, and the second conductive plug structure including a plurality of fourth sub-plugs 320 electrically connecting the second conductive layer 314 to the drain regions 308.

[0140] Specifically, the plurality of first sub-plugs 315 are located on the surface of the contact layer 312 on the source region 307 and are arranged along the first direction X; the plurality of second sub-plugs 316 are located on the surface of the contact layer 312 on the first body region 309 and are arranged along the second direction Y; the plurality of third sub-plugs 317 are located on the first auxiliary gate 305 (such as Fig.23 The plurality of fourth sub-plugs 320 are located on the surface of the contact layer 312 on the drain region 308 and are arranged along the first direction X; the plurality of fifth sub-plugs 318 are located on the second auxiliary gate 306 (as shown in FIG. Fig.23 as shown) surface, and are arranged along the second direction Y; the plurality of sixth sub-plugs 319 are located on the surface of the contact layer 312 on the second body region 310, and are arranged along the second direction Y.

[0141] In this embodiment, the device performance can be accurately adjusted by adjusting various size parameters of the device. For specific size parameter settings, please refer to the previous embodiment and will not be described in detail here.

[0142] Correspondingly, another embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 29 to Figure 32 .

[0143] The main difference between this embodiment and the previous embodiment is that, based on the previous embodiment, the semiconductor structure of this embodiment further includes:

[0144] The active area also includes a third area iii adjacent to the first area i, and the third area iii and the second area ii are respectively located on both sides of the first area i; the gate structure also includes a second auxiliary gate 306 located on the third area iii, the plurality of main gates 304 are connected to the second auxiliary gate 306, and the second auxiliary gate 306 is parallel to the second direction Y; a second body area 310 located in the third area iii, the second body area 310 and the main gate 304 are respectively located on both sides of the second auxiliary gate 306, and the second body area 310 has a second conductivity type; the first conductive layer 313 is also electrically connected to the second body area 310.

[0145] For other parts of the structure described in this embodiment, please refer to the previous embodiment and will not be described in detail here.

[0146] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, It is characterized in that include: A substrate, the substrate comprising an insulating layer and a substrate layer located on the insulating layer, the substrate layer comprising an active region, the active region comprising a first region and a second region arranged along a first direction, the first region and the second region being adjacent; a gate structure located on part of the active area, the gate structure comprising a plurality of main gates located on the first area and a first auxiliary gate located on the second area, the plurality of main gates being connected to the first auxiliary gate, the plurality of main gates being parallel to the first direction and arranged along a second direction, the first auxiliary gate being parallel to the second direction, and the first direction and the second direction being perpendicular to each other; A source region and a drain region in the first region respectively located on both sides of each main gate, each drain region is located between adjacent source regions, and the source region and the drain region have a first conductivity type; A first body region is located in the second region, the first body region and the main gate are respectively located on both sides of the first auxiliary gate, the first body region has a second conductivity type, and the first conductivity type is different from the second conductivity type.

2. The semiconductor structure according to claim 1, It is characterized in that Also includes: A conductive structure is located on the substrate, the conductive structure includes a first conductive layer and a second conductive layer electrically isolated from each other, the first conductive layer electrically connects the plurality of source regions, the first body region and the gate structure, and the second conductive layer is electrically connected to the plurality of drain regions.

3. The semiconductor structure according to claim 2, It is characterized in that Also includes: a barrier layer located on the substrate, the barrier layer covering the surfaces of the plurality of main gates; the barrier layer also extending to the surfaces of the portions of the source regions and the drain regions adjacent to the plurality of main gates, and the surfaces of the portions of the first auxiliary gates; a contact layer located on the surfaces of the source regions, the drain regions, and the first body regions exposed by the barrier layer; The first conductive layer is electrically connected to the plurality of source regions, the first body region and the gate structure through the contact layer; and the second conductive layer is electrically connected to the plurality of drain regions through the contact layer.

4. The semiconductor structure according to claim 3, It is characterized in that The conductive structure also includes a first conductive plug structure and a second conductive plug structure, the first conductive plug structure includes a plurality of first sub-plugs electrically connecting the first conductive layer to the source regions, a plurality of second sub-plugs electrically connecting the first conductive layer to the first body region, and a third sub-plug electrically connecting the first conductive layer to the gate structure, and the second conductive plug structure includes a plurality of fourth sub-plugs electrically connecting the second conductive layer to the drain regions; the plurality of first sub-plugs are located on the surface of the contact layer on the source region and are arranged along the first direction; the plurality of second sub-plugs are located on the surface of the contact layer on the first body region and are arranged along the second direction; the plurality of third sub-plugs are located on the surface of the first auxiliary gate and are arranged along the second direction; the plurality of fourth sub-plugs are located on the surface of the contact layer on the drain region and are arranged along the first direction.

5. The semiconductor structure according to claim 4, It is characterized in that The distance between the first sub-plug and the contact layer on the source region is a first size, and the first size ranges from 0.1 microns to 1 microns; the contact layer on the source region has a second size in the second direction, and the second size ranges from less than or equal to 2 microns; the contact layer on the drain region has a third size in the second direction, and the third size ranges from 0.2 microns to 4 microns; the distance between the contact layer on the drain region and the fourth sub-plug is a fourth size, and the fourth size ranges from 0.1 microns to 1 micron; each of the main gates has a fifth size in the second direction, and the fifth size ranges from 0.1 microns to 1 micron; each of the main gates located on the first region has a sixth size in the first direction, and the sixth size ranges from 5 microns to 40 microns; the first auxiliary gate has a seventh size in the first direction, and the seventh size ranges from 0.2 microns to 2 microns; the distance between the second sub-plug and the first auxiliary gate is an eighth size, and the eighth size ranges from 0.1 microns to 1 micron; the contact layer on the drain region has a ninth size from the first auxiliary gate, and the ninth size ranges from less than or equal to 2 microns.

6. The semiconductor structure according to claim 2, It is characterized in that The active area also includes a third area adjacent to the first area, and the third area and the second area are respectively located on both sides of the first area; the gate structure also includes a second auxiliary gate located on the third area, the plurality of main gates are connected to the second auxiliary gates, and the second auxiliary gates are parallel to the second direction; the structure also includes: a second body area located in the third area, the second body area and the main gate are respectively located on both sides of the second auxiliary gate, and the second body area has a second conductivity type; the first conductive layer is also electrically connected to the second body area.

7. The semiconductor structure according to claim 1, It is characterized in that It also includes: a well region located in the first region and the second region; the bottom of the well region is in contact with the insulating layer; the source region, the drain region and the first body region are all located in the well region; the bottom of the source region, the drain region and the first body region are all in contact with the insulating layer.

8. The semiconductor structure according to claim 1, It is characterized in that The substrate layer also includes an isolation structure surrounding the active area; the plurality of main gates also extend onto a portion of the isolation structure; and the first auxiliary gate also extends onto a portion of the isolation structure.

9. The semiconductor structure according to claim 1, It is characterized in that The material of the insulating layer includes silicon oxide; the material of the substrate layer includes one or more of silicon, silicon germanium and germanium.

10. A method for forming a semiconductor structure, It is characterized in that include: Providing a substrate, the substrate comprising an insulating layer and a substrate layer located on the insulating layer, the substrate layer comprising an active region, the active region comprising a first region and a second region arranged along a first direction, the first region and the second region being adjacent to each other; forming a gate structure on part of the active area, the gate structure comprising a plurality of main gates located on the first area and a first auxiliary gate located on the second area, the plurality of main gates being connected to the first auxiliary gate, the plurality of main gates being parallel to the first direction and arranged along a second direction, the first auxiliary gate being parallel to the second direction, and the first direction and the second direction being perpendicular to each other; Forming a source region and a drain region in the first region on both sides of each main gate respectively, each drain region is located between adjacent source regions, and the source region and the drain region have a first conductivity type; A first body region is formed in the second region. The first body region and the main gate are respectively located on both sides of the first auxiliary gate. The first body region has a second conductivity type, which is different from the second conductivity type.

11. The method for forming a semiconductor structure according to claim 10, It is characterized in that After forming the source region, the drain region and the first body region, the method further includes: forming a conductive structure on the substrate, the conductive structure including a first conductive layer and a second conductive layer electrically isolated from each other, the first conductive layer electrically connecting several of the source regions, the first body region and the gate structure, and the second conductive layer electrically connecting the several drain regions.

12. The method for forming a semiconductor structure according to claim 11, It is characterized in that Before forming the conductive structure, it also includes: forming a barrier layer on the substrate, the barrier layer covering the surfaces of the several main gates; the barrier layer also extends to the surface of the part of the source region and the part of the drain region adjacent to the several main gates, and the surface of the part of the first auxiliary gate; forming a contact layer on the surface of the source region, the drain region and the first body region exposed by the barrier layer; the first conductive layer is electrically connected to the several source regions, the first body region and the gate structure through the contact layer; the second conductive layer is electrically connected to the several drain regions through the contact layer.

13. The method for forming a semiconductor structure according to claim 12, It is characterized in that The contact layer formation process includes a metal silicide treatment process.

14. The method for forming a semiconductor structure according to claim 12, It is characterized in that The conductive structure also includes a first conductive plug structure and a second conductive plug structure, the first conductive plug structure includes a plurality of first sub-plugs electrically connecting the first conductive layer to the source regions, a plurality of second sub-plugs electrically connecting the first conductive layer to the first body region, and a third sub-plug electrically connecting the first conductive layer to the gate structure, and the second conductive plug structure includes a plurality of fourth sub-plugs electrically connecting the second conductive layer to the drain regions; the plurality of first sub-plugs are located on the surface of the contact layer on the source region and are arranged along the first direction; the plurality of second sub-plugs are located on the surface of the contact layer on the first body region and are arranged along the second direction; the plurality of third sub-plugs are located on the surface of the first auxiliary gate and are arranged along the second direction; the plurality of fourth sub-plugs are located on the surface of the contact layer on the drain region and are arranged along the first direction.

15. The method for forming a semiconductor structure according to claim 11, It is characterized in that The active area also includes a third area adjacent to the first area, and the third area and the second area are respectively located on both sides of the first area; the gate structure also includes a second auxiliary gate located on the third area, the plurality of main gates are connected to the second auxiliary gates, and the second auxiliary gates are parallel to the second direction; the method also includes: forming a second body region in the third area, the second body region and the main gate are respectively located on both sides of the second auxiliary gate, and the second body region has a second conductivity type; the first conductive layer is also electrically connected to the second body region.

16. The method for forming a semiconductor structure according to claim 10, It is characterized in that Before forming the gate structure, it also includes: forming a well region in the first region and the second region; the bottom of the well region is in contact with the insulating layer; the source region, the drain region and the first body region are all located in the well region; the bottom of the source region, the drain region and the first body region are all in contact with the insulating layer.

17. The method for forming a semiconductor structure according to claim 16, It is characterized in that The forming process of the well region includes a first ion implantation process; The process parameters of the first ion implantation process include: the implanted ions include N-type or P-type conductive ions, the implantation energy range is 10KeV to 100KeV, and the implantation dose range is 1E12atom / cm 2 To 1E13atom / cm 2 .

18. The method for forming a semiconductor structure according to claim 16, It is characterized in that The substrate layer also includes an isolation region surrounding the active region; before forming the well region, the method further includes: etching the isolation region to form a groove in the substrate, wherein the groove exposes the insulating layer; and forming an isolation structure in the groove.

19. The method for forming a semiconductor structure according to claim 18, It is characterized in that The groove forming method also includes: after exposing the insulating layer, continuing to etch the insulating layer at the bottom of the groove; the groove has a first depth in the insulating layer, and the groove has a second depth in the substrate layer, and the ratio of the first depth to the second depth ranges from 5% to 30%.

20. The method for forming a semiconductor structure according to claim 10, It is characterized in that The process of forming the source region and the drain region includes a second ion implantation process; The process parameters of the second ion implantation process include: doping ions include N-type or P-type conductive ions, implantation energy ranges from 5KeV to 100KeV, and implantation dose ranges from 1E15atom / cm 2 To 9E15atom / cm 2 .

21. The method for forming a semiconductor structure according to claim 10, It is characterized in that The forming process of the first body region includes a third ion implantation process; The process parameters of the third ion implantation process include: doping ions include N-type or P-type conductive ions, implantation energy range is 5KeV to 100KeV, and implantation dose range is 1E15atom / cm 2 To 9E15atom / cm 2 .

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