Preparation method of solar cell, solar cell and photovoltaic module

Abstract

The invention relates to the technical field of new energy batteries, in particular to a preparation method of a solar cell, the solar cell and a photovoltaic module, and solves the problem that the cell efficiency cannot be improved due to the fact that the passivation open voltage of a traditional solar cell is limited. The preparation method of the solar cell comprises the following steps: providing a silicon substrate, wherein the silicon substrate comprises a front surface and a back surface which are arranged oppositely; sequentially preparing a first tunneling oxide layer and a first polycrystalline silicon layer on the front surface of the silicon substrate; and under an anaerobic condition, boron diffusion processing is carried out on the first polycrystalline silicon layer, and the first polycrystalline silicon layer is converted into a P + layer. As no oxygen participates in the boron diffusion treatment process, no silicon dioxide is generated on the surface of the first polycrystalline silicon layer to prevent further diffusion of boron, so that the boron diffusion degree can be improved, the boron doping concentration can be improved, a relatively high passivation open voltage can be kept, and the passivation open voltage on the front surface of the battery is improved; the problem that the front passivation open voltage of a traditional solar cell is limited is solved, and the conversion efficiency of the solar cell is improved.

Description

Technical Field

[0001] The present application relates to the technical field of new energy batteries, and in particular to a method for preparing a solar cell, a solar cell and a photovoltaic module. Background Art

[0002] Due to the increasing concern about environmental issues, solar energy has received more attention as a clean and sustainable energy alternative. Compared with fossil fuels, solar energy is an unlimited, renewable energy source that will not be exhausted, and solar cells have become one of the key technologies for achieving energy transformation and optimizing the power structure. Among the solar cells currently in mainstream production, the Tunnel Oxide Passivating Contact (TOPCon) cell has a high conversion rate and can effectively reduce the loss of low-energy photons, improve the utilization rate of light energy, and has a long battery life. The advantages make TOPCon cells have a wide range of application scenarios in the photovoltaic market and have become one of the current hot research on high-efficiency batteries.

[0003] However, the traditional TOPCon cell technology has a limited passivation opening voltage and cannot be further improved, resulting in the efficiency of the traditional TOPCon cell being unable to reach a higher level. Therefore, there is an urgent need for a solar cell preparation method to solve the problem that the passivation opening voltage of the traditional solar cell cannot be further improved, resulting in the inability to improve the efficiency of the cell. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a method for preparing a solar cell, a solar cell and a photovoltaic module, which solve the problem that the efficiency of the cell cannot be improved due to the inability to further increase the passivation voltage of a traditional solar cell.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a solar cell, comprising: providing a silicon substrate, the silicon substrate comprising a front side and a back side arranged back to back; sequentially preparing a first tunneling oxide layer and a first polysilicon layer on the front side of the silicon substrate; and performing a boron diffusion treatment on the first polysilicon layer under oxygen-free conditions to convert the first polysilicon layer into a P+ layer.

[0006] In some embodiments, in the step of performing the boron diffusion treatment on the first polysilicon layer, a borosilicate glass layer is also formed on the side of the P+ layer away from the first tunneling oxide layer; wherein the method for preparing the solar cell also includes: removing the borosilicate glass layer to expose the P+ layer; depositing a mask layer on the side of the P+ layer away from the first tunneling oxide layer, the material of the mask layer includes silicon dioxide or silicon nitride, and the mask layer includes alternating first preset gate line areas and first preset non-gate line areas; removing the first preset non-gate line area of ​​the mask layer to expose the P+ layer corresponding to the first preset non-gate line area.

[0007] In some embodiments, the method for preparing the solar cell further includes: sequentially preparing a second tunneling oxide layer and a second polysilicon layer on the back side of the silicon substrate; and performing phosphorus diffusion treatment on the second polysilicon layer to convert the second polysilicon layer into an N++ layer.

[0008] In some embodiments, before sequentially preparing a second tunneling oxide layer and a second polysilicon layer on the back side of the silicon substrate, the method for preparing a solar cell further includes: acid polishing the back side of the silicon substrate to expose the silicon substrate.

[0009] In some embodiments, in the step of performing the phosphorus diffusion treatment on the second polysilicon layer, a phosphosilicate glass layer is formed on the side of the N++ layer away from the second tunneling oxide layer, and the back side of the solar cell includes alternating second preset gate line areas and second preset non-gate line areas, wherein the first preset gate line areas correspond to the second preset non-gate line areas in a direction perpendicular to the front side of the silicon substrate, and the first preset non-gate line areas correspond to the second preset gate line areas in a direction perpendicular to the front side of the silicon substrate; wherein the method for preparing the solar cell further includes: removing the phosphosilicate glass layer on the second preset non-gate line area to expose the N++ layer corresponding to the second preset non-gate line area.

[0010] In some embodiments, the method for preparing the solar cell also includes: texturing the P+ layer corresponding to the first preset non-gate line area and the N++ layer corresponding to the second preset non-gate line area to form a front velvet area and a back velvet area, wherein the front velvet area is alternately arranged with the first preset gate line area, and the back velvet area is alternately arranged with the second preset gate line area.

[0011] In some embodiments, the method for preparing the solar cell also includes: coating the front velvet area, the first preset gate line area, the back velvet area and the second preset gate line area with aluminum oxide to obtain a front aluminum oxide film layer and a back aluminum oxide film layer; preparing a front silicon nitride film layer on a side of the front aluminum oxide film layer away from the front velvet area and the first preset gate line area; preparing a back silicon nitride film layer on a side of the back aluminum oxide film layer away from the back velvet area and the second preset gate line area.

[0012] In some embodiments, the method for preparing the solar cell also includes: performing silk screen printing at a position of the front silicon nitride film layer corresponding to the first preset gate line area to obtain a front electrode; and performing silk screen printing at a position of the back silicon nitride film layer corresponding to the second preset gate line area to obtain a back electrode.

[0013] In a second aspect, an embodiment of the present application provides a solar cell, which is prepared using the method for preparing a solar cell described in the first aspect, wherein the solar cell includes: a silicon substrate, including a front side and a back side arranged back to back; a first tunneling oxide layer, arranged on the front side of the silicon substrate, the first tunneling oxide layer including a plurality of first tunneling oxide units arranged at intervals; a P+ layer, arranged on a side of the plurality of first tunneling oxide units away from the silicon substrate.

[0014] In a third aspect, an embodiment of the present application provides a photovoltaic assembly, comprising: a plurality of solar cells electrically connected in sequence, wherein the solar cells include the solar cells mentioned in the second aspect above.

[0015] The method for preparing a solar cell provided in an embodiment of the present application performs a boron diffusion treatment on a first polysilicon layer under oxygen-free conditions to convert the first polysilicon layer into a P+ layer. Since no oxygen is involved in the boron diffusion treatment process, silicon dioxide will not be produced on the surface of the first polysilicon layer to prevent further diffusion of boron. Therefore, the degree of boron diffusion can be increased, and the boron doping concentration can be increased, thereby maintaining a high passivation voltage, improving the passivation voltage on the front side of the battery, solving the problem of limited passivation voltage on the front side of traditional solar cells, and improving the conversion efficiency of solar cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other purposes, features and advantages of the present application will become more apparent by describing the embodiments of the present application in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation on the present application.

[0017] Figure 1The figure is a schematic diagram of the process of a method for preparing a solar cell provided in one embodiment of the present application.

[0018] Figure 2 Shown is a schematic structural diagram of a silicon substrate provided in one embodiment of the present application.

[0019] Figure 3 Shown is a schematic diagram of the structure after the first polysilicon layer is prepared according to an embodiment of the present application.

[0020] Figure 4 Shown is a schematic diagram of the structure after boron diffusion treatment provided in one embodiment of the present application.

[0021] Figure 5 Shown is a schematic flow chart of a method for preparing a solar cell provided in another embodiment of the present application.

[0022] Figure 6 Shown is a schematic diagram of the structure after depositing a mask layer provided in one embodiment of the present application.

[0023] Figure 7 FIG. 1 is a schematic diagram of a structure after removing a first preset non-gate line region of a mask layer provided by an embodiment of the present application.

[0024] Figure 8 Shown is a schematic flow chart of a method for preparing a solar cell provided in another embodiment of the present application.

[0025] Fig. 9 Shown is a schematic diagram of the structure after the second polysilicon layer is prepared according to an embodiment of the present application.

[0026] Fig.10 Shown is a schematic diagram of the structure after phosphorus diffusion treatment provided in one embodiment of the present application.

[0027] Fig.11 Shown is a schematic flow chart of a method for preparing a solar cell provided in another embodiment of the present application.

[0028] Fig.12 FIG. 1 is a schematic diagram of a structure after removing the phosphosilicate glass layer on the second preset non-gate line area provided in an embodiment of the present application.

[0029] Fig.13 Shown is a schematic diagram of the structure after texturing provided by an embodiment of the present application.

[0030] Fig.14 Shown is a schematic diagram of the structure after aluminum oxide coating provided in one embodiment of the present application.

[0031] Fig.15 Shown is a schematic diagram of the structure after preparing the front silicon nitride film layer and the back silicon nitride film layer provided in one embodiment of the present application.

[0032] Fig.16 Shown is a schematic diagram of the structure after preparing the front electrode and the back electrode provided in one embodiment of the present application.

[0033] Fig.17 Shown is a schematic structural diagram of a photovoltaic module provided in one embodiment of the present application.

[0034] Reference numerals:

[0035] 100. Solar cell; 101. Silicon substrate; A. Front side; B. Back side; 102. First tunneling oxide layer; 1021. First tunneling oxide unit; 103. First polysilicon layer; 104. P+ layer; 1041. P+ unit; 105. Mask layer; 1051. First preset gate line region; 1052. First preset non-gate line region; 1053. Front velvet region; 106. Front aluminum oxide film layer; 107. Front silicon nitride film layer; 201, second tunneling oxide layer; 2011, second tunneling oxide unit; 202, second polysilicon layer; 203, N++ layer; 2031, N++ unit; 204, phosphosilicate glass layer; 2041, second preset gate line area; 2042, second preset non-gate line area; 2043, back velvet area; 205, back aluminum oxide film layer; 206, back silicon nitride film layer; 200, photovoltaic module. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] As global attention to environmental issues increases, the demand for clean energy has further increased, making solar energy a clean and sustainable energy alternative that has received more attention. Compared with fossil fuels, solar energy is an unlimited, renewable energy source that will not be exhausted; in addition, solar cells produce lower carbon emissions during their life cycle, which helps reduce greenhouse gas emissions and combat global climate change. Solar cells have become one of the key technologies for achieving energy transformation and optimizing power structure. Currently, the mainstream solar cells include interdigitated back contact (IBC) cells, tunnel oxide passivated contact (TOPCon) cells, and heterojunction cells. Due to the presence of the tunnel oxide layer, TOPCon cells effectively reduce the loss of low-energy photons and improve the utilization rate of light energy; and the surface recombination rate of TOPCon cells is low, which can effectively reduce energy loss and increase the life of the battery. Therefore, TOPCon cells have a wide range of application scenarios in the photovoltaic market and have become one of the hot research topics for high-efficiency batteries.

[0038] However, the front P region of the traditional TOPCon cell mainly increases the passivation opening voltage by boron diffusion (high square resistance), but due to technical limitations, this method has a limited passivation opening voltage and cannot be improved, resulting in the efficiency of the traditional TOPCon cell being unable to reach a high level. Therefore, a method for preparing a solar cell is urgently needed to solve the problem that the passivation opening voltage of the traditional solar cell cannot be further improved, resulting in the inability to improve the efficiency of the cell.

[0039] The following is a detailed introduction to the method for preparing a solar cell provided in the embodiment of the present application in conjunction with the accompanying drawings.

[0040] Figure 1 FIG. 1 is a schematic diagram of a process for preparing a solar cell according to an embodiment of the present application. Figure 1 As shown, the method for preparing a solar cell includes the following steps.

[0041] Step 110 , providing a silicon substrate.

[0042] Figure 2 FIG. 1 is a schematic diagram of the structure of a silicon substrate provided by an embodiment of the present application. Figure 2 As shown, the silicon substrate 101 includes a front side A and a back side B disposed opposite to each other. The "front side" referred to in this application refers to the side where light is incident, which is used to collect sunlight, generate photogenerated carriers (electron-hole pairs), and collect photogenerated electrons through the front electrode. In contrast, the "back side" referred to in this application is the other side opposite to the "front side".

[0043] For example, in the embodiment of the present application, the solar cell refers to a TOPCon cell. The silicon substrate 101 is N-type single crystal silicon, which has the advantages of less impurities, high purity, long minority carrier lifetime, no grain boundary dislocation defects, and easy control of resistivity, so that the N-type single crystal silicon can improve the conversion efficiency of the TOPCon cell.

[0044] Step 120: sequentially prepare a first tunneling oxide layer and a first polysilicon layer on the front surface of the silicon substrate.

[0045] Figure 3 FIG. 1 is a schematic diagram of a structure after the first polysilicon layer is prepared according to an embodiment of the present application. Exemplarily, the first tunnel oxide layer 102 and the first polysilicon layer 103 are prepared by low-pressure chemical vapor deposition (LPCVD) equipment.

[0046] Exemplarily, the deposition thickness of the first tunnel oxide layer 102 is 1nm to 2nm. Exemplarily, if the first tunnel oxide layer is too thin, it is discontinuous and does not form a film, and does not play a role in chemical passivation; if the first tunnel oxide layer is too thick, it will affect electron tunneling and absorption, the electrical properties will deteriorate, and ultimately affect the battery conversion efficiency. When the thickness of the first tunnel oxide layer 102 ranges from 1nm to 2nm, the first tunnel oxide layer can allow majority electrons to tunnel into the polysilicon layer, while blocking the recombination of minority carriers and holes, and play a good chemical passivation role. In addition, when the thickness of the first tunnel oxide layer 102 ranges from 1nm to 2nm, it can also reduce the recombination loss of minority carriers (holes), which is conducive to improving the fill factor, obtaining a higher open circuit voltage, and further improving the passivation open voltage of the solar cell.

[0047] Exemplarily, the deposition thickness of the first polysilicon layer 103 is 150nm to 300nm. Exemplarily, the thickness of the first polysilicon layer 103 is proportional to the overall passivation effect. The greater the thickness, the better the passivation effect, thereby being able to increase the open circuit voltage. The thickness range of the first polysilicon layer 103 of the solar cell provided in the embodiment of the present application is 150nm to 300nm, which is conducive to improving the passivation effect, open circuit voltage and overall efficiency of the TOPCon cell, while reducing the composite loss, thereby further improving the passivation open voltage of the solar cell.

[0048] Exemplarily, before the first tunnel oxide layer 102 and the first polysilicon layer 103 are sequentially prepared on the front side A of the silicon substrate 101, the front side A and the back side B of the silicon substrate 101 may be polished. Specifically, during the diamond wire cutting process, a damaged layer will be formed on the surface of the silicon substrate 101, which contains a large number of defects and recombination centers, which have a great impact on the conversion efficiency and yield of the battery. Therefore, the damaged layer can be corroded and removed. The process of removing the damaged layer is as follows: first, the silicon substrate 101 is polished with an alkaline solution, and then a texturing treatment is performed in the subsequent process. Before and after polishing, ozone (O 3 ) to assist cleaning to obtain a clean surface. For example, a high concentration of KOH (20% to 22%) can be used to etch the surface of the silicon substrate 101, the reaction temperature is 80° C. to 85° C., and the single-side etching depth is 4 μm to 8 μm.

[0049] Step 130 , performing a boron diffusion process on the first polysilicon layer under an oxygen-free condition to convert the first polysilicon layer into a P+ layer.

[0050] Figure 4 The structure schematic diagram after the boron diffusion treatment provided by an embodiment of the present application is shown. Exemplarily, under oxygen-free conditions, the first polysilicon layer 103 is subjected to boron diffusion treatment to convert the first polysilicon layer 103 into a P+ layer 104. The first polysilicon layer 103 can be doped with boron under high temperature oxygen-free conditions to convert the first polysilicon layer 103 into a P+ layer 104, and oxygen is not required in the cooling process. Exemplarily, the temperature of the boron diffusion treatment is 550°C to 600°C.

[0051] Exemplarily, in an oxygen-free condition, the first polysilicon layer 103 is subjected to a boron diffusion process, that is, the first polysilicon layer 103 is doped with boron to form a first doped polysilicon layer, that is, a P+ layer 104 .

[0052] Since there is no oxygen involved in the boron diffusion treatment and cooling process, during the boron diffusion process, silicon dioxide will not be generated on the surface of the first polysilicon layer 103, preventing further diffusion of boron. Therefore, the degree of boron diffusion can be increased, and the boron doping concentration can be increased, so that a high passivation opening voltage can be maintained, and the passivation opening voltage on the front of the battery is improved, which solves the problem of limited passivation opening voltage on the front of traditional solar cells and improves the conversion efficiency of solar cells. The traditional boron diffusion process promotes the acquisition of the emitter in oxygen, which has the problem of affecting the minority carrier lifetime of polysilicon. The embodiment of the present application performs boron diffusion in an oxygen-free environment, which can effectively prevent oxygen from diffusing into the polysilicon body, avoid defects formed in the polysilicon layer, and increase the minority carrier lifetime of doped polysilicon.

[0053] In addition, the method for preparing solar cells provided in the embodiment of the present application performs boron diffusion treatment under anaerobic conditions, avoiding the high-temperature process that requires high-temperature diffusion under a traditional aerobic environment, thereby reducing thermal damage caused by high temperatures (for example, greater than 1000°C) during the preparation of solar cells, making the entire battery preparation process more stable and reliable.

[0054] Exemplarily, the first tunneling oxide layer 102 is made of silicon dioxide (SiO2) or silicon oxynitride (SiON). The first tunneling oxide layer 102 and the first polysilicon layer 103 together constitute a passivation contact structure, which realizes the passivation of the front side of the battery and improves the passivation opening voltage of the TOPCon battery. The first tunneling oxide layer 102 is a silicon oxide layer, which can utilize the quantum tunneling effect to allow majority carriers (majority carriers) to tunnel while blocking minority carriers (minority carriers) from passing through. Without the need for an open-hole passivation contact structure, it is possible to effectively reduce surface recombination and metal contact recombination, thereby improving the opening voltage and energy conversion efficiency. According to research, the conversion rate of the solar cell provided in the embodiment of the present application can reach more than 26%.

[0055] Figure 5 FIG. 1 is a schematic flow chart of a method for preparing a solar cell provided by another embodiment of the present application. In the step of performing boron diffusion treatment on the first polysilicon layer 103, a borosilicate glass layer is also formed on the side of the P+ layer 104 away from the first tunnel oxide layer 102. The borosilicate glass layer is a byproduct of the boron diffusion treatment. Figure 5 As shown, the method for preparing a solar cell also includes the following steps.

[0056] Step 140, removing the borosilicate glass layer to expose the P+ layer.

[0057] Step 150 , depositing a mask layer on a side of the P+ layer away from the first tunnel oxide layer.

[0058] Figure 6 FIG. 1 is a schematic diagram of a structure after a mask layer is deposited according to an embodiment of the present application. Figure 6 As shown, the mask layer 105 includes first preset gate line regions 1051 and first preset non-gate line regions 1052 that are alternately arranged. Figure 6 The first preset gate line area 1051 and the first preset non-gate line area 1052 are divided by dotted lines, which are only for schematic purposes and are not included in actual applications. By way of example, the deposition thickness of the mask layer 105 is 30nm to 40nm. Preferably, the deposition thickness of the mask layer 105 is 40nm. By way of example, a plasma enhanced chemical vapor deposition (PECVD) device can be used to epitaxially grow the mask layer 105 on one side of the P+ layer 104 away from the first tunnel oxide layer 102.

[0059] Exemplarily, the material of the mask layer 105 includes silicon dioxide or silicon nitride. Silicon nitride has the advantages of good corrosion resistance, high light transmittance, good dielectric properties, high hardness, good wear resistance, etc. Silicon dioxide has the advantages of high selectivity, chemical stability, thermal stability, and compact structure. In addition, according to research, it is found that when the thickness of the mask layer 105 is 40nm, the protection effect is best, which can ensure the protection effect while requiring low process cost. The material of the mask layer 105 of the embodiment of the present application is silicon nitride or silicon oxide, and the thickness of the mask layer 105 ranges from 30nm to 40nm, which has a good protection effect on the P+ layer 104 and low process cost.

[0060] Step 160 , removing the first preset non-gate line region of the mask layer to expose the P+ layer corresponding to the first preset non-gate line region.

[0061] Figure 7 The structure diagram after removing the first preset non-gridline area of ​​the mask layer provided by an embodiment of the present application is shown. For example, the first preset non-gridline area 1052 of the mask layer 105 can be removed by laser to expose the P+ layer 104 corresponding to the first preset non-gridline area 1052, in preparation for subsequent texturing.

[0062] Since the borosilicate glass layer is removed, the P+ layer 104 may be corroded during the subsequent texturing. Therefore, a mask layer 105 is provided to protect the P+ layer 104 during the subsequent texturing.

[0063] Figure 8 FIG. 1 is a schematic diagram of a process for preparing a solar cell according to another embodiment of the present invention. Figure 8 As shown, the method for preparing a solar cell also includes the following steps.

[0064] Step 210: sequentially prepare a second tunneling oxide layer and a second polysilicon layer on the back side of the silicon substrate.

[0065] Fig. 9 The figure shows a schematic diagram of the structure after the second polysilicon layer is prepared according to an embodiment of the present application. Exemplarily, the second tunnel oxide layer 201 and the second polysilicon layer 202 are prepared by LPCVD equipment. Exemplarily, the deposition thickness of the second tunnel oxide layer 201 is 1nm to 2nm. Exemplarily, the deposition thickness of the second polysilicon layer 202 is 100nm to 200nm.

[0066] Step 220 , performing phosphorus diffusion treatment on the second polysilicon layer to convert the second polysilicon layer into an N++ layer.

[0067] Fig.10 The figure shows a schematic diagram of a structure after phosphorus diffusion treatment provided by an embodiment of the present application. Fig.10 As shown, the second polysilicon layer 202 is subjected to phosphorus diffusion treatment to form the second polysilicon layer 202 into an N++ layer 203. Exemplarily, the phosphorus diffusion treatment is performed at a temperature of 600° C. and the sheet resistance is 90Ω to 300Ω.

[0068] Exemplarily, a phosphorus diffusion process is performed on the second polysilicon layer 202 , that is, phosphorus is doped on the second polysilicon layer 202 to form a second doped polysilicon layer, that is, an N++ layer 203 .

[0069] Exemplarily, the P+ layer 104 is a first doped polysilicon layer formed by boron doping the first polysilicon layer 103. The N++ layer 203 is a second doped polysilicon layer formed by phosphorus doping the second polysilicon layer 202. The number of "+"s after "P" and "N" indicates the doping concentration of the film layer. For example, the doping concentration of the film layer represented by two "+"s is greater than the doping concentration of the film layer represented by one "+".

[0070] In some embodiments, before sequentially preparing the second tunnel oxide layer and the second polysilicon layer on the back side of the silicon substrate, the process further includes: acid polishing the back side B of the silicon substrate 101 to expose the silicon substrate 101 .

[0071] For example, due to the formation of the mask layer 105, there may be a winding of the mask layer 105 on the back side. In order to ensure the texturing effect of the back side B of the silicon substrate 101, the back side B of the silicon substrate 101 can be chain acid polished until the silicon substrate 101 is polished to the back side B.

[0072] like Fig.10 As shown, in the step of performing phosphorus diffusion treatment on the second polysilicon layer 202, a phosphosilicate glass layer 204 is also formed on the side of the N++ 203 layer away from the second tunnel oxide layer 201. The phosphosilicate glass layer 204 is a byproduct of the phosphorus diffusion treatment. The film thickness of the phosphosilicate glass layer 204 is 50nm to 70nm.

[0073] The back side of the solar cell 100 includes a second preset gridline region 2041 and a second preset non-gridline region 2042 that are alternately arranged. The first preset gridline region 1051 corresponds to the second preset non-gridline region 2042 in a direction perpendicular to the front side A of the silicon substrate 101, and the first preset non-gridline region 1052 corresponds to the second preset gridline region 2041 in a direction perpendicular to the front side A of the silicon substrate 101. Even if the first preset gridline region 1051 is staggered from the second preset gridline region 2041, the stress distribution on the solar cell can be made more uniform, thereby reducing the bending of the solar cell caused by stress concentration.

[0074] Fig.11FIG. 1 is a schematic diagram of a process for preparing a solar cell according to another embodiment of the present invention. Fig.11 As shown, the method for preparing a solar cell also includes the following steps.

[0075] Step 230 , removing the phosphosilicate glass layer on the second preset non-gate line region to expose the N++ layer corresponding to the second preset non-gate line region.

[0076] Fig.12 The structure diagram after removing the phosphosilicate glass layer on the second preset non-gridline area provided by an embodiment of the present application is shown. For example, the phosphosilicate glass layer 204 on the second preset non-gridline area 2042 can be removed by laser to expose the N++ layer 203 corresponding to the second preset non-gridline area 2042, in preparation for subsequent texturing.

[0077] Step 240 , texturing the P+ layer corresponding to the first preset non-gate line region and the N++ layer corresponding to the second preset non-gate line region to form a front side velvet region and a back side velvet region.

[0078] The front suede area 1053 and the back suede area 2043 are both suede structures.

[0079] Fig.13 The figure shows a schematic diagram of the structure after the texturing process provided by an embodiment of the present application. Fig.13 As shown, after texturing, the front velvet area 1053 and the first preset gate line area 1051 are alternately arranged, and the back velvet area 2043 and the second preset gate line area 2041 are alternately arranged. The front velvet area 1053 is located on the front side A of the silicon substrate 101, and the back velvet area 2043 is located on the back side B of the silicon substrate 101. In other words, during the texturing process, the P+ layer 104, the first tunneling oxide layer 102, the N++ layer 203, and the second tunneling oxide layer 201 that are not covered by the first preset gate line area 1051 and the second preset gate line area 2041 are corroded away, so that the P+ layer 104, the first tunneling oxide layer 102, the N++ layer 203, and the second tunneling oxide layer 201 are formed into multiple disconnected units. For example, as Fig.13 As shown, the P+ layer 104 includes a plurality of P+ units 1041 disposed at intervals, the first tunneling oxide layer 102 includes a plurality of first tunneling oxide units 1021 disposed at intervals, the N++ layer 203 includes a plurality of N++ units 2031 disposed at intervals, and the second tunneling oxide layer 201 includes a plurality of second tunneling oxide units 2011 disposed at intervals.

[0080] By texturing the P+ layer 104 corresponding to the first preset non-gate line area 1052 and the N++ layer 203 corresponding to the second preset non-gate line area 2042, a front velvet area 1053 and a back velvet area 2043 are formed, and the light trapping effect is utilized to improve the light absorption effect on both sides, thereby further improving the conversion efficiency of the solar cell.

[0081] Exemplarily, an alkaline solution is used to form a pyramid velvet surface on the front side A and the back side B of the silicon substrate 101. Since the pyramid velvet has a certain angle with the incident angle of sunlight, the sunlight can enter the battery again after reflection, which can increase the amount of sunlight entering the battery. When light is incident on a slope at a certain angle, the light will be reflected to a slope at another angle, forming secondary or multiple absorption, and enhancing the light absorption effect, that is, the velvet structure increases the light trapping effect on the surface of the silicon substrate 101 and enhances the light absorption effect. The surface velvet of the silicon substrate 101 is made by utilizing the different densities of silicon atoms in different crystal orientations, which have different reaction rates during chemical reactions, and then using certain additives to control the reaction rate. By controlling the concentration of the alkaline solution and the additives and their mutual ratios, a pyramid velvet surface can be formed on the surface of the silicon substrate 101 at a certain reaction temperature and reaction time.

[0082] The embodiment of the present application forms a suede structure on the non-metallized areas (i.e., non-gridline areas) on the front and back sides of the silicon substrate, utilizes the light trapping effect, improves the light absorption effect on both sides, and further improves the conversion efficiency of the solar cell.

[0083] like Fig.11 As shown, the method for preparing a solar cell also includes the following steps.

[0084] Step 310 , performing aluminum oxide coating on the front suede area, the first preset gate line area, the back suede area, and the second preset gate line area to obtain a front aluminum oxide film layer and a back aluminum oxide film layer.

[0085] Fig.14 The structure diagram after aluminum oxide coating is shown in one embodiment of the present application. Fig.14 As shown, the front suede area 1053 , the first preset gate line area 1051 , the back suede area 2043 and the second preset gate line area 2041 are subjected to aluminum oxide coating to obtain a front aluminum oxide film layer 106 and a back aluminum oxide film layer 205 .

[0086] For example, the front aluminum oxide film layer 106 and the back aluminum oxide film layer 205 can be obtained by single-insertion double-sided coating using atomic layer deposition (ALD). For example, the film thickness of the front aluminum oxide film layer 106 and the back aluminum oxide film layer 205 can be 6nm to 8nm.

[0087] Step 320 , forming a front silicon nitride film layer on a side of the front aluminum oxide film layer away from the front suede region and the first preset gate line region.

[0088] Step 330 , forming a back side silicon nitride film layer on a side of the back side aluminum oxide film layer away from the back side velvet area and the second preset gate line area.

[0089] Fig.15 The figure shows a schematic diagram of the structure after preparing the front silicon nitride film layer and the back silicon nitride film layer according to an embodiment of the present application. Fig.15 As shown, a front silicon nitride film layer 107 is formed on the side of the front aluminum oxide film layer 106 away from the front velvet area 1053 and the first preset gate line area 1051. A back silicon nitride film layer 206 is formed on the side of the back aluminum oxide film layer 205 away from the back velvet area 2043 and the second preset gate line area 2041.

[0090] For example, the thickness of the front silicon nitride film layer 107 and the back silicon nitride film layer 206 may both be 75 nm to 80 nm.

[0091] Exemplarily, appropriate gas (such as trimethylaluminum, etc.) is introduced into the chamber of the PECVD device, and under the action of the radio frequency power supply, the front aluminum oxide film layer 106 and the back aluminum oxide film layer 205 are reacted. In the chamber of the PECVD device, an appropriate amount of reaction gas (such as silicon source gas, etc.) and possible oxidant are introduced, and under the action of glow discharge, these gases undergo chemical reaction and plasma reaction to form the front silicon nitride film layer 107 and the back silicon nitride film layer 206.

[0092] The solar cell provided in the embodiment of the present application forms a front passivation effect through the front aluminum oxide film layer 106 together with the first tunnel oxide layer 102 and the P+ layer 104 to reduce the carrier recombination on the front side. In addition, the front silicon nitride film layer 107 can reduce surface reflection, further improving the conversion efficiency of the cell.

[0093] like Fig.11 As shown, the method for preparing a solar cell also includes the following steps.

[0094] Step 340 , screen printing is performed at a position of the front silicon nitride film layer corresponding to the first preset gate line region to obtain a front electrode.

[0095] Step 350 , screen printing is performed at a position of the back silicon nitride film layer corresponding to the second preset gate line region to obtain a back electrode.

[0096] Fig.16 The figure shows a schematic diagram of the structure after preparing the front electrode and the back electrode according to an embodiment of the present application. Fig.16As shown, screen printing is performed at a position corresponding to the first preset gate line region 1051 of the front silicon nitride film layer 107 to obtain the front electrode 108. Screen printing is performed at a position corresponding to the second preset gate line region 2041 of the back silicon nitride film layer 206 to obtain the back electrode 207.

[0097] like Figures 12 to 16 As shown, the embodiment of the present application further provides a solar cell 100. The solar cell 100 is prepared by the method for preparing a solar cell provided by the above embodiment, and therefore, the solar cell 100 has all the technical effects of the method for preparing a solar cell, which will not be described in detail here.

[0098] The solar cell 100 includes a silicon substrate 101, a first tunneling oxide layer 102 and a P+ layer 104. The silicon substrate 101 includes a front side A and a back side B disposed opposite to each other. The first tunneling oxide layer 102 is disposed on the front side A of the silicon substrate 101. The first tunneling oxide layer 102 includes a plurality of first tunneling oxide units 1021 disposed at intervals. The P+ layer 104 is disposed on a side of the plurality of first tunneling oxide units 1021 away from the silicon substrate 101.

[0099] In some embodiments, the solar cell 100 further includes a mask layer 105, a front aluminum oxide film layer 106, and a front silicon nitride film layer 107. In some embodiments, the solar cell 100 further includes a second tunneling oxide layer 201, an N++ layer 203, a phosphorus silicon glass layer 204, a back aluminum oxide film layer 205, and a back silicon nitride film layer 206. The positions and shapes of the above-mentioned film layers can be referred to the above-mentioned method embodiments, and will not be repeated here.

[0100] Fig.17 FIG. 1 is a schematic diagram of the structure of a photovoltaic module provided by an embodiment of the present application. Fig.17 As shown, a photovoltaic assembly 200 provided in an embodiment of the present application includes a plurality of solar cells 100 electrically connected in sequence, and the solar cell 100 is the solar cell 100 in the above embodiment. Exemplarily, the solar cells 100 may be connected together by serial welding.

[0101] Since the photovoltaic assembly 200 includes a plurality of solar cells 100 electrically connected in sequence, the photovoltaic assembly 200 has all the technical features and effects of the solar cell 100, which will not be described in detail herein.

[0102] The phrases "one embodiment", "an embodiment", etc. mentioned in the specification indicate that the embodiment described may include a specific feature, structure or characteristic, but not every embodiment may include the specific feature, structure or characteristic. In addition, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such feature, structure or characteristic in conjunction with other embodiments, whether explicitly or not explicitly described.

[0103] It should be understood that “on,” “above,” and “over” in this application should be interpreted in the broadest manner, so that “on” not only means “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “above” or “over” not only includes the meaning of “above something” or “over,” but also may include the meaning of “above something” or “over” with no intervening features or layers therebetween (i.e., directly on something).

[0104] Additionally, spatially relative terms, such as "below," "below," "beneath," "above," "above," etc., may be used herein for ease of description to describe the relationship of one component or feature to other components or features as shown in the figures. The spatially relative terms are intended to encompass different orientations of the component in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0105] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0106] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0107] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A method for preparing a solar cell, characterized in that: include: Providing a silicon substrate, wherein the silicon substrate comprises a front side and a back side disposed opposite to each other; Sequentially preparing a first tunneling oxide layer and a first polysilicon layer on the front surface of the silicon substrate; Under oxygen-free conditions, a boron diffusion process is performed on the first polysilicon layer to convert the first polysilicon layer into a P+ layer.

2. The method for preparing a solar cell according to claim 1, characterized in that: In the step of performing the boron diffusion treatment on the first polysilicon layer, a borosilicate glass layer is also formed on a side of the P+ layer away from the first tunneling oxide layer; wherein the method for preparing the solar cell further includes: Removing the borosilicate glass layer to expose the P+ layer; Depositing a mask layer on a side of the P+ layer away from the first tunnel oxide layer, wherein the material of the mask layer includes silicon dioxide or silicon nitride, and the mask layer includes first preset gate line regions and first preset non-gate line regions that are alternately arranged; The first preset non-gate line region of the mask layer is removed to expose the P+ layer corresponding to the first preset non-gate line region.

3. The method for preparing a solar cell according to claim 2, characterized in that: Also includes: Sequentially preparing a second tunneling oxide layer and a second polysilicon layer on the back side of the silicon substrate; The second polysilicon layer is subjected to a phosphorus diffusion process to convert the second polysilicon layer into an N++ layer.

4. The method for preparing a solar cell according to claim 3, characterized in that: Before sequentially preparing a second tunnel oxide layer and a second polysilicon layer on the back side of the silicon substrate, the method further comprises: Acid polishing is performed on the back side of the silicon substrate to expose the silicon substrate.

5. The method for preparing a solar cell according to claim 3, characterized in that: In the step of performing the phosphorus diffusion treatment on the second polysilicon layer, a phosphorus silicon glass layer is formed on a side of the N++ layer away from the second tunneling oxide layer, and the back side of the solar cell includes second preset gate line regions and second preset non-gate line regions that are alternately arranged, wherein the first preset gate line regions correspond to the second preset non-gate line regions in a direction perpendicular to the front side of the silicon substrate, and the first preset non-gate line regions correspond to the second preset gate line regions in a direction perpendicular to the front side of the silicon substrate; Wherein, the method for preparing the solar cell further comprises: The phosphosilicate glass layer on the second preset non-gate line area is removed to expose the N++ layer corresponding to the second preset non-gate line area.

6. The method for preparing a solar cell according to claim 5, characterized in that: Also includes: The P+ layer corresponding to the first preset non-gate line area and the N++ layer corresponding to the second preset non-gate line area are textured to form a front velvet area and a back velvet area, wherein the front velvet area is alternately arranged with the first preset gate line area, and the back velvet area is alternately arranged with the second preset gate line area.

7. The method for preparing a solar cell according to claim 6, characterized in that: Also includes: Performing aluminum oxide coating on the front suede area, the first preset gate line area, the back suede area and the second preset gate line area to obtain a front aluminum oxide film layer and a back aluminum oxide film layer; Forming a front silicon nitride film layer on a side of the front aluminum oxide film layer away from the front velvet area and the first preset gate line area; A back side silicon nitride film layer is formed on a side of the back side aluminum oxide film layer away from the back side velvet area and the second preset gate line area.

8. The method for preparing a solar cell according to claim 7, characterized in that: Also includes: Performing screen printing at a position of the front silicon nitride film layer corresponding to the first preset gate line region to obtain a front electrode; The screen printing is performed at a position of the back silicon nitride film layer corresponding to the second preset gate line region to obtain a back electrode.

9. A solar cell, characterized in that: Prepared by the method for preparing a solar cell according to any one of claims 1 to 8, wherein the solar cell comprises: A silicon substrate, comprising a front side and a back side disposed opposite to each other; A first tunneling oxide layer is disposed on the front surface of the silicon substrate, wherein the first tunneling oxide layer comprises a plurality of first tunneling oxide units disposed at intervals; The P+ layer is arranged on a side of the plurality of first tunneling oxidation units away from the silicon substrate.

10. A photovoltaic module, characterized in that: include: A plurality of solar cells electrically connected in sequence, wherein the solar cells include the solar cell according to claim 9.

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