Capacitor and manufacturing method thereof

Abstract

The invention relates to a manufacturing method of a capacitor. A method of manufacturing a capacitor includes forming a bottom electrode layer, forming an insulating layer on the bottom electrode layer, crystallizing the insulating layer, and forming a top electrode layer on the crystallized insulating layer. An oxide diffusion barrier layer containing titanium oxynitride is disposed between the top electrode layer and the insulating layer. The oxygen concentration in the oxide diffusion barrier layer is far higher than that of the top electrode layer, so that oxide atoms in the oxide diffusion barrier layer are difficult to diffuse to the top electrode layer. Therefore, the problem of electric leakage caused by a thinner top electrode layer and a smaller critical size of the capacitor can be reduced. The bottom electrode layer contains silicon titanium nitride, has high mechanical strength, reduces the collapse possibility of the capacitor, and enables the electrical performance of the capacitor not to be affected by the collapse problem.

Description

Technical Field

[0001] The present disclosure relates to a capacitor and a method for manufacturing the same. Background Art

[0002] Semiconductor devices are widely used in the electronics industry. The critical dimensions of capacitors are gradually reduced and the thickness of each stack becomes thinner. As a result, capacitor collapse caused by thinner electrodes and insufficient mechanical strength can lead to leakage and capacitance drop.

[0003] In view of this, how to provide a capacitor and a manufacturing method thereof that can solve the above problems is still one of the goals that the industry is working hard to study. Summary of the invention

[0004] A technical aspect of the present disclosure is a method for manufacturing a capacitor.

[0005] In one embodiment of the present disclosure, a method for manufacturing a capacitor includes forming a bottom electrode layer, forming an insulating layer on the bottom electrode layer, crystallizing the insulating layer, and forming a top electrode layer on the crystallized insulating layer.

[0006] In one embodiment of the present disclosure, the step of crystallizing the insulating layer is performed by an annealing process.

[0007] In one embodiment of the present disclosure, the step of crystallizing the insulating layer is performed before the step of forming the top electrode layer.

[0008] In one embodiment of the present disclosure, the method for manufacturing a capacitor further includes forming an oxide diffusion barrier layer between the insulating layer and the top electrode layer.

[0009] In one embodiment of the present disclosure, the oxide diffusion barrier layer includes titanium oxynitride.

[0010] In one embodiment of the present disclosure, the temperature of the step of crystallizing the insulating layer is in a range of 400 degrees to 600 degrees.

[0011] In one embodiment of the present disclosure, the time for the step of crystallizing the insulating layer is in a range of 30 seconds to 100 seconds.

[0012] In one embodiment of the present disclosure, the time for the step of crystallizing the insulating layer is shorter than the time for forming the top electrode layer.

[0013] In one embodiment of the present disclosure, the bottom electrode layer includes titanium silicon nitride.

[0014] Another technical aspect of the present disclosure is a method for manufacturing a capacitor.

[0015] In one embodiment of the present disclosure, a method for manufacturing a capacitor includes forming a bottom electrode layer, forming an insulating layer on the bottom electrode layer, forming a titanium oxynitride layer on the insulating layer, and forming a top electrode layer on the insulating layer.

[0016] In one embodiment of the present disclosure, the method for manufacturing a capacitor further includes performing an annealing process on the insulating layer.

[0017] In one embodiment of the present disclosure, the annealing process is performed before the step of forming the top electrode layer.

[0018] In one embodiment of the present disclosure, the temperature of the annealing process is in the range of 400 degrees to 600 degrees.

[0019] In one embodiment of the present disclosure, the annealing process lasts for a period of time ranging from 30 seconds to 100 seconds.

[0020] Another technical aspect of the present disclosure is a capacitor.

[0021] In one embodiment of the present disclosure, a capacitor includes a bottom electrode layer, an insulating layer, an oxide diffusion barrier layer, and a top electrode layer. The insulating layer is disposed on the bottom electrode layer. The oxide diffusion barrier layer is disposed on the insulating layer. The top electrode layer is disposed on the oxide diffusion barrier layer.

[0022] In one embodiment of the present disclosure, the top electrode layer comprises titanium nitride, and the oxide diffusion barrier layer comprises titanium oxynitride.

[0023] In one embodiment of the present disclosure, the bottom electrode layer includes titanium silicon nitride.

[0024] In one embodiment of the present disclosure, the material of the bottom electrode layer is different from the material of the top electrode layer.

[0025] In one embodiment of the present disclosure, the bottom electrode layer has a higher mechanical strength than the top electrode layer.

[0026] In one embodiment of the present disclosure, the oxygen concentration of the oxide diffusion barrier layer is higher than the oxygen concentration of the top electrode layer.

[0027] In the above embodiment, an oxide diffusion barrier layer containing titanium oxynitride is disposed between the top electrode layer and the insulating layer. Since the oxygen concentration in the oxide diffusion barrier layer is much higher than that in the top electrode layer, it is difficult for the oxide atoms in the oxide diffusion barrier layer to diffuse into the top electrode layer. In this way, the leakage problem caused by the thinner top electrode layer and the smaller critical size of the capacitor can be reduced. In addition, the bottom electrode layer contains titanium silicon nitride, which has a higher mechanical strength. Therefore, the possibility of capacitor collapse is reduced, so that the electrical performance of the capacitor will not be affected by the collapse problem. In addition, the step of crystallizing the insulating layer is performed before the step of forming the top electrode layer. The temperature of the step of crystallizing the insulating layer is in the range of 400 degrees to 600 degrees. The time of the step of crystallizing the insulating layer is in the range of 30 seconds to 100 seconds, which is shorter than the time period of the step of forming the top electrode layer. Therefore, fewer by-products are formed in this process, and the electrical performance of the insulating layer can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 FIG. 4 is a cross-sectional view of a capacitor array structure according to an embodiment of the present disclosure.

[0029] Figure 2 for Figure 1 A partial view of the capacitor array structure in .

[0030] Figure 3 for Figure 1 Flow chart of a method for manufacturing a capacitor.

[0031] Figure 4 A cross-sectional view showing an intermediate step in a method for manufacturing a capacitor.

[0032] Figure 5 A cross-sectional view showing an intermediate step in a method for manufacturing a capacitor.

[0033] Figure 6 A cross-sectional view showing an intermediate step in a method for manufacturing a capacitor.

[0034] Figure 7 A cross-sectional view showing an intermediate step in a method for manufacturing a capacitor.

[0035] Figure 8 A cross-sectional view showing an intermediate step in a method for manufacturing a capacitor. DETAILED DESCRIPTION

[0036] The following will disclose multiple embodiments of the present invention with the accompanying drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is, in some embodiments of the present invention, these practical details are not necessary. In addition, in order to simplify the drawings, some conventional structures and elements will be illustrated in the drawings in a simple schematic manner. And for the sake of clarity, the thickness of the layers and regions in the drawings may be exaggerated, and the same element symbols represent the same elements in the description of the drawings.

[0037] Figure 1 FIG. 1 is a cross-sectional view of a capacitor array structure 100 according to an embodiment of the present disclosure. The capacitor array structure 100 includes a substrate 110 , a capacitor contact 120 , a metal layer 130 , a dielectric layer 140 and a capacitor 150 .

[0038] The substrate 110 may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), SiGeC, gallium (Ga), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), silicon germanium-on-insulator, or silicon-on-insulator. The substrate 110 includes an insulating structure, an active region, and a transistor (not shown) formed in the active region.

[0039] The capacitor contact 120 is disposed on the substrate 110 and is electrically connected to the transistor therein. The metal layer 130 is disposed on the capacitor contact 120 and serves as a conductive pad. The capacitor contact 120 is electrically connected to the capacitor 150 through the metal layer 130. In some embodiments, the materials of the capacitor contact 120 and the metal layer 130 include polysilicon, titanium (Ti), titanium nitride (TiN), tantalum (Ta), TaN, tungsten (W), copper (Cu), aluminum (Al), or alloys thereof.

[0040] The dielectric layer 140 surrounds the capacitor contact 120 and the metal layer 130. The material of the dielectric layer 140 may include silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), tetraethoxysilane (TEOS), fluorosilicate glass (FSG), PI or a combination thereof.

[0041] The capacitor 150 includes a bottom electrode layer 152 , an insulating layer 154 disposed on the bottom electrode layer 152 , an oxide diffusion barrier layer 156 disposed on the insulating layer 154 , and a top electrode layer 158 disposed on the oxide diffusion barrier layer 156 .

[0042] Figure 2 for Figure 1 1. A partial view of the capacitor array structure 100 in FIG. As the critical dimension of the capacitor 150 decreases and the thickness of each stack becomes thinner, the possibility of the tunneling effect increases. The insulating layer 154 is a high dielectric material layer and may include aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), hafnium silicate (HfSiO 4 )、ZrO 2 ), zirconium oxynitride (ZrON), zirconium silicate (ZrSiO 2 ), yttrium oxide (Y 2 O 3 ), lanthanum oxide (La 2 O 3 ), cerium oxide (CeO 2 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ) or a combination thereof. In this embodiment, the insulating layer 154 is a composite material, which is sandwiched between two layers of zirconium dioxide (ZrO 2 ) between the aluminum oxide (Al 2 O 3 ) layer. Therefore, when the top electrode layer 158 is formed on the insulating layer 154 using a conventional method, oxygen atoms diffuse from the insulating layer 154 to the top electrode layer 158. Therefore, since the thickness of the top electrode layer 158 is relatively thin and the oxygen atoms diffuse, a leakage problem will occur.

[0043] In the present embodiment, the top electrode layer 158 includes titanium nitride (TiN), and the oxide diffusion barrier layer 156 includes titanium oxynitride (TiON). Since the oxygen concentration in the oxide diffusion barrier layer 156 (i.e., the TiON layer) is much higher than that in the top electrode layer 158, it is difficult for the oxide atoms in the oxide diffusion barrier layer 156 to diffuse toward the top electrode layer 158. Therefore, such a configuration can reduce the leakage problem caused by the thinner top electrode layer 158 and the smaller critical size of the capacitor 150.

[0044] like Figure 1 and Figure 2 As shown, as the critical dimension of the capacitor 150 is reduced and the thickness of each stacked layer is thinned, Figure 1The aspect ratio of the trench capacitor shown becomes higher. In such an embodiment, the structural support strength is mainly provided by the bottom electrode layer 152. Therefore, due to the thinner bottom electrode layer 152, the capacitor 150 is more likely to collapse, making it more likely that two adjacent capacitors will contact each other.

[0045] In the present embodiment, the bottom electrode layer 152 comprises titanium silicon nitride (TiSiN), which is titanium nitride doped with silicon. In other words, the material of the bottom electrode layer 152 is different from the material of the top electrode layer 158. Titanium silicon nitride has a high mechanical strength. Therefore, the possibility of capacitor collapse can be reduced, and the electrical performance of the capacitor 150 will not be affected by the collapse problem.

[0046] It should be noted that the connection relationship, materials and advantages of the above elements will not be repeated. In the following paragraphs, the manufacturing method of the capacitor 150 will be described.

[0047] Figure 3 for Figure 1 Flow chart of a method for manufacturing a capacitor 150. The method begins in step S1, forming a bottom electrode layer in a trench in a dielectric structure. The method proceeds to step S2, removing a sacrificial layer covering the dielectric structure and the bottom electrode layer. The method proceeds to step S3, forming an insulating layer on the bottom electrode layer. The method proceeds to step S4, crystallizing the insulating layer. The method proceeds to step S5, forming an oxide diffusion barrier layer on the insulating layer. Finally, in step S6, a top electrode layer is formed on the oxide diffusion barrier layer.

[0048] Figure 4 A cross-sectional view of an intermediate step in a method for manufacturing a capacitor. Figure 3 and Figure 4 In step S1, a bottom electrode layer 152 is formed in the trench TR formed in the dielectric structure 160. The bottom electrode layer 152 may be formed by electroplating, printing, chemical, vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes, but the present disclosure is not limited thereto.

[0049] The dielectric structure 160 is formed over the substrate 110, the capacitor contact 120, and the metal layer 130. The metal layer 130 is exposed from the trench TR, and the bottom electrode layer 152 contacts the metal layer 130.

[0050] In the present embodiment, the dielectric structure 160 includes a sacrificial layer 162, a support layer 164, and an etch stop layer 166, but the present disclosure is not limited thereto. In some other embodiments, the dielectric structure may include a stacked sacrificial layer and a support layer. The sacrificial layer 162 may be an oxide layer such as TEOS, and the support layer 164 may be a nitride layer, but the present disclosure is not limited thereto.

[0051] Figure 5 A cross-sectional view of an intermediate step in a method for manufacturing a capacitor. Figure 3 and Figure 5 In step S2, the sacrificial layer 162 and the bottom electrode layer 152 located above the dielectric structure 160 are removed by an etching process such as wet etching. It should be noted that this step may be omitted or exchanged with other steps depending on the actual structure of the dielectric structure 160.

[0052] Figure 6 A cross-sectional view of an intermediate step in a method for manufacturing a capacitor. Figure 3 and Figure 6 . In step S3, an insulating layer 154 is formed above the bottom electrode layer 152. In the present embodiment, since the capacitor 150 is a double-sided capacitor, the bottom of the insulating layer 154 is warped. The insulating layer 154 covers the bottom electrode layer 152 and the support layer 164 and covers the etching stop layer 166. In other embodiments, the capacitor may be a single-sided capacitor, and the insulating layer 154 at least covers the bottom electrode layer 152. The insulating layer 154 may be formed by electroplating, printing, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other appropriate processes, but the present disclosure is not limited thereto.

[0053] Figure 7 A cross-sectional view of an intermediate step in a method for manufacturing a capacitor. Figure 3 and Figure 7 In step S4 , the insulating layer 154 is crystallized. In the present embodiment, the step of crystallizing the insulating layer 154 is performed by an annealing process A, so that the capacitance value of the capacitor 150 is increased.

[0054] Figure 8 A cross-sectional view of an intermediate step in a method for manufacturing a capacitor. Figure 3 and Figure 8 In step S5, an oxide diffusion barrier layer 156 is formed on the insulating layer 154. Specifically, the oxide diffusion barrier layer 156 is conformally formed on the insulating layer 154. The oxide diffusion barrier layer 156 is a titanium oxynitride layer. The titanium oxynitride layer can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other appropriate processes, but the present disclosure is not limited thereto.

[0055] Reference Figure 3 and Figure 1 In step S6, a top electrode layer 158 is formed on the oxide diffusion barrier layer 156. Figures 7 and 8 as well as Figure 1 As shown, corresponding to steps S4-S6, a step of crystallizing the insulating layer 154 is performed before the step of forming the top electrode layer 158. As the critical dimension of the capacitor 150 is reduced, the thickness of each stack becomes thinner, and the capacitance of the capacitor 150 decreases. In the conventional method, the crystallization of the insulating layer 154 occurs during the step of forming the top electrode layer 158 to increase the capacitance. However, such a method may produce byproducts in the capacitor, thereby affecting its electrical performance.

[0056] For example, in the conventional method, the temperature of the step of forming the top electrode layer and simultaneously crystallizing the insulating layer is 400 to 500 degrees, and the time of this step is 300 to 350 seconds. In step S4 of the present embodiment, the temperature of the step of crystallizing the insulating layer 154 is 400 to 600 degrees. The time of the step of crystallizing the insulating layer 154 is in the range of 30 to 100 seconds. Therefore, the time period of the step of crystallizing the insulating layer 154 is shorter than the time period of the step of forming the top electrode layer 158. Since the time period of step S4 is much shorter than the time period of step S5, less by-products are generated in this process. Therefore, such a method can increase the capacitance and improve the electrical performance of the insulating layer.

[0057] In summary, the oxide diffusion barrier layer containing titanium oxynitride is arranged between the top electrode layer and the insulating layer. Since the oxygen concentration in the oxide diffusion barrier layer is much higher than that in the top electrode layer, it is difficult for the oxide atoms in the oxide diffusion barrier layer to diffuse into the top electrode layer. In this way, the leakage problem caused by the thinner top electrode layer and the smaller critical size of the capacitor can be reduced. In addition, the bottom electrode layer contains titanium silicon nitride, which has a higher mechanical strength. Therefore, the possibility of capacitor collapse is reduced, so that the electrical performance of the capacitor will not be affected by the collapse problem. In addition, the step of crystallizing the insulating layer is performed before the step of forming the top electrode layer. The temperature of the step of crystallizing the insulating layer is in the range of 400 degrees to 600 degrees. The time of the step of crystallizing the insulating layer is in the range of 30 seconds to 100 seconds, which is shorter than the time period of the step of forming the top electrode layer. Therefore, fewer by-products are formed in this process, and the electrical performance of the insulating layer can be improved.

[0058] Although the present invention has been disclosed as above in the form of implementation modes, it is not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the attached claims.

[0059]

Explanation of symbols

[0060] 100: Capacitor array structure

[0061] 110:Substrate

[0062] 120: Capacitor contact

[0063] 130:Metal layer

[0064] 140: Dielectric layer

[0065] 150:Capacitor

[0066] 152: Bottom electrode layer

[0067] 154: Insulation layer

[0068] 156: Oxide diffusion barrier layer

[0069] 158: Top electrode layer

[0070] 160: Dielectric structure

[0071] 162: Sacrificial layer

[0072] 164: Support layer

[0073] 166: Etching stop layer

[0074] S1~S6: Steps

[0075] A: Annealing process.

Claims

1. A method for manufacturing a capacitor, characterized in that: Include: forming a bottom electrode layer; forming an insulating layer on the bottom electrode layer; crystallizing the insulating layer; and A top electrode layer is formed on the crystallized insulating layer.

2. The method for manufacturing a capacitor according to claim 1, wherein: The step of crystallizing the insulating layer is performed by an annealing process.

3. The method for manufacturing a capacitor according to claim 2, wherein: The step of crystallizing the insulating layer is performed before the step of forming the top electrode layer.

4. The method for manufacturing a capacitor according to claim 1, wherein: Also includes: An oxide diffusion barrier layer is formed between the insulating layer and the top electrode layer.

5. The method for manufacturing a capacitor according to claim 4, characterized in that: The oxide diffusion barrier layer includes titanium oxynitride.

6. The method for manufacturing a capacitor according to claim 1, wherein: The bottom electrode layer includes titanium silicon nitride.

7. The method for manufacturing a capacitor according to claim 1, wherein: The temperature of the step of crystallizing the insulating layer is in the range of 400 degrees to 600 degrees.

8. The method for manufacturing a capacitor according to claim 1, wherein: The time of the step of crystallizing the insulating layer is in the range of 30 seconds to 100 seconds.

9. The method for manufacturing a capacitor according to claim 1, wherein: The time of the step of crystallizing the insulating layer is shorter than the time of forming the top electrode layer.

10. A method for manufacturing a capacitor, characterized in that: Include: forming a bottom electrode layer; forming an insulating layer on the bottom electrode layer; forming a titanium oxynitride layer on the insulating layer; and A top electrode layer is formed on the insulating layer.

11. The method for manufacturing a capacitor according to claim 10, wherein: Also includes: An annealing process is performed on the insulating layer.

12. The method for manufacturing a capacitor according to claim 11, wherein: The annealing process is performed before the step of forming the top electrode layer.

13. The method for manufacturing a capacitor according to claim 11, wherein: The temperature of the annealing process is in the range of 400 to 600 degrees.

14. The method for manufacturing a capacitor according to claim 11, wherein: The annealing process time is in the range of 30 seconds to 100 seconds.

15. A capacitor, characterized in that: Include: bottom electrode layer; An insulating layer, disposed on the bottom electrode layer; an oxide diffusion barrier layer disposed on the insulating layer; and A top electrode layer is disposed on the oxide diffusion barrier layer.

16. The capacitor according to claim 15, characterized in that The top electrode layer comprises titanium nitride and the oxide diffusion barrier layer comprises titanium oxynitride.

17. The capacitor according to claim 15, characterized in that The bottom electrode layer includes titanium silicon nitride.

18. The capacitor according to claim 15, characterized in that The material of the bottom electrode layer is different from the material of the top electrode layer.

19. The capacitor according to claim 15, characterized in that The bottom electrode layer has a higher mechanical strength than the top electrode layer.

20. The capacitor according to claim 15, characterized in that The oxide diffusion barrier layer has an oxygen concentration higher than that of the top electrode layer.

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