Method, controller and power electronics module for diagnosing degradation

Abstract

The invention relates to a method for diagnosing degradation of a power electronics module (2), said power electronics module (2) comprising a semiconductor component (3). The method comprises the following steps: providing an input signal of the power electronic module (2), the input signal comprising a large signal part provided for activating the semiconductor component (3); and receiving an output signal of the power electronics module to facilitate degradation diagnosis of the power electronics module (2), the output signal being based on an input signal, where the input signal comprises a periodic signal portion.

Description

Technical Field

[0001] The invention relates to a method as well as a control unit and a power electronics module having the features of the generic term according to claim 1 .

[0002] The following background technology is intended only to provide information necessary to understand the context of the inventive ideas and concepts disclosed herein. Therefore, this background technology section may include patentable subject matter and should not be regarded as prior art itself. Background Art

[0003] Power electronics are used in many applications such as the distribution of electrical energy or in electric vehicles. However, failure of power electronic module components, such as power converters, is one of the most common causes of failure in modern systems, such as wind turbines or photovoltaic systems. These failures can be attributed to defects in the assembly and connection technology of the power electronic modules or to the aging of the semiconductor devices themselves. In order to ensure high reliability in such applications without costly oversized power electronic components, reliable information about the aging condition of the power electronic modules is necessary. This enables the power electronic modules to be operated safely over an extended period of time until critical aging is reached and predictive maintenance is triggered.

[0004] The invention is based on the problem of creating a simpler degradation diagnosis with less effort. Summary of the invention

[0005] The purpose of this summary is to present a selection of features and concepts of the invention, which are further described in the following description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0006] According to the invention, the above problem is solved by the features of the independent claims.

[0007] Specifically, the problem is solved by a method for degradation diagnosis of a power electronic module. The power electronic module has a semiconductor device. The method includes providing an input signal of the power electronic module. The input signal has a large signal component. The large signal component is provided for turning on the power electronic module, preferably the semiconductor device. The method includes recording an output signal of the power electronic module, preferably the semiconductor device. The output signal of the power electronic module is based on the input signal. By recording the output signal, degradation diagnosis of the power electronic module can be achieved. In addition, the input signal includes a periodic signal component.

[0008] The invention has the advantage that the prerequisites are created for performing degradation detection or degradation diagnosis in a power electronic module having power electronic components such as semiconductor devices in a simpler and more cost-effective manner. This makes it possible to locate and thus determine the aging condition of individual components of the power electronic module.

[0009] For example, the large signal component of the input signal may be a DC signal, which corresponds to a DC voltage or a DC current. The periodic signal component may be a periodic small signal component. The periodic signal component may be a rectangular or sinusoidal signal component, preferably a small signal component. The periodic signal component of the input signal may be an AC signal, which corresponds to an AC voltage or an AC current. The input signal may substantially contain a large signal component and a periodic signal component. The amount of the large signal component may be greater than 2.5 times (or 5 times or 7.5 times) the amplitude of the periodic signal component. The size of the large signal component may be less than 25 times (or 20 times or 15 times) the amplitude of the periodic signal component. For example, the large signal component may be in the range of 7.5 times to 12.5 times the amplitude of the periodic signal component.

[0010] In one example, the large signal component may have a voltage in the range of 5V to 15V (or 7.5V to 12.5V). The input signal may have a voltage in the range of 3V to 17V (or 5V to 15V). The output signal may be a voltage signal that is offset in time relative to the input signal. The amplitude of the output signal may be greater than the amplitude of the input signal, for example, deviating by up to 2V (or 1V or 0.5V).

[0011] A power electronic module may be a circuit designed for high power or high voltage / high current, such as a rectifier, an inverter, a DC converter, an AC converter or a switch-mode power supply. A power electronic module may be suitable for converting electrical energy. For example, a power electronic module may be used as a converter or frequency converter, for example in the field of electric drive technology, solar inverters and converters for wind turbines, for feeding regeneratively generated energy into a grid or a switch-mode power supply unit.

[0012] The semiconductor device may have a bidirectional trigger diode, a bipolar power transistor, a power MOSFET, a thyristor, a GTO thyristor, an IGC thyristor, an MC thyristor, an IGBT, a bidirectional thyristor or a diode for rectification, or a freewheeling diode.

[0013] The power electronics module, preferably the semiconductor component, can modify an input signal in such a way that an output signal is generated which is different from the input signal and has a modified large-signal component and / or a periodic signal component.

[0014] The periodic signal component may be a continuous periodic signal such as a sinusoidal or rectangular signal. The periodic signal component may be specified by input phase information and associated input frequency information. Therefore, the periodic signal component may be a function of the input phase information and the associated input frequency information. Similarly, the output signal may include output phase information and associated output frequency information. The input frequency information may be substantially the same as the output frequency information, in particular the frequency information. In particular, the output phase information and the input phase information may represent a phase response associated with the frequency information. For example, degradation diagnosis may be performed by evaluating the phase response in particular according to the output phase information and the input phase information with associated frequency information. The amplitude response from the output signal and the input signal, in particular the amplitude of the output signal and the amplitude of the periodic signal component, may be ignored here. The output phase information, which is preferably frequency resolved with the associated frequency information, may be compared with the target output phase information for degradation diagnosis. The target output phase information may be based on a target output signal, which is obtained by providing a target input signal to a reference power electronic module. Here, the target input signal may correspond to the input signal or at least include the same periodic signal component.

[0015] Advantageous embodiments of the invention are indicated in the dependent claims.

[0016] The periodic signal component may be a chirp. The chirp may be provided by varying the frequency of the periodic signal component over time.

[0017] This enables frequency-adjusted measurements to be performed to check the degradation of various components of the power electronics module during one operation.

[0018] The chirp may have a frequency range between 0.1 mHz and 100 Hz. For example, the chirp may have a frequency greater than 0.1 mHz (or 0.5 mHz or 1 mHz). For example, the chirp may have a frequency less than 100 Hz (or 10 Hz or 1 Hz).

[0019] This enables the chirp to be tuned to the component to perform degradation diagnostics.

[0020] The large signal component of the input signal can ensure the on-state of the semiconductor device during the duration of the chirp. Therefore, as long as the chirp is fed to or modulated onto the power electronic module or the semiconductor device, the large signal component can ensure that the semiconductor device is turned on.

[0021] This enables the conduction losses to be effectively modulated onto the semiconductor device and provides a simple solution for degradation diagnostics.

[0022] An input signal may be provided at a control terminal of the semiconductor device. In this case, an input current may be applied to the control terminal, or an input voltage at least connected to the control terminal may be provided, such as an input voltage between the control terminal and a source terminal of the semiconductor element. An output signal may be recorded at a drain terminal of the semiconductor device. In this case, an output current may be recorded in the drain terminal or from the drain terminal to the source terminal (or from the source terminal to the drain terminal), or an output voltage at least connected to the drain terminal may be recorded, such as an output voltage between the drain terminal and the source terminal of the semiconductor element.

[0023] This enables a cost-effective and simple on-site implementation.

[0024] Corresponding to the technology of the semiconductor device, the terms control terminal, drain terminal and source terminal may be gate, drain and source or base, collector and emitter. However, no specific technology is explicitly mentioned here.

[0025] The method may further comprise determining degradation of one or more components. The one or more components may be associated with a power electronic module. Preferably, the one or more components are part of the power electronic module or components thereof. The determination may be performed by a frequency-resolved comparison (preferably within a frequency range) of the phase of the output signal with the phase of the input signal. The phase of the input signal may correspond to the phase of a periodic signal component of the input signal.

[0026] The degradation of the plurality of components associated with the power electronics module can be determined by a phase difference between an output signal and an input signal in a corresponding frequency sub-range that can be associated with the plurality of components associated with the power electronics module, preferably within a frequency range. The frequency sub-range can be different for different ones of the components associated with the power electronics module.

[0027] In simple terms, a power electronic module in operation may have a phase response (between an output signal and an input signal). The phase response during operation generated by the recorded output signal and the provided input signal may be referred to herein as an operating phase response. The operating phase response of the power electronic module may be different from, for example, a target phase response of the power electronic module in a state before commissioning of the power electronic module. By comparing the operating phase response with the target phase response, for example by comparing a curve between the operating phase response and the target phase response, the degradation of (individual) components of the power electronic module may be determined. For example, if the difference between the operating phase response and the target phase response in a predetermined frequency sub-range of the frequency range exceeds a threshold value (e.g., 0.1° or 0.25°), there may be degradation of the component associated with the predetermined frequency sub-range. The frequency sub-range may be less than 0.2 times (or 0.1 times) the bandwidth of the frequency range. For example, predetermined different frequency sub-ranges of the frequency range may be associated with components of the power electronic module. If the difference between the operating phase response and the target phase response in one or more predetermined frequency sub-ranges in the predetermined frequency sub-range exceeds a threshold value, there may be degradation in the component associated with one or more frequency sub-ranges.

[0028] The above problem is also solved by a computer program. The computer program comprises instructions, which, when executed by a computer or a controller, cause the computer or the controller to perform the above method or at least one of the steps of the method. The computer program may be, for example, a module for starting / running a power electronic module as described herein.

[0029] The above problem is also solved by a data carrier. The computer program can be stored on a machine-readable, processor-readable or computer-readable data carrier, for example on a permanent or rewritable storage medium. This also includes that the computer program can be provided on a server or cloud server for downloading, for example via a data network such as the Internet or a communication connection such as a wireless connection.

[0030] The above problem is also solved by a controller. The controller is used for degradation diagnosis of a power electronic module having a semiconductor device. The controller is suitable for providing an input signal of the power electronic module, preferably the semiconductor device, the input signal including a large signal component provided for turning on the semiconductor device. The controller is suitable for recording an output signal of the power electronic module, preferably the semiconductor device, based on the input signal, so as to enable degradation diagnosis of the power electronic module. The input signal includes a periodic signal component such as a sinusoidal or rectangular small signal component.

[0031] The controller may be implemented as a module and thus integrated into or attached to the power electronics module. This may result in a simple implementation option that is also cost effective.

[0032] The controller may be adapted to adjust the power to be delivered to the semiconductor device based on a result of a degradation diagnosis, the degradation diagnosis being performed based on a comparison of the output signal with the input signal.

[0033] The above problems are also solved by a power electronic module. The power electronic module has a semiconductor device. The power electronic module is suitable for receiving an input signal of the power electronic module, preferably the semiconductor device, the input signal including a large signal component provided for turning on the semiconductor device. The power electronic module is suitable for sending an output signal of the power electronic module, preferably the semiconductor device, based on the input signal, so as to enable degradation diagnosis of the power electronic module. The input signal includes a periodic signal component such as a sinusoidal or rectangular small signal component.

[0034] The power electronic module may have components such as a carrier, a substrate for thermally connecting a semiconductor device to the carrier, and a heat sink. The semiconductor device may be connected to the substrate via a solder connection. The heat sink may be connected to the carrier via a thermally conductive layer. The controller may be adapted to perform a degradation diagnosis of at least one of the components of the power electronic module.

[0035] The above problems can also be solved by a power electronic system. The power electronic system is used for degradation diagnosis and has the power electronic module as described above and the controller as described above.

[0036] Power electronic systems may form an integral part of a motor vehicle, a photovoltaic system or a wind turbine.

[0037] Thus, a complete system as well as modular components may be provided, enabling a more cost-effective implementation of degradation diagnostics without having to resort to temperature sensors.

[0038] In other words, the present invention relates to a new method for diagnosing various degradation or aging effects in power electronic modules (including power electronic modules) in a minimally invasive manner and without using expensive sensors. In particular, the present invention may relate to degradation diagnosis in power electronic modules by detecting the phase shift of the electrical response. Different degradation states affect the phase of the frequency response of the thermal impedance at certain frequencies. Therefore, at these frequencies, the phase shift between the semiconductor losses and the junction temperature is different for different degradation / aging effects.

[0039] In order to utilize the phase shift, the semiconductor losses and the junction temperature are determined in the previous methods. For this purpose, accurate loss calculations and temperature sensors with high bandwidth are used in the previous methods. Temperature-sensitive electrical parameters (TSEP) can be used here. However, these usually depend not only on temperature, but also on degradation, etc. Therefore, recalibration may be required for different degrees of degradation in the previous methods.

[0040] On the other hand, the method proposed here can use information about the phase of the thermal impedance without determining the thermal impedance itself. This means that both the temperature sensor and the loss calculation can be omitted. In order to indirectly determine the phase of the thermal impedance, periodic conduction losses with low frequency can be applied or influenced, for example, by means of (small) signal manipulation of the control electrode of the power semiconductor. In addition, the phase shift between the loss imprint and a temperature-dependent voltage (as TSEP), such as the forward voltage, can be measured. The phase shift can essentially be caused by the dynamic response of the thermal impedance, since the phase shift junction temperature affects the TSEP. Therefore, a change in the phase shift can identify the corresponding type of degradation.

[0041] In other words, (small) signal losses with different frequencies can be applied to the semiconductor device. A possible implementation of this can be to modulate the gate-source voltage of a transistor as a semiconductor device (e.g., SiC MOSFET) with a (small) signal excitation. Due to the dependence of the on-resistance on the gate-source voltage, the resulting drain-source voltage of the SiC MOSFET is also superimposed with this signal, preferably a small signal. In addition, the on-resistance can depend on the temperature. The temperature has a time-delayed reaction to changes in the conduction losses, which can be identified by the phase of the thermal impedance. This phase shift between the conduction losses and the temperature response can be affected by various aging mechanisms, such as changes in the thermal path between the semiconductor and the heat sink. Therefore, due to the temperature dependence of the on-resistance of the semiconductor device, the phase-shifted temperature signal can cause a phase shift between the gate-source voltage and the drain-source voltage. Alternatively, other voltages or currents that depend on the junction temperature of the semiconductor device under consideration can also be considered. Changes in the phase shift between the excitation signal and the temperature-dependent voltage / current at certain frequencies can indicate degradation in the power electronic module. The frequency at which the phase shift changes occur may enable the degradation phenomenon to be localized.

[0042] The (small) signal excitation of the gate-source voltage of the transistor as a semiconductor device can be used with Si MOSFET, IGBT and wide bandgap transistors such as GaN HEMT and SiC MOSFET. Using bipolar transistors as semiconductor devices, (small) signal excitation of the base current is possible. One possible implementation may be as follows: a periodic, for example sinusoidal or rectangular, gate-source voltage is adjusted via a digital-to-analog converter (DAC), and the digital-to-analog converter (DAC) is controlled by a microcontroller (e.g., as part of the controller described herein). The voltage measurement of the gate-source voltage and the drain-source voltage can be performed via a high-impedance voltage tap using a corresponding instrumentation amplifier. The tap voltage can be converted into a digital signal by an analog-to-digital converter (ADC). Prior to this, the tap voltage can be processed according to the requirements of the ADC, for example using a single-ended to differential amplifier and an anti-aliasing filter. The fundamental frequency of the two voltages can be determined using a fast Fourier transform. The phase information associated with the fundamental frequency can then be used to determine the phase shift.

[0043] Compared to previous methods, the method proposed here does not require accurate loss and temperature determination, including temperature sensors, which significantly simplifies the implementation in power electronic systems and makes the implementation more cost-effective. For example, the method can be used by module manufacturers to test their modules before they are sold. The method can also be used for predictive maintenance of power components in difficult to access locations, such as offshore wind turbines.

[0044] Thermomechanically induced degradation modes such as fatigue of conductive electronic components such as solders and thermal interfaces can be identified, for example, without monitoring changes in thermal response, and correlated to local degradation modes. This eliminates the need for methods that simply stamp periodic losses into the semiconductor and extract the junction temperature response using TSEP. In particular, the magnitude of thermal impedance and phase changes can be correlated to degradation modes with peak sensitivity at the excitation frequency.

[0045] Compared to the present invention, previous thermal impedance spectroscopy has the following disadvantages: 1) when performed using TSEP, the required accurate temperature measurement is complex and expensive because it requires high bandwidth measurement of electrical parameters; 2) accurate calculation or measurement of component losses is difficult to achieve; and 3) most TSEPs are affected by component degradation, thereby requiring recalibration at different degrees of degradation.

[0046] Although some of the aspects described above relate to methods, power electronics modules or power electronics systems, these aspects may also apply in a corresponding manner to other aspects thereof.

[0047] In one example, the power electronic system, the power electronic module and / or the controller can be implemented using a hardware circuit system, a software device or a combination thereof. For example, such as when multiple functions are implemented in software, multiple units of the power electronic system, the power electronic module and / or the controller can each be implemented in a single physical unit. The units of the power electronic system, the power electronic module and / or the controller can also be implemented in hardware components. The units of the power electronic system, the power electronic module and / or the controller should each be understood as functional units that do not have to be physically separated from each other. For example, the power electronic system, the power electronic module and / or the controller can be implemented at least in part as a computer, a field programmable logic array (FPLA), a field programmable gate array (FPGA), a microcontroller, a CPU (e.g., with multiple cores), a graphics processing unit (GPU), an application specific integrated circuit (ASIC) and / or a digital signal processor (DSP).

[0048] All technical and scientific terms used herein have meanings corresponding to the general understanding of a person skilled in the art of power electronics technology; these terms are to be interpreted based on definitions found in dictionaries or technical terms related to this technical field. If technical terms are used incorrectly here and thus do not express the technical idea of ​​the present invention, they may be replaced by technical terms that convey the correct understanding to a person skilled in the art.

[0049] If it is meant that a certain component is "connected" to another component in the present case, for the purpose of the present disclosure, this may mean that these components may also be directly connected to each other. The term "directly" indicates that there are no other components in between.

[0050] Unless otherwise explicitly or implicitly indicated, for example if these method steps cannot be interchanged for technical reasons, the method steps described herein should not be interpreted herein as having to be performed in any particular order. The method steps may also be performed directly one after another (without additional intermediate steps) and / or continuously. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In the following description of the embodiments, with reference to the associated drawings, further objects, features, advantages and possible applications are shown, which description should not be understood as limiting. The same or similar elements in the drawings are always marked with the same or similar reference numerals. As long as the detailed description of known functions and structures has a negative impact on the present invention, they are omitted.

[0052] The accompanying drawings show:

[0053] Figure 1 Schematic representation of the power electronics system;

[0054] Figure 2 Schematic representation of the method used for degradation diagnosis;

[0055] Figure 3 Schematic representation of the controller;

[0056] Figure 4 Control block diagrams for degradation diagnostics; and

[0057] Figure 5 Frequency resolved phase plot. DETAILED DESCRIPTION

[0058] Methods, power electronic systems, power electronic modules and controllers will be described with respect to embodiments. Without limitation thereto, specific details are set forth to provide a deeper understanding of the present invention.

[0059] Figure 1 1 shows a schematic representation of a power electronic system 1. The power electronic system 1 has a power electronic module 2 having a semiconductor device 3. The semiconductor device has a control terminal 4, a drain terminal 5 and a source terminal 6. In the following, it is assumed that the semiconductor device 3 is a MOSFET, such as a SiC MOSFET. GS and the drain-source voltage v ds The measurements are made in such a way that the conduction losses are modulated (see Figure 4 ). The power electronic module 2 to be tested can be connected to a heat sink on the underside of the semiconductor device 3, for example. The electrical contacts of the power electronic module 2 are connected to a circuit board of other circuit elements 7 to 14 of the power electronic system 1. The power electronic system 1 also has a controller 7 for dynamically adjusting the gate-source voltage v of the semiconductor device 3 via a digital-to-analog converter (DAC) 8, for example a 12-bit digital-to-analog converter IC. GS .

[0060] The gate-source voltage and the drain-source voltage are determined via respective measuring units 9, 10 and 12, 13 and analog-to-digital converters (ADC 11, 14). One or more of these elements 9 to 14 may also be part of the controller 7 or integrated in the controller 7. For a better understanding, these are listed separately. Figure 1 1 and 13. Here, in the measurement unit associated with the drain-source voltage, the first instrumentation amplifier 9 is connected upstream of the first anti-aliasing filter 10, and the output of the first anti-aliasing filter 10 is connected to the first ADC 11. In the measurement unit associated with the gate-source voltage, the second instrumentation amplifier 12 is connected upstream of the second anti-aliasing filter 13, and the output of the second anti-aliasing filter 13 is connected to the second ADC 14.

[0061] As a further option, the corresponding measuring unit can also be divided into three parts: The voltage to be measured (gate-source or drain-source) is connected to the power electronic module 2 via an instrumentation amplifier with high input impedance. A single-ended to differential amplifier with a cascaded operational amplifier can then convert the voltage into a differential signal, which can be converted into a digital signal by, for example, a 24-bit sigma-delta ADC of the controller 7 after it has been filtered by an anti-aliasing filter.

[0062] For example, in both alternatives, the voltage can be tapped via the gate-source and drain-source with high impedance.

[0063] The controller 7 determines the gate-source voltage by adjusting the output voltage of the DAC 8, for example, via a serial peripheral interface (SPI). The output voltage can be connected to an instrumentation amplifier that converts the output voltage into a gate-source voltage in the range of -5V to 20V. The modulation of the gate-source voltage is achieved by generating a periodic voltage, such as a sine wave voltage or a square wave voltage, with a variable sampling frequency at the output of the DAC 8. The variable update frequency is selected so that the number of sampling points per cycle remains constant. The advantage of this method is that the value of the periodic voltage cycle can be stored on the controller 7 and does not have to be calculated in real time. The frequency of updating the gate-source and drain-source voltage values ​​via the DAC 8 corresponds to the sampling frequency of the ADC 11 and 14. The time-resolved voltage values ​​and / or frequency-resolved voltage values ​​recorded via the ADC 11 and 14 can be transmitted to an external computer for evaluation.

[0064] In post-processing, a Fast Fourier Transform (FFT) can be used to determine the gate-source voltage v GS and the drain-source voltage v ds The phase information of the fundamental frequency is then used to determine the gate-source voltage v GS and the drain-source voltage v ds The phase shift between .

[0065] When this method is executed, the MOSFET can remain permanently turned on and can conduct any drain-source current i (ds)， For example, about 5 A, which is only constant in certain cases. A periodic, preferably sinusoidal or rectangular (low) signal voltage v with variable frequency and an amplitude of 1 V ac Modulated to a constant gate-source voltage V of 10V 0Each frequency is applied to the gate for half or a whole period, such as a sine wave or square wave period. For example, integer period components or integer divisors of the period (e.g. 1 / 2, 1 / 3, 1 / 4, ... 1 / 8) can be used. Here, the method is not limited to a single oscillation such as a sine wave or a square wave, but a method for modulation can be used in which a periodic, such as a sinusoidal or rectangular, (low) signal voltage v ac Having several frequencies, the entire or several frequency ranges within the frequency ranges described herein. This can reduce the time required.

[0066] The bandwidth (also called frequency subrange) over which the thermal impedance change occurs provides information about where the aging effects are in the thermal path. The closer the aging effects are to the device, the higher the frequency to consider.

[0067] Reference Figure 1 , Figure 2 A schematic representation of a method S0 for degradation diagnosis of a power electronic module 2 having a semiconductor device 3 is generally shown. The method S0 comprises providing S1 an input signal of the power electronic module 2, the input signal comprising a large signal component intended to turn on the semiconductor device 3. The method S0 also comprises recording S2 an output signal of the power electronic module 2 based on the input signal to achieve degradation diagnosis of the power electronic module 2. The input signal comprises a periodic, e.g. sinusoidal or rectangular, (small) signal component. To this end, the degradation of one or more components associated with the power electronic module 2 is optionally determined by a frequency-resolved comparison of the phase of the output signal with the phase of the input signal.

[0068] For example, Figure 2 The method steps shown in the blocks of the block diagram in FIG. 1 can be substantially mapped in a machine-readable data carrier, a processor-readable data carrier or a computer-readable data carrier and thus by, for example, the following description of Figure 3 The computer or processor described herein executes. The example may also be or relate to a computer program comprising a program for executing when the computer program is executed on a computer or processor. Figure 2 The program code of at least a part of the method steps. For example, the following also Figure 3 As described, the examples may also have volatile memory or permanent storage that is machine-readable, processor-readable, or computer-readable and encodes a machine-executable, processor-executable, or computer-executable program with instructions that cause some or all of the method steps to be performed.

[0069] Figure 3 A schematic representation of a controller in the form of a computer is shown. The controller 7 implements the following Figure 2In particular, the controller 7 provides functionality, such as computer software, that runs on the controller 7 and executes one or more steps of the method. In particular, the controller 7 can execute instructions that are associated with input signals and / or output signals included in the computer program described herein and cause the controller 7 to execute one or more steps of the method.

[0070] It is provided herein that the controller 7 takes any suitable physical form. As an example, the controller 7 may be adapted, at least in part, to be an embedded computer, a microcontroller, a system on a chip (SOC) and / or a single board computer (SBC). The controller 7 may be integral or distributed, or may span one or more locations. The controller 7 may perform one or more steps of the method without significant spatial or temporal limitations. As an example, the controller 7 may perform one or more steps of the method in real time, in parallel, or in batch mode. The controller 7 may perform the steps of the method at different times or locations.

[0071] The controller 7 has at least one or more of the following components: a processor 15, a volatile memory 16, a permanent storage device 17 having an NVM controller 18 and a non-volatile memory device (NVM) 19, a bus 20, an arbiter 21, a communication interface 22, a power terminal 23, a main power supply 24, and an auxiliary power supply 25. The components of the controller 7 may be implemented at least partially in hardware and / or software. For simplicity only, the interconnection of the components of the controller 7 is shown as follows. Figure 3 In particular, the wiring and connections may differ in implementation due to signal processing and signaling.

[0072] The processor 15 has means for executing instructions, which are associated with input signals / output signals of, for example, a computer program described herein. For example, the processor 15 may load instructions associated with input signals / output signals included in the computer program described herein, for example, from the volatile memory 16 and / or the permanent storage device 17, and then execute these instructions, which in turn causes the processor 15 to perform, for example, Figure 2One or more steps of the method shown. The processor 15 may have an internal register / cache for data based on the input signal / output signal, for instructions associated with the data based on the input signal / output signal, and / or for associated addresses. The processor 15 may have an FPLA, FPGA, microcontroller, CPU, GPU, ASIC, and / or DSP for accessing the internal register / cache. As an example, in order to execute an instruction associated with the input signal / output signal, the processor 15 may retrieve the instruction from the internal register / cache of the processor 15, the volatile memory 16, or the permanent storage device 17; decode the instruction and execute the instruction; and then write the result to the internal register / cache of the processor 15, the volatile memory 16, or the permanent storage device 17.

[0073] As an example, the processor 15 may have an instruction cache, a data cache, and / or a translation buffer (TLB). The instructions in the instruction cache related to the input signal / output signal may be a copy of the instructions in the volatile memory 16 and / or the permanent storage device 17, and the instruction cache may accelerate the retrieval of these instructions related to the input signal / output signal by the processor 15. The data based on the input signal / output signal in the data cache may be a copy of the data of the instruction currently executed on the processor 15 and related to the input signal / output signal in the volatile memory 16 and / or the permanent storage device 17. The result of the previous instruction executed on the processor 15 and related to the input signal / output signal may be provided for access by the subsequent instruction to be executed on the processor 15 and related to the input signal / output signal, or for writing to the volatile memory 16 and / or the permanent storage device 17. The data cache may accelerate the read or write operation of the processor 15. The address related to the input signal / output signal in the TLB may be an address reference to an address in the volatile memory 16 and / or the permanent storage device 17 to accelerate the virtual address translation of the processor 15.

[0074] The volatile memory 16 may be a dynamic RAM (DRAM) or a static RAM (SRAM). In particular, the volatile memory 16 may be adapted to be a data carrier described herein on which the computer program described herein may be stored at least temporarily. In addition, the volatile memory 16 may be a single-channel or multi-channel RAM. The volatile memory 16 may have a main memory to store instructions related to input signals / output signals for the processor 15, which are then executed by the processor 15; or to store data based on input signals / output signals for the processor 15 to operate. As an example, the controller 7 may load these instructions from a permanent storage device 17 or another source (e.g., another computer, a network, or a cloud) into the volatile memory 16. The processor 15 may then load these instructions from the volatile memory 16 into the internal registers / cache of the processor 15. In order to execute these instructions, the processor 15 may extract these instructions from the corresponding internal registers / cache and decode them. During or after the execution of these instructions, the processor 15 may write the results (which may be intermediate results or final results) to the internal registers / cache. Processor 15 may then write the result to volatile memory 16 .

[0075] For example, the processor 15 executes only instructions related to the input signal / output signal in the internal register / cache of the processor 15 or in the volatile memory 16 (as opposed to the permanent storage device 17), and operates only on data based on the input signal / output signal in the internal register / cache of the processor 15 or in the volatile memory 16 (as opposed to the permanent storage device 17). A memory management unit (MMU-not shown) may be located between the processor 15 and the volatile memory 16, and may support access to the volatile memory 16 requested by the processor 15 in association with the input signal / output signal.

[0076] The volatile memory 16 may be a memory shared by the processor 15 and the communication interface 22. Thus, the communication interface 22 accesses the shared volatile memory 16 via the processor 15. For example, the communication interface 22 may not include a built-in memory. Here, the communication interface 22 may share the volatile memory 16 connected to the processor 15. The processor 15 may have a memory access path that enables access to the shared volatile memory 16 associated with the input signal / output signal. The communication interface 22 accesses the shared volatile memory 16 via the memory access path of the processor 15. The communication interface 22 is able to access the shared volatile memory 16 associated with the input signal / output signal when the memory access path is activated and the processor 15 is not activated. Here, the memory access path is activated without the intervention of the processor 15. When the processor 15 and the communication interface 22 are not activated, the memory access path is closed. When the memory access path is closed and the communication interface 22 is activated, once a request to pair the memory access path with the processor 15 is received, the memory access path is opened without the intervention of the processor 15.

[0077] The permanent storage device 17 has a large-capacity storage device, such as a non-volatile memory (NVM) 19 for data based on input signals / output signals or instructions related to input signals / output signals. In particular, the permanent storage device 17 can be adapted to be a data carrier described herein on which the computer program described herein can be stored. As an example, the permanent storage device 17 can be a solid-state storage device (SSD), a flash memory, a non-volatile memory card, a secure digital memory card (SD), an embedded multimedia card (eMMC) and / or a universal serial bus (USB). The permanent storage device 17 can store data based on input signals / output signals in an erasable or non-erasable manner. The permanent storage device 17 can be located in the controller 7, that is, inside the controller 7 or outside the controller 7. The permanent storage device 17 can have an NVM controller 18, which supports communication for transferring data based on input signals / output signals between the processor 15 and the permanent storage device 17 (particularly the NVM 19 of the permanent storage device 17).

[0078] The bus 20 can be understood in this context as a subsystem of the controller 7 that transmits data and / or power based on input / output signals between components of the controller 7. A bus 20 can connect components of the controller 7 via the same set of wiring. The bus 20 can be adapted for dedicated communication of data based on input / output signals between two or more of the components of the controller 7. The bus 20 can have a ring topology, a star topology, a (partial) mesh topology, a bus topology, a tree topology, and / or a line topology. The bus 20 can have one or more of the following bus types: Accelerated Graphics Port (AGP), HyperTransport (HT), Industry Standard Architecture (ISA), Peripheral Component Interconnect (PCI), PCI-Express (PCIe), Serial Advanced Technology Attachment (SATA), and / or INFINIBAND.

[0079] The bus 20 can be a system bus via which the processor 15 is connected to other components of the controller 7. Here, the bus 20 can be synchronous - the transmission of data based on input / output signals occurs bidirectionally with the clock edges of the clock of the bus 20 - and / or can be asynchronous - without a clock but with handshaking occurring to transmit data based on input / output signals. In such a semi-synchronous system bus, the bus 20 is timed, but control lines allow wait cycles in order to also use slow components such as the permanent storage device 17 via the bus 20.

[0080] An arbiter 21 can be provided for at least partial control of the bus 20. The arbiter 21 can be understood as a coprocessor attached to the processor 15. Based on a two-way handshake or a three-way handshake, the arbiter 21 controls access to the bus 20 associated with input / output signals. For this purpose, three signal buses are used: a bus request (BREQ) for forwarding data based on input / output signals, a bus grant (BGRT) for acknowledging and approving the forwarding, and a bus grant acknowledgment (BGA) for optionally forwarding feedback.

[0081] The arbiter 21 receives several BREQs from different components of the controller 7 via the bus 20 at the same time. The arbiter 21 sorts the BREQs according to the priority and forwards them sequentially in the pipeline to the processor 15. Once the processor 15 has received the BREQ, the processor 15 sends a BGRT to the arbiter 21 or directly to the component of the controller 7 that transmits the BREQ. In response to the BGRT sent by the processor 15 about the BREQ with priority in the pipeline and related to at least a part of the data based on the input signal / output signal, a lower priority BREQ in the BREQ in the pipeline, for example, from another component of the controller 7, is forwarded to the processor 15. After processing at least a part of the data based on the input signal / output signal, the BGRT associated with the lower priority BREQ is transmitted from the processor 15 to the arbiter 21. For example, the arbiter 21 may respond to the BGRT associated with the lower-ranked BREQ and then transmit another lower-ranked BREQ in the pipeline of BREQs to the processor 15 (the other lower-ranked BREQ, for example, is related to another part of the data based on the input signal / output signal). Similarly, in response to each BGRT from the processor 15, the arbitrator 21 may send the corresponding BGA associated therewith to the processor 15. In the process described herein, the BGA may also be omitted entirely. This saves the overhead of communication between components of the controller 7, i.e., a two-way handshake is provided instead of a three-way handshake.

[0082] The bus 20 may also have a data bus, an address bus, and a control bus. In this case, data based on the input signal / output signal is bidirectionally transmitted between the components of the controller 7 via the data bus. The address bus is operated only by the processor 15, and unidirectionally transmits a memory address related to the input signal / output signal. The control bus is controlled only by the arbiter 21, for example, in the sense of a monitor, and transmits its control to the processor in a pipeline-like manner as described above, so as to control the transmission of data based on the input signal / output signal.

[0083] The communication interface 22 enables the controller 7 to communicate with a network, for example with at least a part of an ad hoc network, a wireless personal area network ((W)PAN) (e.g. Bluetooth WPAN), a local area network (LAN), a WI-FI network, a WI-MAX network, a mobile radio system (e.g. 4G, 5G or 6G) and / or the Internet. In particular, the communication interface 22 can use this to forward data based on the input signal / output signal to an evaluation unit. The communication interface 22 can also provide a direct and / or fixed connection to an evaluation unit (e.g. a PC).

[0084] The power terminal 23 may be arranged at a dedicated connection point on the housing of the controller 7. The power terminal 23 may represent a central power supply point for components of the controller 7 (but also of the power electronics module 2) and connects the controller 7 or its components (preferably the main power supply 24) to an external power source (external to the controller 7). In the case of an integrated main power supply 24, the power terminal 23 may also be an integrated component of the controller 7 or the main power supply 24.

[0085] The main power supply 24 supplies power to at least one or more of the components of the controller 7, for example, via the bus 20. In particular, for example, in the case where the main power supply 24 is connected to a power source external to the controller 7, the main power supply 24 charges the auxiliary power supply 25 with power, for example, from outside the controller 7. Here, the main power supply 24 may represent a preferred component for supplying power to the components of the controller 7, and has, for example, a battery or a battery. The main power supply 24 may have additional components, such as a voltage regulator, a DC voltage stabilizer, a series regulator, a buck converter and / or a boost converter, to meet the corresponding requirements of the components of the controller 7. Here, the power terminal 23 may have a dedicated fixed power supply connection to an external power source such as a power grid, or may have a detachable power supply connection for charging the battery or battery of the main power supply 24. To this end, the main power supply 24 may have an inverter to provide a predetermined DC power supply from an AC power source connected via the power terminal 23 as an external power source. A predetermined DC power supply may also be provided from a DC power source connected via the power terminal 23 as an external power source. The DC power supply may be controlled by the above-mentioned voltage regulator and supplied to components of the controller 7 as a set DC power supply.

[0086] The auxiliary power supply 25 is connected to the volatile memory 16 and / or the permanent storage device 17 via the bus 20. The auxiliary power supply 25 is charged by the power of the main power supply 24. The auxiliary power supply 25 can be located inside or outside the controller 7, or inside or outside the volatile memory 16 and / or the permanent storage device 17. For example, the auxiliary power supply 25 can be accommodated on the main board of the controller 7 so as to supply auxiliary power to the volatile memory 16 and / or the permanent storage device 17. In particular, the auxiliary power supply 25 can be implemented in the form of a supercapacitor, a storage battery and / or a battery. The power capacity / energy capacity of the main power supply 24 can be many times larger than the power capacity / energy capacity of the auxiliary power supply 25, for example at least 10 times or 50 times larger.

[0087] The processor 15 monitors changes in the power supplied by the main power supply 24. In the event of a sudden power failure, such as when a power source external to the controller 7 is disconnected from the main power supply 24 or the main power supply 24 is degraded or fails for some other reason, and the processor 15 determines that the power supplied by the main power supply 24 to one or more of the components of the controller 7 has dropped below a threshold, such as 0.8 or 0.75 of the operating power of the main power supply 24, the processor 15 disconnects the auxiliary power supply 25 from the main power supply 24. The processor 15 causes the auxiliary power supply 25 to take over the remaining supply power for the shutdown operation of the controller 7. The shutdown operation includes supplying power to at least the processor 15, the volatile memory 16, and / or the permanent storage device 17 by electrical power during the time of the shutdown operation. During the shutdown process, data based on input signals / output signals currently in the volatile memory 16 and / or data based on input signals / output signals currently being processed in the processor 15 (e.g. in registers / cache of the processor 15) are transferred from the volatile memory 16 and / or the processor 15 to the meta area of ​​the permanent storage device 17. For this purpose, the meta area of ​​the permanent storage device 17 can remain available, in particular for the shutdown process.

[0088] In the case of a startup operation of the controller 7, the processor 15 loads data based on the input signals / output signals from the meta area of ​​the permanent storage device 17, wherein the main power supply 24 again provides operating power in order to achieve faster data processing. After the startup process or subsequently during the startup process, the meta area of ​​the permanent storage device can be released.

[0089] Figure 4 A control block diagram for degradation diagnosis is shown. The block diagram illustrates the method proposed in this paper. In order to diagnose the degradation of the power electronic module 2, the periodic conduction losses in the semiconductor device are excited. In the example of a MOSFET, these conduction losses can be calculated as where v ds is the forward voltage (drain-source voltage), R DS,on is the on-resistance, and i ds is the drain-source current of the MOSFET. To generate periodic conduction losses within the device, the on-resistance R DS,on The on-resistance of the MOSFET is R DS,on Depends on the gate-source voltage v GS and junction temperature T j On-resistance R DS,on The modulation can therefore be achieved by the gate-source DC voltage V 0 A periodic, preferably sinusoidal or rectangular gate-source AC voltage v is superimposed on ac to achieve.

[0090] On-resistance R DS,on This periodic excitation leads to conduction losses P cond and the drain-source voltage v ds The periodic (small) signal modulation, the conduction loss P cond and the drain-source voltage v ds Both are relative to v for low frequencies GS With a constant phase delay of 180°. Figure 4 In simplified form, the thermal resistance R th and heat capacity C th Thermal impedance Z th (jω) describes the junction temperature T j How to respond to periodic loss excitation in terms of magnitude and phase. In addition to affecting the on-resistance R DS,on The gate-source voltage v GS In addition, the junction temperature T j This also results in a drain-source voltage v ds Therefore, when the degradation affects the thermal impedance Z th (jω) phase, for example, due to the total R th The change of drain-source voltage v ds Therefore, the gate-source voltage v GS and the drain-source voltage v ds The change in phase shift between indicates the change in thermal impedance phase ∠ Z(th) (jω), which occurs when the characteristics of the heat dissipation path change due to changes in degradation modes or convection conditions. Therefore, the proposed method is able to detect different degradation modes separately by focusing on the phase delay at different frequencies, because different degradation modes leave traces at bandwidths that can be clearly determined.

[0091] Figure 5 A frequency resolved phase diagram with corresponding phase responses F1 to F3 is shown for a better understanding of the method. Here, Figure 5 The three phase responses F1 to F3 at the top differ in that a small change of the thermal path below the semiconductor device 3 is artificially introduced. In this example, the heat conducting layer of the heat sink of the power electronic module 2 is removed by a small amount F2 and all F3 in order to map the degradation effects. Such degradation effects below the power electronic module 2 can be identified by the phase of the thermal impedance in the millihertz range. The frequencies of the (low) signals in the range of 1 mHz to 5 Hz are particularly suitable for this purpose.

[0092] At this point it should be noted that all the components described above are considered essential to the invention both individually and in any combination, in particular the details shown in the drawings, variations of which will be familiar to those skilled in the art.

[0093] Reference numerals list

[0094] 1 Power Electronics System

[0095] 2 Power Electronics Module

[0096] 3 Semiconductor devices

[0097] 4 Control terminals

[0098] 5 Drain terminal

[0099] 6 source terminal

[0100] 7 Controller

[0101] 8 DAC

[0102] 9. First Instrumentation Amplifier

[0103] 10 First anti-aliasing filter

[0104] 11. First ADC

[0105] 12 Second instrumentation amplifier

[0106] 13 Second anti-aliasing filter

[0107] 14 Second ADC

[0108] 15 Processor

[0109] 16 Volatile Memory

[0110] 17 Permanent storage device

[0111] 18 NVM controller

[0112] 19 NVM

[0113] 20 Bus

[0114] 21 Arbitrator

[0115] 22 Communication Interface

[0116] 23 Power Terminals

[0117] 24 Main power supply

[0118] 25 Auxiliary power supply

[0119] Phase response of F1 without degradation

[0120] Phase response of F2 in the first type of degradation

[0121] Phase response of F3 in the second type of degradation

[0122] V 0 Gate-source DC voltage

[0123] v ac Gate-source AC voltage

[0124] v GS Gate-source voltage

[0125] R DS,on On-resistance

[0126] T j Junction temperature

[0127] v ds Drain-Source Voltage

[0128] i ds Drain-Source Current

[0129] P cond Power loss

[0130] C th Heat capacity

[0131] R th Thermal resistance

Claims

1. A method (S0) for degradation diagnosis of a power electronic module (2), the power electronic module (2) having a semiconductor component (3), the method (S0) include: Providing (S1) an input signal (v GS ), the input signal (v GS ) includes a large signal component (V 0 ); Record (S2) the power electronic module (2) based on the input signal (v GS ) output signal (v ds ) to enable degradation diagnosis of the power electronic module (2); Among them, the input signal (v GS ) includes periodic signal components (v AC ).

2. The method according to claim 1 (S0), in, The periodic signal component (v AC ) is obtained by changing the periodic signal component (v AC ) frequency and provide a chirp of (S1).

3. The method (S0) according to claim 2, in, The chirp has a frequency range between 0.1 mHz and 100 Hz.

4. The method (S0) according to claim 3, in, The input signal (v GS ) ensures the on-state of the semiconductor device (3) during the duration of the chirp.

5. The method (S0) according to one of the preceding claims, in, Through the output signal (v ds ) is in phase with the input signal (v GS ) is used to determine (S3) degradation of one or more components associated with the power electronic module (2) by frequency-resolved comparison of the phase of the power electronic module (2).

6. The method (S0) according to claim 5, in, By adjusting the output signal (v) in a corresponding frequency sub-range that can be associated with a plurality of components associated with the power electronic module (2), ds ) and the input signal (v GS ) are used to determine the degradation of the multiple components associated with the power electronic module (2), and the frequency sub-ranges are different for different components among the components associated with the power electronic module (2).

7. A computer program, in, The computer program comprises instructions which, when executed by a computer or a controller (7), cause the computer or the controller (7) to perform or initiate the method (S0) or at least one of the steps of the method (S0) according to one of the preceding claims.

8. A data carrier (C42, C43, C45), in, A computer program according to claim 7 is stored on the data carrier (C42, C43, C45).

9. A controller (7) for degradation diagnosis of a power electronic module (2), the power electronic module (2) having a semiconductor device (3), the controller (7) being adapted to: Providing the input signal (v GS ), the input signal (v GS ) includes a large signal component (V 0 ); Recording the power electronic module (2) based on the input signal (v GS ) output signal (v ds ) to enable degradation diagnosis of the power electronic module (2); in, The input signal (v GS ) includes periodic signal components (v AC ).

10. A power electronic module (2) having a semiconductor device (3), in, The power electronic module (2) is suitable for: Receive (S1) an input signal (v GS ), the input signal (v GS ) includes a large signal component (V 0 ); Transmitting (S2) the power electronic module (2) based on the input signal (v GS ) output signal (v ds ) to enable degradation diagnosis of the power electronic module (2); Among them, the input signal (v GS ) includes periodic signal components (v AC ).

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