Resistive random access memory integrated by hybrid bonding

Abstract

The embodiment of the invention provides a memory device and a method for executing write operation in the memory device. The memory device includes: a memory chip including a plurality of memory cells fabricated at a first process node; and a control chip including a control circuit fabricated in a second process node, the first process node being more advanced than the second process node. Wherein the control chip and the memory chip are bonded together to form the memory device, and the control circuit is used for controlling the operation of the plurality of memory units in the memory chip.

Description

Technical Field

[0001] The present invention generally relates to a method for manufacturing a novel resistive random access memory chip, and more specifically to a method for manufacturing a resistive random access memory chip using heterogeneous integration. Background Art

[0002] Resistive random access memory (RRAM) is a non-volatile memory that can switch its resistance between a low resistance state (LRS) and a high resistance state (HRS) by applying a suitable voltage to the memory. The resistance difference between the low resistance state and the high resistance state can be used to store digital data "0" and "1".

[0003] In a general RRAM memory integrated circuit, various peripheral circuits are formed along the RRAM array, and the memory array and the peripheral circuits are manufactured using the same process node. However, this is not the best practice because only the memory array needs to be manufactured using the most advanced process technology to achieve high density, while the peripheral circuits can be manufactured using more mature (lower cost) process nodes. Summary of the invention

[0004] In order to solve the above problems, according to an embodiment of the present invention, a dual-chip solution using heterogeneous integration is provided.

[0005] According to a first aspect of the present invention, there is provided a memory device, comprising: a memory chip, the memory chip comprising a plurality of memory cells manufactured at a first process node; and a control chip, the control chip comprising a control circuit manufactured at a second process node, wherein the first process node is more advanced than the second process node, wherein the control chip and the memory chip are bonded together by hybrid bonding integration technology to form the memory device, and the control circuit is used to control the operation of the plurality of memory cells within the memory chip.

[0006] In another embodiment of the present invention, the control circuit further includes a multiplexer for controlling a source line or a bit line of the memory cell.

[0007] In another embodiment of the present invention, the memory chip does not include a multiplexer for controlling source lines or bit lines of the memory cells.

[0008] In another embodiment of the present invention, the control circuit further comprises a decoder for controlling a word line of the memory cell.

[0009] In another embodiment of the present invention, the memory chip does not include a decoder for controlling word lines of memory cells.

[0010] In another embodiment of the present invention, the control circuit further includes a sense amplifier for amplifying a signal from the memory cell.

[0011] In another embodiment of the present invention, the control circuit further comprises a charge pump for generating a voltage required for programming the memory cell.

[0012] In another embodiment of the present invention, the control chip further includes a processor.

[0013] In another embodiment of the present invention, the control chip further includes an analog circuit.

[0014] In another embodiment of the present invention, the control chip further includes a transmitter.

[0015] In another embodiment of the present invention, the control chip further includes a sensor.

[0016] In another embodiment of the present invention, the gate length of the transistor in the memory chip is smaller than the gate length of the transistor in the control chip.

[0017] In another embodiment of the present invention, the memory chip includes only one type of transistors, and the control chip includes multiple types of transistors.

[0018] In another embodiment of the present invention, the memory chip includes only NMOS transistors.

[0019] In another embodiment of the present invention, the memory chip includes only PMOS transistors.

[0020] In another embodiment of the present invention, each memory cell includes a memory element formed on a substrate.

[0021] In another embodiment of the present invention, the memory element is selected from the group consisting of: a resistive random access memory (RRAM) element; a conductive bridging random access memory (CBRAM) element; a magnetoresistive random access memory (MRAM) element; a ferroelectric random access memory (FeRAM) element; and a phase change random access memory (PCRAM) element.

[0022] In another embodiment of the present invention, each memory cell includes a resistive memory element formed on a substrate.

[0023] In another embodiment of the present invention, the memory cell includes: an access transistor formed on the substrate; a contact; a first metal layer; a bottom electrode; the resistive memory element; a first via; and a second metal layer, wherein the contact is arranged between a terminal of the access transistor and the first metal layer, the bottom electrode is arranged between the first metal layer and the resistive memory element, and the first via is arranged between the resistive memory element and the second metal layer.

[0024] In another embodiment of the present invention, the top surface of the memory chip includes a plurality of first conductive pads and a first insulating region, and the top surface of the control chip includes a plurality of second conductive pads and a second insulating region.

[0025] In another embodiment of the present invention, the first conductive pad is bonded to the second conductive pad, and the first insulating region is bonded to the second insulating region.

[0026] In another embodiment of the present invention, the multiple first conductive pads are connected to the second metal layer in the memory chip through multiple memory chip vias, and the multiple second conductive pads are connected to the second metal layer in the control chip through multiple control chip vias, wherein the multiple memory chip vias have the same length.

[0027] In another embodiment of the present invention, before performing a write operation on the memory cell, the control circuit is used to perform a read operation on the memory cell.

[0028] In another embodiment of the present invention, before performing a write operation on the memory cell, the control circuit is used to compare the data to be written with the read operation result.

[0029] In another embodiment of the present invention, the control circuit is used to perform the write operation only when the data to be written does not match the read operation result.

[0030] According to a second aspect of the present invention, a method for performing a write operation in a memory device is provided, wherein the memory device comprises: a memory chip, the memory chip comprising a plurality of memory cells manufactured at a first process node; and a control chip, the control chip comprising a control circuit manufactured at a second process node, wherein the first process node is more advanced than the second process node, wherein the control chip and the memory chip are bonded together to form the memory device, wherein the control circuit is used to control the operation of the plurality of memory cells in the memory chip, the method comprising: receiving, by the control chip, an address of a memory cell in the memory chip and data to be written to the memory cell; performing a read operation on the memory cell; and after the read operation, performing a write operation on the memory cell.

[0031] In another embodiment of the present invention, the method further comprises: before performing the write operation on the memory unit, comparing the to-be-written data with the read operation result.

[0032] In another embodiment of the present invention, performing a write operation on the memory cell after the read operation includes: after the read operation, performing a write operation on the memory cell only when the to-be-written data does not match the read operation result.

[0033] In the present invention, the memory chip is manufactured at an advanced process node, while the control chip is manufactured at a mature node. The two chips are then combined together through three-dimensional integration techniques such as hybrid bonding to form a fully functional memory chip.

[0034] According to the embodiments of the present invention, only the memory cells are manufactured at advanced process nodes, while the peripheral circuits are manufactured at mature nodes, thereby significantly reducing the cost of the memory chip and increasing the density of the memory cells at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Embodiments of the present invention will be more easily understood by referring to the following drawings.

[0036] FIG. 1A is a schematic diagram of a common memory device architecture in the industry.

[0037] Figure 1B Schematic diagram of a novel memory device architecture using a hybrid bonding structure according to an embodiment of the present invention.

[0038] FIG. 2A is a schematic diagram of a memory chip architecture in a common hybrid bonding structure memory device in the industry.

[0039] Figure 2B FIG. 4 is a schematic diagram of a novel multiplexer-free memory chip architecture according to an embodiment of the present invention.

[0040] Figure 3 Schematic diagram of a new user-customized memory device architecture using a hybrid bonding structure according to an embodiment of the present invention.

[0041] Figure 4 Schematic diagram of a novel memory device architecture using a hybrid bonding structure according to an embodiment of the present invention.

[0042] FIG. 5A to FIG. 5B Schematic diagram of thickness and material of each layer in the RRAM stack in the new embedded RRAM process according to an embodiment of the present invention.

[0043] Figure 6 FIG. 1 is a flowchart of executing a write operation on a memory device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In a general RRAM memory integrated circuit, in addition to the RRAM array, many peripheral circuits are required to support the functions of the RRAM. As shown in FIG. 1A, a general RRAM memory integrated circuit 100 may include an RRAM array 101, a bit line (BL) / source line (SL) multiplexer (Mux) 102, a word line (WL) decoder 103, a sense amplifier 104, a charge pump 105, an analog circuit 106, and a digital circuit 107. Therefore, a large amount of precious wafer area is used to manufacture peripheral circuits, thereby limiting the area available for manufacturing RRAM memory cells. In addition, the manufacture of memory cells requires the use of the most advanced processes to achieve high density, while the peripheral circuits can be manufactured using mature nodes. However, different process nodes cannot be used on the same wafer. The present invention proposes a dual-chip solution in which the RRAM array is manufactured at an advanced node and other circuits are manufactured at a mature node. Subsequently, the two chips are combined together by hybrid bonding technology. In this way, the area of ​​the advanced process node wafer can be fully dedicated to the manufacture of high-density memory cells, thereby improving the competitiveness of memory devices. In addition, since only one type of transistor with a repetitive regular pattern needs to be manufactured, the advanced process for manufacturing high-density memory cells can be further simplified, which ultimately greatly reduces process defects and improves chip yield.

[0045] like Figure 1B As shown, the present invention proposes a dual chip solution, wherein the RRAM array is manufactured at an advanced node, while other circuits are manufactured at a mature node. The memory device 110 may include a memory chip 111 and a control chip 112. The memory chip 111 includes a plurality of memory cells ( Figure 1B The control chip 112 includes a control circuit manufactured using a second process node, wherein the first process node is more advanced than the second process node. The two chips are bonded together using a hybrid bonding technique ( Figure 1B The memory device 110 is formed by bonding the memory cells 111 with the memory cells 112 and 113 (referred to as “hybrid bonding structure 113” in the figure) to form the memory device 110. The control circuit is used to control the operation of the plurality of memory cells in the memory chip 111. Hybrid bonding includes metal bonding and insulating bonding. Figure 4 The description explains this in further detail. For the purpose of clarity, Figure 1B Only the metal bond 113 is shown, but the insulating bond is not shown, but it is also part of the hybrid bonding structure.

[0046] Since the wafer used to manufacture the memory chip 111 only includes memory units but does not include control circuits, more memory units can be manufactured on the same wafer, thereby optimizing wafer utilization.

[0047] like Figure 1B As shown, the control chip 112 includes a multiplexer (Mux) 102, a decoder 103, a sense amplifier 104, a charge pump 105, an analog circuit 106, and a digital circuit 107. The multiplexer 102 in the control chip 112 is used to control the source line or the bit line of the memory cell in the RRAM array 101, while the memory chip 111 does not include a multiplexer for controlling the source line or the bit line of the memory cell in the RRAM array 101. The decoder 103 in the control chip 112 is used to control the word line of the memory cell in the RRAM array 101, while the memory chip 111 does not include a decoder for controlling the word line of the memory cell in the RRAM array 101. The sense amplifier 104 in the control chip 112 is used to amplify the signal from the memory cell in the RRAM array 101, while the memory chip 111 does not include a sense amplifier for amplifying the signal from the memory cell in the RRAM array 101. The charge pump 105 in the control chip 112 is used to generate the programming voltage required by the memory cells in the RRAM array 101, while the memory chip 111 does not include the charge pump for generating the programming voltage required by the memory cells in the RRAM array 101. In addition, the memory chip 111 does not include the analog circuit 106 and the digital circuit 107.

[0048] As shown in FIG. 2A , the prior art using a hybrid bonding structure has a bit line (BL) / source line (SL) multiplexer 202 and a word line (WL) decoder 203 on a memory chip 200, and hybrid bonding connections 213a, 213b, 213c are provided downstream of the BL / SL multiplexer 202 or the WL decoder 203. Figure 2B As shown, since the memory chip 230 of the present invention only includes one type of transistor (NMOS or PMOS) formed on the RRAM chip, no multiplexer is required. The hybrid bonding connection 213 is directly connected to the word line 223, the bit line 221 and the source line 222 respectively.

[0049] Figure 3 Schematic diagram of a custom memory (Customer Defined Memory, CDM) 300, which may include a memory chip 321 and a custom function module chip 322 connected by hybrid bonding (for the purpose of facilitating reading, Figure 3Only metal bonding 323 is shown, and insulating bonding is not shown, but insulating bonding is also part of the hybrid bonding structure). The user-customized functional module chip 322 may include a multiplexer 302, a decoder 303, a read amplifier 304, an MCU 305, an analog circuit 306, a digital circuit 307, an ECC memory 308, a passive device 309, a sensor 310, a transmitter 311 and other user-customized modules. Other user-customized functional modules may include other memories (such as SRAM), power management integrated circuits, mixed signal interfaces and radio frequency components. The analog circuit 306 may include analog circuits such as ADC, DAC, PLL, V / I reference DC / DC converter, power supply, etc. The digital circuit 307 may include digital circuits such as MCU, NPU, GPU, CPU, etc. The passive device 309 may include passive devices such as inductors, capacitors, resistors, etc. The sensor 310 may include sensors such as image sensors, CCD sensors, temperature sensors, pressure sensors, and gas sensors. The mixed signal interface may include mixed signal interfaces such as PCIe, SerDes, DDR, CXL, SPI / QPI, etc. The radio frequency components may include radio frequency components such as LNA, VCO, mixer, etc. The transmitter 311 may transmit communication signals. The memory chip 321 may include high-density, high-bandwidth, low-power memory. In some embodiments, the memory chip 321 may only include a simple memory unit.

[0050] The user-defined memory 300 provides a comprehensive solution of non-volatile memory (NVM) space and non-volatile static random access memory (NVSRAM) space, which is the most cost-effective solution with a density of about several megabits (M) to several gigabits (G) and a finer granularity of storage capacity.

[0051] In addition to integrating user-customized functional modules, the user-customized memory 300 can also provide greater value within the same cost range. This flexibility enables cost-effective customization solutions that not only meet customers' specific requirements, but also lowers the threshold for using emerging storage technologies such as RRAM because only the control chip needs to be taped out with a low-cost mature process, while the advanced node memory chip can be reused.

[0052] The Customized Memory 300 improves storage density through multi-layer 3D integration and achieves high bandwidth through 2.5D interposer technology, thereby achieving functional expansion. The Customized Memory 300 is compatible with advanced memory interfaces including SPI / QPI, DDR5, CXL, PCIe 6.0, and 112G SerDes.

[0053] In addition, the user-customized memory 300 achieves a random access speed compatible with SRAM, and is suitable for AI applications in both edge and data center environments, thereby improving performance while reducing power consumption.

[0054] The user-customized memory 300 of the present invention allows customers to select specific functions that meet their needs, thereby improving versatility. This approach enables the memory to integrate multiple control functions and allows the control circuit to be directly integrated with the memory unit, thereby providing a more adaptable and feature-rich solution.

[0055] like Figure 4 As shown, the memory 400 includes a memory chip 431 and a control chip 432. The memory chip 431 uses a more advanced node than the control chip 432. The memory chip 431 includes a plurality of memory cells. The memory chip 431 includes only one type of transistor 410, which can be either an NMOS transistor or a PMOS transistor. On the other hand, the control chip 432 can include a plurality of different types of transistors, which can be NMOS, PMOS, IO and other transistors.

[0056] Since the memory chip 431 uses a more advanced node than the control chip 432, the gate length 421 of the access transistor 401 in the memory chip 431 is smaller than the gate length 422 of all transistors in the control chip 432:

[0057] L Gate_Memory <L Gate_Control .

[0058] The present invention uses only one type of transistor in the memory chip 431, thereby greatly simplifying the manufacturing process. By reducing the number of transistors required, this approach reduces technical complexity, reduces the number of masks required, and minimizes the required manufacturing steps. This simplified process not only reduces production difficulty, but also improves yield and reliability, thereby ultimately reducing overall manufacturing costs.

[0059] The memory chip 431 includes a P-type silicon substrate, a back-end-of-line (BEOL) metal and dielectric layer 433, and a hybrid bonding metal and dielectric layer 434. The P-type silicon substrate includes an access transistor 401. The BEOL metal and dielectric layer 433 includes a contact 402, a first metal layer 403, a bottom electrode 404, a resistive memory element 405, a first via 406, a second metal layer 407, and an insulating layer 415, wherein the contact 402 is located between a terminal of the access transistor 401 and the first metal layer 403, the bottom electrode 404 is located between the first metal layer 403 and the resistive memory element 405, and the first via 406 is located between the resistive memory element 405 and the second metal layer 407. Including the resistive memory element 405, the BEOL metal and dielectric layers and their components are formed above the substrate.

[0060] The resistive memory device 405 is in the back end of line (BEOL) process of the memory chip 431 .

[0061] The resistive memory element 405 may be a resistive random access memory (RRAM) element, a conductive bridging random access memory (CBRAM) element, a magnetoresistive random access memory (MRAM) element, a ferroelectric random access memory (FeRAM) element, or a phase change random access memory (PCRAM) element.

[0062] The resistive memory element 405 may have two RRAM stacks disposed in the RRAM region 520: (a) Figure 5A As shown in FIG. 1 , a RRAM stack having only one bottom electrode (BE) material; and (b) as shown in FIG. Figure 5B As shown, a RRAM stack with two bottom electrodes. Figure 5A The thickness of the RRAM bottom electrode 522 can be 5nm to 500nm, and the material of the RRAM bottom electrode 522 can be metal (Ti, Hf, Ta, Ru, Ir, Pt, etc.), metal oxide (TiOx, TaOx, HfOx, etc.), metal nitride (TiN, TaN, AlN, etc.), metal oxynitride (TiON, TaON, AlON, etc.), or other suitable conductive materials. The thickness of the dielectric layer 523 can be 0.1nm to 50nm, and the material of the dielectric layer 523 can be dielectric (SiO 2 、 2 O 5 、TiO 2 、ZrO 2 , HfO 2 、Al 2 O 3The thickness of the cap layer 524 may be 1 nm to 500 nm, and the material of the cap layer 524 may be a metal (Ti, Hf, Ta, Ru, Ir, Pt, etc.), a metal oxide (TiOx, TaOx, HfOx, etc.), a metal nitride (TiN, TaN, AlN, etc.), a metal nitride oxide (TiON, TaON, AlON, etc.), or other suitable conductive materials. The thickness of the top electrode 525 may be 1 nm to 500 nm, and the material of the top electrode 525 may be a metal (Ti, Hf, Ta, Ru, Ir, Pt, etc.), a metal oxide (TiOx, TaOx, HfOx, etc.), a metal nitride (TiN, TaN, AlN, etc.), a metal nitride oxide (TiON, TaON, AlON, etc.), or other suitable conductive materials. A hard mask layer 526 is also deposited on top of the RRAM stack. The material of the hard mask layer 526 may be SiN. In this embodiment, vias V are used. x+1 527 and metal layer M x+2 528, where the via V x+1 527 is etched through the hard mask 526 and connected to the RRAM top electrode 525 .

[0063] refer to Figure 5B , a second RRAM bottom electrode 522a is deposited between the dielectric layer 523 and the first RRAM bottom electrode 522. The thickness of the second RRAM bottom electrode 522a may be 1 nm to 500 nm, and the material of the second RRAM bottom electrode 522a may be a metal (Ti, Hf, Ta, Ru, Ir, Pt, etc.), a metal oxide (TiOx, TaOx, HfOx, etc.), a metal nitride (TiN, TaN, AlN, etc.), a metal oxynitride (TiON, TaON, AlON, etc.), or other suitable conductive materials.

[0064] like Figure 4As shown, the memory chip portion of the hybrid bonding metal and dielectric layer 434 includes a memory chip via 411, a memory chip pad 412, and an insulating layer 416. The control chip portion of the hybrid bonding metal and dielectric layer 434 includes a control chip via 414, a control chip pad 413, and an insulating layer 416. The top surface of the memory chip 431 includes a plurality of first conductive pads as memory chip pads 412 and a first insulating region. The top surface of the control chip 432 includes a plurality of second conductive pads as control chip pads 413 and a second insulating region. In the hybrid bonding process, the memory chip pad 412 is bonded to the control chip pad 413, and the first insulating region is bonded to the second insulating region. The multiple memory chip pads 412 are connected to the metal layer 407 in the memory chip 431 through multiple vias serving as memory chip vias 411, and the multiple second conductive pads 413 are connected to the metal layer in the control chip 432 through multiple second vias serving as control chip vias 414, wherein the multiple memory chip vias 411 have the same length to avoid forming a step shape.

[0065] Below, reference Figure 6 , a method of performing a write operation within a memory device is described. Figure 6 The method shown includes the following control flow steps:

[0066] S601: The control chip receives the address of the memory unit of the memory chip and the data to be written into the memory unit;

[0067] S602: Decode the address and send a signal to the multiplexer and decoder to activate specific BL and WL;

[0068] S603: Control the chip to perform a read operation on the memory unit;

[0069] S604: The selective memory device receives a read bias and returns a current;

[0070] S605: The readout amplifier distinguishes whether the current of the selective RRAM is a logic "0" or a logic "1";

[0071] S606: The control chip compares the data to be written with the read operation result;

[0072] S607: If the data to be written matches the read operation result, the write operation ends;

[0073] S608: If the data to be written does not match the read operation result, a write operation is performed on the memory cell.

[0074] S609: The selective storage device receives a write bias, and the resistance of the storage device changes to a desired resistance state.

[0075] The above-mentioned memory device includes: a memory chip, which includes a plurality of memory cells manufactured at a first process node; and a control chip, which includes a control circuit manufactured at a second process node, wherein the first process node is more advanced than the second process node, the control chip and the memory chip are bonded to each other to form the memory device, and the control circuit is used to control the operation of the plurality of memory cells in the memory chip.

[0076] In S601 , S602 , S605 , S606 , and S607 , signals are transmitted within the same chip (control chip or memory chip).

[0077] In S603 , S604 , S608 , and S609 , signals are sent between the control chip and the memory chip.

[0078] In the prior art, all bits need to be programmed regardless of the value to be stored. The present invention proposes an efficient method that is different from the prior art. Before the write operation, the control chip performs a read operation on the memory cell to determine whether the bit needs to be programmed. If the stored value matches the required data, the programming operation is not performed. In addition, the present invention eliminates the need for a refresh operation.

[0079] This selective writing process of the present invention reduces unnecessary write cycles. This is particularly beneficial for RRAM due to its limited write tolerance. By reducing the number of write operations, the present method simultaneously extends the service life of the RRAM and the entire device, thereby improving durability and reliability.

[0080] The above description of the illustrated embodiments of the present invention (including the description in the Abstract) is not intended to be exhaustive or to limit the invention to the exact forms disclosed. Although specific embodiments and examples of the present invention are described herein for illustrative purposes, various equivalent modifications may be made within the scope of the present disclosure, as will be appreciated by those skilled in the relevant art. Other embodiments may have layers arranged in a different order than the illustrated embodiments, or may increase or decrease the number of layers based on the illustrated embodiments.

[0081] Although the above operations are described as multiple independent operations in order to describe the operations in a manner that is most helpful for understanding the present invention, the order of description should not be understood as implying that the operations must be sequence-dependent. Specifically, the operations do not necessarily need to be performed in the order described.

[0082] In this specification, the words "above", "above", "below", "between" and "on" are used to indicate the relative position of a material layer or component to other layers or components. For example, when a layer is described as being deposited "above", "on" or "below" another layer, it means that the layer can be in direct contact with the other layer or there can be one or more intermediate layers. In addition, when a layer is described as being deposited "between" two layers, it means that the layer can be in direct contact with the two layers or there can be one or more intermediate layers. In contrast, when a first layer is described as being "on" a second layer, it means that it is in direct contact with the second layer. Similarly, unless otherwise explicitly stated, when a component is described as being deposited "between" two layers, it means that the component can be in direct contact with the adjacent components or there can be one or more intermediate layers.

[0083] In this specification, the words "example" and "illustrative" are used to mean as an example, instance or illustration. In this article, any aspect or design described as an "example" or "illustrative" should not necessarily be understood as being preferred or more advantageous than other aspects or designs. On the contrary, the purpose of using the words "example" or "illustrative" is to state the concept in a specific way. In this specification, the word "or" is intended to mean "or" in an inclusive sense, not "or" in an exclusive sense. That is, unless otherwise specified or clearly seen from the context, "X includes A or B" is intended to mean any one of the natural inclusive permutations and combinations. That is, if: "X includes A"; "X includes B"; or X includes A and B at the same time, "X includes A or B" is satisfied in any of the above situations. In addition, "one" and "an" in this specification and the appended claims can be generally understood as "one or more" in number, unless otherwise clearly specified or clearly seen from the context as a single. In addition, "embodiment" or "one embodiment" used in the text is not intended to mean the same embodiment unless it is described as having this meaning. In this specification, the words "first", "second", "third", "fourth" etc. are intended to be used as marks to distinguish different elements, and do not necessarily have the ordinal meaning represented by their numerical parts.

Claims

1. A storage device, characterized in that: include: a memory chip comprising a plurality of memory cells manufactured at a first process node; as well as A control chip, wherein the control chip includes a control circuit manufactured using a second process node, wherein the first process node is more advanced than the second process node, The control chip and the memory chip are bonded together to form the memory device, and the control circuit is used to control the operations of the multiple memory cells in the memory chip.

2. The memory device according to claim 1, wherein: The control circuit also includes a multiplexer for controlling a source line or a bit line of the memory cell.

3. The memory device according to claim 2, wherein: The memory chip does not include a multiplexer for controlling source lines or bit lines of the memory cells.

4. The memory device according to claim 1, wherein: The control circuit also includes a decoder for controlling a word line of the memory cell.

5. The memory device according to claim 4, wherein: The memory chip does not include a decoder for controlling word lines of the memory cells.

6. The memory device according to claim 1, wherein: The control circuit also includes a sense amplifier for amplifying a signal from the memory cell.

7. The memory device according to claim 1, wherein: The control circuit also includes a charge pump for generating a voltage required to program the memory cell.

8. The memory device according to claim 1, wherein: The control chip also includes a processor.

9. The memory device according to claim 1, wherein: The control chip also includes an analog circuit.

10. The memory device according to claim 1, wherein: The control chip also includes a transmitter.

11. The memory device according to claim 1, wherein: The control chip also includes a sensor.

12. The memory device according to claim 1, wherein: The gate length of the transistor in the memory chip is smaller than the gate length of the transistor in the control chip.

13. The memory device according to claim 1, wherein: The memory chip includes only one type of transistor, and the control chip includes a plurality of types of transistors.

14. The memory device according to claim 13, wherein: The memory chip includes only NMOS transistors.

15. The memory device according to claim 13, wherein: The memory chip includes only PMOS transistors.

16. The memory device according to claim 1, wherein: Each memory cell includes a memory element formed on a substrate.

17. The memory device according to claim 16, wherein: The memory element is selected from the group consisting of: Resistive random access memory element; Conductive bridging random access memory element; Magnetoresistive random access memory elements; Ferroelectric random access memory elements; as well as Phase change random access memory element.

18. The memory device according to claim 1, wherein: Each memory cell includes a resistive memory element formed on a substrate.

19. The memory device according to claim 18, wherein: The memory unit comprises: an access transistor formed on the substrate; Contacts; A first metal layer; bottom electrode; The resistive memory element; a first via hole; and The second metal layer, The contact is arranged between the terminal of the access transistor and the first metal layer, the bottom electrode is arranged between the first metal layer and the resistive memory element, and the first via is arranged between the resistive memory element and the second metal layer.

20. The memory device according to claim 18, wherein: The top surface of the memory chip includes a plurality of first conductive pads and a first insulating region, and the top surface of the control chip includes a plurality of second conductive pads and a second insulating region.

21. The memory device according to claim 20, wherein: The first conductive pad is bonded to the second conductive pad, and the first insulating region is bonded to the second insulating region.

22. The memory device according to claim 20, wherein: The multiple first conductive pads are connected to the second metal layer in the memory chip through multiple memory chip vias, and the multiple second conductive pads are connected to the second metal layer in the control chip through multiple control chip vias, wherein the multiple memory chip vias have the same length.

23. The memory device according to claim 1, wherein: Before performing a write operation on the memory cell, the control circuit is used to perform a read operation on the memory cell.

24. The memory device according to claim 23, wherein: Before performing a write operation on the memory unit, the control circuit is used to compare the data to be written with the read operation result.

25. The memory device according to claim 23, wherein: The control circuit is used to perform the write operation only when the to-be-written data does not match the read operation result.

26. A method for performing a write operation in a memory device, characterized in that: The storage device comprises: a memory chip comprising a plurality of memory cells manufactured at a first process node; and A control chip, wherein the control chip includes a control circuit manufactured using a second process node, wherein the first process node is more advanced than the second process node, The control chip and the memory chip are bonded together to form the memory, and the control circuit is used to control the operation of the plurality of memory cells in the memory chip. Wherein, the method comprises: The control chip receives the address of the memory unit in the memory chip and the data to be written into the memory unit; performing a read operation on the memory cell; and After the read operation, a write operation is performed on the memory cell.

27. The method of claim 26, wherein: Also includes: Before performing the write operation on the memory cell, the to-be-written data is compared with the read operation result.

28. The method of claim 27, wherein: Performing a write operation on the memory cell after the read operation includes: after the read operation, performing a write operation on the memory cell only when the to-be-written data does not match the read operation result.

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