Multi-level inverter for wireless power transfer

Abstract

Described herein are multi-level inverters configured for wireless power systems and methods for such inverters and systems. The inverter includes at least one capacitor and at least one switching leg. Each switching leg includes a plurality of switches having at least one switch coupled to the at least one capacitor. The plurality of switches of each switching branch are configured to be controlled such that during operation: (i) an output voltage is generated having an asymmetric multi-level distribution having at least four non-zero unequal voltage levels, and (ii) at least one switch of the plurality of switches operates at zero voltage switching.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 379,537, filed on October 14, 2022, entitled “MULTI-LEVEL INVERTER FOR WIRELESS POWER TRANSMISSION,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The following disclosure is directed to multi-level inverters for wireless power transfer, and more particularly, to methods and systems for generating asymmetric multi-level voltages for wireless power transfer. Background Art

[0004] The wireless power system may include one or more wireless power transmitters configured to transfer power to one or more wireless power receivers via an oscillating electromagnetic field. The wireless power receivers may be coupled to one or more batteries such that the received power is used to charge the batteries. The wireless power system may be configured to power a variety of electronic devices (e.g., phones, laptops, medical devices, vehicles, robots, etc.). Summary of the invention

[0005] At least one aspect of the present disclosure is directed to an inverter configured for a wireless power system. The inverter includes at least one capacitor and at least one switch branch. Each switch branch includes a plurality of switches, the plurality of switches having at least one switch coupled to the at least one capacitor. The plurality of switches of each switch branch are configured to be controlled so that during operation: (i) an output voltage is generated, the output voltage having an asymmetric multi-level distribution having at least four non-zero unequal voltage levels, and (ii) at least one of the plurality of switches operates with zero voltage switching.

[0006] In one embodiment, the plurality of switches of each switch branch are configured to be controlled so that during operation: (iii) at least one of the plurality of switches is operated to transition from a minimum voltage level of the output voltage to a maximum voltage level of the output voltage by providing a first non-zero voltage level for a first duration and a second non-zero voltage level for a second duration, and (iv) at least one of the plurality of switches is operated to transition from a maximum voltage level of the output voltage to a minimum voltage level of the output voltage by providing a first non-zero voltage level for a third duration and a second non-zero voltage level for a fourth duration, wherein the first and third durations and / or the second and fourth durations have different lengths. In some embodiments, transitioning from the minimum voltage level of the output voltage to the maximum voltage level of the output voltage includes operating at least one of the plurality of switches to provide a zero voltage level for a fourth duration. In various embodiments, transitioning from the maximum voltage level of the output voltage to the minimum voltage level of the output voltage includes operating at least one of the plurality of switches to provide a zero voltage level for a fifth duration.

[0007] In some embodiments, the inverter includes at least one input configured to receive an input voltage Vdc. In one embodiment, the minimum voltage level is -Vdc, the first non-zero voltage level is -Vdc / n, the second non-zero voltage level is +Vdc / n, and the maximum voltage level is +Vdc, where n is a positive integer equal to or greater than 2. In various embodiments, the multi-level distribution includes at least five different voltage levels, including a minimum voltage level of -Vdc, a first non-zero voltage level of -Vdc / 2, a zero voltage level, a second non-zero voltage level of +Vdc / 2, and a maximum voltage level of +Vdc. In some embodiments, each of the plurality of switches is an N-channel MOSFET.

[0008] In one embodiment, the plurality of switches of each switch branch include a first switch, a second switch, a third switch, and a fourth switch. In some embodiments, the at least one capacitor includes (i) a first capacitor coupled between a first node and a second node, and (ii) a second capacitor coupled between a second node and a third node, wherein the first switch of the switch branch is coupled between the first node and a fourth node, the second switch of the switch branch is coupled between the fourth node and the third node, wherein the third switch of the switch branch and the fourth switch of the switch branch are coupled between the second node and the fourth node, wherein the source of the third switch of the switch branch is connected to the source of the fourth switch of the switch branch. And wherein the first node and the third node are inputs to the inverter. In some embodiments, the first switch of the switch branch is coupled between the first node and the second node, the second switch of the switch branch is coupled between the second node and the third node, the third switch of the switch branch is coupled between the third node and the fourth node, and the fourth switch of the switch branch is coupled between the fourth node and the fifth node, wherein the capacitor is coupled between the second node and the fourth node, and wherein the first node and the fifth node are inputs to the inverter.

[0009] In some embodiments, the at least one capacitor includes (i) a first capacitor coupled between a first node and a second node, and (ii) a second capacitor coupled between a second node and a third node, wherein the first switch of the switch leg is coupled between the first node and a fourth node, the second switch of the switch leg is coupled between the fourth node and a fifth node, the third switch of the switch leg is coupled between the fifth node and a sixth node, and the fourth switch of the switch leg is coupled between the sixth node and the third node, wherein the first device is coupled between the second node and the fourth node. The second device is coupled between the second node and the sixth node, wherein the first node and the third node are inputs to the inverter. In one embodiment, the first and second devices are diodes. In various embodiments, the first and second devices are switches.

[0010] In one embodiment, the at least one capacitor includes (i) a first capacitor coupled between a first node and a second node, (ii) a second capacitor coupled between the first node and a third node, and (iii) a third capacitor coupled between the second node and the third node, wherein the first switch of the first switch branch is coupled between the first node and a fourth node, the second switch of the first switch branch is coupled between the fourth node and the third node, the third switch of the first switch branch is coupled between the third node and a fifth node, and the fourth switch of the first switch branch is coupled between the fifth node and the second node. Wherein the first switch of the second switch branch is coupled between the first node and the sixth node, the second switch of the second switch branch is coupled between the sixth node and the third node, the third switch of the second switch branch is coupled between the third node and the seventh node, and the fourth switch of the second switch branch is coupled between the seventh node and the second node, wherein the fifth switch of the first switch branch is coupled between the fourth node and the eighth node, the fifth switch of the second switch branch is coupled between the seventh node and the eighth node, the sixth switch of the first switch branch is coupled between the fourth node and the ninth node, and the sixth switch of the second switch branch is coupled between the sixth node and the ninth node, and wherein the first node and the second node are inputs of the inverter.

[0011] In some embodiments, the at least one capacitor includes (i) a first capacitor coupled between a first node and a second node, (ii) a second capacitor coupled between the first node and a third node, and (iii) a third capacitor coupled between the second node and the third node, wherein the first switch of the first switch branch is coupled between the first node and a fourth node, the second switch of the first switch branch is coupled between the fourth node and the third node, the third switch of the first switch branch is coupled between the third node and a fifth node, and the fourth switch of the first switch branch is coupled between the fifth node and the second node. Wherein the first switch of the second switch branch is coupled between the first node and a sixth node, the second switch of the second switch branch is coupled between the sixth node and the third node, the third switch of the second switch branch is coupled between the third node and a seventh node, and the fourth switch of the second switch branch is coupled between the seventh node and the second node, and wherein the first node and the second node are inputs to the inverter. In one embodiment, the inverter is a half-bridge inverter. In some embodiments, the inverter is a full-bridge inverter.

[0012] Another aspect of the present disclosure relates to a wireless power system, comprising an inverter having at least one capacitor and at least one switch branch. Each switch branch comprises a plurality of switches, the plurality of switches having at least one switch coupled to the at least one capacitor. The plurality of switches of each switch branch are configured to be controlled so that during operation: (i) an output voltage is generated, the output voltage having an asymmetric multi-level distribution, the asymmetric multi-level distribution having at least four non-zero unequal voltage levels, and (ii) the plurality of switches operate with zero voltage switching.

[0013] In some embodiments, the plurality of switches of each switch branch are configured to be controlled so that during operation: (iii) at least one of the plurality of switches is operated to transition from a minimum voltage level of the output voltage to a maximum voltage level of the output voltage by providing a first non-zero voltage level of a first duration and a second non-zero voltage level of a second duration, and (iv) at least one of the plurality of switches is operated to transition from a maximum voltage level of the output voltage to a minimum voltage level of the output voltage by providing a first non-zero voltage level of a third duration and a second non-zero voltage level of a fourth duration, wherein the first and third durations have different lengths and / or the second and fourth durations have different lengths. In one embodiment, the inverter is disposed in a wall box, and wherein the output of the inverter is connected to the impedance matching network via a cable. In various embodiments, the inverter is disposed within a charging pad, the charging pad being configured to be positioned under the vehicle, and wherein the input of the inverter is connected to the cable.

[0014] Another aspect of the present disclosure is directed to a controller for a wireless power system. The system includes an inverter configured to output an output current, and the controller is configured to generate a gate drive signal for driving each switch of the inverter. The controller includes: a control module configured to generate a first control signal having a first voltage level and a second control signal having a second voltage level; and a modulator configured to (a) receive a signal representing the output current and (b) generate a carrier signal based on the output current. The carrier signal includes a first carrier signal and a second carrier signal, so that: (i) when the first carrier signal is greater than the first voltage level, the first gate drive signal for the first switch is high, and (ii) when the second carrier signal is greater than the second voltage level, the second gate drive signal for the second switch is high, thereby driving the inverter to output a multi-level voltage having a first output level based on the first drive signal and a second output level based on the second drive signal.

[0015] In one embodiment, the multi-level voltage has an asymmetric waveform. In some embodiments, the carrier signal is at least partially configured to maintain zero voltage switching performed by the switch of the inverter. In various embodiments, the voltage value of the second output level is approximately equal to the value of the second voltage level. In some embodiments, the voltage value of the first output level is approximately half of the value of the second voltage level.

[0016] In some embodiments, the first gate drive signal is high for a first duration, wherein the first carrier signal is greater than a first voltage level, and the second gate drive signal is high for a second duration, wherein the second carrier signal is greater than a second voltage signal. In one embodiment, the first voltage level is based on a value of the second voltage level. In some embodiments, at least one of the first carrier signal and the second carrier signal has a sawtooth modulation. In various embodiments, at least one of the first carrier signal and the second carrier signal has a triangular modulation.

[0017] In one embodiment, the modulator is configured to receive and generate analog signals. In some embodiments, the modulator is configured to receive and generate digital signals.

[0018] Another aspect of the present disclosure is directed to a method for controlling a wireless power system, the wireless power system comprising an inverter configured to output an output current and a controller configured to generate a gate drive signal for driving a corresponding switch of the inverter. The method comprises: generating a first control signal having a first voltage level and a second control signal having a second voltage level via the controller; receiving a signal representing the output current at the controller; and generating a carrier signal based on the output current via the controller. The carrier signal comprises a first carrier signal and a second carrier signal, such that: (i) when the first carrier signal is greater than the first voltage level, the first gate drive signal for the first switch is high, and (ii) when the second carrier signal is greater than the second voltage level, the second gate drive signal for the second switch is high, thereby driving the inverter to output a multi-level voltage having a first output level based on the first gate drive signal and a second output level based on the second gate drive signal.

[0019] In one embodiment, the multi-level voltage has an asymmetric waveform. In some embodiments, generating a carrier signal based on the output current includes generating a carrier signal that is at least partially configured to maintain zero voltage switching through switches of the inverter. In various embodiments, the voltage value of the second output level is approximately equal to the value of the second voltage level. In some embodiments, the voltage value of the first output level is approximately half the value of the second voltage level.

[0020] In some embodiments, the first gate drive signal is high for a first duration, wherein the first carrier signal is greater than a first voltage level, and the second gate drive signal is high for a second duration, wherein the second carrier signal is greater than a second voltage signal. In one embodiment, the first voltage level is based on a value of the second voltage level. In some embodiments, at least one of the first carrier signal and the second carrier signal has a sawtooth wave modulation. In some embodiments, at least one of the first carrier signal and the second carrier signal has a triangle wave modulation.

[0021] In one embodiment, the controller is configured to receive and generate analog signals. In some embodiments, the controller is configured to receive and generate digital signals.

[0022] Another aspect of the present disclosure is directed to a rectifier configured for use in a wireless power system. The rectifier includes at least one capacitor and at least one switch branch, each switch branch including a plurality of switches, the plurality of switches having at least one switch coupled to the at least one capacitor. The plurality of switches of each switch branch are configured to be controlled such that, during operation: (i) a plurality of output voltages are generated, the plurality of output voltages including at least two non-zero unequal voltage levels, and (ii) at least one of the plurality of switches operates with zero voltage switching. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a block diagram of an exemplary wireless power system.

[0024] Figure 2 is a block diagram of an exemplary wireless power transmitter.

[0025] Figure 3A and 3B It is a graphic with Figure 2 A graph of exemplary waveforms associated with a wireless power transmitter.

[0026] Figure 4A is a block diagram of a wireless power transmitter according to at least one embodiment described herein.

[0027] Figure 4B is a block diagram of another wireless power transmitter according to at least one embodiment described herein.

[0028] Figure 5 It is the block diagram of a multilevel inverter.

[0029] Fig. 6A is a schematic diagram of an exemplary T-type inverter switching branch.

[0030] Figure 6B is a schematic diagram of an example flying capacitor (FC) inverter switching leg.

[0031] Figure 6C is a schematic diagram of an example neutral point clamped (NPC) inverter switch branch.

[0032] Fig.6D is a schematic diagram of an exemplary active neutral point clamped (ANPC) inverter switching leg.

[0033] Figure 7 is a graph illustrating an exemplary symmetric multi-level voltage waveform.

[0034] Figure 8 is a graph illustrating an asymmetric multi-level voltage waveform according to at least one embodiment described herein.

[0035] Fig. 9 is a flow chart of a method for selecting a switching sequence to generate an asymmetric waveform according to at least one embodiment described herein.

[0036] Fig. 10A is a diagram illustrating multiple switch branch states according to at least one embodiment described herein.

[0037] Fig. 10B is a table illustrating multiple modes of inverter configuration according to at least one embodiment described herein.

[0038] Fig. 10C is a graph of a multi-level voltage waveform according to at least one embodiment described herein.

[0039] Fig.11A is a schematic diagram of a multilevel inverter according to at least one embodiment described herein.

[0040] Fig. 11B is a diagram showing at least one embodiment according to the present invention Fig.11A Graph of the switching sequence of a multilevel inverter.

[0041] Fig. 12A - Figure 12G is a diagram illustrating at least one embodiment described herein. Fig.11A Schematic diagram of the operation of a multilevel inverter.

[0042] Fig.13 is a block diagram of a modulator according to at least one embodiment described herein.

[0043] Fig.14A According to at least one embodiment described herein Fig.13 A graph of the carrier signal associated with the modulator.

[0044] Fig. 14Bis a graph illustrating a synchronization technique associated with the modulator of FIG. 12 in accordance with at least one embodiment described herein.

[0045] Fig. 14C is an illustration of a method for Fig.13 A graph of multiple waveforms associated with a modulator.

[0046] Fig.15A is a diagram showing an example single-step inverter commutation sequence.

[0047] Fig. 15B is a diagram illustrating a multi-step inverter commutation sequence according to at least one embodiment described herein.

[0048] Fig.16 is a diagram illustrating a plurality of voltage conversion techniques according to at least one embodiment described herein.

[0049] Fig.17A is an illustration of a heat sink package according to at least one embodiment described herein.

[0050] Fig. 17B According to at least one embodiment described herein Fig.17A Figure 4 is a diagram of the contact guard of the radiator cover.

[0051] Fig.18 is a schematic diagram of an inverter according to at least one embodiment described herein.

[0052] Fig.19 is a schematic diagram of another inverter according to at least one embodiment described herein.

[0053] Fig. 20 is a schematic diagram of a multi-level rectifier according to at least one embodiment described herein.

[0054] Fig.21 is a diagram illustrating a method according to at least one embodiment described herein. Fig. 20 A graph of multiple waveforms associated with the operation of a multi-level rectifier.

[0055] Fig.22A - Figure 22R is a diagram illustrating at least one embodiment described herein. Fig. 20 Schematic diagram of the operation of a multi-level rectifier.

[0056] Fig.23 is a diagram illustrating a method according to at least one embodiment described herein. Fig. 20 A graph of multiple waveforms associated with the operation of a multi-level rectifier.

[0057] Fig.24A - Fig.24Iis a diagram illustrating at least one embodiment described herein. Fig. 20 Schematic diagram of the operation of a multi-level rectifier.

[0058] Fig.25 is a diagram illustrating a method according to at least one embodiment described herein. Fig. 20 A graph of multiple waveforms associated with the operation of a multi-level rectifier.

[0059] Fig.26A - Fig.26D is a diagram illustrating at least one embodiment described herein. Fig. 20 Schematic diagram of the operation of a multi-level rectifier.

[0060] Fig. 27 is a diagram illustrating a method according to at least one embodiment described herein. Fig. 20 A graph of multiple waveforms associated with the operation of a multi-level rectifier.

[0061] Fig.28A - Figure 28G is a diagram illustrating at least one embodiment described herein. Fig. 20 Schematic diagram of the operation of a multi-level rectifier.

[0062] Fig.29 is a diagram illustrating a method according to at least one embodiment described herein. Fig. 20 A graph of multiple waveforms associated with the operation of a multi-level rectifier.

[0063] Fig. 30A - Fig. 30C is a diagram illustrating at least one embodiment described herein. Fig. 20 Schematic diagram of the operation of a multi-level rectifier.

[0064] Fig.31 is a diagram illustrating at least one embodiment described herein. Fig. 20 Plot of the input impedance of a multi-level rectifier.

[0065] Fig.32 is a diagram illustrating at least one embodiment described herein. Fig. 20 Plot of the input impedance of a multi-level rectifier.

[0066] Fig.33 - Fig.35 is a diagram showing an indication of at least one embodiment described herein Fig. 20 Graph of parameters of a multi-level active rectifier and its impact on grounded components and inverter. DETAILED DESCRIPTION

[0067] Disclosed herein are exemplary embodiments of systems and methods for providing wireless power transfer using a multi-level inverter, and more particularly, methods and systems for generating an asymmetric multi-level voltage waveform for wireless power transfer.

[0068] Wireless Power Systems

[0069] Figure 1 1 is a block diagram of an exemplary wireless power system 100. System 100 includes a wireless power transmitter 102 and a wireless power receiver 104. In transmitter 102, a power source 105 (e.g., an AC power source, a battery, etc.) provides power to an inverter 108. Additional components may include a power factor correction (PFC) circuit 106 before the inverter stage 108. Inverter 108 drives a transmitter resonator coil and a capacitive component 112 ("resonator") via an impedance matching network 110 (including fixed or adjustable network components). Resonator 112 generates an oscillating magnetic field that induces a current or voltage in a receiver resonator 114. The received energy is provided to a rectifier 118 via an impedance matching network 116 (including fixed or adjustable network components). Ultimately, the rectified power is provided to a load 120 (e.g., one or more batteries of an electric or hybrid vehicle). In some embodiments, the battery voltage level may affect various parameters (e.g., impedance) of wireless power system 100. Thus, the battery voltage level may be received, determined, or measured to be provided as an input to other portions of the wireless power system 100. For example, a typical battery voltage range for an electric vehicle includes 280V-420V, among others.

[0070] In some embodiments, one or more components of the transmitter 102 and the receiver 104 may be coupled to controllers 122, 126, respectively, which may each include a communication module (e.g., Wi-Fi, radio, Bluetooth, in-band signaling mechanism, etc.). In some embodiments, one or more components of the transmitter 102 and the receiver 104 may be coupled to one or more sensors 124, 128 (e.g., current sensor, voltage sensor, power sensor, temperature sensor, fault sensor, etc.). The controllers 122, 126 and the sensors 124, 128 may be operably coupled to control portions of the transmitter 102 and the receiver 104 based on feedback signals from the sensors 124, 128.

[0071] Examples of wireless power systems can be found in U.S. Patent 8,461,719, issued on June 11, 2013, and entitled “Wireless Energy Transfer System,” and U.S. Patent 8,933,594, issued on January 13, 2015, and entitled “Wireless Energy Transfer for Vehicles,” both of which are incorporated herein by reference in their entirety.

[0072] In some embodiments, the exemplary impedance matching network 110, 116 may include one or more variable impedance components. One or more variable impedance elements may be collectively referred to herein as a "tunable matching network" (TMN). The TMN may be used to adjust the impedance (e.g., including reactance) of the wireless power transmitter 102 and the receiver 104. In some embodiments, the tunable matching network may be referred to as a "tunable reactance circuit". In some applications (e.g., wireless power transmission), the impedance seen by the wireless power transmitter 102 and the receiver 104 may be dynamically changed. In such applications, impedance matching between the receiver resonator coil (114) and the load 120, as well as impedance matching between the transmitter resonator coil (112) and the inverter 108 may be required to prevent unnecessary energy loss and excessive heat.

[0073] The high power wireless power transmitter may be configured to transmit wireless power in applications that rely on high power to power or charge batteries of vehicles, industrial machines, robots, or electronic devices, for example. For purposes of illustration, the following disclosure focuses on wireless power transmission of vehicles (e.g., electric vehicles, hybrid vehicles, etc.). However, it should be appreciated that any one or more of the embodiments described herein may be applied to other applications where wireless power may be used.

[0074] As discussed herein, a wireless power transmitter (e.g., wireless power transmitter 102) or at least a portion of a wireless power transmitter may be referred to as a "ground assembly" or "GA." Likewise, a wireless power receiver (e.g., wireless power receiver 104) or at least a portion of a wireless power receiver may be referred to as a "vehicle assembly" or "VA."

[0075] Wireless Power Transmitter

[0076] As described above, the wireless power transmitter 102 generates an oscillating magnetic field that induces a current or voltage in the receiver resonator 114. The inverter 108 of the wireless power transmitter 102 receives DC power from the PFC circuit 106. In some examples, the PFC circuit 106 includes a DC / DC converter configured to convert the DC power output from the PFC circuit 106. For example, the DC / DC converter converts the DC power from a first voltage level to one or more second voltage levels. The one or more second voltage levels may correspond to the configuration of the inverter 108. In other examples, an external DC / DC converter is located between the PFC circuit 106 and the inverter 108.

[0077] Figure 2 is a block diagram of an exemplary wireless power transmitter 200. In one example, the wireless power transmitter 200 corresponds to Figure 1A wireless power transmitter 102 is shown. As shown, the transmitter 200 includes a PFC circuit 206 that receives power from a grid 205, a DC / DC converter 207, an inverter 208, a transmitter (Tx) cable 209, and a transmitter resonator coil 210. In some examples, the PFC circuit 206, the DC / DC converter 207, and the inverter 208 are included in a common component. For example, the common component can be a "wall box" component installed in a private garage, a public garage, a parking lot, etc. Similarly, the transmitter resonator coil 210 and additional impedance matching components can be included in a GA coupled to the wall box component via the Tx cable 209. The Tx cable 209 provides AC power to the transmitter resonator coil 210 from the inverter 208.

[0078] In one example, the inverter 208 is an H-bridge resonant inverter. In order to drive a load via wireless power transfer (eg, the resonator coil 210), the inverter 208 outputs AC power having a plurality of different voltage levels. Figure 3A is an exemplary input voltage waveform provided to the inverter 208, Figure 3B is an exemplary output waveform provided by inverter 208. Inverter 108 generates a waveform having three different voltage levels: +Vdc, 0, and -Vdc (e.g., Figure 3B In such an example, the inverter 208 receives a wide input voltage range (eg, −Vdc to +Vdc) to generate different voltage levels (eg, Figure 3A ). A wide input voltage range results from the combination of the PFC circuit 206 and the DC / DC converter 207. However, such a wide input voltage range may increase the complexity and cost of the PFC circuit 206. In addition, including the DC / DC converter 207 may increase the cost while reducing the efficiency of the transmitter 200 (or wireless power system 100). Thus, the DC / DC converter 207 may be eliminated by using a multi-level inverter in the wireless power transmitter. The use of a tunable matching network (TMN) may also be eliminated by using a multi-level inverter.

[0079] Figure 4A is a block diagram of a wireless power transmitter 400 including a multi-level inverter. In one example, the wireless power transmitter 400 corresponds to Figure 14. The wireless power transmitter 102 of FIG. 400. As shown, the transmitter 400 includes a PFC circuit 406, a multi-level inverter 408, a Tx cable 409, and a transmitter resonator coil 410. In some examples, the PFC circuit 406 and the inverter 408 are included in a wall box assembly. Similarly, the transmitter resonator coil 410 and additional impedance matching components may be included in a GA coupled to the wall box assembly via the Tx cable 409. The Tx cable 409 provides AC power (e.g., high frequency AC power) from the inverter 408 to the transmitter resonator coil 410. Figure 4B 4 is a block diagram of a wireless power transmitter 450 including a multi-level inverter. Figure 4B In the example of Figure 1 Wireless power transmitter 102. As shown, transmitter 450 includes a PFC circuit 456, a Tx cable 457, a multi-level inverter 458, and a transmitter resonator coil 459. In some examples, the PFC circuit 456 is included in a wall box assembly, and the multi-level inverter 458, the transmitter resonator coil 459, and additional impedance matching components are included in a GA coupled to the wall box assembly via the Tx cable 457. The Tx cable 457 provides DC power from the PFC circuit 456 to the multi-level inverter 458. In some instances, since the Tx cable 457 is configured to provide DC power, the cost and size of the Tx cable 457 can be reduced (e.g., relative to the Tx cables 209, 409). In addition, the power dissipation in the Tx cable 457 can be reduced (e.g., relative to the Tx cables 209, 409).

[0080] In one example, the multilevel inverter 408 or 458 is one of a T-type inverter, a fast capacitor (FC) inverter, a neutral point clamped (NPC) inverter, an active neutral point clamped (ANPC) inverter, or any other suitable multilevel inverter type. In order to drive a load via wireless power transmission, the inverter outputs AC power having a plurality of different voltage levels. In one example, the PFC circuit 406 or 456 is configured to provide DC power having a fixed voltage level to the multilevel inverter. The multilevel inverter converts the DC power directly into output AC power. In this way, the need for a DC / DC converter is eliminated, thereby reducing costs while improving the efficiency of the transmitter 400, 450 (and the wireless power system 100 thereby). In some examples, the complexity and cost of the PFC circuit are also reduced.

[0081] Multilevel inverter topology for wireless power transfer

[0082] As described above, the wireless power transmitters 400, 450 may include a multilevel inverter configured as a T-type inverter, a FC inverter, an NPC inverter, an ANPC inverter, or any other suitable multilevel inverter type. Several of these multilevel inverter topologies are described in more detail below.

[0083] Figure 5 5 is a block diagram of a multilevel inverter 500. The inverter 500 includes a first input 502a, a second input 502b, a plurality of switch branches 504, and a plurality of outputs 506. The plurality of switch branches 504 includes n switch branches, where n≥1. In one example, the plurality of outputs 506 includes n outputs (e.g., one output per switch branch). However, in other examples, the plurality of outputs 506 may include a different number of outputs (e.g., 2n or two outputs per switch branch). The first and second inputs 502a, 502b receive input DC power Vdc (e.g., from a PFC circuit). Similarly, the plurality of outputs provide AC power Vac (e.g., to a transmitting resonator coil). Although not shown, one or more capacitors may be coupled between the first and second inputs 502a, 502b.

[0084] A plurality of switch branches 504 are coupled between the first and second inputs 502a, 502b and convert the input DC power received at the first and second inputs 502a, 502b into output AC power provided at the plurality of outputs 506. The plurality of switch branches are operated to generate output waveforms having a plurality of different voltage levels. In one example, the number of n switch branches included in the inverter 500 corresponds to the configuration of the inverter. For example, the inverter 500 may include one switch branch of a half-bridge structure and two switch branches of a full-bridge structure. In some examples, the number of different voltage levels included in the output waveform corresponds to the number of n switch branches included in the inverter 500. A single-branch inverter (ie, n=1) can generate an output waveform having a maximum of three different voltage levels (e.g., 0V, +Vdc / 2, +Vdc). For a multi-branch inverter (ie, n>1), the voltage difference on each switch branch (e.g., multiple outputs 506) is used to generate additional voltage levels. For example, a dual-branch inverter (i.e., n=2) can generate an output waveform having a maximum of five different voltage levels (e.g., -Vdc, -Vdc / 2, 0V, +Vdc / 2, +Vdc). The multiple switch branches 504 are operated using various switching sequences to generate asymmetric multi-level waveforms, as described in more detail herein.

[0085] The inverter 500 can be configured as a T-type inverter, a FC inverter, an NPC inverter, an ANPC inverter, or any other suitable multi-level inverter type. Thus, each of the plurality of switch branches 504 has a specific topology corresponding to the inverter type (e.g., T-type, FC, NPC, etc.). Fig. 6A - Fig.6D Multiple examples of these switch branch topologies are described in more detail in . In these and subsequent figures, multiple switches are shown, each switch having a gate, a drain, and a source. In some examples, each switch is a FET (e.g., an N-channel MOSFET, a P-channel MOSFET, etc.). Other types of transistors or switch technologies can be used.

[0086] Fig. 6A FIG. 6 is a schematic diagram of an exemplary T-type inverter switch branch 600. The switch branch 600 represents a switch branch 600 including Figure 5 6. As shown, the switch branch 600 includes a plurality of switches 604 coupled to a first capacitor 602a and a second capacitor 602b. The switch branch 600 includes a first node 606a, a second node 606b, a third node 606c, and a fourth node 606d. The first and third nodes 606a, 606c are inputs to the switch branch 600 (or inverter 500) and receive DC power (e.g., from a PFC circuit). Similarly, the fourth node 606d is the output of the switch branch 600 (or inverter 500) for providing AC power (e.g., to a transmitting resonator coil). The second node 606b is a midpoint connection.

[0087] The first capacitor 602a is coupled between the first node 606a and the second node 606b. The second capacitor is coupled between the third node 606c and the second node 606b. The input voltage Vdc received at the first node 606a and the third node 606c is separated at both ends of the capacitors 602a and 602b. For example, each capacitor 602a, 602b can store half (e.g., Vdc / 2) of the input voltage Vdc. In some examples, the capacitors 602a, 602b are referred to as bus capacitors. In one example, a single group of capacitors 602 is included in the inverter 500; however, in other examples, for each instance of the switch branch 600 in the inverter 500, a group of capacitors 602 can be included.

[0088] In the exemplary switch branch 600, the plurality of switches 604 include a first switch 604a, a second switch 604b, a third switch 604c, a fourth switch 604d, a fifth switch 604e, and a sixth switch 604f. The number of switches included in the switch branch 600 is proportional (or proportional) to the input voltage Vdc. In some examples, the second switch 604b and the fourth switch 604d may be optional, depending on the input voltage Vdc or the rated voltage of the remaining switches (e.g., switches 604a, 604c).

[0089] The first switch 604a and the second switch 604b are coupled in series between the first node 606a and the fourth node 606d. The drain of the first switch 604a is coupled to the first node 606a, the source of the first switch 604a is coupled to the drain of the second switch 604b, and the source of the second switch 604b is coupled to the fourth node 606d. The third switch 604c and the fourth switch 604d are coupled in series between the third node 606c and the fourth node 606d. The drain of the third switch 604c is coupled to the fourth node 606d, the source of the third switch 604c is coupled to the drain of the fourth switch 604d, and the source of the fourth switch 604d is coupled to the third node 606c. The fifth switch 604e and the sixth switch 604f are coupled in series between the second node 606b and the fourth node 606d. The drain of the fifth switch 604e is coupled to the second node 606d, the source of the fifth switch 604e is coupled to the source of the sixth switch 604f, and the drain of the sixth switch 604f is coupled to the fourth node 606d. In some examples, the fifth and sixth switches 604e, 604f correspond to bidirectional switches.

[0090] Figure 6B FIG. 6 is a schematic diagram of an example FC inverter switch branch 610. The switch branch 610 represents a switch branch 610 including Figure 5 610 . As shown, the inverter 610 includes a capacitor 612 and a plurality of switches 614. The inverter 610 includes a first node 616a, a second node 616b, a third node 616c, a fourth node 616d, and a fifth node 616e. The first and fifth nodes 616a, 616e are inputs to the switch branch 610 (or inverter 500) and receive DC power (e.g., from a PFC circuit). Similarly, the third node 616c is the output of the switch branch 610 (or inverter 500) to provide AC power (e.g., to a transmitting resonator coil).

[0091] The capacitor 612 is coupled between the second node 616b and the fourth node 616d. The input voltage Vdc is received at the first node 616a and the fifth node 616e. A portion of the input voltage Vdc is stored by the capacitor 612 (eg, Vdc / 2).

[0092] In the exemplary switch branch 610, the plurality of switches 614 include a first switch 614a, a second switch 614b, a third switch 614c, and a fourth switch 614d. The first switch 614a is coupled between a first node 616a and a second node 616b. The drain of the first switch 614a is coupled to the first node 616a, and the source of the first switch 614a is coupled to the second node 616b. The second switch 614b is coupled between the second node 616b and a third node 616c. The drain of the second switch 614b is coupled to the second node 616b, and the source of the second switch 614b is coupled to the third node 616c. The third switch 614c is coupled between the third node 616c and the fourth node 616d. The drain of the third switch 614c is coupled to the third node 616c, and the source of the third switch 614c is coupled to the fourth node 616d. The fourth switch 614d is coupled between the fourth node 616d and the fifth node 616e. The drain of the fourth switch 614d is coupled to the fourth node 616d, and the source of the fourth switch 614d is coupled to the fifth node 616e.

[0093] Figure 6C FIG. 6 is a schematic diagram of an exemplary NPC inverter switch branch 620. The switch branch 620 represents a switch branch 620 including Figure 5 620 is an example of a switch branch 504 in an inverter 500. As shown, the switch branch 620 includes a first diode 623a, a second diode 623b and a plurality of switches 624. The diodes 523a, 523b and the plurality of switches 624 are coupled to a first capacitor 622a and a second capacitor 622b. The switch branch 620 includes a first node 626a, a second node 626b, a third node 626c, a fourth node 626d, a fifth node 626e and a sixth node 626f. The first and third nodes 626a, 626c are inputs to the switch branch 620 (or inverter 500) and receive DC power (e.g., from a PFC circuit). Similarly, the fifth node 626e is the output of the switch branch 620 (or inverter 500) to provide AC power (e.g., to a transmitting resonator coil). The second node 626b is a midpoint connection.

[0094] The first capacitor 622a is coupled between the first node 626a and the second node 626b. The second capacitor 622b is coupled between the third node 626c and the second node 626b. In some instances, capacitors 622a, 622b are referred to as bus capacitors. The input voltage Vdc received at the first node 626a and the third node 626c is separated at both ends of capacitors 622a, 622b. For example, each capacitor 622a, 622b can store half (e.g., Vdc / 2) of the input voltage Vdc. In one example, a single group of capacitors 622 is included in the inverter 500; however, in other examples, for each instance of the switch branch 620 in the inverter 500, a group of capacitors 622 can be included.

[0095] The first diode 623a is coupled between the second node 626b and the fourth node 626d. The anode of the first diode 623a is coupled to the second node 626b, and the cathode of the first diode 623a is coupled to the fourth node 626d. The second diode 623b is coupled between the second node 626b and the sixth node 626f. The cathode of the second diode 623b is coupled to the second node 626b and the anode of the second diode 623b is coupled to the sixth node 626f.

[0096] In the exemplary switch branch 620, the plurality of switches 624 include a first switch 624a, a second switch 624b, a third switch 624c, and a fourth switch 624d. The first switch 624a is coupled between a first node 626a and a fourth node 626d. The drain of the first switch 624a is coupled to the first node 626a, and the source of the first switch 624a is coupled to the fourth node 626d. The second switch 624b is coupled between the fourth node 626d and the fifth node 626e. The drain of the second switch 624b is coupled to the fourth node 626d, and the source of the second switch 624b is coupled to the fifth node 626e. The third switch 624c is coupled between the fifth node 626e and the sixth node 626f. The drain of the third switch 624c is coupled to the fifth node 626e, and the source of the third switch 624c is coupled to the sixth node 626f. The fourth switch 624d is coupled between the sixth node 626f and the third node 626c. A drain of the fourth switch 624d is coupled to the sixth node 626f, and a source of the fourth switch 624d is coupled to the third node 626c.

[0097] Fig.6D FIG. 6 is a schematic diagram of an exemplary ANPC inverter switch branch 630. The switch branch 630 represents a switch branch 630 including Figure 5630 is an example of a switch branch 504 in an inverter 500. As shown, the switch branch 630 includes a plurality of switches 634 coupled to a first capacitor 632a and a second capacitor 632b. The switch branch 630 includes a first node 636a, a second node 636b, a third node 636c, a fourth node 636d, a fifth node 636e, and a sixth node 636f. In one example, the first and third nodes 636a, 636c are inputs to the switch branch 630 (or inverter 500) and receive DC power (e.g., from a PFC circuit). Similarly, the fifth node 636e is the output of the switch branch 630 (or inverter 500) to provide AC power (e.g., to a transmitting resonator coil). The second node 636b is a midpoint connection.

[0098] The first capacitor 632a is coupled between the first node 636a and the second node 636b. The second capacitor 632b is coupled between the third node 636c and the second node 636b. In some instances, capacitors 632a, 632b are referred to as bus capacitors. The input voltage Vdc received at the first node 636a and the third node 636c is separated at both ends of capacitors 632a, 632b. For example, each capacitor 632a, 632b can store half (e.g., Vdc / 2) of the input voltage Vdc. In one example, a single group of capacitors 632 is included in the inverter 500; however, in other examples, for each instance of the switch branch 630 in the inverter 500, a group of capacitors 632 may be included.

[0099] In the example of the switch branch 630, the plurality of switches 634 include a first switch 634a, a second switch 634b, a third switch 634c, a fourth switch 634d, a fifth switch 634e, and a sixth switch 634f. The first switch 634a is coupled between a first node 636a and a fourth node 636d. The drain of the first switch 634a is coupled to the first node 636a, and the source of the first switch 634a is coupled to the fourth node 636d. The second switch 634b is coupled between the fourth node 636d and the fifth node 636e. The drain of the second switch 634b is coupled to the fourth node 636d, and the source of the second switch 634b is coupled to the fifth node 636e. The third switch 634c is connected between the fifth node 636e and the sixth node 636f. The drain of the third switch 634c is coupled to the fifth node 636e, and the source of the third switch 634c is coupled to the sixth node 636f. The fourth switch 634d is coupled between the sixth node 636f and the third node 636c. The drain of the fourth switch 634d is coupled to the sixth node 636f, and the source of the fourth switch 634d is coupled to the third node 636c. The fifth switch 634e is coupled between the fourth node 636d and the second node 636b. The drain of the fifth switch 634e is coupled to the fourth node 636d, and the source of the fifth switch 634e is coupled to the second node 636b. The sixth switch 634f is coupled between the sixth node 636f and the second node 636b. The drain of the sixth switch 634f is coupled to the second node 636b, and the source of the sixth switch 634f is coupled to the sixth node 636f.

[0100] Multi-level voltage waveforms for wireless power transfer

[0101] As described above, the inverter 500 generates an output waveform having a plurality of different voltage levels (eg, three levels, five levels, seven levels, etc.). Figure 7 A graph 700 of an exemplary multi-level voltage waveform 702 is shown. The y-axis 704 represents the voltage level of the waveform and the x-axis 706 represents time (e.g., in μs). In one example, the waveform 702 includes five different voltage levels. The voltage levels may correspond to the input voltage Vdc to the inverter. For example, the waveform 702 has a first voltage level at -Vdc (e.g., -800V), a second voltage level at -Vdc / 2 (e.g., -400V), a third voltage level at 0V, a fourth voltage level at +Vdc / 2 (e.g., 400V), and a fifth voltage level at +Vdc (e.g., 800V).

[0102] As shown, waveform 702 is symmetrical about y-axis 704. In this article, "symmetrical" refers to the duration (or width) of each voltage step. For example, at time t1, waveform 702 is symmetrical about a first reference line 708a parallel to y-axis 704. Before time t1, waveform 702 steps down with a first step at +Vdc, a second step at +Vdc / 2, a third step at -Vdc / 2, and a fourth step at -Vdc. After time t1, waveform 702 returns in the opposite order of the first step at -Vdc, the second step at -Vdc / 2, the third step at +Vdc / 2, and the fourth step at +Vdc. When stepping up or down, the duration of the step at each voltage level is substantially the same. For example, a voltage step falling at -Vdc / 2 has a first duration ts1 that is substantially equal to a second duration ts2 of a voltage step rising at -Vdc / 2. Waveform 702 maintains the symmetrical configuration over time. For example, at time t2, waveform 702 is symmetric about a second reference line 708b parallel to y-axis 704. At time t3, waveform 702 is symmetric about a third reference line 708c parallel to y-axis 704, and so on. In some examples, the step durations are substantially the same for each voltage level. For example, the first and second durations ts1, ts2 of the voltage step at -Vdc / 2 may be substantially equal to the third duration ts3 of the voltage step at +Vdc / 2, and so on.

[0103] The inverter 500 may be controlled using a conventional switching sequence to generate a symmetrical waveform (e.g., Figure 7 Waveform 702 of symmetrical waveform 702). For example, such a switching sequence may include conventional pulse width modulation (PWM) techniques. Operating the inverter to produce a symmetrical waveform can achieve a simplified implementation of DC to AC power conversion. However, the symmetrical waveform 702 does not take into account zero voltage switching (ZVS) of the inverter switches. Therefore, when controlled to produce the symmetrical waveform 702, the inverter 500 operates at a reduced efficiency. This reduction in efficiency may provide undesirable performance for wireless power transmission. Therefore, it is necessary to control the inverter to produce a waveform optimized for wireless power transmission.

[0104] Figure 8 Graph 800 illustrates a multi-level voltage waveform 802 having an asymmetric implementation configured for wireless power transmission. The waveform is generated with specific switching times to ensure that the inverter switches are not hard switching. The multi-level voltage waveform 802 allows the inverter of the transmitter (e.g., inverter 500) to operate with an extended operating range. The extended operating range supports the use of a battery voltage (e.g., Figure 1 The load 120 in the Figure 1 Various load conditions that change dynamically as a function of the alignment of the coils 112, 114 in FIG.

[0105] exist Figure 8 8, y-axis 804 represents the voltage level of the waveform and x-axis 806 represents time (e.g., in μs). In one example, waveform 802 includes five different voltage levels. The voltage levels may correspond to an input voltage Vdc to an inverter (e.g., inverter 500). For example, waveform 802 has a first voltage level at -Vdc (e.g.,

[0106] 420V), a third voltage level at +Vdc / 2 (e.g., 420V), and a fifth voltage level at +Vdc (e.g., 840V). Although the illustrated waveform includes five different voltage levels, it should be understood that an asymmetric waveform may have a different number of voltage levels. For example, the waveform may have a first voltage level at -Vdc / 2 (e.g., -420V), a second voltage level at 0V, and a third voltage level at +Vdc / 2 (e.g., 420V). In another example, the waveform may have a first voltage level at -Vdc (e.g., -840V), a second voltage level at -Vdc / 2 (e.g., -420V), a third voltage level at 0V, a fourth voltage level at +Vdc / 2 (e.g., 420V), and a fourth voltage level at +Vdc (e.g., 840V). The number of voltage levels included in the waveform may vary as a function of the load conditions (eg, based on the battery voltage and coupling strength).

[0107] As shown, waveform 802 is asymmetric about y-axis 804. In this article, "asymmetric" refers to the duration of each voltage step. For example, at time t1, waveform 802 is asymmetric about reference line 808 parallel to y-axis 804. Before time t1, waveform 802 rises stepwise with a first step at -Vdc, a second step at -Vdc / 2, a third step at 0V, a fourth step at +Vdc / 2, and a fifth step at +Vdc. After time t1, waveform 802 retreats in reverse order, with a first step at +Vdc, a second step at +Vdc / 2, a third step at 0V, a fourth step at -Vdc / 2, and a fifth step at -Vdc. In one example, the step duration of one or more voltage levels changes when stepping up or down. For example, a voltage step rising at +Vdc / 2 has a first duration ts1 that is different (i.e., shorter or longer) than a second duration ts2 of a voltage step falling at +Vdc / 2. In some examples, the step duration can vary between voltage levels. For example, at least one of the first and second durations ts1, ts2 of the voltage step at +Vdc / 2 can be different (i.e., shorter or longer) than the third duration ts3 of the voltage step at -Vdc / 2. Similarly, for the voltage step at -Vdc / 2, at least one of the first, second, and third durations ts1, ts2, ts3 can be different (i.e., shorter or longer) than the fourth duration ts4. In some examples, the waveform 802 maintains this asymmetric configuration over time.

[0108] It should be understood that the asymmetric configuration of the waveform can be dynamically updated over time. For example, the asymmetric configuration can change from cycle to cycle (or cycle to cycle) of the waveform 802. In some instances, the number of voltage levels included in the waveform can be dynamically updated over time. For example, although the above-mentioned waveform 802 includes five different voltage levels, the waveform can be generated with two different voltage levels, three different voltage levels, four different voltage levels, six different voltage levels, etc. In some instances, the number of voltage levels included in the waveform can be changed based on cycle to cycle (or cycle to cycle). In one example, operating the inverter to generate an asymmetric waveform allows the ZVS of the inverter switch. In this way, the efficiency of the inverter can be improved relative to the symmetrical waveform operation. In some instances, other performance characteristics of the inverter (e.g., bus balance, switch loss balance, etc.) are improved by operating the inverter to generate an asymmetric waveform.

[0109] Switching sequences for multi-level asymmetric voltage waveforms

[0110] A number of different switching sequences may be used to control the inverter 500 to generate an asymmetric waveform (e.g., Figure 8In some examples, an optimal switching sequence is selected from a plurality of switching sequences based on an inverter type and at least one desired performance characteristic of the inverter.

[0111] Fig. 9 is a flow chart of a method 900 for selecting a switching sequence to generate an asymmetric waveform. In one example, the method 900 can be used for the inverter 500.

[0112] At block 902, different switch states of each switch branch 504 of the inverter 500 are analyzed. In one example, the analysis includes all possible combinations of on / off switches to produce a desired number of voltage levels (e.g., 0V, Vdc / 2, Vdc, etc.) at the output 506 of the switch branch 504. In this document, "on" refers to a closed switch state and "off" refers to an open switch state. In some instances, the analysis is limited to include actual switch states. For example, Fig. 6A The analysis of the switch branch 600 may include only combinations (e.g., six different combinations) where two switches in the plurality of switches 604 are turned on simultaneously. In some instances, switch states may be eliminated from the analysis based on undesirable performance. For example, switch states that produce a breakdown state may be eliminated.

[0113] Fig. 10A Several switching states of an exemplary switch branch 1000 are shown. In one example, switch branch 1000 corresponds to switch branch 504 of inverter 500. Switch branch 1000 is a T-type switch branch. In some examples, switch branch 1000 is substantially the same as switch branch 504 except that switch branch 1000 includes four switches instead of six switches. Fig. 6A 1004 is the same as the switch branch 600 of FIG. 1000. For example, the switch branch 1000 includes a first switch 1002a, a second switch 1002b, a third switch 1002c, and a fourth switch 1002d. In other examples, the switch branch 1000 may include a different number of switches (e.g., six, eight, etc.). The switch 1004 is coupled to the first capacitor 1002a and the second capacitor 1002b, and operates to provide various bus voltages (e.g., Vdc, Vdc / 2, 0V) to the output node 1006.

[0114] In one instance, Fig. 10AThe switch states shown in correspond to the actual switch states identified by the analysis of the switch branch 1000 in block 902. As shown, the switch branch 1000 operates in a first state "a" to provide 0V to the output node 1006. In state "a", the second and fourth switches 1004b, 1004d are turned on (i.e., closed) to couple the output node 1006 to the neutral (or ground) connection 1008 so that 0V is provided to the output node 1006a. The switch branch 1000 operates in a second state "m" to provide Vdc / 2 to the output node 1006. In state "m", the third and fourth switches 1004c, 1004d are turned on (i.e., closed) to couple the output node 1006 to the second capacitor 1002b. In this way, half of the bus voltage Vdc / 2 is provided to the output node 906 during state "m". The switch branch 1000 operates in a third state "b" to provide Vdc to the output node 1006. In state "b", the first and third switches 1004a, 1004c are turned on (i.e., closed) to couple the output node 1006 across the first and second capacitors 1002a, 1002b. Thus, the full bus voltage Vdc is provided to the output node 1006 during state "b".

[0115] Back to Fig. 9 At block 904, the resulting switch state is used to identify a mode for generating an output voltage level of the multi-branch inverter 500. In one example, the inverter 500 is configured to have two switch branches (e.g., Fig. 10A Each switch branch can be independently controlled so that the inverter 500 generates five output voltage levels: -Vdc, -Vdc / 2, 0V, Vdc / 2, and Vdc (or level 0: 0V, level 1: |Vdc / 2|, and level 2: |Vdc|).

[0116] Fig. 10B1020 is a diagram illustrating multiple example modes for a five-level, two-branch inverter configuration. In a first mode, the first and second switch branches of the inverter are both operated in switch state "a" to provide 0V. The voltage difference between the first switch branch and the second switch branch (e.g., 0V-0V) produces a level 0 output voltage (i.e., 0V) in the first mode. Similarly, in a second mode, the first and second switch branches are both operated in switch state "m" to provide Vdc / 2. The voltage difference between the first switch branch and the second switch branch (e.g., Vdc / 2-Vdc / 2) produces a level 0 output voltage 0V in the second mode. Assuming that the first and second switch branches provide offset voltages, the common mode voltage (e.g., noise) is reduced in the second mode. Similarly, in a third mode, the first and second switch branches are both operated in switch state "b" to provide Vdc. The voltage difference between the first switch branch and the second switch branch (e.g., Vdc-Vdc) produces a level 0 output voltage 0V in the third mode. In this way, the dual-branch inverter can have three different modes for generating a level 0 output voltage 0V. As described above, when the inverter is operated in the second mode to generate a level 0 output voltage 0V, the undesirable common-mode voltage is reduced. The inverter can rotate (e.g., periodically or dynamically) between the three modes to minimize the common-mode voltage when generating a level 0 output voltage. Similarly, assuming that the power loss distribution is different in each of the three modes, the inverter can be operated to distribute power losses (e.g., heat) between switches. For example, the inverter can rotate between three different modes so as to distribute power losses on the switches of the inverter in a substantially equal manner. Alternatively, the inverter can rotate between the three modes to concentrate power losses on one or more specific switches.

[0117] In the fourth mode, the first switch branch is operated in switch state "m" to provide Vdc / 2, and the second switch branch is operated in switch state "a" to provide 0V. The voltage difference between the first switch branch and the second switch branch (e.g., Vdc / 2-0V) produces a level 1 output voltage +Vdc / 2 in the fourth mode. Similarly, in the fifth mode, the first switch branch is operated in switch state "a" to provide 0V, and the second switch branch is operated in switch state "m" to provide Vdc / 2. The voltage difference between the first switch branch and the second switch branch (e.g., 0V-Vdc / 2) produces a level 1 output voltage -Vdc / 2 in the fifth mode. Similarly, in the sixth mode, the first switch branch is operated in switch state "b" to provide Vdc, and the second switch branch is operated in switch state "m" to provide Vdc / 2. In the sixth mode, the voltage difference between the first switch branch and the second switch branch (e.g., Vdc-Vdc / 2) produces a level 1 output voltage +Vdc / 2. In the seventh mode, the first switch branch operates in switch state "m" to provide Vdc / 2, and the second switch branch operates in switch state "b" to provide Vdc. The voltage difference between the first switch branch and the second switch branch (e.g., Vdc / 2-Vdc) produces a level 1 output voltage -Vdc / 2 in the seventh mode. In this way, the dual-branch inverter can have four different modes for generating a level 1 output voltage |Vdc / 2|.

[0118] In the eighth mode, the first switch branch operates in switch state "b" to provide Vdc, and the second switch branch operates in switch state "a" to provide 0V. In the eighth mode, the voltage difference between the first switch branch and the second switch branch (e.g., Vdc-0V) produces a level 2 output voltage +Vdc. Similarly, in the ninth mode, the first switch branch operates in switch state "a" to provide 0V, and the second switch branch operates in switch state "b" to provide Vdc. In the ninth mode, the voltage difference between the first switch branch and the second switch branch (e.g., 0V-Vdc) produces a level 2 output voltage -Vdc. In this way, the dual-branch inverter can have two different modes for generating a level 2 output voltage |Vdc|.

[0119] Back to Fig. 9 , at block 906, the total number of switching sequences used to generate the multi-level waveform is determined. Fig. 10CAs shown in the curve 1040 of , a multi-level voltage waveform 1042 is generated by operating the inverter to generate a level 0 output voltage during a first interval, a level 1 output voltage (e.g., +Vdc / 2) during a second interval, a level 2 output voltage (e.g., +Vdc) during a third interval, a level 1 output voltage (e.g., +Vdc) during a fourth interval, and so on. As described above, the inverter can be operated in different modes to generate different output voltages. For example, the inverter can operate in one of three different modes (e.g., the first, second, or third mode) to generate a level 0 output voltage 0V during a first interval, operate in one of two different modes (e.g., the fourth or sixth mode) to generate a level 1 output voltage +Vdc / 2 during a second interval, operate in one mode (e.g., the eighth mode) to generate a level 2 output voltage +Vdc during a third interval, operate in one of two different modes (e.g., the fourth or sixth mode) to generate a level 1 output voltage +Vdc / 2 during a fourth interval, and so on. As such, the inverter has many possible switching sequences for generating the multi-level waveform 1042. For example, a two-branch five-level inverter configuration may have 1296 possible switching sequences for generating the waveform 1042.

[0120] Back to Fig. 9 At block 908, the total number of switching sequences is filtered to identify a switching sequence that enables the inverter to operate with desired performance for wireless power transfer. In one example, a switching sequence is determined to be practical for wireless power transfer if the sequence enables one or more desired performance characteristics of the inverter. For example, such performance characteristics may include: turn-on ZVS, turn-off voltage clamping, top-level synchronization, DC link cap voltage balancing, single element switching, balanced loss distribution, or any combination thereof.

[0121] Turn-on ZVS refers to ZVS for each inverter switch when it is turned on. In some examples, the turn-on ZVS performance feature may be optional for lighter load applications. In one example, ZVS is provided for a single switch that is turned on during a switching event (e.g., a state change) of the inverter. In some examples, ZVS is provided for turning on two or more switches simultaneously.

[0122] Turn-off voltage clamping refers to partial soft switching achieved by clamping the switch voltage during turn-off to a level lower than the full bus voltage (i.e., Vdc). In some examples, the turn-off voltage clamping performance feature may be optional for maximum duty cycle applications, otherwise maintaining a rollover condition for ZVS, or low duty cycle applications.

[0123] Top-level synchronization refers to the top-level voltage pulse (e.g. Fig. 10C The synchronization performance characteristics are described in more detail below.

[0124] DC link cap voltage balancing refers to balancing the capacitors that split the DC input bus equally by using them inherently evenly (e.g. Fig. 6A In other words, the inverter switches may be operated such that substantially equal power is provided from each capacitor during one cycle of the switching sequence.

[0125] Single element switching means that only a single switch is actively turned on at a given time during a switching sequence.

[0126] Balanced loss distribution refers to evenly balancing power dissipation among similar devices (eg, inverter switches). In some examples, the switching sequence can be periodically alternating to enable the described performance characteristics of the inverter (described in more detail below).

[0127] In some examples, additional criteria may be used to select the actual switching sequence. For example, it may not be considered to use different switching patterns to select the actual switching sequence at consecutive intervals (e.g., Fig. 10C In addition, switching sequences that switch more than one pair of switches between intervals may not be considered. In other examples, additional criteria may be used for switching sequence selection.

[0128] Although the above example describes a five-level inverter with two switching branches, it should be understood that the method 900 can be used with different inverter configurations. For example, the method 900 can be used to identify the switching sequence of a three-level inverter, a seven-level inverter, etc. Similarly, the method 900 can be used to identify the switching sequence of a single-branch inverter, a three-branch inverter, etc.

[0129] Fig.11A is a schematic diagram of a portion of a transmitter including a multilevel inverter 1100, Fig. 11B is a graph 1150 of an exemplary switching sequence 1152 of a multilevel inverter 1100. In one example, the inverter 1100 corresponds to Figure 5 In some examples, the switching sequence 1152 corresponds to the inverter 500. Fig. 9 The method 900 identifies a switching sequence for wireless power transfer.

[0130] The multilevel inverter 1100 is a T-type inverter including a first switch branch 1101a and a second switch branch 1101b. In one example, each switch branch 1101a, 1101b is substantially the same as Fig. 10A The switch branches 1000 are the same. In other examples, the inverter 1100 can include a different number of switch branches (eg, one, three, etc.) and / or a different number of switches per switch branch (eg, six, eight, etc.).

[0131] As shown, the inverter 1100 includes a first capacitor 1102a, a second capacitor 1102b, and a plurality of switches 1104. The inverter 1100 includes a first node 1106a, a second node 1106b, a third node 1106c, a fourth node 1106d, and a fifth node 1106e. The first and third nodes 1106a, 1106c are inputs to the inverter 1100 and receive DC power (e.g., from the PFC circuit 1108). Similarly, the fourth and fifth nodes 1106d, 1106e are outputs of the inverter 1100 to provide AC power (e.g., to the resonant tank 1110). The second node 1106b is a midpoint connection. The resonant tank 1110 includes a resonator coil and an impedance matching component. In some examples, the resonant tank 1110 corresponds to Figure 4A , transmitter resonator coils 410, 459 of 4B.

[0132] The first capacitor 1102a is coupled between the first node 1106a and the second node 1106b. The second capacitor is coupled between the third node 1106c and the second node 1106b. The input voltage Vdc received at the first node 1106a and the third node 1106c is split across the capacitors 1102a, 1102b. For example, each capacitor 1102a, 1102b can store half of the input voltage Vdc (e.g., Vdc / 2).

[0133] The plurality of switches 1104 include a first switch 1104a, a second switch 1104b, a third switch 1104c, a fourth switch 1104d, a fifth switch 1104e, a sixth switch 1104f, a seventh switch 1104g, and an eighth switch 1104h. In one example, the first switch branch 1101a includes the first switch 1104a, the second switch 1104b, the third switch 1104c, and the fourth switch 1104d. The second switch branch 1101b includes the fifth switch 1104e, the sixth switch 1104f, the seventh switch 1104g, and the eighth switch 1104h.

[0134] The drain of the first switch 1104a is coupled to the first node 1106a, and the source of the first switch 1104a is coupled to the fourth node 1104d. The drain of the second switch 1104b is coupled to the fourth node 1104d, and the source of the second switch 1104b is coupled to the third node 1106c. The third and fourth switches 1104c, 1104d are coupled in series between the second node 1106b and the fourth node 1106d. The drain of the third switch 1104c is coupled to the second node 1106b, the source of the third switch 1104c is coupled to the source of the fourth switch 1104d, and the drain of the fourth switch 1104d is coupled to the fourth node 1106d. The drain of the fifth switch 1104e is coupled to the first node 1106a, and the source of the fifth switch 1104e is coupled to the fifth node 1106e. The drain of the sixth switch 1104f is coupled to the fifth node 1106e, and the source of the sixth switch 1104f is coupled to the third node 1106c. The seventh and eighth switches 1104g, 1104h are coupled in series between the second node 1106b and the fifth node 1106e. The drain of the seventh switch 1104g is coupled to the second node 1106b, the source of the seventh switch 1104g is coupled to the source of the eighth switch 1104h, and the drain of the eighth switch 1104h is coupled to the fifth node 1106e.

[0135] The plurality of switches 1104 converts the input DC power (or input voltage Vdc) received at the first and third nodes 1106a, 1106c into output AC power (or output voltage Vac) provided at the fourth and fifth nodes 1106d, 1106e. In some examples, the plurality of switches 1104 are connected via Fig. 11B The switching sequence 1152 is operated to generate an asymmetric multi-level waveform. Fig. 11B As shown, the switch sequence 1152 includes multiple control signals 1158. In one example, each of the multiple control signals 1158a-h corresponds to a switch in the multiple switches 1104a-h. For example, the first control signal 1158a corresponds to the first switch 1104a, the second control signal 1158b corresponds to the second switch 1104b, and so on. In one example, each control signal is a gate drive signal provided to the gate of each switch 1104. In some examples, when the control signal is high ('1'), the switch is turned on (or closed), and when the control signal is low ('0'), the switch is turned off (or disconnected). In other instances, the switches may be configured to operate differently (e.g., low-state active switches).

[0136] The plurality of switches 1104 are operated according to a switching sequence 1152 to generate an asymmetric multi-level voltage waveform 1154. The voltage waveform 1154 generates a corresponding current 1156 having a sinusoidal (or substantially sinusoidal) waveform. Fig. 11BAs shown, multiple switches 1104 are operated so that the inverter 1100 provides different output voltages (e.g., level 0, level 1, and level 2 voltages) during different time intervals (labeled as (I), (II), etc.). For example, during interval (I), the switch sequence 1152 operates the inverter 1100 to provide a level 0 output voltage of 0V. During interval (II), the switch sequence 1152 operates the inverter 1100 to provide a level 1 output voltage of +Vdc / 2, and so on. In one example, the switch sequence 1152 is configured to enable one or more performance characteristics of the inverter 1100, as described above with respect to Fig. 9 As described in method 900. Thus, switching sequence 1152 can operate inverter 1100 to provide: turn-on ZVS, turn-off voltage clamping, top-level synchronization, DC link cap voltage balancing, single element switching, balanced loss distribution, or any combination thereof.

[0137] Fig. 12A - Figure 12G Various states of the inverter 1100 when operated by a switching sequence 1152 to generate an asymmetric multi-level voltage waveform 1154 are shown.

[0138] Fig. 12A Corresponding to the operation of the inverter 1100 during the first interval (I) (ie, time t0 to time t1). In one example, the switch sequence 1152 controls the inverter 1100 to operate at a constant speed during the first interval (I). Fig. 10B The second mode operation is shown in Table 1020. Thus, the first and second switch branches 1101a, 1101b are both operated in switch state "m". Fig. 11B As shown, at time t0, the third control signal 1158c is driven high to turn on the third switch 1104c using ZVS. The second control signal 1158b is driven low to turn off the second switch 1104b. The fourth switch 1104d, the seventh switch 1104g, and the eighth switch 1104h operate in a static on state during the first interval (I). Similarly, the first switch 1104a, the fifth switch 1104e, and the sixth switch 1104f operate in a static off state during the first interval (I).

[0139] Back to Fig. 12A, providing a first commutation path 1202 by turning on switches 1104c, 1104d, 1104g, and 1104h. Current is received from the resonant tank 1110 at the fourth node 1106d. The first commutation path 1202 directs current to the fifth node 1106e, where the current returns to the resonant tank 1110. The switches 1104c, 1104d of the first switch branch 1101a are configured to clamp the fourth node 1106d to the second node 1106b to provide a voltage level of Vdc / 2 at the fourth node 1106d. Similarly, the switches 1104g, 1104h of the second switch branch 1101b are configured to clamp the fifth node 1106e to the second node 1106b to provide a voltage level of Vdc / 2 at the fifth node 1106e. Thus, the voltage difference (eg, Vdc / 2−Vdc / 2) between the fourth node 1106 d and the fifth node 1106 e provides a level 0 output voltage of 0V across the resonant tank 1110 .

[0140] Fig. 12B Corresponding to the operation of the inverter 1100 during the second interval (II) (ie, time t1 to time t2). In one example, the switch sequence 1152 controls the inverter 1100 to operate at Fig. 10B The fourth mode operation is shown in Table 1020. Thus, the first switch branch 1101a operates in the switch state "m" and the second switch branch 1101b operates in the switch state "a". Fig. 11B As shown, at time t1, the sixth control signal 1158f is driven high to turn on the sixth switch 1104f with ZVS. The seventh control signal 1158g is driven low to turn off the seventh switch 1104g. The third switch 1104c, the fourth switch 1104d, and the eighth switch 1104h operate in a static on state during the second interval (II). Similarly, the first switch 1104a, the second switch 1104b, and the fifth switch 1104e operate in a static off state during the second interval (II).

[0141] Back to Fig. 12B, a second commutation path 1204 is provided by "turning on" switches 1104c, 1104d and 1104f. Current is received from the resonant tank 1110 at the fourth node 1106d. The second commutation path 1204 directs the current to the fifth node 1106e, where the current returns to the resonant tank 1110. The switches 1104c, 1104d of the first switch branch 1101a are configured to couple the fourth node 1106d to the second node 1106b. Similarly, the switch 1104f of the second switch branch 1101b is configured to couple the fifth node 1106e to the third node 1106c. In this way, the resonant tank 1110 is coupled across the second capacitor 1102b. The voltage level at the fourth node 1106d is Vdc / 2 and the voltage level at the fifth node 1106e is 0V. Assuming that the second commutation path 1204 directs current from the fourth node 1106d to the fifth node 1106e, the voltage difference between the fourth node 1106d and the fifth node 1106e (eg, Vdc / 2-0V) provides a level 1 output voltage of +Vdc / 2 across the resonant tank 1110.

[0142] Fig. 12C Corresponding to the operation of the inverter 1100 during the third interval (III) (ie, time t2 to time t3). Fig. 11B As shown, during the third interval (III) from negative to positive (e.g., changing direction), the inverter current passes through zero. In one example, the switch sequence 1152 controls the inverter 1100 to switch to zero during the third interval (III). Fig. 10B Thus, the first switch branch 1101a operates in switch state "b", while the second switch branch 1101b operates in switch state "a". Fig. 11B As shown, at time t2, the first control signal 1158a is driven high to turn on the first switch 1104a with ZVS. The fourth control signal 1158d is driven low to turn off the fourth switch 1104d. The third switch 1104c, the sixth switch 1104f, and the eighth switch 1104h operate in a static on state during the third interval (III). Similarly, the second switch 1104b, the fifth switch 1104e, and the seventh switch 1104g operate in a static off state during the third interval (III).

[0143] Back to Fig. 12C, a third commutation path 1206 is provided by "turning on" switches 1104a and 1104f. Current is received from the resonant tank 1110 at the fourth node 1106d. The third commutation path 1206 directs the current to the fifth node 1106e, where the current returns to the resonant tank 1110. The switch 1104a of the first switch branch 1101a is configured to couple the fourth node 1106d to the first node 1106a. Similarly, the switch 1104f of the second switch branch 1101b is configured to couple the fifth node 1106e to the third node 1106c. In this way, the resonant tank 1110 is coupled across the first capacitor 1102a and the second capacitor 1102b. The voltage level at the fourth node 1106d is Vdc and the voltage level at the fifth node 1106e is 0V. Assuming that the third commutation path 1206 directs current from the fourth node 1106d to the fifth node 1106e, the voltage difference between the fourth node 1106d and the fifth node 1106e (eg, Vdc-0V) provides a level 2 output voltage +Vdc across the resonant tank 1110.

[0144] Fig.12D The switching sequence 1152 controls the inverter 1100 to operate at a constant current during the fourth interval (IV) (i.e., from time t3 to time t4). Fig. 10B The fourth mode of operation is shown in Table 1020. Thus, the first switch branch 1101a operates in the switch state "m" and the second switch branch 1101b operates in the switch state "a". Fig. 11B As shown, at time t3, the fourth control signal 1158d is driven high to turn on the fourth switch 1104d using ZVS. The first control signal 1158a is driven low to turn off the first switch 1104a. The third switch 1104c, the sixth switch 1104f, and the eighth switch 1104h operate in a static on state during the fourth interval (IV). Similarly, the second switch 1104b, the fifth switch 1104e, and the seventh switch 1104g operate in a static off state during the fourth interval (IV).

[0145] Back to Fig.12D, a fourth commutation path 1208 is provided by "turning on" switches 1104c, 1104d, and 1104f. Current is received from the resonant tank 1110 at the fifth node 1106e. The fourth commutation path 1208 directs current to the fourth node 1106d, where the current returns to the resonant tank 1110 (e.g., now in reverse). The switches 1104c, 1104d of the first switch branch 1101a are configured to couple the fourth node 1106d to the second node 1106b. Similarly, the switch 1104f of the second switch branch 1101b is configured to couple the fifth node 1106e to the third node 1106c. In this way, the resonant tank 1110 is coupled across the second capacitor 1102b. The voltage level at the fourth node 1106d is Vdc / 2 and the voltage level at the fifth node 1106e is 0V. Assuming that the fourth commutation path 1208 directs current from the fifth node 1106e to the fourth node 1104d, the voltage difference between the fourth node 1106d and the fifth node 1106e (eg, Vdc / 2-0V) provides a level 1 output voltage of +Vdc / 2 across the resonant tank 1110.

[0146] Fig.12E The switching sequence 1152 controls the inverter 1100 to operate at a constant current during the fifth interval (V) (i.e., from time t4 to time t5). Fig. 10B The second mode operation shown in Table 1020 is shown in FIG. 1021 . Thus, both the first and second switch branches 1101a operate in switch state "m". Fig. 11B As shown, at time t4, the seventh control signal 1158g is driven high to turn on the seventh switch 1104g using ZVS. The sixth control signal 1158f is driven low to turn off the sixth switch 1104f. The third switch 1104c, the fourth switch 1104d, and the eighth switch 1104h are operated in a static on state during the fifth interval (V). Similarly, the first switch 1104a, the second switch 1104b, and the fifth switch 1104e are operated in a static off state during the fifth interval (V).

[0147] Back to Fig.12E, a fifth commutation path 1210 is provided by turning “ON” switches 1104c, 1104d, 1104g and 1104h. Current is received from the resonant tank 1110 at the fifth node 1106e. The fifth commutation path 1210 directs current to the fourth node 1106d, where the current returns to the resonant tank 1110. The switches 1104c, 1104d of the first switch branch 1101a are configured to clamp the fourth node 1106d to the second node 1106b to provide a voltage level of Vdc / 2 at the fourth node 1106d. Similarly, the switches 1104g, 1104h of the second switch branch 1101b are configured to clamp the fifth node 1106e to the second node 1106b to provide a voltage level of Vdc / 2 at the fifth node 1106e. Thus, the voltage difference (eg, Vdc / 2−Vdc / 2) between the fourth node 1106 d and the fifth node 1106 e provides a level 0 output voltage of 0V across the resonant tank 1110 .

[0148] Fig.12F Corresponding to the operation of the inverter 1100 during the sixth interval (VI) (ie, time t5 to time t6). In one example, the switch sequence 1152 controls the inverter 1100 to operate at Fig. 10B Thus, the first switch branch 1101a operates in the switch state "m", and the second switch branch 1101b operates in the switch state "b". Fig. 11B As shown, at time t5, the fifth control signal 1158e is driven high to turn on the fifth switch 1104e using ZVS. The eighth control signal 1158h is driven low to turn off the eighth switch 1104h. The third switch 1104c, the fourth switch 1104d, and the seventh switch 1104g are operated in a static on state during the sixth interval (VI). Similarly, the first switch 1104a, the second switch 1104b, and the sixth switch 1104f are operated in a static off state during the sixth interval (VI).

[0149] Back to Fig.12F, a sixth commutation path 1212 is provided by "turning on" switches 1104c, 1104d and 1104e. Current is received from the resonant tank 1110 at the fifth node 1106e. The sixth commutation path 1212 directs current to the fourth node 1106d, where the current returns to the resonant tank 1110. The switches 1104c, 1104d of the first switch branch 1101a are configured to couple the fourth node 1106d to the second node 1106b. Similarly, the switch 1104e of the second switch branch 1101b is configured to couple the fifth node 1106e to the first node 1106a. In this way, the resonant tank 1110 is coupled across the first capacitor 1102a. The voltage level at the fourth node 1106d is Vdc / 2 and the voltage level at the fifth node 1106e is Vdc. Assuming the sixth commutation path 1212 directs current from the fifth node 1106 e to the fourth node 1104 d , the voltage difference between the fourth node 1106 d and the fifth node 1106 e (eg, Vdc / 2−Vdc) provides a level 1 output voltage −Vdc / 2 across the resonant tank 1110 .

[0150] Figure 12G The switching sequence 1152 controls the inverter 1100 to operate at a constant current during the seventh interval (VII) (i.e., from time t6 to time t7). Fig. 10B Thus, the first switch branch 1101a operates in switch state "a", while the second switch branch 1101b operates in switch state "b". Fig. 11B As shown, at time t6, the second control signal 1158b is driven high to turn on the second switch 1104b with ZVS. The third control signal 1158c is driven low to turn off the third switch 1104c. The fourth switch 1104d, the fifth switch 1104e and the seventh switch 1104g operate in a static on state during the seventh interval (VII). Similarly, the first switch 1104a, the sixth switch 1104f and the eighth switch 1104h operate in a static off state during the seventh interval (VII).

[0151] Back to Figure 12G, providing a seventh commutation path 1214 by turning on switches 1104b and 1104e. Current is received from the resonant tank 1110 at the fifth node 1106e. The seventh commutation path 1214 directs current to the fourth node 1106d, where the current returns to the resonant tank 1110. The switch 1104b of the first switch branch 1101a is configured to couple the fourth node 1106d to the third node 1106c. Similarly, the switch 1104e of the second switch branch 1101b is configured to couple the fifth node 1106e to the first node 1106a. In this way, the resonant tank 1110 is coupled across the first capacitor 1102a and the second capacitor 1102b. The voltage level at the fourth node 1106d is 0V and the voltage level at the fifth node 1106e is Vdc. Assuming that the seventh commutation path 1214 directs current from the fifth node 1106 e to the fourth node 1104 d , the voltage difference between the fourth node 1106 d and the fifth node 1106 e (eg, 0V−Vdc) provides a level 2 output voltage −Vdc across the resonant tank 1110 .

[0152] The switch sequence 1152 may continue to operate the inverter 1100 to generate an asymmetric multi-level voltage waveform 1154. In some examples, the inverter mode used to generate the various voltage levels of the waveform 1154 may change on a cycle-to-cycle (or period-to-period) basis. For example, during a first cycle of the waveform 1154 (e.g., time t0 to time t8), the switch sequence 1152 may control the inverter 1100 to provide a level 1 output voltage of +Vdc / 2 by operating the inverter 1100 in a fourth mode. In a second cycle of the waveform 1154 (e.g., time t8 to time t16), the switch sequence 1152 may control the inverter 1100 to provide a level 1 output voltage of +Vdc / 2 by operating the inverter 1100 in a sixth mode. Likewise, the switch sequence 1152 can control the inverter 1100 to provide a level 1 output voltage of -Vdc / 2 by operating the inverter 1100 in the seventh mode during the first cycle and operating the inverter 1100 in the fifth mode during the second cycle. This alternating configuration of the switch sequence 1152 is referred to herein as "alternating". In some examples, alternation enables the switch sequence 1152 to operate the inverter 1100 with DC link capacitor voltage balancing and balanced loss distribution. For example, the switch sequence 1152 can utilize alternation to balance the power (or current) drawn from each capacitor 1102a, 1102b. Similarly, the switch sequence 1152 can utilize alternation to manage the use of each switch 1104 so that the inverter 1100 operates with a balanced loss distribution across multiple switches 1104. In addition to alternation, the switch sequence 1152 can be adjusted or modified in real time based on feedback related to the performance of the inverter 1100.

[0153] Modulation techniques for generating multi-level asymmetric voltage waveforms

[0154] Fig.13 1 is a block diagram of a modulator 1300. The modulator 1300 generates a switching sequence (e.g., Fig. 11B The modulator 1300 is configured to generate a plurality of gate drive signals (eg, Fig. 11B A plurality of control signals 1158) are provided to the inverter 1302 to generate a switching sequence. In some examples, the inverter 1302 corresponds to Fig.11A Inverter 1100.

[0155] As shown, the modulator 1300 includes an adder module 1304, a control module 1306, a limiter module 1308, a gate logic module 1310, and a synchronization module 1312. The adder module 1304 receives a current signal (e.g., a root mean square current signal) "Irms" signal 1314 and a reference current signal (e.g., a reference root mean square current signal) "Irms_Ref" (also referred to as Irms reference) signal 1316. In one example, the Irms signal 1314 represents the current signal generated by the wireless power transmitter (e.g., Figure 1 102). In other words, the Irms signal 1314 represents a sample of the current in the resonator coil (e.g., the Tx resonator coil 112). In some examples, the Irms signal 1314 is sampled after the IMN 1320, which is coupled at the output of the inverter 1302; however, in other examples, the Irms signal 1314 can be sampled before the IMN 1320 (e.g., at the output of the inverter 1302). In some examples, before receiving the transmitted power (e.g., the wireless power receiver 1320), the Irms signal 1314 is sampled. Figure 1 The Irms signal 1314 is sampled at the receiver 104 of the embodiment of the present invention. In such an example, the Irms signal 1314 or data corresponding to the Irms signal 1314 can be sent back to the modulator 1300. The Irms reference signal 1316 represents an ideal or expected version of the Irms signal 1314.

[0156] The adder module 1304 receives the Irms signal 1314 and the Irms reference signal 1316 and generates an error signal 1320 representing the difference between the signals 1314, 1316. The error signal 1322 is provided to the control module 1306. The control module 1306 outputs a single control signal 1324 based on the error signal 1322. In one example, the control signal 1324 represents a level or threshold that is dynamically updated based on the error signal 1322. In some examples, the control signal 1322 corresponds to the output voltage level of the inverter 1302 (e.g., level 2 output voltage |Vdc|). The control signal 1324 is provided to the limiter module 1308. The limiter module 1308 limits the magnitude of the control signal to a value between a predetermined range (e.g., 0.0 to 1.0, 0.0 to 2.0, 1.0 to 3.0, etc.). The predetermined range corresponds to the expected input range of the gate logic module 1310. The limiter module 1308 can provide a rate limiting function that limits the rate of change of the control signal 1324. Therefore, the limiter module 1308 can output a control level signal 1326 that is updated at a predetermined rate. In some examples, the control level signal 1326 represents an average value of the control signal 1324 during each rate period.

[0157] The synchronization module 1312 receives a plurality of carrier signals 1328 and a synchronization reference signal 1330. The synchronization reference signal 1330 represents the current of the AC power 1332 output from the inverter 1302. In some examples, the synchronization reference signal 1330 is substantially the same as the Irms signal 1314. The synchronization module 1312 is configured to synchronize at least a portion of the carrier signal 1328 to a zero crossing point of the current of the AC power 1332 (e.g., as indicated by the synchronization reference signal 1330). For example, the synchronization reference signal 1330 may have a sinusoidal waveform corresponding to the current of the AC power 1332 to provide an indication of the zero crossing position. In other instances, the synchronization reference signal 1330 may have a different waveform (e.g., a pulse) to provide an indication of the zero crossing position.

[0158] Fig.14A Several examples of multiple carrier signals 1328 provided to the synchronization module 1312 are shown. The first plot 1402 includes a first carrier signal 1406 and a second carrier signal 1408. The second plot 1404 includes a third carrier signal 1410 and a fourth carrier signal 1412.

[0159] The first and second carrier signals 1406, 1408 are used to control the level 2 output voltage |Vdc| of the inverter 1302. For example, the first carrier signal 1406 may correspond to the level 2 output voltage +Vdc, and the second carrier signal 1408 may correspond to the level 2 output voltage -Vdc. Fig.14AAs shown, the carrier signals 1406, 1408 have a sawtooth modulation waveform; however, in other examples, the carrier signals 1406, 1408 can have different waveforms (e.g., square, triangle, etc.). As shown, each tooth of the carrier signals 1406, 1408 includes a vertical leading edge 1407 that can be used for zero crossing synchronization. In one example, the first carrier signal 1406 oscillates in the positive domain (e.g., between 0V and 1V), while the second carrier signal 1408 oscillates in the negative domain (e.g., between 0V and -1V). In other instances, the carrier signals 1406, 1408 oscillate in the same domain (e.g., positive or negative). In some examples, the first carrier signal 1406 and the second carrier signal 1408 are offset in phase (e.g., offset by 180 degrees).

[0160] The third and fourth carrier signals 1410, 1412 are used to control the level 1 output voltage |Vdc / 2| of the inverter 1302. For example, the third carrier signal 1410 may correspond to the level 1 output voltage +Vdc / 2, and the fourth carrier signal 1412 may correspond to the level 1 output voltage -Vdc / 2. Fig.14A As shown, the carrier signals 1410, 1412 have a triangular modulation waveform; however, in other examples, the carrier signals 1410, 1412 can have different waveforms (e.g., square, sawtooth, etc.). In one example, the third carrier signal 1410 oscillates in the positive domain (e.g., between 0V and 1V), while the fourth carrier signal 1412 oscillates in the negative domain (e.g., between 0V and -1V). In other instances, the carrier signals 1410, 1412 oscillate in the same domain (e.g., positive or negative). In some examples, the third carrier signal 1410 and the fourth carrier signal 1412 are offset in phase (e.g., offset by 180 degrees).

[0161] Fig. 14BA plot 1450 including exemplary waveforms associated with the synchronization module 1312 and the inverter 1302 is shown. The plot 1450 includes an asymmetric multi-level voltage waveform 1452 corresponding to the voltage of the AC power 1332 output from the inverter 1302. Similarly, the plot 1450 includes a sinusoidal current waveform 1454 corresponding to the AC power 1332 output from the inverter 1302. As described above, the synchronization module 1312 is configured to synchronize at least a portion of the carrier signal 1328 to the zero crossings of the current of the AC power source 1332. The synchronization module 1312 synchronizes the first carrier signal 1406 to the zero crossings of the current waveform 1454, so that the voltage waveform 1452 transitions from the level 1 output voltage |Vdc / 2| to the level 2 output voltage level |Vdc| at each zero crossing or slightly before each zero crossing (e.g., at time t1). In some instances, the synchronization module 1312 is configured to synchronize the first carrier signal 1406 to the zero crossings of the current waveform 1454 by adjusting or shifting the phase of the first carrier signal 1406 (e.g., via a time delay) so that the leading edge 1407 of the carrier signal 1406 appears at or slightly before each zero crossing. In one example, the first carrier signal 1406 is synchronized so that the level 2 output voltage |Vdc| starts pulsing slightly before the zero crossing to address multiple factors. These factors may include increasing the output power range and reducing the turn-on loss. By starting the level 2 pulse early, a higher effective AC voltage output can be obtained, thereby obtaining higher power. Assuming that the second carrier signal 1408 is offset by a fixed amount (e.g., 180 degrees) from the first carrier signal 1406, the second carrier signal 1408 can be automatically synchronized based on the adjustment of the first carrier signal 1406. In some examples, the second carrier signal 1408 can be independently synchronized.

[0162] Back to Fig.13 The gate drive logic module 1310 receives the control level signal 1326 from the limiter module 1308 and the multiple synchronous carrier signals 1334 from the synchronization module 1312. The gate drive logic module 1310 provides a comparator function that derives a switching sequence for the inverter 1302 based on the control level signal 1326 and the multiple synchronous carrier signals 1334.

[0163] Fig. 14C A number of graphs are shown of exemplary waveforms associated with the drive logic module 1310 and the inverter 1302. In one example, Fig. 14CThe waveforms of represent the comparator function of the gate drive logic module 1310. The first curve 1472 represents the comparison between the derived control level signal 1478 and the third carrier signal 1410 for determining the timing and pulse width of the level 1 output voltage +Vdc / 2 in the multi-level voltage waveform 1452. The second curve 1474 represents the comparison between the control level signal 1326 and the synchronization carrier signal 1481 corresponding to the first carrier signal 1406 for determining the timing and pulse width of the level 2 output voltage +Vdc in the multi-level voltage waveform 1452. The third curve 1476 includes a multi-level voltage waveform 1452 corresponding to the voltage of the AC power 1332 output from the inverter 1302.

[0164] The control level signal 1326 provided by the limiter module 1308 corresponds to the level 2 output voltage +Vdc, while the derived control level signal 1478 corresponds to the level 1 output voltage +Vdc / 2. In some examples, the derived control level signal 1478 is derived from the control level signal 1326 based on a fixed relationship between the two signals. For example, the derived control level signal 1478 can be a fixed percentage (e.g., 60%) of the control level signal 1326. In this way, when the modulator 1300 dynamically adjusts the control level signal 1326, the derived control level signal 1478 can be adjusted.

[0165] As shown in curve 1472, the first gate drive signal 1480 is driven high ("1") as long as the third carrier signal 1410 is above (or greater than) the derived control level signal 1478. When the first gate drive signal 1480 is high, the multi-level voltage waveform 1452 has a level 1 voltage level of +Vdc / 2 (or higher). For example, at time t1, when the third carrier signal 1410 rises above the derived control level signal 1478, driving the first gate drive signal 1480 to a high level, the voltage waveform 1452 transitions from a level 0 output voltage of 0V to a level 1 output voltage level of +Vdc / 2. Similarly, at time t4, when the third carrier signal 1410 falls below the derived control level signal 1478 that drives the first gate drive signal 1480 to a low ('0'), the voltage waveform 1452 transitions from a level 1 output voltage of +Vdc / 2 to a level 0 output voltage level of 0V.

[0166] As shown in curve 1474, the synchronization carrier signal 1481 corresponds to the first carrier signal 1406 after being synchronized by the synchronization module 1312. Whenever the synchronization carrier signal 1481 is higher (or greater than) the control level signal 1326, the second gate drive signal 1482 is driven high ("1"). When the second gate drive signal 1482 is high, the multi-level voltage waveform 1452 has a level 2 voltage level +Vdc. For example, at time t2, when the synchronization carrier signal 1481 rises to be higher than the control level signal 1326 that drives the second gate drive signal 1482 high, the voltage waveform 1452 transitions from the level 1 output voltage +Vdc / 2 to the level 2 output voltage level +Vdc. Similarly, at time t3, when the synchronization carrier signal 1481 drops to be lower than the control level signal 1326 that drives the second gate drive signal 1482 low ('0'), the voltage waveform 1452 transitions from the level 2 output voltage +Vdc to the level 1 output voltage level +Vdc / 2.

[0167] Although not shown, the gate drive logic module 1310 may operate in a similar manner to determine the timing and pulse width of the level 1 output voltage −Vdc / 2 and the level 2 output voltage −Vdc in the multi-level voltage waveform 1452 .

[0168] Back to Fig.13 , the gate drive logic module 1310 provides a plurality of gate drive signals 1336 to the inverter 1302. In some examples, the plurality of gate drive signals 1336 include Fig. 14C The inverter 1302 (or the controller of the inverter 1302) may use the plurality of gate drive signals 1336 to determine a switching sequence for generating the asymmetric multi-level voltage waveform 1452. For example, the plurality of gate drive signals 1336 may be associated with Fig. 9 The switching sequence selection method 900 is used in conjunction with the switching sequence selection method 900 to select a desired switching sequence for generating the voltage waveform 1452. The switching sequence is converted into a plurality of control signals (e.g., Fig. 11B 1452) for operating the switches of the inverter 1302 to generate the voltage waveform 1452. In other examples, the plurality of gate drive signals 1336 may correspond to other signals. For example, the gate drive logic module 1310 may convert the gate drive signals 1480, 1482 into switch level control signals corresponding to the desired switching sequence. In some examples, the plurality of gate drive signals 1336 may include a digital representation of the voltage waveform 1452 processed by the inverter 1302 (or a controller of the inverter 1302) to derive the desired switching sequence and corresponding switch control.

[0169] Multi-stage commutation sequence

[0170] In some instances, the step size of the commutation sequence used to generate the asymmetric multi-level voltage waveform can affect the performance of the inverter and / or the wireless power transmitter. Fig.15A An example commutation sequence 1500 for transitioning between two voltage levels is shown. Commutation sequence 1500 represents a transition from a level 2 output voltage +Vdc to a level 2 output voltage -Vdc. A plurality of switch controls 1504 are provided to an inverter (e.g., Fig.11A The switches of the inverter 1100) are used to provide a voltage transition from +Vdc to -Vdc. As shown, when waveform 1502 transitions from +Vdc to -Vdc, a large current spike (or transient) 1506 appears in the common mode current of the inverter. The current spike 1506 causes the inverter switches to operate with increased switching losses during the voltage transition. The current spike 1506 can generate (or induce) common mode noise, which causes the inverter to operate with undesirable performance during the voltage transition. Therefore, it may be advantageous to transition the voltage waveform in incremental steps to prevent (or minimize) common mode transients.

[0171] Fig. 15BAn improved commutation sequence 1510 for transitioning between two voltage levels is shown. Commutation sequence 1510 represents a multi-step transition from a level 2 output voltage +Vdc to a level 2 output voltage -Vdc. Multiple switch controls 1514 are provided to the switches of the inverter to provide a voltage transition from +Vdc to -Vdc. As shown, multiple switch controls 1514 are configured to transition a voltage waveform 1512 from +Vdc to -Vdc by reducing the voltage one level at a time. For example, waveform 1412 includes a first step from a level 2 output voltage +Vdc to a level 1 output voltage +Vdc / 2, a second step from a level 1 output voltage +Vdc / 2 to a level 0 output voltage 0V, a third step from a level 0 output voltage 0V to a level 1 output voltage -Vdc / 2, and a fourth step from a level 1 output voltage -Vdc / 2 to a level 2 output voltage -Vdc. In one example, the duration of each step is a minimum step time Tcrop. The minimum step time Tcrop can take into account the switching time of the inverter switch and the parasitic effects of the inverter components (e.g., bus capacitors). Given the reduced size of the voltage transition of each step, the common-mode transients generated by each step are reduced. As shown, multiple current spikes 1516 appear during the voltage transition. Each spike corresponds to a step (e.g., first step, second step, etc.) of the multi-step voltage transition. In some examples, each spike has substantially the same amplitude. The amplitude of each spike is reduced relative to the large spike 1506, allowing the inverter switch to operate with improved efficiency during the transition. In addition, common-mode noise during the voltage transition can be reduced. In some instances, the commutation sequence 1510 can simplify the design of the inverter and / or wireless power transmitter to better comply with electromagnetic compatibility (EMC) standards.

[0172] Smooth transitions between output voltage levels

[0173] The multilevel inverter may have a minimum pulse width for each output voltage level (e.g., level 0, level 1, and level 2), which may be implemented in an asymmetric multilevel voltage waveform. Fig.16 As shown, the level 2 output voltage |Vdc| has a minimum pulse width (or duty cycle) T that can be achieved by the inverter. pwm_min In some examples, the switching sequence for operating the inverter corresponds to a multi-level voltage waveform having level 2 output voltage pulses having a minimum pulse width T pwm_min Short pulse width duty lv2 In this case, the inverter can be commanded with one of three different options A, B and C to take into account the pulse width duty lv2 In one example, detection of these events and corresponding selection of option A, B, or C is handled by the modulator 1300 (eg, the limiter module 1308).

[0174] In option A, the inverter is commanded to exclude (or ignore) the pulse width duty lv2 The voltage waveform includes an extended Level 1 output voltage step and may have a lower voltage than desired during the transition period. In Option B, the inverter is commanded to include a Level 2 output voltage pulse, but with a minimum pulse width T pwm_min . As such, the voltage waveform includes an extended Level 2 output voltage step and may have a higher voltage than desired during the transition period. In both Options A and B, the desired configuration of the asymmetric multi-level voltage waveform is modified and may cause the inverter to operate with undesirable performance for wireless power transfer. The output voltage of the inverter changes abruptly during the transition between the Level 1 and Level 2 output voltages, resulting in undesirable oscillations or an increase in battery ripple current. Such a modified waveform may increase the output power error at the corresponding receiver. In Option C, the command inverter includes a minimum pulse width T pwm_min The level 2 output voltage pulse can be trimmed and the level 1 output voltage pulse width can be trimmed. shrink In one example, the shrinkage amount T shrink It is expressed as:

[0175] T shrink =T pwm_min -duty lv2

[0176] In this way, the voltage waveform includes extended Level 2 output voltage steps and shortened Level 1 output voltage steps to provide the desired voltage during the transition period.

[0177] Ground Inverter Package

[0178] As described above, a multilevel inverter may be included in a ground assembly (GA) of a wireless power transmitter (e.g., Figure 4B The GA is a wireless power-enabled vehicle that is configured to provide a wireless power supply for a vehicle that is capable of providing a wireless power supply to a user. The GA is a wireless power-enabled vehicle that is configured to provide a wireless power supply for a user that is capable of providing a wireless power supply to ...

[0179] Fig.17AAn example heat sink housing 1700 is shown. In one example, the heat sink housing 1700 is made of aluminum; however, in other examples, the heat sink housing 1700 can be made of different materials (e.g., other metals). In some examples, the heat sink housing 1700 is substantially flat on the top and bottom. Heat sink fins are included on the sides and are configured to provide additional heat extraction from the inverter. Fig. 17B As shown, a contact guard 1702 can be connected to the top and / or bottom of the heat sink housing 1700. In one example, the contact guard 1702 is made of plastic or other similar material. The contact guard 1702 can prevent a user from accidentally contacting the heat sink housing 1700. In this way, the contact guard 1702 protects the user from being harmfully exposed to the heat sink housing 1700.

[0180] The contact protection device 1702 includes a plurality of grooves 1704. In some examples, each of the plurality of grooves 1704 has the same size. In other examples, the size of the grooves may be different. For example, in the hotter area of ​​the heat sink housing 1700, the grooves may be smaller. The plurality of grooves 1704 may be positioned across the top / bottom surface of the heat sink package 1700 in a grid-like arrangement. The grooves 1704 of the touch protection member 1702 allow the heat sink housing 1700 to have an operating temperature higher than the standard safe touch temperature limit. In this way, the contact protection member 1702 can reduce the size of the heat sink cover 1700. For example, the contact protection device 1702 can reduce the size of the heat sink cover 1700 by 200-300%. It should be understood that the heat sink cover 1700 and the contact protection device 1702 can be used with any type of inverter or power converter, and are not limited to use with the multi-level inverter described herein.

[0181] Additional Multilevel Inverter Topologies

[0182] As mentioned above, Figure 5 The inverter 500 may be configured as a T-type inverter, a FC inverter, an NPC inverter or an ANPC inverter to generate a multi-level asymmetric voltage waveform. Fig.18 and 19 Multi-level inverter topologies are shown that represent two additional configurations of inverter 500 .

[0183] Fig.181 is a schematic diagram of an inverter 1800. The inverter 1800 includes a first switch branch 1801a and a second switch branch 1801b. The first switch branch 1801a corresponds to the switch branch 504a of the inverter 500, and the second switch branch 1801b corresponds to the switch branch 504b of the inverter 500. As shown in the figure, the inverter 1800 includes a first capacitor 1802a, a second capacitor 1802b, a third capacitor 1802c, a plurality of switches 1804, a first inductor 1808a and a second inductor 1808b. The inverter 1800 includes a first node 1806a, a second node 1806b, a third node 1806c, a fourth node 1806d, a fifth node 1806e, a sixth node 1806f, a seventh node 1806g, an eighth node 1806h and a ninth node 1806i. The first and second nodes 1806a, 1806b are inputs to the inverter 1800 and receive DC power (e.g., from a PFC circuit). Similarly, the eighth and ninth nodes 1806h, 1806i are outputs of the inverter 1800 to provide AC power (e.g., to a transmit resonator coil). The eighth node 1806h is coupled to the first inductor 1808a and the ninth node 1806i is coupled to the second inductor 1808b. The third node 1806c is a midpoint connection.

[0184] As shown, the first capacitor 1802a is coupled between the first node 1806a and the second node 1806b. The first capacitor 1802a can be referred to as a DC link capacitor. The second capacitor 1802b is coupled between the first node 1806a and the third node 1806c. The third capacitor 1802c is coupled between the second node 1806b and the third node 1806c. In some examples, the capacitors 1802b, 1802c are referred to as bus capacitors. The input voltage Vdc received at the first node 1806a and the second node 1806b is stored by the first capacitor 1802a and is divided across the second and third capacitors 1802b, 1802c. For example, each capacitor 1802b, 1802c can store half of the input voltage Vdc (e.g., Vdc / 2).

[0185] In the example inverter 1800, the plurality of switches 1804 include a first switch 1804a, a second switch 1804b, a third switch 1804c, a fourth switch 1804d, a fifth switch 1804e, a sixth switch 1804f, a seventh switch 1804g, an eighth switch 1804h, a ninth switch 1804i, a tenth switch 1804j, an eleventh switch 1804k, and a twelfth switch 1804l. The first switch branch 1801a includes the first switch 1804a, the second switch 1804b, the third switch 1804c, the fourth switch 1804d, the ninth switch 1804i, and the twelfth switch 1804l. The second switch branch 1801b includes the fifth switch 1804e, the sixth switch 1804f, the seventh switch 1804g, the eighth switch 1804h, the tenth switch 1804j, and the eleventh switch 1804k.

[0186] The first switch 1804a is coupled between the first node 1806a and the fourth node 1806d. The drain of the first switch 1804a is coupled to the first node 1806a, and the source of the first switch 1804a is coupled to the fourth node 1806d. The second switch 1804b is coupled between the third node 1806c and the fourth node 1806d. The drain of the second switch 1804b is coupled to the fourth node 1806d, and the source of the second switch 1804b is coupled to the third node 1806c. The third switch 1804c is coupled between the third node 1806c and the fifth node 1806e. The drain of the third switch 1804c is coupled to the third node 1806c, and the source of the third switch 1804c is coupled to the fifth node 1806e. The fourth switch 1804d is coupled between the second node 1806b and the fifth node 1806e. The drain of the fourth switch 1804d is connected to the fifth node 1806e, and the source of the fourth switch 1804d is connected to the second node 1806b. The fifth switch 1804e is coupled between the first node 1806a and the sixth node 1806f. The drain of the fifth switch 1804e is coupled to the first node 1806a and the source of the fifth switch 1804e is coupled to the sixth node 1806f. The sixth switch 1804f is connected between the third node 1806c and the sixth node 1806f. The drain of the sixth switch 1804f is coupled to the sixth node 1806f, and the source of the sixth switch 1804f is coupled to the third node 1806c. The seventh switch 1804g is connected between the third node 1806c and the seventh node 1806g. The drain of the seventh switch 1804g is coupled to the third node 1806c, and the source of the seventh switch 1804g is coupled to the seventh node 1806g. The eighth switch 1804h is coupled between the second node 1806b and the seventh node 1806g. The drain of the eighth switch 1804h is coupled to the seventh node 1806g, and the source of the eighth switch 1804h is coupled to the second node 1806b. The ninth switch 1804i is coupled between the fourth node 1806d and the eighth node 1806h. The drain of the ninth switch 1804i is coupled to the fourth node 1806d, and the source of the ninth switch 1804i is coupled to the eighth node 1806h. The tenth switch 1804j is coupled between the seventh node 1806g and the eighth node 1806h. The drain of the tenth switch 1804j is coupled to the eighth node 1806h, and the source of the tenth switch 1804j is coupled to the seventh node 1806g. The tenth switch 1804j is coupled between the seventh node 1806g and the eighth node 1806h. The drain of the tenth switch 1804j is coupled to the eighth node 1806h, and the source of the tenth switch 1804j is coupled to the seventh node 1806g. The eleventh switch 1804k is coupled between the sixth node 1806f and the ninth node 1806i.The drain of the eleventh switch 1804k is coupled to the sixth node 1806f, and the source of the eleventh switch 1804k is coupled to the ninth node 1806i. The twelfth switch 1804i is coupled between the fifth node 1806e and the ninth node 1806i. The drain of the twelfth switch 1804l is coupled to the ninth node 1806l and the source of the twelfth switch 1804l is coupled to the fifth node 1806e.

[0187] Fig.19 1 is a schematic diagram of an inverter 1900. The inverter 1900 includes a first switch branch 1901a and a second switch branch 1901b. The first switch branch 1901a corresponds to the switch branch 504a of the inverter 500, and the second switch branch 1901b corresponds to the switch branch 504b of the inverter 500. As shown in the figure, the inverter 1900 includes a first capacitor 1902a, a second capacitor 1902b, a third capacitor 1902c, a plurality of switches 1904, a first inductor 1908a, a second inductor 1908b, a third inductor 1908c and a fourth inductor 1908d. The inverter 1900 includes a first node 1906a, a second node 1906b, a third node 1906c, a fourth node 1906d, a fifth node 1906e, a sixth node 1906f and a seventh node 1906g. The first and second nodes 1906a, 1906b are inputs to the inverter 1900 and receive DC power (e.g., from a PFC circuit). Similarly, the fourth, fifth, sixth, and seventh nodes 1906d-1906g are outputs of the inverter 1900 to provide AC power (e.g., to a transmitting resonator coil). The sixth node 1906f is coupled to the first inductor 1908a, the seventh node 1906g is coupled to the second inductor 1908b, the fourth node 1906d is coupled to the third inductor 1908c, and the fifth node 1908e is coupled to the fourth inductor 1908d. The third node 1906c is a midpoint connection.

[0188] As shown, the first capacitor 1902a is coupled between the first node 1906a and the second node 1906b. In one example, the first capacitor 1902a can be referred to as a DC link capacitor. The second capacitor 1902b is coupled between the first node 1906a and the third node 1906c. The third capacitor 1902c is coupled between the second node 1906b and the third node 1906c. In some instances, capacitors 1902b, 1902c are referred to as bus capacitors. The input voltage Vdc received at the first node 1906a and the second node 1906b is stored by the first capacitor 1902a and separated on the second and third capacitors 1902b, 1902c. For example, each capacitor 1902b, 1902c can store half of the input voltage Vdc (e.g., Vdc / 2).

[0189] In the example inverter 1900, the plurality of switches 1904 include a first switch 1904a, a second switch 1904b, a third switch 1904c, a fourth switch 1904d, a fifth switch 1904e, a sixth switch 1904f, a seventh switch 1904g, and an eighth switch 1904h. The first switch branch 1901a includes the first switch 1904a, the second switch 1904b, the third switch 1904c, and the fourth switch 1904d. The second switch branch 1901b includes the fifth switch 1904e, the sixth switch 1904f, the seventh switch 1904g, and the eighth switch 1904h.

[0190] The first switch 1904a is coupled between the first node 1906a and the fourth node 1906d. The drain of the first switch 1904a is coupled to the first node 1906a, and the source of the first switch 1904a is coupled to the fourth node 1906d. The second switch 1904b is coupled between the third node 1906c and the fourth node 1906d. The drain of the second switch 1904b is coupled to the fourth node 1906d, and the source of the second switch 1904b is coupled to the third node 1906c. The third switch 1904c is coupled between the third node 1906c and the fifth node 1906e. The drain of the third switch 1904c is coupled to the third node 1906c, and the source of the third switch 1904c is coupled to the fifth node 1906e. The fourth switch 1904d is coupled between the second node 1906b and the fifth node 1906e. The drain of the fourth switch 1904d is coupled to the fifth node 1906e, and the source of the fourth switch 1904d is coupled to the second node 1906b. The fifth switch 1904e is coupled between the first node 1906a and the sixth node 1906f. The drain of the fifth switch 1904e is coupled to the first node 1906a, and the source of the fifth switch 1904e is coupled to the sixth node 1906f. The sixth switch 1904f is coupled between the third node 1906c and the sixth node 1906f. The drain of the sixth switch 1904f is coupled to the sixth node 1906f, and the source of the sixth switch 1904f is coupled to the third node 1906c. The seventh switch 1904g is coupled between the third node 1906c and the seventh node 1906g. The drain of the seventh switch 1904g is coupled to the third node 1906c, and the source of the seventh switch 1904g is coupled to the seventh node 1906g. The eighth switch 1904h is coupled between the second node 1906b and the seventh node 1906g. The drain of the eighth switch 1904h is coupled to the seventh node 1906g, and the source of the eighth switch 1904h is coupled to the second node 1906b.

[0191] It should be understood that the inverters 1800, 1900 can be operated using the techniques and switching sequences described above to generate an asymmetric multilevel waveform. For example, a plurality of switches 1804 convert the input DC power (i.e., input voltage Vdc) received at the first and second nodes 1806a, 1806b into the output AC power (i.e., output voltage Vac) provided at the eighth and ninth nodes 1806h, 1806i. Similarly, a plurality of switches 1904 convert the input DC power (i.e., input voltage Vdc) received at the first and second nodes 1906a, 1906b into the output AC power (i.e., output voltage Vac) provided at the fourth, fifth, sixth, and seventh nodes 1906d - 1906g. The output voltage waveform provided by the inverter 1800 or 1900 can have multiple different voltage levels (e.g., five different voltage levels).

[0192] Multilevel active rectifier

[0193] Although the above examples describe multilevel inverters and asymmetric multilevel voltage waveforms for wireless power transmission, it should be understood that similar techniques can be applied to multilevel active rectifiers for wireless power reception. For example, the AC power received from a wireless power transmitter can be converted into DC power using a switching sequence and modulation scheme similar to those described above.

[0194] Fig. 20 is a schematic diagram of a wireless power receiver 2000. The wireless power receiver 2000 includes a receiver resonator 2014, a receiver IMN 2016, and a multilevel active rectifier 2018. In some examples, the receiver resonator 2014 includes a coil 2022 and capacitor components 2024a, 2024b; however, in other examples, different resonator configurations can be used. In some examples, the receiver IMN 2016 includes capacitor components 2026 and inductor components 2028a, 2028b; however, in other examples, different IMN configurations can be used.

[0195] The multi-level active rectifier 2018 includes a first switch branch 2020a and a second switch branch 2020b. As shown, the rectifier 2018 includes a plurality of switches 2030, a first capacitor 2032a and a second capacitor 2032b. The rectifier 2018 includes a first node 2034a, a second node 2034b, a third node 2034c, a fourth node 2034d and a fifth node 2034e. The first and second nodes 2034a, 2034b are inputs to the rectifier 2018 and receive AC power (e.g., from the resonator 2014 via IMN 2016). The first capacitor 2032a is coupled between the third node 2034c and the fifth node 2034e. The second capacitor 2032b is coupled between the fourth node 2034d and the fifth node 2034e. In some examples, the capacitors 2032a, 2032b are referred to as bus capacitors (e.g., DC bus capacitors). The output voltage (e.g., Vdc) can be split across capacitors 2032a, 2032b. For example, each capacitor 2032a, 2032b can store half of the output voltage Vdc (e.g., Vdc / 2). In some examples, capacitors 2032a, 2032b are charged in an unequal distribution.

[0196] In the example rectifier 2018, the plurality of switches 2030 include a first switch 2030a, a second switch 2030b, a third switch 2030c, a fourth switch 2030d, a fifth switch 2030e, a sixth switch 2030f, a seventh switch 2030g, and an eighth switch 2030h. The first switch branch 2020a includes the first switch 2030a and the second switch 2030b. The second switch branch 2020b includes the third switch 2030c and the fourth switch 2030d.

[0197] The first switch 2030a is coupled between the second node 2034b and the third node 2034c. The drain of the first switch 2030a is coupled to the third node 2034c, and the source of the first switch 2030a is coupled to the second node 2034b. The second switch 2030b is coupled between the second node 2034b and the fourth node 2034d. The drain of the second switch 2030b is coupled to the second node 2034b, and the source of the second switch 2030b is coupled to the fourth node 2034d. The third switch 2030c is coupled between the first node 2034a and the third node 2034c. The drain of the third switch 2030c is coupled to the third node 2034c, and the source of the third switch 2030c is coupled to the first node 2034a. The fourth switch 2030d is coupled between the first node 2034a and the fourth node 2034d. The drain of the fourth switch 2030d is coupled to the first node 2034a, and the source of the fourth switch 2030d is coupled to the fourth node 2034d. The fifth switch 2030e is coupled between the first node 2034a and the drain of the sixth switch 2030f. The drain of the fifth switch 2030e is coupled to the drain of the sixth switch 2030f, and the source of the fifth switch 2030e is coupled to the first node 2034a. The sixth switch 2030f is coupled between the drain of the fifth switch 2030e and the fifth node 2034e. The drain of the sixth switch 2030f is coupled to the drain of the fifth switch 2030e, and the source of the sixth switch 2030f is coupled to the fifth node 2034e. The seventh switch 2030g is coupled between the second node 2034b and the drain of the eighth switch 2030h. The drain of the seventh switch 2030g is coupled to the drain of the eighth switch 2030h, and the source of the seventh switch 2030g is coupled to the second node 2034b. The eighth switch 2030h is coupled between the drain of the seventh switch 2030g and the fifth node 2034e. The drain of the eighth switch 2030h is coupled to the drain of the seventh switch 2030g, and the source of the eighth switch 2030h is coupled to the fifth node 2034e.

[0198] The rectifier 2018 is operated to convert the input AC power into multi-level DC power. Fig.21 21 is a graph 2100 that includes a multi-level voltage waveform 2102 corresponding to a plurality of DC voltage levels generated by a rectifier 2018 based on an input current waveform 2104. In some examples, the rectifier 2018 is configured to output five different voltage levels (e.g., -Vdc, -Vdc / 2, 0V, +Vdc / 2, +Vdc). Fig.22A -22R shows various states of the rectifier 2018 when operated to generate five-level DC power.

[0199] Fig.22ACorresponding to the operation of the rectifier 1208 during the first interval (d0) (i.e., time tzc0 to time t0). A commutation path is provided by switches 2030e, 2030f, 2030g, and 2030h. Current is received from the coil 2022 at the first node 2034a. The commutation path directs the current to the fifth node 2034e, where the current returns to the coil 2022 via the second node 2034b. As such, a first DC voltage level (e.g., 0V) is provided at the output of the rectifier 2018 (e.g., at node 2034e).

[0200] Fig. 22B Corresponding to the operation of the rectifier 1208 at the first transition time (t0). A commutation path is provided by switches 2030c, 2030g, and 2030h. In some examples, a commutation path is provided by the body diode of switch 2030c. Current is received from the coil 2022 at the first node 2034a. The commutation path directs the current to the third node 2034c to charge the first capacitor 2032a before returning to the coil 2022 via nodes 2034b and 2034e.

[0201] Fig. 22C Corresponding to the operation of the rectifier 1208 during the second interval (d1) (i.e., time t0 to time t1). A commutation path is provided by switches 2030c, 2030g, and 2030h. Current is received from the coil 2022 at the first node 2034a. The commutation path directs the current to the third node 2034c to continue charging the first capacitor 2032a before returning to the coil 2022 via nodes 2034b and 2034e. In this way, a second DC voltage level (e.g., +Vdc / 2) is provided at the output of the rectifier 2018 (e.g., across the first capacitor 2032a).

[0202] Fig.22D Corresponding to the operation of the rectifier 1208 at the second transition time (t1). A commutation path is provided by switches 2030c and 2030b. In some examples, a commutation path is provided by the body diode of switch 2030b, receiving current from the coil 2022 at a first node 2034a. The commutation path directs the current to a third node 2034c to charge the first and second capacitors 2032a, 2023b before returning to the coil 2022 via nodes 2034b and 2034d.

[0203] Fig.22ECorresponding to the operation of the rectifier 1208 during the third interval (d2) (i.e., time t1 to time t2). A commutation path is provided by switches 2030c and 2030b. Current is received from the coil 2022 at the first node 2034a. The commutation path directs the current to the third node 2034c to continue charging the first and second capacitors 2032a, 2023b before returning to the coil 2022 via nodes 2034b and 2034d. In some examples, switch 2030f is turned on during the third interval. As such, a third DC voltage level (e.g., +Vdc) is provided at the output of the rectifier 2018 (e.g., across the first capacitor 2032a and the second capacitor 2032b).

[0204] Fig.22F Corresponding to the operation of the rectifier 1208 at the third transition time (t2). A commutation path is provided by switches 2030e, 2030f, and 2030b. In some examples, a commutation path is provided by the body diode of switch 2030e. Current is received from the coil 2022 at the first node 2034a. The commutation path directs the current to the fifth node 2034e to charge the second capacitor 2032b before returning to the coil 2022 via nodes 2034b and 2034d.

[0205] Figure 22G Corresponding to the operation of the rectifier 1208 during the fourth interval (d3) (i.e., time t2 to time t3). A commutation path is provided by switches 2030e, 2030f, and 2030b. Current is received from the coil 2022 at the first node 2034a. The commutation path directs the current to the fifth node 2034e to continue charging the second capacitor 2032b before returning to the coil 2022 via nodes 2034b and 2034d. As such, a third DC voltage level (e.g., +Vdc / 2) is provided at the output of the rectifier 2018 (e.g., across the second capacitor 2032b).

[0206] Fig.22H The operation of the rectifier 1208 corresponding to the zero-crossing tzc1 event (tzc1-dt) is similar to the operation during the fourth interval (d3) (eg, Figure 22G shown).

[0207] Fig.22ICorresponding to the operation of the rectifier 1208 after the zero crossing event tzc1 (tzc1+dt). A commutation path is provided by switches 2030e, 2030f, and 2030b. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the fourth node 2034d and through the second capacitor 2032b before returning to the coil 2022 via nodes 2034a and 2034e. In some examples, the switch 2030h is turned on during the period.

[0208] Fig.22J Corresponding to the operation of the rectifier 1208 at the fourth transition time (t3). A commutation path is provided by switches 2030e, 2030f, 2030g, and 2030h. In some examples, a commutation path is provided by the body diode of switch 2030g. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the fifth node 2034e, where the current returns to the coil 2022 via the first node 2034a.

[0209] Figure 22K Corresponding to the operation of the rectifier 1208 during the fifth interval (d4) (i.e., time t3 to time t4). A commutation path is provided by switches 2030e, 2030f, 2030g, and 2030h. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the fifth node 2034e, where the current returns to the coil 2022 via the first node 2034a. As such, a first DC voltage level (e.g., 0V) is provided at the output of the rectifier 2018 (e.g., at node 2034e).

[0210] Figure 22L Corresponding to the operation of the rectifier 1208 at the fifth transition time (t4). A commutation path is provided by switches 2030d, 2030g, and 2030h. In some examples, a commutation path is provided by the body diode of switch 2030d. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the fifth node 2034e to charge the second capacitor 2032b before returning to the coil 2022 via nodes 2034a and 2034d.

[0211] Figure 22MCorresponding to the operation of the rectifier 1208 during the sixth interval (d5) (i.e., time t4 to time t5). A commutation path is provided by switches 2030d, 2030g, and 2030h. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the fifth node 2034e to continue charging the second capacitor 2032b before returning to the coil 2022 via nodes 2034a and 2034d. As such, a fourth DC voltage level (e.g., -Vdc / 2) is provided at the output of the rectifier 2018 (e.g., across the second capacitor 2032b).

[0212] Fig.22N Corresponding to the operation of the rectifier 1208 at the sixth transition time (t5). A commutation path is provided by switches 2030a and 2030d. In some examples, a commutation path is provided by the body diode of switch 2030a. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the third node 2034c to charge the first and second capacitors 2032a, 2032b before returning to the coil 2022 via nodes 2034a and 2034d.

[0213] Graph 220 corresponds to the operation of rectifier 1208 during the seventh interval (d6) (i.e., time t5 to time t6). A commutation path is provided by switches 2030a and 2030d. Current is received from coil 2022 at second node 2034b. The commutation path directs current to third node 2034c to continue charging first and second capacitors 2032a, 2032b before returning to coil 2022 via nodes 2034a and 2034d. In some examples, switch 2030e is turned on during the seventh interval. Thus, a fifth DC voltage level (e.g., -Vdc) is provided at the output of rectifier 2018 (e.g., across first and second capacitors 2032a, 2032b).

[0214] Figure 22P Corresponding to the operation of the rectifier 1208 at the seventh transition time (t6). A commutation path is provided by switches 2030a, 2030e, and 2030f. In some examples, a commutation path is provided by a body diode of switch 2030f. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the third node 2034c to charge the first capacitor 2032a before returning to the coil 2022 via nodes 2034a and 2034e.

[0215] Figure 22QCorresponding to the operation of the rectifier 1208 during the eighth interval (d7) (i.e., time t6 to time t7). A commutation path is provided by switches 2030a, 2030e, and 2030f. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the third node 2034c to continue charging the first capacitor 2032a before returning to the coil 2022 via nodes 2034a and 2034e. In some examples, switch 2030g is turned on during the eighth interval. In this way, a fourth DC voltage level (e.g., -Vdc / 2) is provided at the output of the rectifier 2018 (e.g., across the first capacitor 2032a).

[0216] Figure 22R Corresponding to the operation of the rectifier 1208 at the eighth transition time (t7). A commutation path is provided by switches 2030e, 2030f, 2030g, and 2030h. In some examples, a commutation path is provided by a body diode of switch 2030h. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the fifth node 2034e, where the current returns to the coil 2022 via the first node 2034a.

[0217] Although the above example describes operating rectifier 2018 to generate DC power having five different voltage levels, it should be understood that rectifier 2018 can be operated to provide DC power having different multi-level variations. Fig.23 2300 includes a multi-level voltage waveform 2302 corresponding to a plurality of DC voltage levels generated by the rectifier 2018 based on the input current waveform 2304. As shown, the rectifier 2018 is configured to output three different voltage levels (e.g., -Vdc, 0V, +Vdc). When generating the three different output voltages, the first and second capacitors 2032a, 2032b are substantially equally charged. Fig.24A -24I shows various states of the rectifier 2018 when it is operated to generate three-level DC power.

[0218] Fig.24A Corresponding to the operation of the rectifier 1208 during the first interval (d0) (i.e., time tzc0 to time t0). A commutation path is provided by switches 2030e, 2030f, 2030g, and 2030h. Current is received from the coil 2022 at the first node 2034a. The commutation path directs the current to the fifth node 2034e, where the current returns to the coil 2022 via the second node 2034b. As such, a first DC voltage level (e.g., 0V) is provided at the output of the rectifier 2018 (e.g., at node 2034e).

[0219] Fig. 24B Corresponding to the operation of the rectifier 1208 at the first transition time (t0). A commutation path is provided by switches 2030c, 2030g, and 2030h. In some examples, a commutation path is provided by the body diode of switch 2030c. Current is received from the coil 2022 at the first node 2034a. The commutation path directs the current to the third node 2034c to charge the first capacitor 2032a before returning to the coil 2022 via nodes 2034b and 2034e.

[0220] Fig.24C Corresponding to the operation of the rectifier 1208 during the second interval (d1) (i.e., time t0 to time t1). A commutation path is provided by switches 2030c, 2030g, and 2030h. Current is received from the coil 2022 at the first node 2034a. The commutation path directs the current to the third node 2034c to continue charging the first capacitor 2032a before returning to the coil 2022 via nodes 2034b and 2034e. As such, a second DC voltage level (e.g., +Vdc) is provided at the output of the rectifier 2018 (e.g., across the first capacitor 2032a).

[0221] Fig.24D Corresponding to the operation of the rectifier 1208 at the second transition time (t1). A commutation path is provided by switches 2030c and 2030b. In some examples, a commutation path is provided by the body diode of switch 2030b. Current is received from coil 2022 at a first node 2034a. The commutation path directs the current to a third node 2034c to charge the first and second capacitor elements 2032a, 2032b before returning to coil 2022 via nodes 2034b and 2034d. In some examples, switch 2030f is turned on at the second transition time.

[0222] Fig.24E Corresponding to the operation of the rectifier 1208 resulting in a zero crossing tzc1 event (tzc1-dt). A commutation path is provided by switches 2030e, 2030f and 2030b. Current is received from the coil 2022 at a first node 2034a. The commutation path directs the current to a fifth node 2034e and through a second capacitor 2032b before returning to the coil 2022 via nodes 2034b and 2034d.

[0223] Fig.24FCorresponding to the operation of the rectifier 1208 after the zero crossing event tzc1 (tzc1+dt). A commutation path is provided by switches 2030e, 2030f, and 2030b. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the fourth node 2034d and through the second capacitor 2032b before returning to the coil 2022 via nodes 2034a and 2034e. In some examples, the switch 2030h is turned on during the period.

[0224] Figure 24G Corresponding to the operation of the rectifier 1208 during the third interval (d2) (i.e., time t1 to time t2). A commutation path is provided by switches 2030e, 2030f, 2030g, and 2030h. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the fifth node 2034e, where the current returns to the coil 2022 via the first node 2034a. As such, a first DC voltage level (e.g., 0V) is provided at the output of the rectifier 2018 (e.g., at node 2034e).

[0225] Fig.24H Corresponding to the operation of the rectifier 1208 at the third transition time (t2). A commutation path is provided by switches 2030d, 2030g, and 2030h. In some examples, a commutation path is provided by a body diode of switch 2030d. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the fifth node 2034e to charge the second capacitor 2032b before returning to the coil 2022 via nodes 2034a and 2034d.

[0226] Fig.24I Corresponding to the operation of the rectifier 1208 during the fourth interval (d3) (i.e., time t2 to time t3). A commutation path is provided by switches 2030d, 2030g, and 2030h. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the fifth node 2034e to continue charging the second capacitive element 2032b before returning to the coil 2022 via nodes 2034a and 2034d. As such, a third DC voltage level (e.g., -Vdc) is provided at the output of the rectifier 2018 (e.g., across the second capacitor 2032b).

[0227] Although the above examples describe transitioning one or more switches of the rectifier 2018 at a zero-crossing event, it should be understood that the rectifier 2018 may be operated without being aligned with a zero-crossing event. Fig.25is a graph 2500 including a multi-level voltage waveform 2502 corresponding to a plurality of DC voltage levels generated by the rectifier 2018 based on an input current waveform 2504 . Fig.26A -26D shows various states of the rectifier 2018 when operated to generate multi-level DC power.

[0228] Fig.26A Corresponding to the operation of the rectifier 1208 during the fourth interval (d3) (i.e., time t2 to time t3). A commutation path is provided by switches 2030e, 2030f, and 2030b. Current is received from the coil 2022 at the first node 2034a. The commutation path directs the current to the fifth node 2034e and through the second capacitor 2032b before returning to the coil 2022 via nodes 2034b and 2034d. At time t3-dt, switch 2030g is turned on.

[0229] Fig.26B Corresponding to the operation of the rectifier 1208 at the fourth transition time (t3). A commutation path is provided by switches 2030e, 2030f, 2030g, and 2030h. In some examples, a commutation path is provided by a body diode of switch 2030h. Current is received from the coil 2022 at the first node 2034a. The commutation path directs the current to the fifth node 2034e, where the current returns to the coil 2022 via the second node 2034b.

[0230] Fig.26C Corresponding to the operation of the rectifier 1208 during the fifth interval (d4) and before the zero crossing event (i.e., time t3 to time tzc1). A commutation path is provided by switches 2030e, 2030f, 2030g, and 2030h. Current is received from the coil 2022 at the first node 2034a. The commutation path directs the current to the fifth node 2034e, where the current returns to the coil 2022 via the second node 2034b.

[0231] Fig.26D Corresponding to the operation of the rectifier 1208 during the fifth interval (d4) and after the zero crossing event (i.e., time t2c1 to time t4). A commutation path is provided by switches 2030e, 2030f, 2030g, and 2030h. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the fifth node 2034e, where the current returns to the coil 2022 via the first node 2034a.

[0232] Rectifier 2018 can be operated to provide negative power. For example, Fig. 272700 includes a multi-level voltage waveform 2702 corresponding to a plurality of DC voltage levels generated by the rectifier 2018 based on an input current waveform 2704 . Fig.28A -28G shows various states of the rectifier 2018 when operated to generate multi-level DC power.

[0233] Fig.28A Corresponding to the operation of the rectifier 1208 during the fourth interval (d3) and before the zero crossing event (i.e., time t2 to time tzc1). A commutation path is provided by switches 2030e, 2030f, and 2030b. Current is received from the coil 2022 at the first node 2034a. The commutation path directs the current to the fifth node 2034e and through the second capacitor 2032b before returning to the coil 2022 via nodes 2034b and 2034d. In some examples, the switch 2030g is turned on during the period.

[0234] Fig.28B Corresponding to the operation of the rectifier 1208 during the fourth interval (d3) and after the zero crossing event (i.e., time t2c1 to time t3). A commutation path is provided by switches 2030e, 2030f, and 2030b. Current is received from the coil 2022 at the second node 2034b. The commutation path guides the current through the second capacitor 2032b and reaches the fifth node 2034e, and then returns to the coil 2022 via node 2034a. In some examples, the switch 2030h is turned on during the period. In this way, negative power is provided across the second capacitor 2032b.

[0235] Fig.28C Corresponding to the operation of the rectifier 1208 at the fourth transition time (t3). A commutation path is provided by switches 2030e, 2030f, 2030g, and 2030h. In some examples, a commutation path is provided by the body diode of switch 2030g. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the fifth node 2034e, where the current returns to the coil 2022 via the first node 2034a.

[0236] Fig.28D Corresponding to the operation of the rectifier 1208 during the fifth interval (d4) (i.e., time t3 to time t4). A commutation path is provided by switches 2030e, 2030f, 2030g, and 2030h. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the fifth node 2034e, where the current returns to the coil 2022 via the first node 2034a.

[0237] Fig.28ECorresponding to the operation of the rectifier 1208 during the eighth interval (d7) and before the zero crossing event (i.e., time t6 to time tzc2). A commutation path is provided by switches 2030a, 2030e, and 2030f. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current through the first capacitor 2032a and to the fifth node 2034e before returning to the coil 2022 via node 2034a.

[0238] Fig.28F Corresponding to the operation of rectifier 1208 during the eighth interval (d7) and after the zero crossing event (i.e., time t2c2 to time t7). A commutation path is provided by switches 2030a, 2030e and 2030f. Current is received from coil 2022 at a first node 2034a. Before returning to coil 2022 via node 2034b, the commutation path guides current to a fifth node 2034e and passes through a first capacitor 2032a. In some examples, switch 2030g is turned on during the period. In this way, negative power is provided at both ends of the first capacitive element 2032a.

[0239] Figure 28G Corresponding to the operation of the rectifier 1208 at the eighth transition time (t7). A commutation path is provided by switches 2030e, 2030f, 2030g, and 2030h. In some examples, a commutation path is provided by a body diode of switch 2030h. Current is received from the coil 2022 at the first node 2034a. The commutation path directs the current to the fifth node 2034e, where the current returns to the coil 2022 via the second node 2034b.

[0240] The rectifier 2018 can be operated in an inductive case. For example, Fig.29 is a graph 2900 that includes a multi-level voltage waveform 2902 corresponding to multiple DC voltage levels generated by the rectifier 2018 based on an input current waveform 2904. Fig. 30A -30C shows various states of the rectifier 2018 when operated to generate multi-level DC power.

[0241] Fig. 30A Corresponding to the operation of the rectifier 1208 during the first interval (d0). A commutation path is provided by switches 2030e, 2030f, 2030g, and 2030h. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the fifth node 2034e, where the current returns to the coil 2022 via the first node 2034a.

[0242] Fig. 30BThe first option corresponds to the operation of the rectifier 1208 during the second interval (d1) and before the zero crossing event (i.e., time t0 to time tzc0). A commutation path is provided by switches 2030c, 2030g, and 2030h. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current to the fifth node 2034e and through the first capacitor 2032a before returning to the coil 2022 via node 2034a.

[0243] Fig. 30C The second option corresponds to the operation of the rectifier 1208 during the second interval (d1) and before the zero crossing event (i.e., time t0 to time tzc0). A commutation path is provided by switches 2030b, 2030e, and 2030f. Current is received from the coil 2022 at the second node 2034b. The commutation path directs the current through the second capacitor 2032b and to the fifth node 2034e before returning to the coil 2022 via node 2034a. Fig. 30B and 30C In the first and second options shown, the rectifier 2018 operates with hard switching and provides negative power.

[0244] The following equations (1)-(5) represent the parameters of the rectifier 2018 (and the wireless power receiver 2000) when the top and bottom pulses are aligned. Equation (1) represents the fundamental component of the rectifier voltage (d = rectifier duty cycle (eg, 0-0.5)).

[0245] Equation (1):

[0246] Equation (2) represents the basic components of the rectifier current, assuming there is no phase shift across the rectifier. The rectifier current increases as the duty cycle decreases.

[0247] Equation (2):

[0248] Equation (3) represents the equivalent AC impedance of the rectifier.

[0249] Equation (3):

[0250] Equation (4) represents the equivalent load resistance seen by a vehicle assembly (VA) coil (eg, coil 2022).

[0251] Equation (4):

[0252] Equation (5) represents the VA coil current (eg, the current in coil 2022).

[0253] Equation (5):

[0254] The following equations (6)-(9) represent the general situation of the rectifier 2018. Equation (6) represents the voltage of the rectifier.

[0255] Equation (6):

[0256] Parameter Δτ = delay of voltage at the rectifier relative to current. The parameter is implemented by the operation of the active rectifier. If the parameter is zero, the middle of the positive cycle of the voltage waveform will be one quarter cycle after the negative to positive zero crossing of the rectifier current. Positive Δτ delays the voltage waveform relative to the current. Parameters Δτb and Δτt are the delays at the bottom and top pulses, respectively.

[0257] Equation (7) represents the current of the rectifier.

[0258] Equation (7):

[0259] Equation (8) represents the voltage of the bottom pulse.

[0260] Equation (8):

[0261] Equation (9) represents the voltage of the top pulse.

[0262] Equation (9):

[0263] Fig.31 and Equation (10) represent the input impedance of a three-level rectifier operating at constant power and ZVS. Fig.31 As shown, the input impedance ZAC of the three-level rectifier for ZVS falls on the curve corresponding to equation (10).

[0264] Equation (10):

[0265] Fig.32 and Equation (11) represents the input impedance of the five-level rectifier operating at constant power and ZVS. Fig.32 As shown, because the five-level rectifier can change state at non-zero crossings of the input current, the input impedance ZAC can fall anywhere in the fourth quadrant defined by the curve corresponding to equation (11). To prevent battery discharge, the rectifier delay is limited by equation (11).

[0266] Equation (11): in

[0267] The following equations (12)-(16) represent the input impedance of a five-level rectifier with a general non-inductive load.

[0268] Equation (12): Z AC =Z AC,b +Z AC,t

[0269] Equation (13): in

[0270] Equation (14): Where 0 < Δτ t <β b -β t ,

[0271] P Target,t ≤P Target,b ,

[0272] P Target =P Target,t +P Target,b

[0273] Equation (15):

[0274] Equation (16): Im{Z VA +(X L,VA -X VA )}=0

[0275] Re{Z VA} * can be expressed by b , Δτ t , β b , β t , P target，b and P target，t Choose an appropriate value to maximize.

[0276] Fig.33 -35 represents various parameters indicating the impact of the multi-level active rectifier on the ground assembly (GA) and the inverter.

[0277] Hardware and software implementation

[0278] Embodiments of the subject matter, functional operations, and processes described in this specification may be implemented in other types of digital electronic circuits, in tangibly embodied computer software or firmware, in computer hardware (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more of them. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-volatile program carrier for execution by a data processing device or for controlling the operation of a data processing device. Alternatively or additionally, program instructions may be encoded on an artificially generated propagated signal (e.g., a machine-generated electrical, optical, or electromagnetic signal) that is generated to encode information for transmission to an appropriate receiver device for execution by a data processing device. A computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access storage device, or a combination of one or more of them.

[0279] The term "system" may include all kinds of devices, devices and machines for processing data, including, for example, a programmable processor, a computer or multiple processors or computers. A processing system may include special-purpose logic circuits, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). In addition to hardware, a processing system may include code that creates an execution environment for the computer program in question, for example, code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0280] A computer program (which may also be referred to or described as a program, software, software application, module, software module, script or code) may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines or code portions). A computer program may be deployed to execute on one or more computers located at one site or distributed across multiple sites and interconnected by a communications network.

[0281] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuits, and the devices can also be implemented as special purpose logic circuits, such as FPGAs (field programmable gate arrays) or ASICs (application specific integrated circuits).

[0282] For example, a computer suitable for executing a computer program may include a general or special purpose microprocessor or both, or any other type of central processing unit. Typically, the central processing unit will receive instructions and data from a read-only memory or a random access memory or both. A computer typically includes a central processing unit for executing or executing instructions and one or more storage devices for storing instructions and data. Typically, a computer will also include one or more large-capacity storage devices for storing data, or operably coupled to receive data from one or more large-capacity storage devices for storing data or transmit data to one or more large-capacity storage devices for storing data or both, the large-capacity storage device being, for example, a magnetic disk, a magneto-optical disk, or an optical disk. However, a computer need not have such a device. In addition, a computer may be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device (such as a universal serial bus (USB) flash drive), to name a few examples.

[0283] Computer-readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and memory may be supplemented by, or incorporated in, special purpose logic circuitry.

[0284] Embodiments of the subject matter described in this specification may be implemented in a computing system that includes a back-end component (e.g., as a data server), or includes a middleware component (e.g., an application server), or includes a front-end component (e.g., a client computer with a graphical user interface or a web browser through which a user can interact with an implementation of the subject matter described in this specification), or any combination of one or more such back-end, middleware, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include local area networks ("LANs") and wide area networks ("WANs"), such as the Internet.

[0285] A computing system may include clients and servers. Clients and servers are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0286] Although this specification includes many specific implementation details, these details should not be interpreted as limitations on the scope of the claimed protection, but should be interpreted as descriptions of features peculiar to a particular embodiment. Certain features described in this specification in the context of a separate embodiment may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a variant of a sub-combination or a sub-combination.

[0287] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in sequence, or that all of the operations shown be performed to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single product or packaged into multiple products.

[0288] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes described in the accompanying drawings do not necessarily require the particular order shown or the sequential order to achieve the desired results. In certain implementations, multitasking and parallel processing may be advantageous. Other steps or stages may be provided, or steps or stages may be removed from the described processes. Therefore, other implementations are within the scope of the appended claims.

[0289] the term

[0290] The phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting.

[0291] The term "about", the phrase "approximately equal to" and other similar phrases (e.g., "X has a value of approximately Y" or "X is approximately equal to Y") used in the specification and claims should be understood to mean that one value (X) is within a predetermined range of another value (Y). Unless otherwise specified, the predetermined range can be plus or minus 20%, 10%, 5%, 3%, 1%, 0.1%, or less than 0.1%.

Claims

1. An inverter configured for a wireless power system, the inverter include: at least one capacitor; as well as at least one switching branch, each switching branch comprising a plurality of switches having at least one switch coupled to the at least one capacitor, wherein the plurality of switches of each switching branch are configured to be controlled such that during operation: (i) generating an output voltage having an asymmetric multi-level distribution with at least four non-zero unequal voltage levels; as well as (ii) At least one switch among the plurality of switches operates with zero voltage switching.

2. The inverter according to claim 1, in, The plurality of switches of each switching branch are configured to be controlled such that during operation: (iii) at least one switch of the plurality of switches is operated to transition from a minimum voltage level of the output voltage to a maximum voltage level of the output voltage by providing a first non-zero voltage level for a first duration and a second non-zero voltage level for a second duration; as well as (iv) at least one of the plurality of switches is operated to transition from the maximum voltage level of the output voltage to the minimum voltage level of the output voltage by providing the first non-zero voltage level for a third duration and the second non-zero voltage level for a fourth duration, wherein the first duration and the third duration have different lengths and / or the second duration and the fourth duration have different lengths.

3. The inverter according to claim 2, in, Transitioning from the minimum voltage level of the output voltage to the maximum voltage level of the output voltage includes operating the at least one switch of the plurality of switches to provide a zero voltage level for the fourth duration.

4. The inverter according to claim 3, in, Transitioning from the maximum voltage level of the output voltage to the minimum voltage level of the output voltage includes operating the at least one switch of the plurality of switches to provide the zero voltage level for a fifth duration. 5 . The inverter of claim 2 , further comprising at least one input configured to receive an input voltage Vdc.

6. The inverter of claim 5, wherein the minimum voltage level is -Vdc, the first non-zero voltage level is -Vdc / n, the second non-zero voltage level is +Vdc / n, and the maximum voltage level is +Vdc, where n is a positive integer equal to or greater than 2.

7. The inverter according to claim 5, in, The multi-level distribution includes at least five different voltage levels, including a minimum voltage level of -Vdc, a first non-zero voltage level of -Vdc / 2, a zero voltage level, a second non-zero voltage level of +Vdc / 2 and a maximum voltage level of +Vdc.

8. The inverter according to claim 1, in, Each switch of the plurality of switches is an N-channel MOSFET.

9. The inverter according to claim 1, in, The plurality of switches of each switch branch includes a first switch, a second switch, a third switch and a fourth switch.

10. The inverter according to claim 9, in, The at least one capacitor includes (i) a first capacitor coupled between a first node and a second node, and (ii) a second capacitor coupled between the second node and a third node; The first switch of the switch branch is coupled between the first node and a fourth node, and the second switch of the switch branch is coupled between the fourth node and the third node. wherein the third switch of the switch branch and the fourth switch of the switch branch are coupled between the second node and the fourth node, wherein the source of the third switch of the switch branch is connected to the source of the fourth switch of the switch branch, and Wherein the first node and the third node are inputs to the inverter.

11. The inverter according to claim 9, in, The first switch of the switch branch is coupled between a first node and a second node, the second switch of the switch branch is coupled between the second node and a third node, the third switch of the switch branch is coupled between the third node and a fourth node, and the fourth switch of the switch branch is coupled between the fourth node and a fifth node; wherein the capacitor is coupled between the second node and the fourth node, and Wherein the first node and the fifth node are inputs to the inverter.

12. The inverter according to claim 9, in, The at least one capacitor includes (i) a first capacitor coupled between a first node and a second node, and (ii) a second capacitor coupled between the second node and a third node; wherein the first switch of the switch branch is coupled between the first node and a fourth node, the second switch of the switch branch is coupled between the fourth node and a fifth node, the third switch of the switch branch is coupled between the fifth node and a sixth node, and the fourth switch of the switch branch is coupled between the sixth node and the third node, wherein a first device is coupled between the second node and the fourth node, and a second device is coupled between the second node and the sixth node, and Wherein the first node and the third node are inputs to the inverter.

13. The inverter according to claim 12, in, The first device and the second device are diodes.

14. The inverter according to claim 12, in, The first device and the second device are switches.

15. The inverter according to claim 9, in, The at least one capacitor includes: (i) a first capacitor coupled between a first node and a second node, (ii) a second capacitor coupled between the first node and a third node, and (iii) a third capacitor coupled between the second node and the third node, wherein the first switch of the first switch branch is coupled between the first node and the fourth node, the second switch of the first switch branch is coupled between the fourth node and the third node, the third switch of the first switch branch is coupled between the third node and the fifth node, and the fourth switch of the first switch branch is coupled between the fifth node and the second node, wherein the first switch of the second switch branch is coupled between the first node and a sixth node, the second switch of the second switch branch is coupled between the sixth node and the third node, the third switch of the second switch branch is coupled between the third node and a seventh node, and the fourth switch of the second switch branch is coupled between the seventh node and the second node, wherein the fifth switch of the first switch branch is coupled between the fourth node and the eighth node, the fifth switch of the second switch branch is coupled between the seventh node and the eighth node, the sixth switch of the first switch branch is coupled between the fourth node and the ninth node, and the sixth switch of the second switch branch is coupled between the sixth node and the ninth node, and Wherein the first node and the second node are inputs to the inverter.

16. The inverter according to claim 9, in, The at least one capacitor includes: (i) a first capacitor coupled between a first node and a second node, (ii) a second capacitor coupled between the first node and a third node, and (iii) a third capacitor coupled between the second node and the third node, wherein the first switch of the first switch branch is coupled between the first node and a fourth node, the second switch of the first switch branch is coupled between the fourth node and the third node, the third switch of the first switch branch is coupled between the third node and a fifth node, and the fourth switch of the first switch branch is coupled between the fifth node and the second node, wherein the first switch of the second switch branch is coupled between the first node and a sixth node, the second switch of the second switch branch is coupled between the sixth node and the third node, the third switch of the second switch branch is coupled between the third node and a seventh node, and the fourth switch of the second switch branch is coupled between the seventh node and the second node, and Wherein the first node and the second node are inputs to the inverter.

17. The inverter of claim 1, wherein the inverter is a half-bridge inverter.

18. The inverter of claim 1, wherein the inverter is a full-bridge inverter.

19. A wireless power system, include: An inverter comprising at least one capacitor and at least one switch branch, each switch branch comprising a plurality of switches having at least one switch coupled to the at least one capacitor, wherein the plurality of switches of each switch branch are configured to be controlled such that during operation: (i) generating an output voltage having an asymmetric multi-level distribution with at least four non-zero unequal voltage levels; as well as (ii) The plurality of switches are operated with zero voltage switching.

20. The wireless power system of claim 19, wherein the plurality of switches of each switch branch are configured to be controlled such that during operation: (iii) at least one switch of the plurality of switches is operated to transition from a minimum voltage level of the output voltage to a maximum voltage level of the output voltage by providing a first non-zero voltage level for a first duration and a second non-zero voltage level for a second duration; and (iv) at least one of the plurality of switches is operated to transition from the maximum voltage level of the output voltage to the minimum voltage level of the output voltage by providing a first non-zero voltage level for a third duration and a second non-zero voltage level for a fourth duration, wherein the first duration and the third duration have different lengths and / or the second duration and the fourth duration have different lengths.

21. The system according to claim 19, in, The inverter is disposed within a wall box, and wherein an output of the inverter is connected to the impedance matching network via a cable.

22. The system of claim 19, wherein the inverter is disposed within a charging pad configured to be located under a vehicle, and wherein an input of the inverter is connected to a cable.

23. A controller for a wireless power system, wherein the system comprises an inverter configured to output an output current, and the controller is configured to generate a gate drive signal for driving a corresponding switch of the inverter, the controller include: a control module configured to generate a first control signal having a first voltage level and a second control signal having a second voltage level; as well as A modulator configured to (a) receive a signal representing the output current, and (b) generate a carrier signal based on the output current, wherein the carrier signal includes a first carrier signal and a second carrier signal, such that: (i) when the first carrier signal is greater than the first voltage level, the first gate drive signal for the first switch is high, and (ii) when the second carrier signal is greater than the second voltage level, the second gate drive signal for the second switch is high, The inverter is thereby driven to output a multi-level voltage having a first output level based on the first drive signal and a second output level based on the second drive signal.

24. The controller of claim 23, wherein the multi-level voltage has an asymmetric waveform.

25. The controller according to claim 23, in, The carrier signal is configured, at least in part, to maintain zero voltage switching by the switches of the inverter.

26. The controller of claim 23, wherein a voltage value of the second output level is approximately equal to a value of the second voltage level.

27. The controller of claim 23, wherein the voltage value of the first output level is approximately half the value of the second voltage level.

28. The controller of claim 23, wherein the first gate drive signal is high for a first duration when the first carrier signal is greater than the first voltage level, and the second gate drive signal is high for a second duration when the second carrier signal is greater than the second voltage signal.

29. The controller of claim 23, wherein the first voltage level is based on a value of the second voltage level.

30. The controller of claim 23, wherein at least one of the first carrier signal and the second carrier signal has a sawtooth wave modulation.

31. The controller according to claim 23, in, At least one of the first carrier signal and the second carrier signal has a triangle wave modulation.

32. The controller of claim 23, wherein the modulator is configured to receive and generate an analog signal.

33. The controller of claim 23, wherein the modulator is configured to receive and generate a digital signal.

34. A method for controlling a wireless power system, wherein the system comprises an inverter and a controller, the inverter being configured to output an output current, and the controller being configured to generate a gate drive signal for driving a corresponding switch of the inverter, the method include: generating, via the controller, a first control signal having a first voltage level and a second control signal having a second voltage level; receiving, at the controller, a signal representative of the output current; as well as generating a carrier signal based on the output current via the controller, wherein the carrier signal includes a first carrier signal and a second carrier signal, such that: (i) when the first carrier signal is greater than the first voltage level, the first gate drive signal for the first switch is high, and (ii) when the second carrier signal is greater than the second voltage level, the second gate drive signal for the second switch is high, The inverter is thereby driven to output a multi-level voltage having a first output level based on the first gate driving signal and a second output level based on the second gate driving signal.

35. The method of claim 34, wherein the multi-level voltage has an asymmetric waveform.

36. The method of claim 34, wherein the carrier signal is generated based on the output current include: A carrier signal is generated that is configured at least in part to maintain zero voltage switching by the switches of the inverter.

37. The method of claim 34, wherein a voltage value of the second output level is approximately equal to a value of the second voltage level.

38. The method of claim 34, wherein the voltage value of the first output level is approximately half the value of the second voltage level.

39. The method of claim 34, wherein the first gate drive signal is high for a first duration when the first carrier signal is greater than the first voltage level, and the second gate drive signal is high for a second duration when the second carrier signal is greater than the second voltage signal.

40. The method of claim 34, wherein the first voltage level is based on a value of the second voltage level.

41. The method according to claim 34, in, At least one of the first carrier signal and the second carrier signal has a sawtooth wave modulation.

42. The method according to claim 34, in, At least one of the first carrier signal and the second carrier signal has a triangle wave modulation.

43. The method of claim 34, wherein the controller is configured to receive and generate an analog signal.

44. The method of claim 34, wherein the controller is configured to receive and generate digital signals.

45. A rectifier configured for use in a wireless power system, the rectifier include: at least one capacitor; as well as at least one switching branch, each switching branch comprising a plurality of switches having at least one switch coupled to the at least one capacitor, wherein the plurality of switches of each switching branch are configured to be controlled such that during operation: (i) generating a plurality of output voltages, the plurality of output voltages comprising at least two non-zero unequal voltage levels; as well as (ii) At least one switch among the plurality of switches operates with zero voltage switching.

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