Switched mode power supply with modulated peak inductor current

Abstract

In one example, an apparatus (900) includes an amplifier (912), a ramp generation circuit (918), and a comparator (920). The amplifier has a reference input, a power converter feedback input, and an amplifier output. The ramp generation circuit has a ramp slope control terminal and a ramp signal terminal, the ramp slope control terminal coupled to the amplifier output. The comparator has a current sense input, a ramp signal input, and a comparator output, where the ramp signal input is coupled to the ramp signal terminal, and the comparator output is coupled to a power converter control terminal.

Description

Background Art

[0001] A switch mode power supply (SMPS) uses semiconductor switching technology to transfer power from an input power source to a load. An SMPS may include energy storage elements (e.g., inductors, capacitors, transformers, etc.) and switches. Through the operation of the switch, the energy storage element can continuously switch between a charging state and a discharging state in each switching cycle. The controller of the SMPS can determine the on-time and off-time of the switch, which can reflect the duration of the charging and discharging states in the switching cycle, so that the SMPS can provide the required power to the load. Summary of the invention

[0002] A device includes an amplifier, a ramp generation circuit, and a comparator. The amplifier has a reference input, a power converter feedback input, and an amplifier output. The ramp generation circuit has a ramp slope control terminal and a ramp signal terminal, the ramp slope control terminal is coupled to the amplifier output. The comparator has a current sensing input, a ramp signal input, and a comparator output, wherein the ramp signal input is coupled to the ramp signal terminal, and the comparator output is coupled to the power converter control terminal.

[0003] A device includes a power converter and a controller. The power converter has a power input, a power output, a current sensing output, and a control input. The controller has a control output, a feedback voltage input, a reference voltage input, and a current sensing input. The control output is coupled to the control input. The feedback voltage input is coupled to the power output. The current sensing input is coupled to the current sensing output. The controller includes an amplifier, a ramp generation circuit, and a comparator. The amplifier has an amplifier output and first and second amplifier inputs, the first amplifier input is coupled to the reference voltage input, and the second amplifier input is coupled to the feedback voltage input. The ramp generation circuit has a ramp slope control terminal and a ramp signal terminal, the ramp slope control terminal is coupled to the amplifier output. The comparator has a comparator output and first and second comparator inputs, the first comparator input is coupled to the current sensing input, the second comparator input is coupled to the ramp signal terminal, and the comparator output is coupled to the control output.

[0004] In one method, a current sense signal is received that represents a current through a switch of a power converter. An error signal is generated that indicates a load condition. In response to the error signal indicating that a light load condition is satisfied: a ramp signal having a ramp rate is generated based on the error signal. A current target signal is generated based on subtracting the ramp signal from the error signal. The current target signal is compared to the current sense signal to generate a decision. And, a switching signal is provided to the power converter in response to the decision. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1A schematic diagram including an example of a switched mode power supply (SMPS).

[0006] Figure 2 , Figure 3 , Figure 4 and Figure 5 is a graph illustrating an example operation of an SMPS.

[0007] Figure 6 , Figure 7 and Figure 8 is a graph illustrating an example operation of an SMPS.

[0008] Fig. 9 FIG. 4 is a schematic diagram illustrating an example controller of an SMPS.

[0009] Fig.10 , Fig.11 and Fig.12 To illustrate Fig. 9 Graph of example operation of an SMPS and controller.

[0010] Fig.13 and Fig.14 for Fig. 9 A schematic diagram of an example internal components of a controller.

[0011] Fig.15 , Fig.16 and Fig.17 To illustrate Fig. 9 Graph of example operation of an SMPS and controller.

[0012] Fig.18 is a graph illustrating example efficiency properties of an SMPS under different control schemes.

[0013] Fig.19 is a flow chart of an example method of operating a SMPS.

[0014] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0015] Figure 1 A schematic diagram of an example of a switch mode power supply (SMPS) 100 is shown. Figure 1 In the first schematic diagram, SMPS 100 may include a power stage 102 and an energy storage element 104 coupled between a power source 106, a capacitor 108, and a load 110. The power source 106 can provide an input voltage (at Figure 1 The mark "V in”) is provided to the SMPS 100. The power stage 102 may include switches 112a and 112b. The switch 112a may include a transistor, such as a field effect transistor (FET). The switch 112b may be configured as a rectifier switch, and if the switch 112b is a synchronous switch, it may include a diode or a transistor (e.g., a FET). The energy storage element 104 may include, for example, an inductor, a capacitor, or a transformer. The power stage 102 may receive a switching signal 114, which may switch the states of the switches 112a and 112b. By switching the switches 112a and 112b, the energy storage element 104 may store the energy received from the power source 106 in the energy storage element 104 and the energy storage element 104 may output a voltage (at Figure 1 The mark "V out ”) and switches between a discharging state in which the stored energy is provided to the load 110 in the form of an output current. The capacitor 108 can smooth the ripple of the output voltage. Figure 1 Other schematic diagrams of FIG. 1 show example configurations of the power stage 102 and energy storage elements 104 , such as a buck converter 120 , a boost converter 122 , and a buck-boost converter 124 , where the energy storage element 104 may be an inductor.

[0016] Figure 2 and Figure 3 FIG. 2 is a waveform diagram showing an example operation of SMPS 100. Figure 2 2, graph 200 is a plot of the voltage of the switching signal 114 versus time, and graph 202 is a plot of the current conducted through the energy storage element (e.g., inductor) 104. Graph 200 depicts two example switching cycles of the switching signal 114 labeled sw0 and sw1. Switching cycle sw0 begins at time T 0 Across to T 2 , and the switching cycle sw1 starts from time T 2 Across to T 4 The switching cycle sw0 has a 0 With T 1 The conduction time T on,0 , where the inductor 104 is in a charging state; and at T 1 With T 2 The off time T off,0 , where the inductor 104 is in a discharge state. In addition, the switching cycle sw1 has a 2 With T 3 The conduction time T on,1 and in T 3 With T 4 The off time T off,1 , during the on-time, the inductor 104 is in a charging state again, and during the off-time, the inductor 104 is in a discharging state again.

[0017] When the power stage 102 is enabled, the inductor 104 may be in a charging state, which includes the switch 112a being turned on and the switch 112b being turned off. When the inductor 104 is in the charging state, the inductor 104 may receive current from the power source 106, and as magnetic energy is stored in the inductor 104, the current increases with respect to time from the non-negative minimum current I min Increase to the peak current I peak The rate of increase of the inductor current during the on-time may be based on the voltage across the inductor 104, which may be based on the input voltage V in .

[0018] When the power stage 102 is disabled, the inductor 104 may be in a discharge state, which includes the switch 112a being turned off and the switch 112b being turned on. When the inductor 104 is in the discharge state, the inductor 104 may release the stored magnetic energy and provide a current that is proportional to the time from I peak Reduce back to I min The rate at which the inductor current decreases during the off time may be based on the voltage across the inductor 104, which may be based on the output voltage V out .

[0019] The duration of the on-time within a switching cycle may affect the peak current and the amount of magnetic energy stored in the inductor 104, which may also affect the energy provided by the inductor 104 to the load 110. For example, in Figure 2 In the switching cycle sw0, the on-time T on,0 Can be longer than the on-time T of the switching cycle sw1 on,1 , and the peak current I in the switching cycle sw0 peak,0 can become greater than the peak current I in the switching cycle sw1 peak,1 Therefore, the inductor 104 can provide more energy to the load 110 in the switching cycle sw1 compared to the switching cycle sw2. And the duty cycle of the switching cycle, which can be defined by the ratio between the on-time and the cycle period duration, can determine the input voltage V in With output voltage V out The ratio between them.

[0020] In some examples, the SMPS 100 may be controlled by a controller that implements a feedback system to adjust the on-time and off-time of the switching cycle so that the SMPS can provide a desired voltage and / or a desired current to the load. Specifically, the controller may receive a measurement of the current conducted by the inductor 104 and a measurement of the voltage provided by the SMPS 100. Based on a comparison of the current conducted by the inductor 104 with the desired / target current value, the controller may adjust the on-time of the switching cycle, which may also adjust the duration of the charging state of the inductor 104 within the switching cycle and the peak inductor current. In addition, based on a comparison of the voltage provided by the SMPS 100 with a reference voltage, the controller may adjust the on-time of the switching cycle and / or the duty cycle to adjust the output voltage of the SMPS 100 to the reference voltage.

[0021] The controller can set the on-time and off-time of the switching cycle based on various techniques including pulse width modulation (PWM) and pulse frequency modulation (PFM). With PWM, the switching cycle period and the switching frequency can be kept constant. Since the switching frequency is constant, PWM can provide a predictable operating frequency and low output ripple characteristics. The SMPS 100 can also operate at high efficiency during heavy load conditions, where the switching losses caused by the power stage 102 may be small compared to the amount of power delivered to the load 110. The controller can adjust the on-time of the switching cycle to adjust the peak inductor current and the output voltage. Figure 2 The operation in can be PWM operation mode. Figure 2 In the example, the switching cycles sw0 and sw1 may have the same cycle period T sw In the switching cycle sw0, the controller can set the on-time T on,0 To obtain the peak inductor current I peak,0 In the switching cycle sw1, the controller can set different on-times T on,1 To obtain different peak inductor currents I peak,1 .

[0022] The controller can also set the on-time and off-time of the switching cycle based on the PFM. Using PFM, the controller can maintain the on-time constant and adjust the switching frequency to adjust the power provided to the load. PFM can improve the efficiency of the SMPS when operating under low load conditions or standby conditions. Under these conditions, when the demand for current from the load is reduced to near zero, the switching frequency can be reduced. The switching losses caused by the power stage 102 can be reduced compared to the power transmitted by the SMPS 100, which can improve the efficiency of the SMPS. And, because the switching frequency is reduced, the average inductor current can be reduced to match the reduced current demand of the load.

[0023] Figure 3Included is a graph illustrating an example operation of SMPS 100 in PFM mode. Figure 3 3 , graph 300 is a plot of the voltage of the switching signal 114 versus time, and graph 302 is a plot of the current conducted by the inductor 104 . Figure 3 Two switching cycles (sw0 and sw1) are shown in Figure 1. Using PFM, the controller can maintain the on-time while adjusting the off-time of the switching cycle. Figure 3 In the two switching cycles sw0 and sw1, the on-time T on , which results in the same peak inductor current I peak However, the switching cycles sw0 and sw1 may have different corresponding off-times T off,0 and T off,1 During each off time, the inductor current can be peak Drop to minimum current I min (e.g., zero) and remain at I min For example, in the switching cycle sw0, the inductor 104 is at T 1' to T 2 Minimum current I min , and in the switching cycle sw1, the inductor 104 is at T 3 'To T 3 Minimum current I min . in I min When I is zero, the two switches 112a and 112b can be disconnected. min The average current between switching cycles may be different depending on the duration of Figure 3 In the case of sw1, T off,1 T longer than sw0 off,0 , so the average current I avg0 Can be higher than the average current I of sw1 avg1 The controller may increase T in response to a decrease in the demand for current from the load 110. off,1 To reduce the average current provided to the load 110 during the switching cycle sw1. The duty cycle of the switching signal (which varies with the off time) can also set the output voltage V out .

[0024] Figure 4 The graph 400 is a graph showing the switching frequency of the SMPS 100 relative to the load current. Referring to the graph 400 , if the load current is lower than the minimum load current I load_min , then the SMPS 100 may stop switching. And, in order to reduce the load_min But below the PWM threshold Ipwm_min The SMPS 100 can operate in PFM mode, and the switching frequency increases with the load current. Also, if the load current is higher than I pwm_min , then the SMPS 100 can operate in PWM mode at a constant switching frequency. The SMPS 100 can adjust the on-time of the switching cycle to adjust the load current.

[0025] Although operating the SMPS100 in PFM mode can improve the efficiency of the power converter under light load conditions, the variable switching frequency in PFM mode can worsen the electromagnetic interference (EMI) between the SMPS100 and other electronic components. Specifically, because the switching frequency varies with the load current, in order to support a wide range of load currents, the SMPS100 can also have a wide switching frequency range in PFM mode. Therefore, the SMPS100 may have a fundamental switching frequency or its harmonics, which are close to the operating frequencies of other electronic components supplying a specific load current, and may violate the EMI requirements of those components. For example, various automotive electromagnetic compatibility (EMC) test standards, such as the International Special Committee on Radio Interference (CISPR), contain thresholds for radio interference in various frequency ranges. The SMPS100 operating in PFM mode may emit an electromagnetic signal having a fundamental frequency (or harmonic frequency) within those frequency ranges and having a power exceeding the threshold defined in the CISPR standard. Therefore, the SMPS100 operating in PFM mode under certain load conditions may not meet the CISPR standard and may not be suitable for automotive applications.

[0026] In some examples, the SMPS 100 may also operate in a forced PWM (FPWM) mode under light load conditions. The switching frequency of the SMPS 100 in PWM mode may be selected to comply with certain EMI requirements (eg, CISPR). Figure 5 Included is a graph illustrating an example operation of the SMPS 100 in FPWM mode under light load conditions. Figure 5 , graph 500 is a plot of the current conducted by inductor 104, and graph 502 is a plot of the voltage of switching signal 114 versus time. Referring to graph 502, SMPS 100 may switch at a constant frequency, and the switching cycle may have a constant cycle period T sw And, within the switching cycle, the off time T is extended off This allows the inductor current to reach a negative minimum value, I min , then in the subsequent cycle the on-time T on In the case of min Increase to the positive peak I peak The controller can adjust the on-time T of the switching cycleon and / or off time T off To set the negative minimum inductor current I min and the positive peak inductor current I peak .

[0027] exist Figure 5 In FPWM operation, the average current supplied to the load is I avg The switching frequency can be reduced due to the negative inductor current while the switching frequency can be selected to meet EMI requirements. However, the conduction of the negative inductor current in each switching cycle, which consumes a lot of power, can significantly reduce the efficiency of the SMPS 100. Under light load conditions where the negative current is comparable to or even exceeds the load current, the efficiency of the SMPS 100 can become extremely low.

[0028] Figure 6 , Figure 7 and Figure 8 Graphs are shown illustrating example techniques for operating the SMPS 100 under different light load conditions that may address at least some of the issues described above. Figure 6 The load conditions in Figure 7 The load condition in is heavier (e.g., the current demand of load 110 is greater), and Figure 7 The load conditions in the Figure 8 The load conditions in are heavier.

[0029] refer to Figures 6 to 8 , the controller can provide a ramp signal to modulate the peak inductor current. An example of a ramp signal is shown in Figure 6 The curve graph 600, Figure 7 The graph 700 and Figure 8 The ramp signal may have a constant cycle period T ramp , which is the switching cycle period T SW In some examples, the switching frequency may be 2.4 megahertz (MHz), and the frequency of the ramp signal may be 400 kilohertz (kHz), such that each ramp cycle period may include up to six switching cycles.

[0030] Within each ramp cycle period, the magnitude of the ramp signal may decrease over time. The magnitude of the ramp signal may define the peak inductor current target for a particular switching cycle. Both the initial value of the ramp signal at the start of the ramp cycle period and the rate at which the ramp signal decreases over time (ramp / slew rate) may depend on load conditions. For example, the initial peak inductor current target at the start of the ramp cycle period may be Figure 6 I peak_init0 , Figure 7 I peak_init1 and Figure 8 Ipeak_init2 , where I peak_init0 Higher than I peak_init1 , and I peak_init1 Higher than I peak_init2 And, the ramp rate of the ramp signal has an inverse relationship with the load condition, with a lower ramp rate for heavier load conditions and a higher ramp rate for lighter load conditions. Depending on the ramp rate, the ramp signal can decrease from an initial value at the beginning of the cycle period to a final value at the end of the cycle period, for example Figure 6 I peak_final , or it can be reduced to a minimum current value I at or before the cycle period min (e.g., zero), such as Figure 7 and 8 as shown in .

[0031] Figures 6 to 8 Graphs 602, 702, and 802 illustrate example effects of a ramp signal on an inductor current, and Figures 6 to 8 Graphs 604, 704, and 804 of FIG. 1 depict example effects of a ramp signal on the switching signal 114. As described above, the magnitude of the ramp signal may define a peak inductor current target for a particular switching cycle. In response to the inductor current reaching the peak inductor current target for the switching cycle, the controller may stop the on-time of the switching cycle and the charging of the inductor, and start the off-time of the switching cycle and the discharging of the inductor. Thus, the on-time of the switching cycle (e.g., Figure 6 T on0 to T on5 and Figure 7 T on0 to T on3 ) gradually decreases over time during the ramp cycle.

[0032] The controller may adjust the slope (ramp rate) of the ramp signal to adjust the average output current supplied to the load 110 and the capacitor 108 . Figures 6 to 8 The average output current is marked as I avg0 ,I avg1 and I avg2 , where I avg0 Higher than I avg1 , and I avg1 Higher than I avg2 And, the slope of the ramp signal changes from Figure 6 to Figure 7 and from Figure 7 to Figure 8Gradually becomes steeper. Specifically, referring to graphs 602, 702, and 802, because the magnitude of the ramp signal defines the peak inductor current target for a particular switching cycle, the peak inductor current target may decrease more slowly over the ramp cycle period if the ramp signal has a relatively shallow slope. This may increase the total amount of current supplied to the inductor during the charging state, which may also increase the average current supplied to the load by the SMPS 100.

[0033] The slope of the ramp also sets the width of the ramp signal, T ramp_width , which means that the peak inductor current target is higher than I min The ramp signal width can set the number of switching cycles in the ramp period. Specifically, in some instances, if the peak inductor current target is close to or below I min , then the controller may disable switching of the power stage 102, which may indicate that the output current to be supplied by the SMPS 100 is below the minimum load condition. Therefore, in the case where the ramp signal has a steeper slope and a narrower width, the number of switching cycles within the ramp cycle period may be reduced, which may further reduce the average current supplied to the load by the SMPS 100. For example, in Figure 6 In the middle, the slope width T ramp_width0 With ramp cycle period T ramp is the same, and there are six switching cycles in each ramp cycle. Figure 7 In the example, since the ramp signal is steeper, the ramp width T ramp_width1 Shorter than T ramp_width0 , and the number of switching cycles in each ramp cycle is reduced to four. In addition, Figure 8 The ramp signal has a ratio Figure 7 The steeper the slope, the wider the slope, T ramp_width2 Shorter than T ramp_width1 , and each ramp cycle contains only a single switching cycle. Figure 8 In the example, the slope of the ramp signal can allow a minimum on-time T on_min Due to the delay in turning off switch 112a and turning on switch 112b, the inductor current may become negative due to ringing, which may further reduce the average current supplied to the load by SMPS 100.

[0034] Figures 6 to 8 The example control techniques described in can improve the compliance of SMPS 100 with EMI requirements when operating under light load conditions. Specifically, both the frequency of the ramp signal and the switching frequency can be selected to comply with EMI requirements, and both frequencies can be constant or invariant with respect to load conditions. Thus, the switching signal can have fundamental and harmonic frequency components that meet EMI requirements regardless of load conditions. Figure 4and 5 Compared to the PFM operation described in , where the switching signal frequency can vary with load and may violate EMI requirements under certain load conditions, Figures 6 to 8 The example control techniques described in allow for more predictable compliance with EMI requirements.

[0035] And, with Figure 5 Compared to the FPWM operation described in Figures 6 to 8 The control technique described in can improve the efficiency of SMPS100 while meeting EMI requirements. As described above, although the switching frequency in FPWM operation can be selected to meet EMI requirements, the off time of each switching cycle is extended to allow the inductor current to reach a negative minimum value to reduce the average output current. However, the conduction of negative current in each switching cycle, which consumes a lot of power, can significantly reduce the efficiency of SMPS100. In contrast, in Figures 6 to 8 In the example control technique described in , the ramp signal can modulate the peak inductor current, and the average output current can be reduced by increasing the slope of the ramp signal. The conduction of negative inductor current can be reduced, and the efficiency of the SMPS 100 can be improved when operating under light load conditions.

[0036] Fig. 9 For implementation Figures 6 to 8 Schematic diagram of an example power system 900 of an example control technique. Fig. 9 , the power system 900 includes the SMPS 100 and a controller 902. The power system 900 also includes a voltage divider 904 (eg, a resistor divider) to provide an output voltage (V out ) feedback voltage (V FB ) 906. The controller 902 may be based on V FB 906 determines the load condition and operates the SMPS 100 in different operating modes depending on the load condition. Under non-light load conditions, the controller 902 may operate the SMPS 100 in a PWM mode, similar to Figure 2 Under light load conditions, the controller 902 may operate the SMPS 100 by providing a ramp signal 908 to modulate the peak inductor current, such as Figures 6 to 8 Described in .

[0037] Specifically, the controller 902 may include amplifiers 912, 914, and 916, a ramp generation circuit 918, a comparator 920, and a switching signal generation circuit 922. The amplifier 912 has a voltage divider 904 coupled to receive V FB Amplifier 912 also has a first input (eg, negative input) for receiving a reference voltage signal (V REF) 930 has a second input (eg, a positive input) which may represent a target output voltage of the SMPS 100. The amplifier 912 may generate a voltage representing V FB 906 and V REF The error signal 932 is a voltage difference between 930 and 931. The magnitude (e.g., voltage) of the error signal 932 may indicate a load condition. This is because if the SMPS 100 is not providing enough current to the load 110, the capacitor 108 may discharge to supply the additional current, which may cause the output voltage (and V FB 906) decreases, and the voltage difference increases. Therefore, an error signal 932 with a large magnitude (e.g., a large voltage) may indicate a larger target current to be supplied by the SMPS 100, which may represent a heavy load condition. And, an error signal 932 with a small magnitude (e.g., a small voltage) may indicate a smaller target current to be supplied by the SMPS 100, which may represent a light load condition.

[0038] In some examples, the controller 902 may include a clamp circuit 933 coupled to the output of the amplifier 912 to set upper and lower limits on the magnitude of the error signal 932. The clamp circuit 933 may include a unity gain voltage buffer. The upper limit of the error signal 932 may represent the peak inductor current limit of the SMPS 100 under heavy load conditions. And, the lower limit of the error signal 932 may represent a threshold for light load conditions. Under light load conditions, the magnitude of the error signal 932 may be at a lower limit, and the controller 902 may modulate the peak inductor current by a combination of the error signal 932 and the ramp signal 908, as will be described below.

[0039] The amplifier 914 has a first input coupled to the output of the amplifier 912 to receive the error signal 932. The amplifier 914 also has a second input coupled to the ramp signal terminal of the ramp generation circuit 918 to receive the ramp signal 908. The amplifier 914, which may include a subtraction circuit, may generate a current target signal 934 by subtracting the ramp signal 908 from the error signal 932. As will be discussed below, during non-light load conditions, the ramp generation circuit 918 may generate a flat / static ramp signal 908 (e.g., at 0v or ground voltage), and the current target signal 934 may represent the error signal 932. Also, during light load conditions, the ramp generation circuit 918 may generate the ramp signal 908 having a ramp rate / slew rate that reflects the load condition, and the current target signal 934 may also include a signal similar to Figures 6 to 8 The ramp signal shown in the graphs 600, 700 and 800 of FIG. The magnitude (eg, voltage) of the current target signal 934 may define the peak current (eg, peak inductor current) conducted by the energy storage element 104 during a switching cycle.

[0040] The comparator 920 may have a first input (e.g., a positive input) coupled to a current sense terminal of the SMPS 100 and a second input (e.g., a negative input) coupled to the output of the amplifier 914. The comparator 920 may receive a current sense signal 940 representing a measurement of an inductor current in the SMPS 100 at a first input and a current target signal 934 at a second input, and generate a decision signal 942 representing a comparison between the inductor current and a peak inductor current target represented by the current target signal 934. If the inductor current is lower than the peak inductor current target, the comparator 920 may generate the decision signal 942 having a first state (e.g., a logical zero), and if the inductor current is equal to the peak inductor current target, the decision signal 942 is switched to a second state (e.g., a logical one). In some examples, if the current target signal 934 is lower than a threshold value representing a minimum load condition (e.g., an input voltage range of the comparator 920), the comparator 920 may maintain the decision signal 942 in the second state.

[0041] A switching signal generator 922, which may include a clocked sequential logic circuit such as a flip-flop, has a first signal input coupled to the output of the comparator 920 to receive the decision signal 942. The switching signal generator 922 also has a second signal input coupled to a voltage source 950 and a clock input that receives a first clock signal 952. The switching signal generator 922 also has a signal output coupled to a control terminal of the power stage 102 (e.g., a control terminal of switches 112a and 112b) to provide a switching signal 114. In some examples, the first signal input may be coupled to a reset input (labeled R) of the flip-flop, the second signal input may be coupled to a data input (labeled D) of the flip-flop, and the signal output may be coupled to a data output (labeled Q) of the flip-flop. The voltage source 950 may provide a voltage representing a logical one.

[0042] The first clock signal 952 may define the switching frequency of the switching signal 114. For example, in the case where the switching frequency is 2.4 MHz, the first clock signal 952 may have a frequency of 2.4 MHz. Each switching cycle begins with the decision signal 942 (and the reset input) having a logic zero state. The on-time (T on) begins. The switching signal 114 may have a first state that enables the power stage 102, and as the inductor is in a charging state, the inductor current increases over time. As the inductor current increases and becomes equal to the peak current target, the decision signal 942 (and the reset input) may switch to a logic one state. In response to the switching of the decision signal 942, the switching signal 114 may also switch to a second state that disables the power stage 102, and the on-time of the switching cycle ends. As the inductor discharges, the inductor current then decreases over time. And, in the event that the minimum load condition is reached, the decision signal 942 (and the reset input) may remain in a logic one state, which keeps the flip-flop in a reset state and keeps the power stage 102 in a disabled state.

[0043] Also, under light load conditions, the amplifier 916 and the ramp generation circuit 918 can generate a ramp signal 908 having a ramp rate / slew rate that reflects the load conditions. Specifically, the amplifier 916 has a first input (e.g., a negative input) coupled to the output of the amplifier 912 to receive the error signal 932. The amplifier 916 has a first input (e.g., a negative input) that receives the current threshold (I TH ) signal 960. The current threshold signal 960 may be a voltage signal representing a threshold of a light load condition. The amplifier 916 may generate a slope signal 962 representing the difference between the error signal 932 and the current threshold signal 960. In some examples, the error signal 932 and the current threshold signal 960 are voltage signals, and the difference is a voltage difference. If the error signal 932 exceeds the current threshold signal 960, the amplifier 916 may generate a slope signal 962 having a disabled / inactive state (e.g., having a voltage / current below the threshold). However, if the error signal 932 is below the current threshold signal 960, which indicates that the load current to be supplied by the SMPS 100 is below the threshold of the light load condition, the amplifier 916 may generate a slope signal 962 in an enabled / active state (e.g., having a voltage / current above the threshold), and the magnitude of the slope signal 962 may represent the difference between the error signal 932 and the current threshold signal 960. The difference may represent an amount of current (eg, an average current) to be supplied by the SMPS 100 to the load 110 under light load conditions.

[0044] The ramp generation circuit 918 includes a slope control terminal, a ramp signal terminal, and a clock input. The slope control terminal of the ramp generation circuit 918 is coupled to the output of the amplifier 916, and the ramp signal terminal of the ramp generation circuit 918 is coupled to the second input of the amplifier 914. The ramp generation circuit 918 can receive the slope signal 962 via the slope control terminal. In response to the slope signal 962 having a disabled / inactive state, the ramp generation circuit 918 can be disabled. And, in response to the slope signal 962 having an enabled / active state, the ramp generation circuit 918 can provide a ramp signal 908 with a ramp / slew rate based on the magnitude of the slope signal 962.

[0045] The ramp generation circuit 918 also has a clock input to receive a second clock signal 964 that defines a cycle period of the ramp signal 908. For example, the second clock signal 964 may have a frequency of 400 kHz. In each ramp cycle period, the ramp generation circuit 918 may provide a ramp signal 908 having a ramp / slew rate based on the slope signal 962.

[0046] In some examples, the ramp generation circuit 918 can generate a ramp signal 908 that increases over time in each ramp cycle period. Thus, the current threshold signal 960 from the subtraction between the error signal 932 and the ramp signal 908 can ramp down and provide a current threshold similar to that generated by Figures 6 to 8 The reduced peak inductor current target represented by the graphs 600, 700, and 800 of FIG. The ramp generation circuit 918 may also set the ramp rate of the ramp signal 908 according to an inverse relationship with the slope signal 962 (which represents the load condition). For example, the ramp generation circuit 918 may decrease the ramp rate of the ramp signal 908 in response to an increase in the magnitude of the slope signal 962. As the ramp rate of the ramp signal 908 decreases, the rate of decrease of the peak inductor current across the switching cycle within the ramp cycle period may be reduced, and the average output current may be increased to meet the relatively heavy load condition. Also, the ramp generation circuit 918 may increase the ramp rate of the ramp signal 908 in response to a decrease in the magnitude of the slope signal 962. As the rate of decrease of the peak inductor current across the switching cycle within the ramp cycle period increases, the average output current may be reduced to meet the relatively light load condition.

[0047] Fig.10 , 11 12 are graphs illustrating examples of the ramp signal 908, the current target signal 934, and the error signal 932 under various light load conditions. Fig.10 The operation of the controller 902 and SMPS 100 shown in FIG. 1 will provide a Fig.11 For larger load currents, Fig.11 Draw the ratio Fig.12 operation in larger load currents. Figures 10 to 12 , the ramp signal 908 and the error signal 932 are represented as voltage signals.

[0048] Fig.10 Graphs 1002, 1004, and 1006 are shown. Graph 1002 shows the change of the peak inductor current target represented by the current target signal 934 over time, graph 1004 shows the change of the error signal 932 over time, and graph 1006 shows the change of the ramp signal 908 over time. Graphs 1002 to 1006 show the controller 902 and the SMPS 100 in accordance with Figure 7 1002 may be compared to the example operation under the same load conditions as in FIG. Figure 7 The graph 700 is the same as that of FIG.

[0049] Referring to graphs 1004 and 1006, in each ramp cycle period T ramp The ramp generation circuit 918 can provide a signal with a slew rate dV based on the slope signal 962. 0 / dt increases with time. 0 At a rate of / dt, the ramp signal 908 can be ramped from the initial ramp voltage V ramp_init0 Increases to the final ramp voltage V ramp_final In some examples, the initial ramp voltage V ramp_init0 Can be 0v (or ground voltage). The final ramp voltage V ramp_final is lower than the voltage of error signal 932, which has a voltage represented by slope signal 962 (and slew rate dV 0 / dt) represents the voltage V under the same load condition error0 .

[0050] Also, referring to graph 1002, amplifier 914 (or subtraction circuit) may generate current target signal 934 by subtracting ramp signal 908 from error signal 932. Thus, the peak inductor current target represented by current target signal 934 may be at a highest value at the beginning of the ramp cycle and have an I peak_init0 As the ramp signal 908 increases, the peak inductor current target decreases over time during the ramp cycle period. The peak inductor current target may have a value of I at the end of the ramp cycle period. peak_final The value of .

[0051] Fig.11Graphs 1102, 1104, and 1106 are shown. Graph 1102 shows the change of the peak inductor current target represented by the current target signal 934 over time, graph 1104 shows the change of the error signal 932 over time, and graph 1106 shows the change of the ramp signal 908 over time. Graphs 1102 to 1106 show the controller 902 and the SMPS 100 in accordance with Figure 8 1102 may be compared to the example operation under the same load conditions as in FIG. Figure 8 The graph 800 is the same as that of FIG.

[0052] Referring to graphs 1104 and 1106, in each ramp cycle period T ramp The ramp generation circuit 918 can provide a signal with a slew rate dV based on the slope signal 962. 1 / dt increases with time. 1 At a rate of / dt, the ramp signal 908 can be increased from the initial ramp voltage V ramp_init (which may be 0 V) ​​increases and reaches the voltage V of the error signal 932 before the end of the ramp cycle period. error1 The ramp signal 908 is from V ramp_init Increase to V error1 The duration of the current target signal 934 may define the ramp width T ramp_width1 The ramp signal 908 may be at V during the remainder of the ramp cycle. error1 , and then switches to V at the beginning of the next ramp cycle ramp_init Voltage V error1 The slope signal 962 (and the slew rate dV 1 / dt) represents the same load condition. As described above, Fig.11 Indicates ratio Fig.10 Therefore, V error1 Lower than Fig.10 V error0 , and the slew rate dV 1 / dt is higher than Fig.10 The rotation rate dV 0 / dt.

[0053] Also, referring to graph 1002, amplifier 914 (or a subtraction circuit) may generate a current target signal 934 by subtracting ramp signal 908 from error signal 932. Thus, the peak inductor current target represented by current target signal 934 may be at a highest value at the beginning of a ramp cycle and have a value of I peak_init1As the ramp signal 908 increases, the peak inductor current target decreases over time during the ramp cycle. When the ramp signal 908 has a value that is consistent with the error signal 932 (V error1 ) at the same voltage, the peak inductor current target can be set from the start of the ramp cycle through T ramp_width1 After the duration reaches the minimum current value I min The peak inductor current target can be maintained at I min .

[0054] Fig.12 Graphs 1202, 1204, and 1206 are shown. Graph 1202 shows the change of the peak inductor current target represented by the current target signal 934 over time, graph 1204 shows the change of the error signal 932 over time, and graph 1206 shows the change of the ramp signal 908 over time. Graphs 1202 to 1206 show the controller 902 and the SMPS 100 in accordance with Figure 8 1202 may be compared to the example operation under the same load conditions as in FIG. Figure 8 The curve diagram 800 is the same as that of FIG.

[0055] Referring to graphs 1204 and 1206, in each ramp cycle period T ramp The ramp generation circuit 918 can provide a signal with a slew rate dV based on the slope signal 962. 2 / dt increases with time. 2 At a rate of / dt, the ramp signal 908 can be increased from the initial ramp voltage V ramp_init (which may be 0 V) ​​increases and reaches the voltage V of the error signal 932 before the end of the ramp cycle period. error2 The ramp signal 908 is from V ramp_init Increase to V error2 The duration of the current target signal 934 may define the ramp width T ramp_width2 The ramp signal 908 may remain at V for the remainder of the ramp cycle. error2 , and then switches to V at the beginning of the next ramp cycle ramp_init Voltage V error2 The slope signal 962 (and the slew rate dV 2 / dt) represents the same load condition. As described above, Fig.12 Indicates ratio Fig.11 Therefore, V error2 Lower than Fig.11 V error1 (and Fig.10 V error0), and the slew rate dV 2 / dt is higher than Fig.11 The rotation rate dV 1 / dt(and Fig.10 The rotation rate dV 0 / dt). Also, due to the higher slew rate and reduced V error2 , the ramp signal 908 may be at a ratio of V error1 A shorter duration from V ramp_init Increase to V error2 ,and Fig.12 The slope width T ramp_width2 Shorter than Fig.11 The slope width T ramp_width1 .

[0056] Also, referring to graph 1202, amplifier 914 (or subtraction circuit) may generate current target signal 934 by subtracting ramp signal 908 from error signal 932. Thus, the peak inductor current target represented by current target signal 934 may be at a highest value at the beginning of the ramp cycle and have a current value of I peak_init2 As the ramp signal 908 increases over time, the peak inductor current target decreases over time during the ramp cycle. When the ramp signal 908 has a value that is consistent with the error signal 932 (V error2 ) at the same voltage, the peak inductor current target can be set from the start of the ramp cycle through T ramp_width2 After the duration reaches the minimum current value I min The peak inductor current target can be maintained at I min .

[0057] Fig.13 FIG. 9 is a schematic diagram showing an example of internal components of the ramp generation circuit 918. Fig.13 , in some examples, the ramp generation circuit 918 includes a capacitor 1302 and a switch 1304. The top plate of the capacitor 1302 is coupled to both the slope control terminal and the ramp signal terminal, and the bottom plate of the capacitor 1302 is coupled to the ground terminal. The switch 1304 is also coupled between the slope control terminal (and the ramp signal terminal) and the ground terminal. The ramp generation circuit 918 also includes a switch driver circuit 1306 coupled between the clock input and the control terminal of the switch 1304. The switch driver circuit 1306 can provide a control signal 1310 in response to the second clock signal 964 to turn on / off the switch 1304.

[0058] Specifically, at the beginning of each ramp cycle, the switch driver circuit 1306 may provide a control signal 1310 of a first state with a short duration to turn on the switch 1304, which shorts the top and bottom plates of the capacitor 1302 to remove the stored charge, and the slope control terminal and the ramp signal terminal may have a V of the ground terminal. ramp_init The switch driver circuit 1306 may then switch the control signal 1310 to a second state to open the switch 1304 for the remainder of the ramp cycle period, and the slope control terminal and the ramp signal terminal may be disconnected from the ground terminal.

[0059] When the switch 1304 is open, the amplifier 916 may provide a slope signal 962 to charge the capacitor 1302. In some examples, the amplifier 916 may include a transconductance amplifier and may provide the slope signal 962 as a current signal, wherein the magnitude of the current signal represents the voltage difference between the error signal 932 and the current threshold signal 960. As described above, the voltage of the error signal 932 increases with the amount of current to be supplied by the SMPS 100. Thus, in light load conditions (e.g., Fig.10 and 11 ), the voltage of the error signal 932 may be close to the light load condition threshold represented by the current threshold signal 960. Therefore, the voltage difference between the error signal 932 and the current threshold signal 960 may be relatively small. The small voltage difference causes the amplifier 916 to provide a reduced current in the slope signal 962 to charge the capacitor 1302. Because the capacitor 1302 is charged with a reduced current, the voltage of the ramp signal 908 at the ramp signal terminal may increase more slowly over time, which results in a relatively slow slew rate, such as Fig.10 and 11 as shown in .

[0060] Also, under very light load conditions (e.g. Fig.12 ), the voltage of the error signal 932 may be relatively small and significantly different from the light load condition threshold represented by the current threshold signal 960. Therefore, the voltage difference between the error signal 932 and the current threshold signal 960 may be relatively large. The increased voltage difference causes the amplifier 916 to provide an increased current in the slope signal 962 to charge the capacitor 1302. Because the capacitor 1302 is charged with the increased current, the voltage of the ramp signal 908 at the ramp signal terminal may increase more rapidly over time, which results in a relatively high slew rate, such as Fig.12 In some examples, amplifier 916 may clamp the voltage of the top plate of capacitor 1302 (and the voltage of the ramp / slope control terminal) to the voltage of error signal 932 (eg, Fig.11 and 12 Verror1 and V error2 ), so that the ramp voltage stops increasing after reaching the voltage of the error signal 932.

[0061] Fig.14 FIG. 9 is a schematic diagram showing an example of internal components of the ramp generation circuit 918. Fig.14 In some examples, the ramp generation circuit 918 includes an analog-to-digital converter (ADC) 1402, a ramp controller 1404, and a digital-to-analog converter (DAC) 1406. The ADC 1402 may have an analog input coupled to a slope control terminal and a digital output coupled to an input of the ramp controller 1404. The output of the ramp controller 1404 may be coupled to a digital input of the DAC 1406, and the analog output of the DAC 1406 is coupled to a ramp signal terminal. Also, the ADC 1402 is coupled to a clock input (CLK), and the ramp controller 1404 is also coupled to the CLK input and a high-speed clock input (HCLK). The HCLK input may receive a first clock signal 952 having a switching frequency, and the CLK input may receive a second clock signal 964 having a ramp signal frequency.

[0062] Specifically, the ADC 1402 may sample the slope signal 962 at the ramp signal frequency and provide a digital signal 1412 of the slope signal 962 to the ramp controller 1404. Based on the digital signal 1412, the ramp controller 1404 may provide a control signal 1414 to the DAC 1406 to generate the ramp signal 908. The ramp controller 1404 may determine whether the light load threshold is reached based on the slope signal 962. If the digital signal 1412 indicates that the light load threshold is not reached (e.g., the digital signal 1412 indicates zero), the ramp controller 1404 may provide a control signal 1414 to the DAC 1406 to provide a ramp signal at V ramp_init A voltage signal (which can be 0v).

[0063] Also, if the digital signal 1412 indicates that the light load threshold is reached (e.g., the digital signal 1412 is non-zero), the ramp controller 1404 may determine the voltage range and slope of the ramp signal 908 based on the digital signal 1412. As described above, under light load conditions, the magnitude of the slope signal 962 may be relatively large (due to the increase in the difference between the error signal 932 and the current threshold signal 960), the digital signal 1412 may represent a large digital value, and the ramp controller 1404 may set a high slew rate for the ramp signal 608. Also, under very light load conditions, the magnitude of the slope signal 962 may be relatively small (due to the decrease in the difference between the error signal 932 and the current threshold signal 960), the digital signal 1412 may represent a small digital value, and the ramp controller 1404 may set a low slew rate for the ramp signal 608. The ramp controller 1404 may also determine a transient voltage of the ramp signal 908 at a switching cycle based on the slew rate and clamp the voltage to the error signal 932. Within each ramp signal cycle, the ramp controller 1404 may provide a control signal 1414 representing the transient voltage and update the control signal 1414 at each switching cycle so that the DAC 1406 may provide a ramp signal 608 representing the load condition that increases over time at the ramp / slew rate, such as Figures 10 to 12 This is shown in graphs 1006 , 1106 , and 1206 .

[0064] Fig.15 , 16 17 and 18 are diagrams showing the current target signal 934, the inductor current, and the output voltage of the SMPS (eg, SMPS 100) under different load conditions across multiple ramp cycles T. ramp Graphs of additional instances of . Fig.15 Included are graphs 1502 , 1504 , and 1506 depicting example operation of controller 902 and SMPS 100 when providing an average current of 500 mA. Fig.16 Included are graphs 1602 , 1604 , and 1606 that illustrate example operation of controller 902 and SMPS 100 when providing an average current of 200 mA. Fig.17 Included are graphs 1702, 1704, and 1706 illustrating example operation of controller 902 and SMPS 100 when providing an average current of 50 mA. Figures 15 to 17 For a ramp signal frequency of 400kHz, the ramp cycle period T ramp is equal to 2.5 microseconds (μs), and for a switching frequency of 2.4 MHz, the switching cycle period T SW Equal to 0.4167μs.

[0065] Fig.18Included is a graph depicting example variations in efficiency of an SMPS (e.g., SMPS 100) relative to load current under different operating modes. The efficiency may be based on the ratio between the amount of power delivered to the SMPS by a power source (e.g., power source 106) and the amount of power delivered to the load by the SMPS. Fig.18 The diagram includes graphs 1802, 1804, and 1806. Graph 1802 is depicted on a screen similar to Figure 3 1804 is an example of a change in the efficiency of an SMPS operating in a PFM mode. Figure 5 Graph 1806 illustrates an example variation in the efficiency of an SMPS in which the peak inductor current is modulated by a ramp signal, such as Figures 6 to 8 and Figures 10 to 12 Described in .

[0066] like Fig.18 As shown in , by modulating the peak inductor current using a ramp signal according to the load conditions, the efficiency of the SMPS can be higher than that of the FPWM mode for an extremely wide range of load conditions (e.g., an output current range of 0.1 μA to 0.2 A). The efficiency improvement is particularly significant under light load conditions (e.g., 0.1 μA to 0.01 mA). This is because in the FPWM mode, the SMPS conducts a constant negative inductor current in each switching cycle to reduce the average current. In contrast, by modulating the peak inductor current using a ramp signal, the average current can be reduced by increasing the ramp rate, and the conduction of the negative inductor current can be reduced or otherwise not required to reduce the average current. Therefore, the reduction in the negative inductor current can substantially improve the efficiency of the SMPS. Under a wide range of load conditions, such as when the load current exceeds 0.01A, the efficiency of the SMPS with ramp modulation of the peak inductor current is also similar to that of the PFM.

[0067] Fig.19 Flowchart of an example method 1900 for controlling a power converter, such as SMPS 100 . Method 1900 may be performed by a controller, such as controller 402 .

[0068] In operation 1902, the controller may receive a current sense signal (e.g., current sense 940) representing an inductor current of the power converter. As described above, when the inductor is in a charging state, the inductor current increases during the on-time of a power stage (e.g., power stage 102) of the power converter. When the inductor is in a discharging state, the inductor current decreases during the off-time of the power stage.

[0069] In operation 1904, the controller may generate an error signal indicative of a load condition. In some examples, the controller may receive a feedback voltage (eg, VFB 906) and a reference voltage signal (eg, V REF 930), and generates an error signal (e.g., error signal 932) representing the difference between the output voltage of the power converter and the reference voltage. The error signal may also represent the amount of current to be supplied by the SMPS to the load, and may indicate a load condition. The reference voltage may represent a target output voltage of the power converter, and the magnitude of the error signal may indicate a load condition. As described above, if the SMPS is providing an insufficient amount of current to the load, which indicates a heavy load condition, the capacitor at the load (e.g., capacitor 108) may discharge to supply additional current, which causes the output voltage to drop and increases the voltage difference. Therefore, an error signal with a large magnitude (e.g., a large voltage) may indicate a larger target current to be supplied by the SMPS, which indicates a heavy load condition. And, an error signal with a small magnitude (e.g., a small voltage) may indicate a smaller target current to be supplied by the SMPS, which indicates a light load condition.

[0070] In operation 1906, the controller may determine whether a light load condition is met based on the error signal. Specifically, the controller (e.g., amplifier 916) may generate a slope signal 962 representing the difference between the error signal and a current threshold signal (e.g., current threshold signal 960). In some examples, both the error signal and the current threshold signal are voltage signals, and the difference may be a voltage difference. The current threshold signal represents a threshold for a light load condition. Reference Fig. 9 , if the error signal 932 exceeds the current threshold signal, indicating that the light load condition is not satisfied, the amplifier 916 may generate a slope signal 962 having a disabled / inactive state. However, if the error signal 932 is below the current threshold signal 960, indicating that the load current to be supplied by the SMPS 100 is below the threshold of the light load condition and the light load condition is satisfied, the amplifier 916 may generate a slope signal 962 in an enabled / active state (e.g., having a voltage / current above the threshold), and the magnitude of the slope signal 962 may represent the difference between the error signal 932 and the current threshold signal 960. The difference may represent the amount of current (e.g., average current) to be supplied by the SMPS 100 to the load 110 under the light load condition.

[0071] If the light load condition is met (e.g., the error signal 932 is lower than the current threshold signal 960), the controller may proceed to operation 1908 and generate a ramp signal (e.g., ramp signal 908) having a ramp rate based on the error signal. Specifically, the controller (e.g., the ramp generation circuit 918) may also set the ramp rate of the ramp signal 908 according to an inverse relationship with the slope signal 962 (which represents the load condition), for example, the ramp generation circuit 918 may decrease the ramp rate of the ramp signal 908 in response to an increase in the magnitude of the slope signal 962, which may reduce the rate of decrease of the peak inductor current across the switching cycle within the ramp cycle period and increase the average output current. Also, the ramp generation circuit 918 may increase the ramp rate of the ramp signal 908 in response to a decrease in the magnitude of the slope signal 962, which may increase the rate of decrease of the peak inductor current across the switching cycle within the ramp cycle period and reduce the average output current.

[0072] In some examples, the controller may include an amplifier (eg, amplifier 916) having an output coupled to a capacitor (eg, capacitor 1302), and the amplifier may charge the capacitor to generate a ramp signal that ramps up over time, such as Fig.13 . The amplifier may include a transconductance amplifier to provide the slope signal 962 as a current. The amplifier may set the current based on the voltage difference between the error signal 932 and the current threshold signal 960. For heavier load conditions where the error signal 932 is close to the current threshold signal 960, the voltage difference may decrease, and for light load conditions where the error signal 932 is far from the current threshold signal 960, the voltage difference may increase. Thus, the controller may be able to operate under very light load conditions (e.g., Fig.12 ) to charge the capacitor with a relatively large current and increase the slew rate of the ramp signal, and under light load conditions (such as Fig.10 and 11 In some examples, the controller may include a DAC, such as Fig.14 As shown, a ramp signal 908 is generated.

[0073] In operation 1910, the controller may provide a current target signal based on the ramp signal and the error signal. For example, the amplifier 914 may generate the current target signal 934 by subtracting the ramp signal 608 from the error signal 932, such that the current target signal 934 ramps down over time at the same ramp / slew rate as the ramp signal 908.

[0074] In operation 1912 , the controller may compare the current target signal to the current sense signal to generate a first decision. The first decision may indicate whether the inductor current is equal to (or above) the current target represented by the current target signal 934 / error signal 932 .

[0075] In operation 1914, the controller may provide a first switching signal to the power converter in response to the first decision. Specifically, if the first decision indicates that the inductor current is below the current target, the controller may set the first switching signal to a first state. And, if the first decision indicates that the inductor current is equal to (or higher than) the current target, the controller may set the first switching signal to a second state. In response to the first switching signal having the first state, the power stage 102 may be turned on and the inductor may be in a charging state. And, in response to the first switching signal having the second state, the power stage 102 may be turned off and the inductor may be in a discharging state. Since the target current decreases over time, the peak inductor current also decreases across the switching cycle at a rate that reflects the load conditions.

[0076] Referring back to operation 1906, if the light load condition is not met (e.g., the error signal 932 is above the current threshold signal 960), the controller may proceed to operation 1918 and generate a flat / quiescent current target signal based on the error signal, and compare the current sense signal to the flat current sense signal to generate a second decision in operation 1920. Specifically, in response to the slope signal being in the disabled state, the ramp generation circuit 918 may generate a flat or zero ramp signal 908, and the amplifier 914 may provide a flat current target signal 934 representing the error signal 932. The second decision may indicate whether the inductor current is equal to (or above) the current target represented by the current target signal 934 / error signal 932.

[0077] In operation 1922, the controller may provide a second switching signal to the power converter in response to the second decision. Specifically, if the second decision indicates that the inductor current is below the current target, the controller may set the second switching signal to a first state. And, if the second decision indicates that the inductor current is equal to (or above) the current target, the controller may set the second switching signal to a second state. In response to the second switching signal having the first state, the power stage 102 may be turned on and the inductor may be in a charging state. And, in response to the second switching signal having the second state, the power stage 102 may be turned off and the inductor may be in a discharging state. Due to the flat current target, the peak inductor current may be constant across multiple switching cycles.

[0078] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, then: (a) in a first instance, device A is directly coupled to device B; or (b) in a second instance, if the intermediate component C does not substantially change the functional relationship between device A and device B, then device A is indirectly coupled to device B through the intermediate component C, so that device B is controlled by device A via the control signal provided by device A.

[0079] In this specification, a device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0080] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described herein as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, either at the time of manufacture or after manufacture, such as by an end user and / or a third party.

[0081] Although certain components may be described herein as belonging to a particular process technology, these components may be exchanged with components of other process technologies. The circuits described herein may be reconfigured to include replaced components to provide functionality at least partially similar to the functionality available prior to component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the impedance amount represented by the displayed resistor. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in series or in parallel between the same two nodes as a single resistor or capacitor, respectively.

[0082] The use of the phrase "ground voltage potential" in this specification includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about", "approximately" or "substantially" before a parameter means within + / -10% of the parameter.

[0083] Modifications are possible in the described examples, and other examples are possible within the scope of the claims.

Claims

1. A device, wherein include: an amplifier having a reference input, a power converter feedback input, and an amplifier output; a ramp generation circuit having a ramp slope control terminal and a ramp signal terminal, the ramp slope control terminal being coupled to the amplifier output; as well as A comparator has a current sense input, a ramp signal input, and a comparator output, wherein the ramp signal input is coupled to the ramp signal terminal and the comparator output is coupled to a power converter control terminal.

2. The apparatus of claim 1 , wherein the ramp generation circuit is configured to: providing a first signal at the ramp signal terminal in response to a second signal at the ramp slope control terminal; and The ramp rate of the first signal is set based on the magnitude of the second signal. 3 . The apparatus of claim 2 , wherein the ramp generation circuit is configured to set the ramp rate to be inversely proportional to the magnitude of the second signal.

4. The apparatus of claim 2 , wherein the amplifier is a first amplifier, the amplifier output is a first amplifier output, and the apparatus further comprises a second amplifier having a second amplifier output and first and second amplifier inputs, the first amplifier input being coupled to the first amplifier output, the second amplifier input being coupled to the ramp signal terminal, the second amplifier output being coupled to the ramp signal input, and the second amplifier being configured to provide at the second amplifier output a third signal representing a difference between a fourth signal at the first amplifier output and the first signal. 5 . The apparatus of claim 4 , wherein the second amplifier is configured to provide the third signal based on subtracting the first signal from the fourth signal.

6. The apparatus of claim 4, wherein the ramp generation circuit has a clock input, and the ramp generation circuit is configured to provide the first signal in response to a clock signal at the clock input.

7. The apparatus of claim 6 , wherein the clock input is a first clock input, the clock signal is a first clock signal, and the apparatus further comprises a driver circuit having a data input, a second clock input, and a data output, the data input being coupled to the comparator output, the data output being coupled to the power converter control terminal, and the driver circuit being configured to set the state of the power converter control terminal in response to the state of the comparator output and the second clock signal at the second clock input.

8. The apparatus of claim 7, wherein the first clock signal has a first frequency, and the second clock signal has a second frequency higher than the first frequency.

9. The apparatus of claim 7, wherein the driver circuit comprises a flip-flop circuit having a reset input coupled to the data input.

10. The apparatus of claim 6, wherein the amplifier is a first amplifier, the amplifier output is a first amplifier output, and the apparatus further comprises a second amplifier having a second amplifier output and first and second amplifier inputs, the second amplifier output coupled to the ramp slope control terminal, the first amplifier input coupled to the first amplifier output, and the second amplifier input coupled to a load threshold terminal; and The ramp generating circuit comprises: a capacitor having a first plate and a second plate, the first plate being coupled to the ramp slope control terminal and the ramp signal terminal, and the second plate being coupled to a ground terminal; and A switch is coupled between the first plate and the second plate, the switch having a control terminal coupled to the clock input.

11. The apparatus of claim 10, wherein the second amplifier comprises a transconductance amplifier configured to provide a current as the second signal at the second amplifier output in response to a difference between the fourth signal and a load threshold signal at the load threshold terminal. 12 . The apparatus of claim 11 , wherein the ramp generation circuit is configured to set the ramp rate of the first signal to zero in response to the second signal having a magnitude greater than the load threshold signal.

13. The apparatus of claim 1, wherein the ramp generation circuit comprises a digital-to-analog converter (ADC) having a digital input and an analog output, the digital input coupled to the ramp slope control terminal and the analog output coupled to the ramp signal terminal.

14. A device, wherein include: a power converter having a power input, a power output, a current sense output, and a control input; as well as a controller having a control output coupled to the control input, a feedback voltage input coupled to the power output, a reference voltage input, and a current sensing input coupled to the current sensing output, the controller comprising: an amplifier having an amplifier output and first and second amplifier inputs, the first amplifier input coupled to the reference voltage input and the second amplifier input coupled to the feedback voltage input; a ramp generation circuit having a ramp slope control terminal and a ramp signal terminal, the ramp slope control terminal being coupled to the amplifier output; as well as A comparator has a comparator output and first and second comparator inputs, the first comparator input coupled to the current sense input, the second comparator input coupled to the ramp signal terminal, and the comparator output coupled to the control output.

15. The apparatus of claim 14, wherein the ramp generation circuit is configured to: providing a first signal at the ramp signal terminal in response to a second signal at the ramp slope control terminal; and The ramp rate of the first signal is set to be inversely proportional to the magnitude of the second signal.

16. The apparatus of claim 15, wherein the ramp generation circuit has a clock input, and the ramp generation circuit is configured to provide the first signal in response to a clock signal at the clock input.

17. The apparatus of claim 16, wherein the controller has a load threshold terminal, the amplifier is a first amplifier, the amplifier output is a first amplifier output, and the apparatus further comprises a second amplifier having a second amplifier output and third and fourth amplifier inputs, the second amplifier output coupled to the ramp slope control terminal, the third amplifier input coupled to the first amplifier output, and the fourth amplifier input coupled to the load threshold terminal; and The ramp generating circuit comprises: a capacitor having a first plate and a second plate, the first plate being coupled to the ramp slope control terminal and the ramp signal terminal, and the second plate being coupled to a ground terminal; and A switch is coupled between the first plate and the second plate, the switch having a control terminal coupled to the clock input.

18. The apparatus of claim 17, wherein the second amplifier comprises a transconductance amplifier configured to provide a current as the second signal at the second amplifier output in response to a difference between a third signal at the first amplifier output and a load threshold signal at the load threshold terminal.

19. A method wherein include: receiving a current sense signal representing a current through a switch of a power converter; generating an error signal indicative of a load condition; In response to the error signal indicating that a light load condition is satisfied: generating a ramp signal having a ramp rate based on the error signal; generating a current target signal based on subtracting the ramp signal from the error signal; comparing the current target signal to the current sense signal to generate a decision; as well as A switching signal is provided to the power converter in response to the decision.

20. The method of claim 19, wherein the ramp rate has an inverse relationship with the error signal.

21. The method of claim 19, wherein the decision is a first decision, the switching signal is a first switching signal, and the method further comprises, in response to the error signal indicating that a light load condition is satisfied: generating a flat current target signal based on the error signal; comparing the flat current target signal to the current sense signal to generate a second decision; and A second switching signal is provided to the power converter in response to the second decision.

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