Cross-clock domain communication circuit and data read-write method

Abstract

The invention discloses a cross-clock domain communication circuit and a data read-write method, and relates to the field of cross-clock domain communication. A level unfolding unit in the circuit outputs a level signal under a first clock according to an original write enable signal and a communication end mark signal; the communication ending mark signal is in a valid state when the write communication instruction is ended and the N bytes of target data are written into the cache, the write mark signal generation unit is used for outputting a write mark signal under a first clock, and when the write mark signal is in an invalid state, the N bytes of target data are written into the cache. When the level signal and the communication end mark signal are both in the effective state, the signal is set to be in the effective state and kept; the synchronization unit synchronizes the write flag signal under the second clock to obtain a synchronization signal, so that the write enable signal generation unit generates a write enable signal under the second clock. The scheme does not need to additionally start a high-frequency clock and is beneficial to reducing power consumption; and the write-in time of the multi-byte target data under the second clock can be reasonably determined, and the corresponding write-in time is the same.

Description

Technical Field

[0001] The present invention relates to the technical field of cross-clock domain communication, and in particular to a cross-clock domain communication circuit and a data reading and writing method. Background Art

[0002] Data interaction in an asynchronous clock domain is a common situation during inter-module communication. Especially when writing from a relatively high-frequency communication clock to a relatively low-frequency system clock, data synchronization and write enable signal synchronization are key issues to be solved. For this purpose, the current solutions mainly include the following two: The first method is to additionally introduce a high-frequency clock and a corresponding clock tree outside the communication clock and the system clock. Then, for the write instructions sent by the communication interface, the high-frequency clock is used for decoding to obtain the write data and the write enable, and the write data is written into the cache. Subsequently, a handshake signal is sent to the module that follows the system clock to transfer the write enable to the relatively low-frequency system clock domain through a handshake mechanism, so that the module in the system clock domain can complete data writing from the cache according to the corresponding clock frequency. However, in this method, the high-frequency clock needs to be started every time a write instruction is received for writing, which increases power consumption, and the introduction of the high-frequency clock also correspondingly increases the layout and wiring complexity and the timing analysis difficulty.

[0003] The second method is to set a write flag signal and obtain the write enable signal accordingly. However, the disadvantage of this solution is that it is difficult to determine the writing moment. Specifically, in this method, when each byte is written into the system clock domain, it depends on the corresponding write enable signal. Usually, the moment corresponding to the write enable signal is regarded as the writing moment of this byte. However, when there are multiple bytes to be written in the communication, the generation times of the write enable signals corresponding to each byte are different, resulting in differences in the writing moments corresponding to each byte. Such differences are not allowed in scenarios with high requirements for the write operation time, such as in the write log scenario. Originally, multiple bytes that should correspond to the same moment, but according to the above method, the writing moments corresponding to each byte in the system clock domain are not the same. It can be seen that when facing multiple bytes, the current solution for determining the writing moment in the system clock domain is not reasonable.

[0004] Therefore, how to provide a cross-clock domain communication scheme with a more reasonable determination of the writing moment for multiple bytes is an urgent problem to be solved currently. Summary of the Invention

[0005] In view of this, the present invention provides a cross-clock domain communication circuit and a data reading and writing method, which do not need to additionally start a high-frequency clock, are beneficial to reducing power consumption; are beneficial to reasonably determining the writing moment of the target data of multiple bytes under the second clock, and can ensure that the writing moments corresponding to the target data of multiple bytes in one communication are the same.

[0006] To solve the above technical problems, the present application provides a cross-clock domain communication circuit, including a level expansion unit, a write flag signal generation unit, a synchronization unit, and a write enable signal generation unit connected in sequence; The level expansion unit is configured to perform level expansion on the received original write enable signal and communication end flag signal under the first clock to output a level signal; the original write enable signal is in an effective state when a write communication instruction is received under the first clock, and the communication end flag signal is in an effective state when the write communication instruction has ended and the target data of N bytes has been written into the cache, where N is an integer not less than 1; The write flag signal generation unit is configured to output a write flag signal under the first clock according to the received level signal and communication end flag signal; the write flag signal is configured to be set to an effective state and maintained when both the level signal and the communication end flag signal are in an effective state while being in an invalid state; The synchronization unit is configured to synchronize the write flag signal under the second clock to obtain a synchronization signal, so that the write enable signal generation unit performs edge extraction according to the synchronization signal to generate a write enable signal under the second clock; wherein, the first clock and the second clock are asynchronous clocks.

[0007] Further, the level expansion unit includes a trigger logic circuit and a first flip-flop; The first input terminal of the trigger logic circuit is configured to receive the original write enable signal, the second input terminal is configured to receive the communication end flag signal, the third input terminal is connected to the data output terminal of the first flip-flop and the common connection end is connected to the write flag signal generation unit, and the output terminal is connected to the data input terminal of the first flip-flop, and is configured to output a first level when the original write enable signal changes from an invalid state to an effective state, and maintain the output of the first level until the communication end flag signal changes from an effective state to an invalid state and then output a second level; The clock signal input terminal of the first flip-flop is connected to the first clock, and is configured to output a level signal in an effective state when receiving the first level, and output a level signal in an invalid state when receiving the second level.

[0008] Further, the write flag signal generation unit includes a first AND gate, a first NOT gate, a second AND gate, a first OR gate, and a second flip-flop; The first input terminal of the first AND gate is connected to the output terminal of the level expansion unit, the second input terminal is configured to receive the communication end flag signal, and the output terminal is respectively connected to the input terminal of the first NOT gate and the first input terminal of the first OR gate; The first input terminal of the second AND gate is connected to the data output terminal of the second flip-flop, and the common terminal of the connection is connected to the synchronization unit. The second input terminal is connected to the output terminal of the first NOT gate, and the output terminal is connected to the second input terminal of the first OR gate; The data input terminal of the second flip-flop is connected to the output terminal of the first OR gate, and the clock signal input terminal is connected to the first clock.

[0009] Further, the synchronization unit includes M third flip-flops connected in sequence, where M is an integer not less than 3; The clock signal input terminals of each of the third flip-flops are connected to the second clock. The data input terminal of the first third flip-flop is connected to the data output terminal of the second flip-flop. The data output terminal of the (M - 1)-th third flip-flop is respectively connected to the data input terminal of the M-th third flip-flop and the first input terminal of the write enable signal generation unit. The data output terminal of the M-th third flip-flop is connected to the second input terminal of the write enable signal generation unit.

[0010] Further, the write enable signal generation unit includes a second NOT gate and a third AND gate; The input terminal of the second NOT gate serves as the second input terminal of the write enable signal generation unit; The first input terminal of the third AND gate serves as the first input terminal of the write enable signal generation unit. The second input terminal is connected to the output terminal of the second NOT gate, and the output terminal is used to output the generated write enable signal under the second clock.

[0011] Further, the cross-clock domain communication circuit further includes a state reset unit; The input terminal of the state reset unit is connected to the data output terminal of the M-th third flip-flop, and the output terminal is connected to the third input terminal of the second AND gate, and is used to synchronize the received synchronization signal output by the M-th third flip-flop under the first clock to output a state reset signal; wherein, the state reset signal is in an effective state after being synchronized when the synchronization signal is in an effective state, so as to convert the currently effective write flag signal into an ineffective state.

[0012] Further, the state reset unit includes a third NOT gate, a fourth NOT gate, a fourth AND gate, and S fourth flip-flops, where S is an integer not less than 3; The S fourth flip-flops are connected in sequence, and the clock signal input terminals of each of the fourth flip-flops are connected to the first clock. The data input terminal of the first fourth flip-flop serves as the input terminal of the state reset unit. The data output terminal of the (S - 1)-th fourth flip-flop is respectively connected to the data input terminal of the S-th fourth flip-flop and the first input terminal of the fourth AND gate. The data output terminal of the S-th fourth flip-flop is connected to the input terminal of the third NOT gate; The second input terminal of the fourth AND gate is connected to the output terminal of the third NOT gate, and the output terminal is connected to the input terminal of the fourth NOT gate; The output terminal of the fourth NOT gate serves as the output terminal of the status reset unit.

[0013] Furthermore, the cross-clock domain communication circuit further includes a reset unit; The reset terminal of the reset unit is used to receive the original write enable signal, the input terminal is used to receive a reference signal, the first output terminal is connected to the reset terminal of the write flag signal generation unit, and the second output terminal is connected to the reset terminal of the synchronization unit, and is used to, under the second clock, output a first reset signal through its first output terminal according to the original write enable signal received by its reset terminal, and output a second reset signal through its second output terminal according to the original write enable signal and the reference signal; Wherein, the first reset signal is in an invalid state when the original write enable signal is in an invalid state, and is in a valid state when the original write enable signal is in a valid state to reset the write flag signal generation unit, so as to reset the currently valid write flag signal to an invalid state; The second reset signal is in an invalid state and remains so after being synchronized when the original write enable signal is in an invalid state, and is in a valid state when the original write enable signal is in a valid state to reset the synchronization unit, so that the synchronization unit resynchronizes the received write flag signal under the second clock.

[0014] Furthermore, the reset unit includes a fifth NOT gate and T fifth flip-flops, where T is an integer not less than 2; The T fifth flip-flops are connected in sequence, and the clock signal input terminals of each of the fifth flip-flops are connected to the second clock, and the reset terminals of each of the fifth flip-flops are connected to the output terminal of the fifth NOT gate, and the common connection end serves as the first output terminal of the reset unit; The input terminal of the fifth NOT gate serves as the reset terminal of the reset unit; the data input terminal of the first fifth flip-flop serves as the input terminal of the reset unit, and the output terminal of the T-th fifth flip-flop serves as the second output terminal of the reset unit.

[0015] To solve the above technical problems, the present invention also provides a data reading and writing method, which is applied to an electronic device, and the electronic device includes the cross-clock domain communication circuit as described above; the data reading and writing method includes: When a write communication instruction is received, write the target data into the cache under the first clock, and based on the write enable signal generated by the cross-clock domain communication circuit, write the target data from the cache into the register under the second clock; When a read communication instruction is received, obtain the write flag signal output by the write flag signal generation unit in the cross-clock domain communication circuit; Determine whether the write flag signal is in an effective state; If so, in response to the read communication instruction, perform data reading from the cache; If not, in response to the read communication instruction, perform data reading from the register.

[0016] This application provides a cross-clock domain communication circuit and a data reading and writing method. In this circuit, the level expansion unit is used to perform level expansion according to the original write enable signal and the communication end flag signal at the first clock to output a level signal. The communication end flag signal is in an effective state when the current write communication instruction has ended and the target data of N bytes has been written into the cache. The write flag signal generation unit is used to output a write flag signal according to the level signal and the communication end flag signal at the first clock. When the write flag signal is in an invalid state, it is set to an effective state and maintained when both the level signal and the communication end flag signal are in an effective state for subsequent synchronization. The synchronization unit is used to synchronize the write flag signal at the second clock to obtain a synchronization signal, so that the write enable signal generation unit can perform edge extraction according to the synchronization signal to generate a write enable signal at the second clock, and then write the target data into the register at the second clock based on the write enable signal. It can be seen that this solution does not require an additional high-frequency clock to be started, which is beneficial to reducing power consumption. When the write communication instruction has ended and the target data of N bytes has been written into the cache, a communication end flag signal is generated, and the moment when the communication instruction end flag signal is received is determined, which is beneficial to reasonably determining the writing moment of the target data of multiple bytes at the second clock accordingly, and can ensure that the writing moments corresponding to the target data of multiple bytes in one communication are the same, which is beneficial to reliable communication in the cross-clock domain in practical applications.

[0017] The above description is only an overview of the technical solution of this application. In order to be able to understand the technical means of this application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of this application more obvious and easy to understand, the specific embodiments of this application are specifically given below. Brief Description of the Drawings

[0018] The drawings described herein are used to provide a further understanding of this application and constitute a part of this application. The schematic embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation to this application. In the drawings: Figure 1 It is a schematic structural diagram of a cross-clock domain communication circuit provided by the present invention; Figure 2 It is a schematic diagram of the level waveform change of each signal in a cross-clock domain communication circuit provided by the present invention; Figure 3 Schematic diagram of another cross - clock - domain communication circuit provided by the present invention; Figure 4 Flowchart of a data reading and writing method provided by the present invention. Detailed implementation manners

[0019] The core of the present invention is to provide a cross - clock - domain communication circuit and a data reading and writing method, which do not require an additional high - frequency clock to be started, facilitating power consumption reduction; facilitating the reasonable determination of the writing time of the target data of multiple bytes under the second clock, and ensuring that the writing times corresponding to the target data of multiple bytes in one communication are the same.

[0020] Next, the technical solutions in the embodiments of the present application will be clearly described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0021] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually of the same category, and the number of objects is not limited. For example, the first object can be one or multiple. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally represents an "or" relationship between the associated objects before and after.

[0022] Please refer to Figure 1 , Figure 1 Schematic diagram of a cross - clock - domain communication circuit provided by the present invention.

[0023] The cross - clock - domain communication circuit includes a level expansion unit 1, a write flag signal generation unit 2, a synchronization unit 3, and a write enable signal generation unit 4 connected in sequence; The level expansion unit 1 is configured to perform level expansion according to the received original write enable signal and communication end flag signal under the first clock to output a level signal; the original write enable signal is in an effective state when a write communication instruction is received under the first clock, and the communication end flag signal is in an effective state when the write communication instruction has ended and the target data of N bytes has been written into the buffer, where N is an integer not less than 1; The write flag signal generation unit 2 is configured to output a write flag signal according to the received level signal and communication end flag signal under the first clock; the write flag signal is configured to be set to an active state and maintained when both the level signal and the communication end flag signal are in an active state in the case of being in an inactive state; The synchronization unit 3 is configured to synchronize the write flag signal under the second clock to obtain a synchronization signal, so that the write enable signal generation unit 4 performs edge extraction according to the synchronization signal to generate a write enable signal under the second clock; wherein, the first clock and the second clock are asynchronous clocks.

[0024] In this embodiment, the cross-clock domain communication circuit can be applied to cross-clock domain data communication between a first module under a first clock and a second module under a second clock in an electronic device. Here, the first clock and the second clock are asynchronous clocks, which means that the clock frequency corresponding to the first clock is different from the clock frequency corresponding to the second clock, and the phase relationship between the first clock and the second clock is not fixed. With the help of this cross-clock domain communication circuit, reliable writing of target data can be achieved; specifically, the first clock can be generated by a corresponding first clock signal generation circuit, and the specific structure of the first clock signal generation circuit is not particularly limited herein; the second clock can be generated by a corresponding second clock signal generation circuit, and the structure of the second clock signal generation circuit is not particularly limited herein; more specifically, the first clock here can be a communication clock, and the second clock can be a system clock. The clock frequency of the communication clock is higher than the clock frequency of the system clock and there is no fixed phase relationship between the two.

[0025] Specifically, when an instruction is received under the first clock and it is determined that the instruction is a write communication instruction by decoding the instruction, the original write enable signal is in an active state; otherwise, the original write enable signal is in an inactive state. Please refer to Figure 2 , Figure 2 is a schematic diagram of the level waveform changes of each signal in a cross-clock domain communication circuit provided by the present invention. It should be noted that Figure 2 in order to show various situations of the level waveform changes as much as possible, part of the level indications of each signal are omitted in the form of a wavy line; Figure 2 in which rtxclk represents the first clock and sysclk represents the second clock. It can be seen that the clock frequency corresponding to the first clock rtxclk is higher than the clock frequency corresponding to the second clock sysclk; the original write enable signal is represented by wen_rtx. Being in an active state means that the level state corresponding to the original write enable signal wen_rtx is 1, and being in an inactive state means that the level state corresponding to the original write enable signal wen_rtx is 0.

[0026] The write communication instruction is used to indicate writing target data under the first clock into a register under the second clock. For this cross-clock domain communication, when the write communication instruction is received, the target data is written into the cache under the first clock. A single write communication instruction may indicate that N bytes of target data need to be written this time. The communication end flag signal is used to indicate whether the write communication instruction has ended and whether the N bytes of target data have been written into the cache. This communication end flag signal can specifically come from the master control unit. The master control unit receives the write communication instruction through the communication interface, and the communication process essentially follows different communication protocols, so there is a corresponding end flag signal, such as the chip select signal for serial communication, or the stop bit signal for I2C communication (Inter-Integrated Circuit, two-wire serial communication). Based on the end flag signal, it can be determined whether the write instruction has ended; the level expansion here is used to make the output level signal become valid and last for a period of time after the original write enable signal is in the valid state, and the level state of the level signal is controlled by the change in the level states of the original write enable signal and the communication end flag signal. Further, the level expansion is essentially to ensure that even if there are multiple bytes of target data to be written, the valid state of the level signal can be maintained long enough to ensure subsequent reliable acquisition for setting the write flag signal. As Figure 2 shown Figure 2 in which the communication end flag signal is represented by end_flag. Being in the valid state means that the level state corresponding to the communication end flag signal end_flag is 1, and being in the invalid state means that the level state corresponding to the communication end flag signal end_flag is 0; the level signal is represented by wr_level. Being in the valid state means that the level state corresponding to the level signal wr_level is 1, and being in the invalid state means that the level state corresponding to the level signal wr_level is 0.

[0027] The write flag signal generation unit 2 outputs a write flag signal under the first clock. And when the write flag signal is in its own invalid state, it is set to the valid state when both the level signal and the communication end flag signal are in the valid state, and then maintains this valid state until it is subsequently converted and reset to the invalid state by the state reset unit in response to the next write communication instruction, or until it is reset to the invalid state by the reset unit in response to the second write communication instruction adjacent to the first write communication instruction. See the specific description in the following embodiments, which will not be elaborated here; please refer to Figure 2, let the write flag signal be represented by wr_ctrl. Being in the active state means the write flag signal wr_ctrl is set and the corresponding level state is 1, and being in the inactive state means the level state corresponding to the write flag signal wr_ctrl is 0. It can be understood that since the write flag signal wr_ctrl in the inactive state is only valid when both the level signal wr_level and the communication end flag signal end_flag are in the active state to initiate the write operation, it also helps prevent the communication end flag signal unrelated to the current write communication instruction from wrongly starting the write process.

[0028] It should also be noted that according to the generated write enable signal in the active state, N bytes of target data are written from the cache into the register at the second clock, so that the target data at the first clock is written into the register at the second clock; as Figure 2 shown, let the write enable signal be represented by wen_sys. Being in the active state means the level state corresponding to the write enable signal wen_sys is 1, and being in the inactive state means the level state corresponding to the write enable signal wen_sys is 0.

[0029] In addition, for determining the specific writing moment of N bytes of target data, preferably it can be considered as the moment when the communication end flag signal is received. Of course, it can also be considered as the moment when the write enable signal in the active state is generated (the specific calculation method of this moment is described in the following embodiments), and no special limitation is made here.

[0030] In summary, the present application provides a cross-clock domain communication circuit, which does not require an additional high-frequency clock to be started, helping to reduce power consumption; when the write communication instruction has ended and all N bytes of target data have been written into the cache, a communication end flag signal is generated, and the moment when the communication instruction end flag signal is received is determined, so as to help reasonably determine the writing moment of multiple bits of data at the second clock accordingly, and can ensure that the writing moments corresponding to multiple bits of data in one communication are the same, which is beneficial to reliable communication in the cross-clock domain in practical applications.

[0031] Based on the above embodiments: In some embodiments, the level expansion unit 1 includes a trigger logic circuit 11 and a first flip-flop D1; The first input terminal of the trigger logic circuit 11 is used to receive the original write enable signal, the second input terminal is used to receive the communication end flag signal, the third input terminal is connected to the data output terminal of the first flip-flop D1 and the common connection end is connected to the write flag signal generation unit 2, and the output terminal is connected to the data input terminal of the first flip-flop D1, and is used to output a first level when the original write enable signal changes from the inactive state to the active state, and keep outputting the first level until the communication end flag signal changes from the active state to the inactive state and then output a second level; The clock signal input terminal of the first flip-flop D1 is connected to the first clock, and is used to output a level signal in an effective state when receiving the first level, and output a level signal in an invalid state when receiving the second level.

[0032] In this embodiment, the first flip-flop D1 here can be a D flip-flop; when receiving a write communication instruction, the original write enable signal changes from an invalid state to an effective state, and at this time, the trigger logic circuit 11 outputs a first level. Specifically, the first level here is a high level; the first level is maintained when the original write enable signal changes from the effective state to the invalid state and the communication end flag signal is still in the invalid state; the first level is still maintained when the communication end flag signal changes from the invalid state to the effective state; when the communication end flag signal changes from the effective state to the invalid state, a second level is output, and the second level here is a low level.

[0033] Corresponding to Figure 2 , when the original write enable signal wen_rtx is in the effective state for the first time, the level state of the original write enable signal wen_rtx changes from 0 to 1, and the level state of the level signal wr_level output by the data output terminal of the first flip-flop D1 is 1 and is maintained; when the level state of the subsequent communication end flag signal end_flag changes from 0 to 1, even if the level state of the original write enable signal wen_rtx is 0 at this time, through the circuit structure of the level expansion unit 1, the level state of the level signal wr_level can still be 1, so that the write flag signal generation unit 2 sets the write flag signal wr_ctrl at the rising clock edge under the first clock; when the level state of the communication end flag signal end_flag changes from 1 to 0, under the first clock, it is sampled by the first flip-flop D1 at the rising clock edge, so that the level state of the level signal wr_level changes from 1 to 0.

[0034] More specifically, please refer to Figure 3 , Figure 3 which is a schematic structural diagram of another cross-clock domain communication circuit provided by the present invention. Figure 3 In order to simplify the illustration, rtxclk is used to represent the first clock, sysclk is used to represent the second clock, end_flag is used to represent the communication end flag signal, wen_rtx is used to represent the original write enable signal, and wen_sys is used to represent the write enable signal.

[0035] The trigger logic circuit 11 may include a sixth NOT gate U1, a seventh NOT gate U2, a fifth AND gate U3, and a second OR gate U4; the input terminal of the sixth NOT gate U1 is used to be connected to the first input terminal of the second OR gate U4, and the common terminal of the connection serves as the first input terminal of the trigger logic circuit 11, and the output terminal is connected to the first input terminal of the fifth AND gate U3; the input terminal of the seventh NOT gate U2 serves as the second input terminal of the trigger logic circuit 11, and the output terminal is connected to the second input terminal of the fifth AND gate U3; the third input terminal of the fifth AND gate U3 serves as the third input terminal of the trigger logic circuit 11, and the output terminal is connected to the second input terminal of the first OR gate; the output terminal of the second OR gate U4 serves as the output terminal of the trigger logic circuit 11.

[0036] It can be seen that through the above settings, the function of the trigger logic circuit 11 can be reliably realized.

[0037] In some embodiments, the write flag signal generation unit 2 includes a first AND gate U5, a first NOT gate U6, a second AND gate U7, a first OR gate U8, and a second flip-flop D2; The first input terminal of the first AND gate U5 is connected to the output terminal of the level expansion unit 1, the second input terminal is used to receive the communication end flag signal, and the output terminal is respectively connected to the input terminal of the first NOT gate U6 and the first input terminal of the first OR gate U8; The first input terminal of the second AND gate U7 is connected to the data output terminal of the second flip-flop D2, and the common terminal of the connection is connected to the synchronization unit 3. The second input terminal is connected to the output terminal of the first NOT gate U6, and the output terminal is connected to the second input terminal of the first OR gate U8; The data input terminal of the second flip-flop D2 is connected to the output terminal of the first OR gate U8, and the clock signal input terminal is connected to the first clock.

[0038] In this embodiment, the second flip-flop D2 here may be a D flip-flop. Specifically, for the circuit structure, please refer to Figure 3 As shown, from the perspective of the implementation principle, on the basis of this circuit structure, refer to Figure 2 As shown, when the level state of the write flag signal wr_ctrl is 0, when the level state of the level signal wr_level is 1 and the level state of the communication end flag signal end_flag is 1, at the first clock, when the rising clock edge arrives, the write flag signal wr_ctrl can be reliably set and maintained to start the write synchronization operation.

[0039] In some embodiments, the synchronization unit 3 includes M third flip-flops connected in sequence, where M is an integer not less than 3; The clock signal input terminals of each third flip-flop are connected to the second clock. The data input terminal of the first third flip-flop is connected to the data output terminal of the second flip-flop D2. The data output terminal of the (M - 1)-th third flip-flop is respectively connected to the data input terminal of the M-th third flip-flop and the first input terminal of the write enable signal generation unit 4. The data output terminal of the M-th third flip-flop is connected to the second input terminal of the write enable signal generation unit 4.

[0040] In this embodiment, the synchronization unit 3 includes M sequentially connected third flip-flops. The third flip-flop can be a D flip-flop. Preferably, M = 3 can be set. On the one hand, it is beneficial to ensure the stable and reliable generation of the subsequent write enable signal and avoid metastability problems. On the other hand, it is beneficial to ensure the reliable synchronization of the write synchronization signal under the second clock with the least number of third flip-flops and avoid wasting resources by using more third flip-flops. Specifically, please refer to Figure 3 , Figure 3 which takes M = 3 as an example for illustration. That is, the synchronization unit 3 includes the first third flip-flop D3, the second third flip-flop D4, and the third third flip-flop D5. Please further refer to Figure 2 , and denote the first signal output from the data output terminal of the first third flip-flop D3 as d1_sys, the second signal output from the data output terminal of the second third flip-flop D4 as d2_sys, and the third signal output from the data output terminal of the third third flip-flop D5 as d3_sys. Then, under the second clock, each third flip-flop performs input acquisition and output when the rising clock edge arrives. Figure 2 shows the waveform change schematic of the first signal d1_sys, the second signal d2_sys, and the third signal d3_sys over time.

[0041] In some embodiments, the write enable signal generation unit 4 includes a second NOT gate U9 and a third AND gate U10; The input terminal of the second NOT gate U9 serves as the second input terminal of the write enable signal generation unit 4; The first input terminal of the third AND gate U10 serves as the first input terminal of the write enable signal generation unit 4. The second input terminal is connected to the output terminal of the second NOT gate U9, and the output terminal is used to output the write enable signal under the second clock generated.

[0042] Specifically, the synchronization signal includes the above-mentioned second signal d2_sys and third signal d3_sys. Here, the write enable signal is a pulse-shaped signal; refer to Figure 2As shown, when the original write enable signal wen_rtx is in the valid state for the first time, it indicates that there is a write communication instruction. The level expansion unit 1 expands it into a level signal wr_level at the first clock. When the level states of both the level signal wr_level and the communication end flag signal end_flag are 1, the write flag signal wr_ctrl is set, that is, the level state changes from 0 to 1. At the second clock, when the rising clock edge arrives, it is captured by the first third flip-flop D3, and then the level state of the first signal d1_sys changes to 1. When the next rising clock edge arrives, it is captured by the second third flip-flop D4, and then the level state of the second signal d2_sys changes to 1. At this time, through the trigger logic circuit 11 formed by the second NOT gate U9 and the third AND gate U10, the write enable signal wen_sys becomes valid, that is, the level state of the write enable signal wen_sys is 1, and the target data is written from the cache into the register. When the next rising clock edge arrives and is captured by the third third flip-flop D5, the level state of the third signal d3_sys changes to 1, and the level state of the write enable signal wen_sys returns to 0.

[0043] It can be understood that, referring to Figure 2 it can be known that, based on the above circuit structure, the time when the valid write enable signal is generated = the time when the communication end flag signal is received + the time difference. This time difference = two cycles at the second clock + the error, and this error can be controlled within one cycle at the second clock. The reason for the existence of a certain error is that the level state transition occurs at the moment when the rising clock edge arrives.

[0044] In some embodiments, the cross-clock domain communication circuit further includes a state reset unit 5; The input end of the state reset unit 5 is connected to the data output end of the Mth third flip-flop, and the output end is connected to the third input end of the second AND gate U7. It is used to synchronize the received synchronous signal output by the Mth third flip-flop at the first clock to output a state reset signal. Among them, the state reset signal is in the valid state after synchronization when the synchronous signal is in the valid state, so as to convert the currently valid write flag signal into an invalid state.

[0045] In this embodiment, further considering that the write flag signal wr_ctrl remains in the valid state after being set, therefore, when the data writing is completed, it should also be converted to make the write flag signal wr_ctrl recover and be converted into an invalid state, so as to normally respond to the next write communication instruction signal. Therefore, the above state reset unit 5 is set.

[0046] In addition, since the reset terminals of the third flip-flops are active low, the state reset signal being in the active state here means that the level state of the state reset signal is low; and the state reset signal is in the inactive state when the synchronization signal is in the inactive state, and the state reset signal being in the inactive state here means that the level state of the state reset signal is high; the synchronization signal being in the active state here means that the level state of the third signal d3_sys is high, and the synchronization signal being in the inactive state means that the level state of the third signal d3_sys is low.

[0047] It should also be noted that, referring to Figure 3 , when the synchronization unit 3 includes three third flip-flops connected in sequence, the input end of the state reset unit 5 is specifically connected to the data output end of the third third flip-flop D5.

[0048] In some embodiments, the state reset unit 5 includes a third NOT gate U11, a fourth NOT gate U12, a fourth AND gate U13, and S fourth flip-flops, where S is an integer not less than 3; The S fourth flip-flops are connected in sequence, and the clock signal input ends of each fourth flip-flop are connected to the first clock. The data input end of the first fourth flip-flop serves as the input end of the state reset unit 5. The data output end of the (S - 1)th fourth flip-flop is respectively connected to the data input end of the Sth fourth flip-flop and the first input end of the fourth AND gate U13. The data output end of the Sth fourth flip-flop is connected to the input end of the third NOT gate U11; The second input end of the fourth AND gate U13 is connected to the output end of the third NOT gate U11, and the output end is connected to the input end of the fourth NOT gate U12; The output end of the fourth NOT gate U12 serves as the output end of the state reset unit 5.

[0049] In this embodiment, through the above settings, the function of the state reset unit 5 can be reliably realized. Here, the fourth flip-flop can be a D flip-flop. Preferably, S = 3 can be set. On the one hand, it is beneficial to ensure the stable and reliable generation of the fourth signal output to the third NOT gate U11 and avoid metastability problems. On the other hand, it is beneficial to ensure the reliable synchronization of the third signal d3_sys under the first clock with the least number of fourth flip-flops and avoid wasting resources due to using more fourth flip-flops; please refer to Figure 3 , Figure 3 for an illustration with S = 3 as an example, that is, it includes the first fourth flip-flop D6, the second fourth flip-flop D7, and the third fourth flip-flop D8. Please further refer to Figure 2The fifth signal output from the data output terminal of the first fourth flip-flop D6 is represented by d1_rtx, the sixth signal output from the data output terminal of the second fourth flip-flop D7 is represented by d2_rtx, and the fourth signal output from the data output terminal of the third fourth flip-flop D8 is represented by d3_rtx. Then, at the first clock, each fourth flip-flop performs input acquisition and output when the rising clock edge arrives. Figure 2 It shows the waveform change schematic of the fifth signal d1_rtx, the sixth signal d2_rtx, and the fourth signal d3_rtx over time.

[0050] In addition, Figure 2 In [reference], the seventh signal output from the output terminal of the fourth AND gate U13 is represented by pd_wr. When the seventh signal pd_wr is in an effective state (i.e., its level state is 1), the state reset signal output by the fourth NOT gate U12 is in an effective state (i.e., its level state is 0). Thus, at the first clock, when the rising clock edge arrives, the write flag signal wr_ctrl is converted to an invalid state, that is, the level state of the write flag signal wr_ctrl is converted to 0; and after the write flag signal wr_ctrl is converted to a low level, it is sequentially transmitted to the first signal d1_sys, the second signal d2_sys, the third signal d3_sys, the fifth signal d1_rtx, the sixth signal d2_rtx, and the fourth signal d3_rtx, and all write-related signals are restored to a low level, waiting to respond to the next write communication instruction.

[0051] In some embodiments, the cross-clock domain communication circuit further includes a reset unit; The reset terminal of the reset unit is used to receive the original write enable signal, the input terminal is used to receive the reference signal bias, the first output terminal is connected to the reset terminal of the write flag signal generation unit 2, and the second output terminal is connected to the reset terminal of the synchronization unit 3. It is used to output a first reset signal through its first output terminal according to the original write enable signal received by its reset terminal at the second clock, and output a second reset signal through its second output terminal according to the original write enable signal and the reference signal; Among them, the first reset signal is in an invalid state when the original write enable signal is in an invalid state, and is in an effective state when the original write enable signal is in an effective state to reset the write flag signal generation unit 2, so as to reset the currently effective write flag signal to an invalid state; The second reset signal is in an invalid state after synchronization when the original write enable signal is in an invalid state, and is in an effective state when the original write enable signal is in an effective state to reset the synchronization unit 3, so that the synchronization unit 3 can re-synchronize the write flag signal at the second clock.

[0052] In this embodiment, further considering the actual application, when two write communication instructions are separated by a sufficiently long time, that is, the second write communication instruction arrives after the state reset unit 5 converts the write flag signal wr_ctrl, the above method can be accurately responded. However, there is still a situation where two adjacent write communication instructions are adjacent, that is, the synchronization process of the first write communication instruction is still in progress when the second write communication instruction arrives. At this time, according to the second method in the current related technology, the second write communication instruction cannot be reliably responded, that is, the write synchronization process cannot be reliably triggered for the second write communication instruction, so that the latest target data corresponding to the second write communication instruction cannot be reliably written into the register; and in the present application, further, when there are two adjacent write communication instructions, the above settings can be used to quickly reset the synchronization unit 3 and the write flag signal generation unit 2 to ensure reliable response to the second write communication instruction, and then ensure that the latest target data is written into the register, so that the present solution can support the effective execution of multiple write communication instructions with any time interval without generating recovery time or removal time conflicts.

[0053] It should be noted that when the original write enable signal is in an invalid state, the first reset signal is in an invalid state. At this time, the first reset signal does not affect the function of the write flag signal generation unit 2, that is, it does not affect the output of the write flag signal; when the original write enable signal is in an effective state, the first reset signal is in an effective state. At this time, the first reset signal resets the write flag signal generation unit 2 so that the currently effective write flag signal is reset to an invalid state to better respond to the second write communication instruction and re-output the corresponding write flag signal. More specifically, when the write flag signal generation unit 2 includes a first AND gate U5, a first NOT gate U6, a second AND gate U7, a first OR gate U8, and a second flip-flop D2, the reset terminal of the second flip-flop D2 is used as the reset terminal of the write flag signal generation unit 2. In addition, since the reset terminal of the second flip-flop D2 is active low, when the level state of the original write enable signal is high when it is in an effective state, the level state of the first reset signal is low when it is in an effective state; when the level state of the original write enable signal is low when it is in an invalid state, the level state of the first reset signal is high when it is in an invalid state.

[0054] Further, when the original write enable signal is in an invalid state, the second reset signal is in an invalid state, and at this time the level state of the second reset signal is the same as the level state corresponding to the reference signal bias. At this time, it does not affect the synchronization function of the synchronization unit 3 for the write flag signal; when the original write enable signal is in an effective state, the second reset signal is in an effective state, and at this time the level state of the second reset signal is opposite to the level state corresponding to the reference signal bias, so that the synchronization unit 3 is reset.

[0055] Specifically, the synchronization unit 3 may include M third flip - flops. The output terminal of the second reset unit may be connected to the reset terminals of the respective third flip - flops. Since the reset terminal of the third flip - flop is active - low, the reference signal bias may be a signal maintained at a high level at this time; when the second reset signal is in an active state, its level state is low, and when the second reset signal is in an inactive state, its level state is high.

[0056] Please refer to Figure 2 , Figure 2 , where the second reset signal is denoted as rstn_sync. After the first write communication instruction (the arrival of the first write communication instruction here means that the original write enable signal wen_rtx is in an active state for the first time and the corresponding level state is 1), when the second write communication instruction has not arrived, the original write enable signal wen_rtx is in an inactive state and the corresponding level state is 0, and the level state of the second reset signal rstn_sync is 1. At this time, the synchronization function of each third flip - flop is not affected; when the adjacent second write communication instruction arrives, the original write enable signal wen_rtx is in an active state and the corresponding level state is 1. At this time, the level state of the second reset signal rstn_sync is 0 to reset the first signal d1_sys, the second signal d2_sys, and the third signal d3_sys. Of course, at this time, the level state of the first reset signal is also 0 to reset the second flip - flop D2 so that the level state of the write flag signal wr_ctrl is reset to 0, in order to respond to this write communication instruction, which is beneficial to generating the corresponding write enable signal wen_sys at the second clock subsequently.

[0057] In some embodiments, the reset unit includes a fifth NOT gate and T fifth flip - flops, where T is an integer not less than 2; The T fifth flip - flops are connected in sequence, and the clock signal input terminals of each fifth flip - flop are connected to the second clock. The reset terminals of each fifth flip - flop are connected to the output terminal of the fifth NOT gate, and the common connection end is used as the first output terminal of the reset unit; The input terminal of the fifth NOT gate is used as the reset terminal of the reset unit; the data input terminal of the first fifth flip - flop is used as the input terminal of the reset unit, and the output terminal of the T - th fifth flip - flop is used as the second output terminal of the reset unit.

[0058] Specifically, the fifth flip-flop here can be a D flip-flop. When the synchronization unit 3 includes M third flip-flops, the output terminal of the T-th fifth flip-flop is connected to the reset terminals of the third flip-flops. When the write flag signal generation unit 2 includes a first AND gate U5, a first NOT gate U6, a second AND gate U7, a first OR gate U8, and a second flip-flop D2, the reset terminals of the fifth flip-flops are connected to the output terminal of the fifth NOT gate, and the common connection end is connected to the reset terminal of the second flip-flop D2. Preferably, T = 2 to ensure stable and reliable signal output and avoid resource waste; please refer to Figure 3 , Figure 3 Taking T = 3 as an example, the structure of the second reset unit is illustrated, that is, it includes a first fifth flip-flop D9 and a second fifth flip-flop D10. Similarly, Figure 2 the waveform change of the second reset signal rstn_sync in

[0059] is also corresponding to T = 2. Since it takes time for the fifth flip-flop to achieve signal synchronization, after the original write enable signal wen_rtx returns to the invalid state, the second reset signal rstn_sync needs to go through two rising edges of the second clock before releasing the reset. Here, releasing the reset means that the second reset signal rstn_sync changes from the valid state to the invalid state, that is, from low level to high level. Figure 3 This is a schematic illustration of this situation.

[0060] It can be seen that the above settings achieve the asynchronous reset of each fifth flip-flop under the second clock through the original write enable signal wen_rtx under the first clock, and at the same time combine with the synchronous release under the second clock to reset the synchronization unit 3 to ensure the resynchronization of the write flag signal under the second clock.

[0061] Please refer to Figure 4 , Figure 4 which is a flowchart of a data reading and writing method provided by the present invention.

[0062] This data reading and writing method is applied to an electronic device, and the electronic device includes a cross-clock domain communication circuit as described above; this data reading and writing method includes: S11: When receiving a write communication instruction, write the target data into the cache under the first clock, and write the target data from the cache into the register under the second clock based on the write enable signal generated by the cross-clock domain communication circuit; S12: When receiving a read communication instruction, obtain the write flag signal output by the write flag signal generation unit in the cross-clock domain communication circuit; S13: Determine whether the write flag signal is in an active state; if so, go to S14; if not, go to S15; S14: Read data from the cache in response to a read communication instruction; S15: Read data from the register in response to a read communication instruction.

[0063] For the introduction of the data reading and writing method provided in this application, please refer to the embodiments of the above cross-clock domain communication circuit, which will not be elaborated here.

[0064] It can be understood that in the face of cross-clock domain communication, in the methods of the current related technologies, when there is a write communication instruction, data is written first. However, in the case of two adjacent write communication instructions, since the write synchronization process cannot be reliably triggered as described above, the data stored in the register may be the old target data. Then, in response to an immediately following read communication instruction, old data may be read. In this application, relying on the above method, data writing is achieved by using a cross-clock domain communication circuit, and data reading can also be responded to during the process, that is, it is determined whether the data writing is completed according to whether the write flag signal is in an active state, so as to determine the way to respond to an immediately following read communication instruction.

[0065] Specifically, when the write flag signal is in an active state, it indicates that the data writing is not completed yet, and the latest target data is stored in the cache. Therefore, data is read from the cache in response to a read communication instruction; when the write flag signal is in an inactive state, it indicates that the data writing is completed, and the latest target data has been stored in the register. Therefore, data is read from the register in response to a read communication instruction. It can be seen that through the above settings, it is possible to always obtain the latest target data, avoid reading incorrect data, facilitate ensuring data consistency, and support read communication instructions at any time interval after a write communication instruction.

[0066] In addition, in actual operation, the write flag signal wr_ctrl can be obtained and used as the write cache flag signal buf_idx, and then it is determined whether the write cache flag signal buf_idx is in an active state. If so, data is read from the cache in response to a read communication instruction; if not, data is read from the register in response to a read communication instruction. As Figure 2 shown, the waveform change trends of the write flag signal wr_ctrl and the write cache flag signal buf_idx are the same.

[0067] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For related parts, reference can be made to the description in the method section. Relative terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprise", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one" does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0068] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A cross-clock domain communication circuit, characterized in that: It includes a level expansion unit, a write mark signal generating unit, a synchronization unit and a write enable signal generating unit connected in sequence; The level expansion unit is used to perform level expansion according to the received original write enable signal and the communication end mark signal under the first clock to output a level signal; The original write enable signal is in a valid state when a write communication instruction is received under the first clock, and the communication end flag signal is in a valid state when the write communication instruction has ended and N bytes of target data have been written into the cache, where N is an integer not less than 1; The write flag signal generating unit is used to output a write flag signal according to the received level signal and the communication end flag signal under the first clock; the write flag signal is used to be set to be in a valid state and maintained when the level signal and the communication end flag signal are both in a valid state when the write flag signal is in an invalid state; The synchronization unit is used to synchronize the write flag signal under a second clock to obtain a synchronization signal, so that the write enable signal generation unit performs edge extraction according to the synchronization signal to generate a write enable signal under the second clock; wherein the first clock and the second clock are asynchronous clocks.

2. The cross-clock domain communication circuit according to claim 1, characterized in that: The level expansion unit includes a trigger logic circuit and a first trigger; The first input end of the trigger logic circuit is used to receive the original write enable signal, the second input end is used to receive the communication end flag signal, the third input end is connected to the data output end of the first trigger and the common end of the connection is connected to the write flag signal generating unit, the output end is connected to the data input end of the first trigger, and is used to output a first level when the original write enable signal changes from an invalid state to a valid state, and keep outputting the first level until the communication end flag signal changes from a valid state to an invalid state and outputs a second level; The clock signal input terminal of the first trigger is connected to the first clock, and is used to output a level signal in a valid state when the first level is received, and output a level signal in an invalid state when the second level is received.

3. The cross-clock domain communication circuit according to claim 1, characterized in that: The write flag signal generating unit includes a first AND gate, a first NOT gate, a second AND gate, a first OR gate and a second trigger; The first input end of the first AND gate is connected to the output end of the level expansion unit, the second input end is used to receive the communication end flag signal, and the output end is respectively connected to the input end of the first NOT gate and the first input end of the first OR gate; The first input terminal of the second AND gate is connected to the data output terminal of the second flip-flop and the common terminal of the connection is connected to the synchronization unit, the second input terminal is connected to the output terminal of the first NOT gate, and the output terminal is connected to the second input terminal of the first OR gate; The data input terminal of the second trigger is connected to the output terminal of the first OR gate, and the clock signal input terminal is connected to the first clock.

4. The cross-clock domain communication circuit according to claim 3, characterized in that: The synchronization unit includes M third triggers connected in sequence, where M is an integer not less than 3; The clock signal input terminal of each of the third triggers is connected to the second clock, the data input terminal of the first third trigger is connected to the data output terminal of the second trigger, the data output terminal of the M-1 third trigger is respectively connected to the data input terminal of the M third trigger and the first input terminal of the write enable signal generating unit, and the data output terminal of the M third trigger is connected to the second input terminal of the write enable signal generating unit.

5. The cross-clock domain communication circuit according to claim 4, characterized in that: The write enable signal generating unit includes a second NOT gate and a third AND gate; The input end of the second NOT gate serves as the second input end of the write enable signal generating unit; The first input terminal of the third AND gate serves as the first input terminal of the write enable signal generating unit, the second input terminal is connected to the output terminal of the second NOT gate, and the output terminal is used to output the write enable signal generated under the second clock.

6. The cross-clock domain communication circuit according to claim 4, characterized in that: The cross-clock domain communication circuit also includes a state homing unit; The input end of the state reset unit is connected to the data output end of the Mth third trigger, and the output end is connected to the third input end of the second AND gate, and is used to synchronize the received synchronization signal output by the Mth third trigger under the first clock to output a state reset signal; wherein, the state reset signal is in a valid state after synchronization when the synchronization signal is in a valid state, so as to convert the write flag signal that is currently in a valid state into an invalid state.

7. The cross-clock domain communication circuit according to claim 6, characterized in that: The state reset unit includes a third NOT gate, a fourth NOT gate, a fourth AND gate and S fourth flip-flops, where S is an integer not less than 3; S fourth flip-flops are connected in sequence and the clock signal input terminal of each of the fourth flip-flops is connected to the first clock, the data input terminal of the first fourth flip-flop serves as the input terminal of the state reset unit, the data output terminal of the S-1th fourth flip-flop is respectively connected to the data input terminal of the Sth fourth flip-flop and the first input terminal of the fourth AND gate, and the data output terminal of the Sth fourth flip-flop is connected to the input terminal of the third NOT gate; The second input terminal of the fourth AND gate is connected to the output terminal of the third NOT gate, and the output terminal is connected to the input terminal of the fourth NOT gate; The output end of the fourth NOT gate serves as the output end of the state resetting unit.

8. The cross-clock domain communication circuit according to any one of claims 1 to 7, characterized in that: The cross-clock domain communication circuit also includes a reset unit; The reset end of the reset unit is used to receive the original write enable signal, the input end is used to receive the reference signal, the first output end is connected to the reset end of the write flag signal generating unit, and the second output end is connected to the reset end of the synchronization unit, and is used to output a first reset signal through its first output end according to the original write enable signal received by its reset end under the second clock, and output a second reset signal through its second output end according to the original write enable signal and the reference signal; Wherein, the first reset signal is in an invalid state when the original write enable signal is in an invalid state, and is in a valid state when the original write enable signal is in a valid state, so as to reset the write flag signal generating unit, so as to reset the write flag signal currently in a valid state to an invalid state; The second reset signal is in an invalid state and maintained after synchronization when the original write enable signal is in an invalid state, and is in a valid state when the original write enable signal is in a valid state to reset the synchronization unit so that the synchronization unit re-synchronizes the received write flag signal under the second clock.

9. The cross-clock domain communication circuit according to claim 8, characterized in that: The reset unit includes a fifth NOT gate and T fifth flip-flops, where T is an integer not less than 2; T fifth flip-flops are connected in sequence and the clock signal input terminal of each of the fifth flip-flops is connected to the second clock, the reset terminal of each of the fifth flip-flops is connected to the output terminal of the fifth NOT gate, and the common terminal of the connections serves as the first output terminal of the reset unit; The input end of the fifth NOT gate serves as the reset end of the reset unit; The data input terminal of the first fifth flip-flop serves as the input terminal of the reset unit, and the output terminal of the Tth fifth flip-flop serves as the second output terminal of the reset unit.

10. A data reading and writing method, characterized in that: Applied to an electronic device, the electronic device comprising the cross-clock domain communication circuit according to any one of claims 1 to 9; the data reading and writing method comprising: When receiving a write communication instruction, writing the target data into the cache at a first clock, and writing the target data from the cache into a register at a second clock based on a write enable signal generated by the cross-clock domain communication circuit; Upon receiving a read communication instruction, acquiring a write flag signal output by a write flag signal generating unit in the cross-clock domain communication circuit; Determining whether the write flag signal is in a valid state; If so, reading data from the cache in response to the read communication instruction; If not, data is read from the register in response to the read communication instruction.

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