Data processing method and device

Abstract

A data processing method and apparatus, applied to the technical field of computers, the method comprising: receiving a first write command, the first write command being used for writing first data into a first storage space indicated by a first storage address, the first storage space belonging to a memory; compressing the first data to obtain second data, wherein the data volume of the second data is smaller than that of the first data; a second command is sent to the memory, a compression identifier corresponding to the first storage address is generated, the second write command is used for writing the second data into the first storage space, and the compression identifier can be used for indicating that the data stored in the first storage space is compressed data. According to the method provided by the invention, in the process of writing the first data, the first data is compressed and then written, the access bandwidth of a memory can be reduced, and the process is executed in the data writing process, so that the influence on services can be reduced, and the user experience is improved.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a data processing method and apparatus. Background Art

[0002] The power consumption of memory accounts for an increasingly high proportion of the power consumption of the entire computer system. Reducing memory power consumption is considered a key factor in reducing system power consumption. Among them, the power consumption generated by reading and writing data is the main source of memory power consumption. It can be seen that reducing the memory access bandwidth is a research direction for reducing memory power consumption. Summary of the Invention

[0003] Embodiments of this application provide a data processing method and apparatus for reducing the memory access bandwidth, thereby reducing memory power consumption.

[0004] In a first aspect, this application provides a data processing method, which can be executed by a data processing apparatus. The data processing apparatus may be, for example, a memory controller, or may also be a component in the memory controller, without limitation. Taking the memory controller as the execution entity as an example, the method includes: the memory controller receives a first write command for writing first data into a first storage space indicated by a first storage address, where the first storage space belongs to the memory; compressing the first data to obtain second data, where the data volume of the second data is smaller than that of the first data; sending a second command to the memory, and generating a compression identifier corresponding to the first storage address, where the second write command is used to write the second data into the first storage space, and the compression identifier can be used to indicate that the data stored in the first storage space is compressed data.

[0005] In the above embodiments of this application, the memory controller first compresses the first data carried in the write command and then writes it into the memory. The data volume of the compressed first data is smaller than that of the first data. Therefore, compared with directly writing the data carried in the write command into the memory, the embodiments of this application perform compression on a granularity of the data carried in the write command and then write it, which can reduce the memory access bandwidth during the data writing process, thereby reducing the power consumption of the memory. Moreover, real-time compression of the written data can reduce the impact on the service corresponding to the data and improve the user experience.

[0006] The memory controller generates a compression identifier corresponding to the first storage address to identify whether the data stored in the first storage space indicated by the first storage address is compressed data. In this way, the memory controller can send a corresponding read command to the memory according to the compression identifier during the data reading process to correctly read the data.

[0007] Furthermore, after the storage space is allocated, if you want to change the size of the storage space, multiple additional processes need to be triggered (such as the memory controller requesting the corresponding device to reduce the storage space, and the device responding to the request to perform corresponding operations, etc.) to change the corresponding management information. The implementation process is relatively complex and also requires additional processing delays. In the embodiment of the present application, the memory controller compresses the first data and still writes the compressed data into the first storage space without changing the size of the first storage space, so there is no need to change the corresponding management information, which can ensure data consistency, reduce processing delays, and reduce the impact on the service corresponding to the data, improving the user experience.

[0008] Optionally, the write commands (for example, the first write command and the second write command) can be double data rate synchronous dynamic random access memory (DDR SDRAM) burst write commands. For example, the first write command can be a 64-byte write command, and the second write command can be a 32-byte write command. That is, in the embodiment of the present application, data compression and re-writing are performed in units of DDR SDRAM burst write commands, which can achieve real-time compression of the written data and reduce the memory access bandwidth, thereby reducing the power consumption of the memory.

[0009] In a possible implementation manner, the memory controller can generate the compression identifier corresponding to the first storage address in any of the following ways:

[0010] Determine that the compression identifier is stored in the cache according to the first storage address, and update the compression identifier in the cache;

[0011] Alternatively, determine that the compression identifier is not stored in the cache according to the first storage address, and send a first read command, which is used to read the compression identifier from the memory into the cache and update the compression identifier in the cache;

[0012] Alternatively, determine that the compression identifier is stored in the second storage space according to the first storage address, and update the compression identifier in the second storage space. Optionally, the second storage space may or may not belong to the memory, without limitation.

[0013] Through the above implementation methods, the memory controller can generate a compression flag for whether the data is compressed. For example, if the data is compressed, a compression flag is generated for the storage address corresponding to the data; otherwise, no compression flag is generated. Alternatively, the memory controller can also update the status value of the compression flag, with flexible implementation methods. For example, the status value of the compression flag includes a first value and a second value. The first value is used to indicate that the data stored in the storage space indicated by the storage address corresponding to the compression flag is compressed data, and the second value is used to indicate that the data stored in the storage space indicated by the storage address corresponding to the compression flag is not compressed data. Further, the compression flag can be stored in the cache, or it can also not be stored in the cache, such as being stored in a second storage space, with flexible implementation methods. When the compression flag is stored in the cache, the compression flag can be updated through cache hits, which can improve the efficiency of reading the compression flag.

[0014] In a possible implementation method, the compression flag can be stored in the memory, or the compression flag can be stored in the cache, with flexible implementation methods.

[0015] In a possible implementation method, the compression flag can be stored in a second storage space in the memory, and the second storage space and the first storage space belong to different memory banks in the memory.

[0016] Through the above implementation methods, the second storage space for storing the compression flag corresponding to the first storage space and the first storage space belong to different banks in the memory. In this way, the memory controller can simultaneously read the compression flag corresponding to the first storage space and the data stored in the first storage space from different banks, which can avoid row conflicts between the compression flag and the data and improve the scheduling efficiency of the memory controller.

[0017] In another possible implementation method, the compression flag can also be stored in the static random access memory (SRAM) in the memory.

[0018] Through the above implementation methods, introducing (or integrating) SRAM in the memory to store the compression flag does not occupy the available space of the memory and does not reduce the utilization rate of the memory.

[0019] In a possible implementation method, the memory controller can also store the compression flag in the cache to improve the efficiency of reading the compression flag.

[0020] In a possible implementation, the memory controller can also determine that the pattern of the first data is not the first pattern, where the first pattern can be used to avoid storing the first data in the memory, and the compression identifier corresponding to the first pattern can be used to generate the first data. Optionally, the first pattern can be all 0s, or the first pattern can also be all 1s, or the first pattern can also be a preset pattern.

[0021] Through the above implementation, the memory controller can also determine whether the pattern of the first data is the first pattern, so that when the pattern of the first data is the first pattern, the memory controller can not write the first data into the memory, thereby reducing the access bandwidth of the memory and reducing the power consumption of the memory.

[0022] In a second aspect, the present application provides a data processing method, which can be executed by a data processing device. The data processing device can be, for example, a memory controller, or a component in the memory controller, without limitation. Taking the memory controller as the execution entity as an example, the method includes: the memory controller receives a first write command for writing the first data into a first storage space indicated by a first storage address, where the first storage space belongs to the memory; determines that the pattern of the first data is the first pattern; determines not to store the first data in the memory according to the pattern of the first data, and generates a compression identifier corresponding to the first storage address, where the compression identifier corresponding to the first storage address is the compression identifier corresponding to the first pattern, and the compression identifier corresponding to the first pattern can be used to generate the first data.

[0023] In the above embodiments of the present application, when the pattern of the first data is the first pattern, the memory controller can not store the first data in the memory, so there is no need to access the memory. Therefore, the access bandwidth of the memory during the data writing process can be reduced, and the power consumption of the memory can be reduced. The memory controller generates a compression identifier corresponding to the first storage address, and this compression identifier is the compression identifier corresponding to the first pattern. In this way, when the first data needs to be read, the memory controller can generate the first data according to the compression identifier corresponding to the first pattern.

[0024] Optionally, the write command (for example, the first write command) can be a DDR SDRAM burst write command. For example, the first write command can be a 64-byte write command or a 32-byte write command.

[0025] In a possible implementation, the first pattern can be all 0s, or the first pattern can also be all 1s, or the first pattern can also be a preset pattern.

[0026] In a possible implementation, the memory controller can generate the compression identifier corresponding to the first storage address in any of the following ways:

[0027] Determine that the compression flag is stored in the cache according to the first storage address, and update the compression flag in the cache;

[0028] Alternatively, determine that the compression flag is not stored in the cache according to the first storage address, and send a first read command, where the first read command is used to read the compression flag from the memory into the cache, and update the compression flag in the cache;

[0029] Alternatively, determine that the compression flag is stored in the second storage space according to the first storage address, and update the compression flag in the second storage space. Optionally, the second storage space may or may not belong to the memory, without limitation.

[0030] In a possible implementation, the compression flag may be stored in the memory, or the compression flag may be stored in the cache.

[0031] In a possible implementation, the compression flag may be stored in a second storage space in the memory, and the second storage space and the first storage space belong to different banks in the memory.

[0032] In another possible implementation, the compression flag may also be stored in the static random access memory (SRAM) in the memory.

[0033] In a possible implementation, the memory controller may also store the compression flag into the cache.

[0034] For the technical effects achievable by any of the possible implementations in the second aspect above, please refer to the technical effects achievable by any of the possible implementations in the first aspect above accordingly, and details will not be repeated.

[0035] In a third aspect, the present application provides another data processing method, which can be executed by a data processing device. The data processing device may be, for example, a memory controller, or a component in the memory controller, without limitation. Taking the memory controller as the execution entity as an example, the method includes: the memory controller receives a second read command, where the second read command is used to read first data from a first storage space indicated by a first storage address, and the first storage space belongs to the memory; obtain a compression flag corresponding to the first storage address, where the compression flag is used to indicate that the data stored in the first storage space is compressed data; and according to the compression flag, send a third read command to the memory, where the third read command is used to read second data from the first storage space, and the second data is the compressed first data, and the data volume of the second data is smaller than the data volume of the first data.

[0036] In the above embodiments of the present application, the memory controller determines that the data stored in the first storage space indicated by the first storage address is compressed data according to the compression flag corresponding to the first storage address, and sends a third read command for reading the second data to the memory, which can reduce the access bandwidth during the data reading process, thereby reducing the power consumption of the memory.

[0037] Optionally, the read command (e.g., the second read command and the third read command) may be a DDR SDRAM burst read command. For example, the second read command may be a 64-byte read command, and the third read command may be a 32-byte read command.

[0038] In a possible implementation manner, the memory controller may obtain the compression flag corresponding to the first storage address in any of the following ways:

[0039] Determine that the compression flag is stored in the cache according to the first storage address, and obtain the compression flag from the cache;

[0040] Alternatively, determine that the compression flag is not stored in the cache according to the first storage address, send a fourth read command, which can be used to read the compression flag from the memory into the cache, and obtain the compression flag from the cache;

[0041] Alternatively, determine that the compression flag is stored in the second storage space according to the first storage address, and obtain the compression flag from the second storage space. Optionally, the second storage space may or may not belong to the memory, without limitation.

[0042] In a possible implementation manner, the compression flag may be stored in the memory, or the compression flag may be stored in the cache.

[0043] In a possible implementation manner, the compression flag may be stored in a second storage space in the memory, and the second storage space and the first storage space belong to the same bank in the memory.

[0044] In a possible implementation manner, the compression flag may also be stored in the SRAM in the memory.

[0045] In a possible implementation manner, the memory controller may further determine that the compression flag is not the compression flag corresponding to the first code pattern, and the compression flag corresponding to the first code pattern is used to generate the first data. Optionally, the first code pattern may be all 0, or the first code pattern may also be all 1, or the first code pattern may further be a preset code pattern.

[0046] In a possible implementation manner, the memory controller may further perform decompression processing on the second data to obtain the first data.

[0047] For the technical effects achievable by any possible implementation manner of the third aspect above, please refer to the technical effects achievable by any possible implementation manner of the first aspect above accordingly, and no further elaboration will be provided.

[0048] Fourth aspect, the present application provides another data processing method, which can be executed by a data processing device. The data processing device can be, for example, a memory controller, or a component in the memory controller, without limitation. Taking the memory controller as the execution subject as an example, the method includes: the memory controller receives a second read command, where the second read command is used to read first data from a first storage space indicated by a first storage address, and the first storage space belongs to the memory; determining that the compression identifier corresponding to the first storage address is the compression identifier corresponding to a first code pattern; and generating the first data according to the compression identifier.

[0049] In the above embodiments of the present application, the memory controller determines that the compression identifier corresponding to the first storage address is the compression identifier of the first code pattern, and generates the first data according to the compression identifier, so there is no need to access the memory. Therefore, it is possible to reduce the access bandwidth of the memory during the data reading process and reduce the power consumption of the memory.

[0050] Optionally, the read command (for example, the second read command) can be a DDR SDRAM burst read command. For example, the second read command can be a 64-byte read command or a 32-byte read command.

[0051] In a possible implementation manner, the first code pattern can be all 0s, or the first code pattern can also be all 1s, or the first code pattern can further be a preset code pattern.

[0052] In a possible implementation manner, the memory controller can also obtain the compression identifier corresponding to the first storage address.

[0053] Exemplarily, the memory controller can obtain the compression identifier corresponding to the first storage address through any of the following methods:

[0054] Determining that the compression identifier is stored in the cache according to the first storage address, and obtaining the compression identifier from the cache;

[0055] Or, determining that the compression identifier is not stored in the cache according to the first storage address, sending a fourth read command, where the fourth read command can be used to read the compression identifier from the memory into the cache, and obtaining the compression identifier from the cache;

[0056] Or, determining that the compression identifier is stored in a second storage space according to the first storage address, and obtaining the compression identifier from the second storage space. Optionally, the second storage space can belong to the memory or not, without limitation.

[0057] In a possible implementation, the compression identifier can be stored in memory, or the compression identifier can be stored in a cache.

[0058] In a possible implementation, the compression identifier can be stored in a second storage space in memory, and the second storage space and the first storage space belong to different banks in the memory.

[0059] In another possible implementation, the compression identifier can also be stored in the SRAM in memory.

[0060] For the technical effects that can be achieved by any of the possible implementations in the fourth aspect above, please refer to the technical effects that can be achieved by any of the possible implementations in the first aspect above accordingly, and details will not be repeated.

[0061] In a fifth aspect, the present application further provides a data processing device, and the data processing device is configured to execute the method described in any one of the first aspect to the fourth aspect and any of its possible implementations. The data processing device can be, for example, a memory controller, or a functional module in a memory controller, such as a chip.

[0062] In a possible implementation, the data processing device includes a processing module (sometimes also referred to as a processing unit) and a transceiver module (sometimes also referred to as a transceiver unit). The transceiver module can implement a sending function and a receiving function. When the transceiver module implements the sending function, it can be referred to as a sending module (sometimes also referred to as a sending unit). When the transceiver module implements the receiving function, it can be referred to as a receiving module (sometimes also referred to as a receiving unit). The sending module and the receiving module can be the same functional module, and this functional module is called the transceiver module, which can implement the sending function and the receiving function; or, the sending module and the receiving module can be different functional modules, and the transceiver module is a general term for these functional modules.

[0063] In a sixth aspect, the present application further provides a data processing device, and the data processing device includes at least one processor, and the at least one processor is configured to execute one or more computer programs or instructions to implement the method described in any one of the first aspect to the fourth aspect and any of its possible implementations. Optionally, the data processing device can further include a memory, and the memory is configured to store the one or more computer programs or instructions. Optionally, the data processing device can be a chip, or can also be a chip system.

[0064] In a seventh aspect, the present application further provides a data processing device, and the data processing device includes at least one processor and a communication interface. The at least one processor is configured to read and execute instructions through the communication interface, so that the data processing device executes the method described in any one of the first aspect to the fourth aspect and any of its possible implementations.

[0065] In an eighth aspect, the present application further provides a computer-readable storage medium storing a computer program or instructions for implementing the method described in any one of the first to fourth aspects and any possible implementation manner thereof above.

[0066] In a ninth aspect, the present application further provides a computer program product including instructions that, when run on a computer, cause the method described in any one of the first to fourth aspects and any possible implementation manner thereof above to be implemented.

[0067] For the technical effects achievable by the fifth to ninth aspects and any possible implementation manner thereof above, reference may be made correspondingly to the technical effects achievable by the first to fourth aspects and any possible implementation manner thereof above, which will not be elaborated herein. Description of the Drawings

[0068] Figure 1 It is a schematic diagram of the architecture of a system;

[0069] Figure 2 It is a schematic flowchart of a data processing method provided by an embodiment of the present application;

[0070] Figure 3 It is a schematic flowchart of a method for obtaining a compression identifier provided by an embodiment of the present application;

[0071] Figure 4 It is a schematic flowchart of a data processing method provided by an embodiment of the present application;

[0072] Figure 5 It is a schematic flowchart of a data processing method provided by an embodiment of the present application;

[0073] Figure 6 It is a schematic flowchart of another data processing method provided by an embodiment of the present application;

[0074] Figure 7 It is a schematic flowchart of another data processing method provided by an embodiment of the present application;

[0075] Figure 8 It is a schematic flowchart of another data processing method provided by an embodiment of the present application;

[0076] Figure 9 It is a schematic diagram of the structure of a data processing device provided by an embodiment of the present application;

[0077] Figure 10 It is a schematic diagram of the structure of another data processing device provided by an embodiment of the present application;

[0078] Figure 11Schematic diagram of yet another data processing device provided by an embodiment of the present application. Detailed implementation manners

[0079] Embodiments of the present application will be presented around a system including multiple devices, components, modules, etc. It should be understood that the system may include other devices, components, modules, etc. not mentioned, or may only include some of the devices, components, or modules mentioned in the embodiments.

[0080] In the embodiments of the present application, "multiple" may refer to two or more. In view of this, in the embodiments of the present application, "multiple" may also be understood as "at least two". "At least one" can be understood as one or more, for example, understood as one, two, or more. For example, "including at least one" means including one, two, or more. For example, including at least one of A, B, and C, then what can be included are A, B, C, A and B, A and C, B and C, or A, B, and C. "And / or" describes the association relationship of associated objects. Specifically, there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally represents an "or" relationship between the associated objects before and after.

[0081] Ordinal numbers such as "first" and "second" mentioned in the embodiments of the present application are usually used to distinguish different objects, and are not used to limit the order, timing, priority, or importance of multiple objects, etc. For example, the first write command and the second write command involved in the embodiments of the present application are used to distinguish different write commands, and are not used to limit the order, timing, priority, or importance of these two write commands.

[0082] Embodiments of the present application can be applied to scenarios that require access to memory, such as autonomous driving, intelligent cockpits, servers, personal computers, or smart phones, without limitation.

[0083] Figure 1 Exemplarily shown is a schematic diagram of the architecture of a system applicable to the embodiments of the present application. The system can be, for example, a computer system, a storage system, etc., without limitation. As Figure 1 shown, the system may include a memory controller and a memory. The memory controller and the memory are connected by a bus, without limitation. Figure 1 Shown by taking the bus as a straight line as an example.

[0084] A memory controller, which can be used to control the memory and is responsible for data exchange between the memory and the processor. For example, the memory controller can determine the maximum memory capacity that the system can use, the number of memory banks, the memory type and speed, or the data depth and data width of the memory die, without limitation. For another example, the memory controller can determine whether the data can be compressed, compress the data, or decompress the compressed data, without limitation. Exemplarily, the memory controller can be a double data rate synchronous dynamic random access memory memory controller (DMC), or the memory controller can also be an accelerator, etc. The present application does not limit the specific functions and specific implementation forms of the memory controller. In one implementation, the memory controller can be independently deployed, or can also be deployed in the processor, or can also be deployed in the accelerator, without limitation.

[0085] The memory, which can also be referred to as internal memory, main memory, etc., can be used to store the operation data in the processor and the data exchanged with external memories such as hard disks. Exemplarily, the memory can include, but is not limited to, one or more of the following: double data rate synchronous dynamic random access memory (DDR SDRAM), low power DDR SDRAM, or high bandwidth memory (HBM), etc. The present application does not limit the specific implementation form of the memory. For ease of understanding, DDR SDRAM is used as an example for description hereinafter without special explanation.

[0086] DDR SDRAM can also be abbreviated as DDR. Currently, the data transfer mode (or data read / write mode) of DDR is called burst. Burst refers to the way of continuously transmitting data between adjacent storage units in the same row. Among them, the number of storage units (columns) involved in the continuous transmission is called the burst length.

[0087] The memory controller can write data to the DDR by scheduling burst write commands. Exemplarily, the burst write commands can include a 32-byte write command and a 64-byte write command. The 32-byte write command can also be referred to as the DDR SDRAM burst 32-byte write command, or the DDR burst 32-byte write command, etc., without limitation. The 32-byte write command means writing up to 32 bytes of data to the DDR. The 64-byte write command can also be referred to as the DDR SDRAM burst 64-byte write command, or the DDR burst 64-byte write command, etc., without limitation. The 64-byte write command means writing up to 64 bytes of data to the DDR. For example, if the memory controller receives write command 1 and write command 1 is used to request writing 32 bytes of data to the DDR, the memory controller can schedule a 32-byte write command to write the 32 bytes of data to the DDR; or, if write command 1 is used to request writing 64 bytes of data to the DDR, the memory controller can schedule a 64-byte write command to write the 64 bytes of data to the DDR.

[0088] The memory controller can read data from the DDR by scheduling burst read commands. Exemplarily, the burst read commands can include a 32-byte read command and a 64-byte read command. The 32-byte read command can also be referred to as the DDR SDRAM burst 32-byte read command, or the DDR burst 32-byte read command, etc., without limitation. The 32-byte read command means reading up to 32 bytes of data from the DDR. The 64-byte read command can also be referred to as the DDR SDRAM burst 64-byte read command, or the DDR burst 64-byte read command, etc., without limitation. The 64-byte read command means reading up to 64 bytes of data from the DDR. For example, if the memory controller receives read command 1 and read command 1 is used to request reading 32 bytes of data from the DDR, the memory controller can schedule a 32-byte read command to read the 32 bytes from the DDR; or, if read command 1 is used to request reading 64 bytes of data from the DDR, the memory controller can schedule a 64-byte read command to read the 64 bytes of data from the DDR.

[0089] It should be noted that the method provided in the embodiments of the present application is also applicable to future DDRs. The future DDR can still write data through 32-byte write commands and 64-byte write commands, or it can also support write commands with more or fewer bytes (such as 128-byte write commands or 16-byte write commands, etc.) for data writing, without limitation. Similarly, the future DDR can still read data through 32-byte read commands and 64-byte read commands, or it can also support read commands with more or fewer bytes (such as 128-byte write commands or 16-byte write commands, etc.) for data reading, which is also not limited.

[0090] In one implementation, the system may further include at least one processor, which can be used to process data. Figure 1 Taking one processor as an example and shown by a dashed line. The connection between the processor and the memory controller through a bus is not limited. Exemplarily, the processor may include, but is not limited to, one or more of the following: a central processing unit (CPU), a graphics processing unit (GPU), or a neural processing unit (NPU), etc. The specific functions and specific implementation forms of the processor in the present application are not limited.

[0091] In one implementation, the memory controller may include a cache. Figure 1 Shown by a dashed line. In other words, one or more cache spaces may be integrated in the memory controller. For the sake of easy understanding, one cache space is taken as an example for description hereinafter. In another implementation, the system may further include a buffer. The buffer may be located between the processor and the memory controller. For example, the buffer is connected to the processor through a bus, and the buffer is also connected to the memory controller through a bus. Figure 1 Not shown herein.

[0092] The cache, which can also be referred to as a cache space or a buffer, etc., can be used to temporarily store hot data and can interact with the processor prior to the memory, so it can provide a relatively fast access speed. In the embodiments of the present application, the cache can be used to store compression identifiers. The compression identifiers are in one-to-one correspondence with the memory addresses, that is, one compression identifier corresponds to one memory address, and one memory address corresponds to one compression identifier. It should be understood that the name of the compression identifier in the embodiments of the present application is not limited.

[0093] In one implementation, the compression flag can be used to indicate whether the data stored in the storage space indicated by its corresponding storage address is compressed data. For example, compression flag 1 corresponds to storage address 1, and compression flag 2 corresponds to storage address 2. Compression flag 1 can be used to indicate whether the data stored in the storage space indicated by storage address 1 is compressed data, and compression flag 2 can be used to indicate whether the data stored in the storage space indicated by storage address 2 is compressed data.

[0094] Among them, the storage space, which can also be referred to as a storage area or a storage unit, etc., can refer to a storage area allocated in the memory. Exemplarily, the size of a storage space can be 1 byte, or it can also be 32 bytes, or it can also be 64 bytes, or it can also be 128 bytes, etc., without limitation. In the embodiments of the present application, an example is given where a storage space is 64 bytes or greater than 64 bytes. The storage address, which can also be referred to as an address, a storage unit address, or a memory address, etc., can be used to indicate the storage space. The storage address can be understood as the number or serial number of the storage space, etc., without limitation.

[0095] For ease of description, hereinafter, "the data corresponding to the compression flag" is used to represent "the data stored in the storage space indicated by the storage address corresponding to the compression flag". In other words, the term "the data corresponding to the compression flag" and the term "the data stored in the storage space indicated by the storage address corresponding to the compression flag" can be used interchangeably.

[0096] Exemplarily, the value of the compression flag can include a first value and a second value. When the value of the compression flag is the first value, the compression flag can be used to indicate that the data corresponding to the compression flag is compressed data; or, when the value of the compression flag is the second value, the compression flag can be used to indicate that the data corresponding to the compression flag is not compressed data. For example, if the compression flag occupies 1 bit, the first value can be 1 and the second value can be 0; or, the first value can be 0 and the second value can be 1. Another example is that the compression flag can also occupy multiple bits. Taking 2 bits as an example, the first value can be 00 and the second value can be 01, without limitation. The present application does not limit the number of bits occupied by the compression flag and its specific implementation form. In one implementation, when the compression flag is used to indicate that the data corresponding to it is compressed data, the compression flag can also be used to indicate information related to compression such as the compression ratio of the data, without limitation. Among them, the term "the value of the compression flag" can be replaced by "the status value of the compression flag". And, the initial value of the compression flag can be the second value, but this is not limited thereto.

[0097] In another implementation, the compression identifier can be used to indicate that the data stored in the storage space indicated by its corresponding storage address is compressed data. That is, it is determined whether the data stored in the storage space indicated by the storage address is compressed data by whether there is a (or exists) compression identifier corresponding to the storage address. For example, if storage address 1 corresponds to compression identifier 1, the data stored in the storage space indicated by storage address 1 is compressed data; or, if there is no corresponding compression identifier for storage address 1, the data stored in the storage space indicated by storage address 1 is not compressed data. Optionally, the compression identifier can also be used to indicate information related to compression such as the compression ratio of the data, without limitation.

[0098] In yet another implementation, the compression identifier can also be used to generate (or determine) data. For example, the compression identifier can be used to generate or (determine) data of a special code pattern (such as denoted as the first code pattern); or rather, the compression identifier can correspond to a special code pattern (or data of a special code pattern); or rather, the compression identifier can be used to indicate that the code pattern of the data originally to be stored at its corresponding storage address is a special code pattern. This means that the data of the special code pattern can be determined through the compression identifier, so that it is not necessary to write the data of the special code pattern into the memory and it is not necessary to read the data of the special code pattern from the memory. Optionally, the first code pattern can be all 0s, or can also be all 1s, or can also be a preset code pattern, without limitation. Among them, all 0s means that the value (or state value) of each bit is 0. All 1s means that the value of each bit is 1. For example, taking 2 bits as an example, all 0s can refer to 00, and all 1s can refer to 11. Another example is that taking 3 bits as an example, all 0s can refer to 000, and all 1s can refer to 111.

[0099] Exemplarily, the compression identifier and the special code pattern can correspond one by one, that is, one compression identifier corresponds to one special code pattern. One special code pattern corresponds to one compression identifier. Table 1 exemplarily shows the correspondence between the compression identifier and the special code pattern. As shown in Table 1, when the special code pattern is code pattern 1, the compression identifier corresponding to this special code pattern is compression identifier 1; when the special code pattern is code pattern 2, the compression identifier corresponding to this special code pattern is compression identifier 2; when the special code pattern is code pattern 3, the compression identifier corresponding to this special code pattern is compression identifier 3.

[0100] Table 1

[0101] Special code pattern Compression flag Code pattern 1 Compression flag 1 Code pattern 2 Compression flag 2 Code pattern 3 Compression flag 3

[0102] It should be noted that Figure 1 Taking the shown system architecture as an example, the present application is not limited thereto.

[0103] The embodiments of the present application provide a data processing method and apparatus, which are used to reduce the access bandwidth of the memory, thereby reducing the power consumption of the memory. Among them, the method and apparatus of the present application are based on the same technical concept. Since the principles of the method and apparatus for solving problems are similar, the implementation of the apparatus and the method can be referred to each other, and the repeated parts will not be elaborated. This method can be applied to Figure 1 the system architecture shown, but is not limited thereto. For example, this method can be executed by Figure 1 the memory controller in the system shown, or by Figure 1 components in the memory controller in the system shown, without limitation. For the sake of convenience of description, the memory controller is taken as the execution subject in the following text.

[0104] The embodiments of the present application relate to the data writing process and the data reading process. First, the data processing method in the data writing process will be introduced below.

[0105] Figure 2 A schematic flowchart of a data processing method provided by an embodiment of the present application is exemplarily shown. In this embodiment, the memory controller compresses the data to be written (such as denoted as the first data), and then writes the compressed data (such as denoted as the second data) into the memory. As Figure 2 shown, this method may include the following content.

[0106] S201: The memory controller receives a first write command.

[0107] The first write command can be used to write the first data into the first storage space indicated by the first storage address, and the first storage space belongs to the memory. In other words, the first write command can be used to write the first data into the memory, and the storage address of the first data is the first storage address. The first write command can come from a user, or can also be generated by an internal task, etc. The specific implementation form of the sending end of the first write command in the embodiments of the present application is not limited. The first data can be image data, or can also be audio data, or can also be text, etc. The specific implementation form of the first data in the embodiments of the present application is not limited. Exemplarily, the data volume of the first data can be 64 byte, without limitation. Optionally, in this embodiment, the first write command can be a 64-byte write command. For specific reference, please refer to the foregoing content and will not be elaborated.

[0108] S202: The memory controller compresses the first data to obtain the second data.

[0109] The data volume of the second data is less than the data volume of the first data. For example, if the data volume of the first data is 64 byte, the data volume of the second data can be 32 byte, or less, without limitation. It should be noted that the compression method of the first data in the embodiments of the present application is not limited.

[0110] S203: The memory controller sends a second write command to the memory.

[0111] The second write command can be used to write second data into the first storage space. For example, the second write command can be used to write 32-byte second data into the first storage space. Herein, the memory controller sending the second command to the memory can be understood as: the memory controller writing the second data into the first storage space. Optionally, in this embodiment, the second write command can be a 32-byte write command. For specific reference, please refer to the foregoing content and will not be elaborated herein.

[0112] The data volume of the second data is smaller than that of the first data. Compared with directly writing the first data into the memory, writing the second data into the memory in this embodiment can reduce the access bandwidth of the memory, thereby reducing the power consumption of the memory. For example, the first data is 64 bytes. Originally, the memory controller needs to schedule a 64-byte write command to write the first data into the DDR. In the embodiment of the present application, the 64-byte data is compressed into 32-byte data. Therefore, the memory controller can schedule a 32-byte write command to write the compressed first data into the DDR, which is reduced from the original 64 bytes to 32 bytes, reducing the access bandwidth of the memory, improving the effective access bandwidth of the memory, and reducing the power consumption of the memory. Moreover, the compression process of the first data is performed during the writing process of the first data, that is, the written data is compressed in real time, which can reduce the impact on the service corresponding to the data and improve the user experience.

[0113] After the storage space is allocated, if you want to change the size of the storage space, multiple additional processes need to be triggered (such as the memory controller requesting the corresponding device to reduce the storage space, and the device performing corresponding operations in response to the request, etc.) to change the corresponding management information, and the implementation process is relatively complex and requires additional processing delay. In S203, after the memory controller compresses the first data, it still writes the compressed data into the first storage space without changing the size of the first storage space, so there is no need to change the corresponding management information, which can ensure data consistency, reduce processing delay and reduce the impact on the service corresponding to the data, and improve the user experience.

[0114] S204: The memory controller generates a compression identifier corresponding to the first storage address.

[0115] In this embodiment, the compression identifier generated by the memory controller is used to indicate that the data stored in the first storage space indicated by its corresponding first storage address is compressed data. Here, "generate" can be understood as create, update, modify, determine, etc., without limitation. For example, the memory controller can generate or create the compression identifier corresponding to the first storage address, and this compression identifier is used to indicate that the data stored in the first storage space indicated by its corresponding first storage address is compressed data. Another example is that the memory controller can update the compression identifier corresponding to the first storage address, and the updated compression identifier is used to indicate that the data stored in the first storage space indicated by its corresponding first storage address is compressed data. Here, updating the compression identifier corresponding to the first storage address can be understood as: updating (or modifying) the value (or status value, or bit value, etc.) of the compression identifier corresponding to the first storage address. For example, the initial value of the compression identifier can be empty, or it can be a first value, or it can also be a second value. The embodiments of the present application do not limit the specific implementation manner of the initial value of the compression identifier. For example, the value of the updated compression identifier can be the first value. The descriptions of the first value and the second value can refer to the foregoing content and will not be elaborated here. It should be understood that the values of the compression identifier before and after the update can be different or the same, without limitation.

[0116] Among them, "the compression identifier is used to indicate that the data stored in the first storage space indicated by its corresponding first storage address is compressed data" can be replaced with: "the compression identifier is used to indicate that the second data stored in the first storage space indicated by its corresponding first storage address is compressed data"; or it can also be replaced with: "the compression identifier is used to indicate that the data (or second data) stored in the first storage space is compressed data"; or it can also be replaced with: "the compression identifier is used to indicate that the data (or second data) corresponding to it is compressed data"; or it can also be replaced with: "the compression identifier is used to indicate that the second data is compressed data". Optionally, the compression identifier can also indicate that the compression ratio of the second data is equal to the information related to compression, without limitation.

[0117] In one implementation, the memory controller can store the compression identifier in the cache, which can improve the efficiency of the memory controller in scheduling the compression identifier. Or, the memory controller can also store the compression identifier in the second storage space. The second storage space can belong to the memory or not, without limitation. For the sake of simplicity, the following will take the case where the second storage space belongs to the memory as an example for illustration. Optionally, after the memory controller stores the compression identifier in the cache, when the condition is met (such as the effective duration of the compression identifier in the cache expires or is regularly cleared, etc.), the memory controller can migrate the compression identifier from the cache to the memory, without limitation.

[0118] In one implementation, the compression identifier can be stored in a cache, which can improve the efficiency of the memory controller in scheduling the compression identifier. For example, a cache space can be integrated in the memory controller, and this cache space is used to store the compression identifier, as Figure 1 shown. As another example, a buffer can be connected between the memory controller and the processor, and this buffer is used to store the compression identifier.

[0119] In another implementation, the compression identifier can also be stored in a second storage space. For example, the compression identifier can be stored in a second storage space in the memory, that is, a storage space is allocated from the memory to store the compression identifier. Optionally, the second storage space and the first storage space belong to different banks in the memory, so that the memory controller can simultaneously read the compression identifier corresponding to the first storage space and the data stored in the first storage space from different banks, which can avoid row conflicts between the compression identifier and the data and improve the scheduling efficiency of the memory controller. As another example, the compression identifier can be stored in a static random access memory (SRAM) in the memory, that is, a SRAM is introduced (or integrated) in the memory to store the compression identifier, so that it does not occupy the available space of the memory and does not reduce the utilization rate of the memory.

[0120] It should be noted that the embodiments of the present application do not limit the storage method of the compression identifier.

[0121] In S204, the memory controller can generate the compression identifier corresponding to the first storage address in any of the following ways.

[0122] Method 1: The memory controller directly generates or creates the compression identifier corresponding to the first storage address.

[0123] Method 2: The memory controller updates the compression identifier corresponding to the first storage address in the cache.

[0124] If the compression identifier is stored in the cache, the memory controller can update the compression identifier corresponding to the first storage address in the cache. Exemplarily, the memory controller can first attempt to obtain the compression identifier corresponding to the first storage address from the cache, and obtain the compression identifier from the memory when it is determined that the compression identifier is not stored in the cache. Specifically, the memory controller can determine whether the compression identifier is stored in the cache. For example, the memory controller can determine whether the compression identifier is stored in the cache according to the first storage address, as Figure 3 shown in S301. Further, if the memory controller determines that the compression identifier is not stored in the cache according to the first storage address, then the memory controller can send a first read command to the memory, and this first read command can be used to read the compression identifier from the memory into the cache and obtain the compression identifier from the cache, as Figure 3as shown in S302 and S303. Or if the memory controller determines that the compression identifier is stored in the cache according to the first storage address, the memory controller can obtain the compression identifier from the cache, as Figure 3 shown in S304. The Figure 3 exemplarily shows a schematic flowchart of a method for obtaining a compression identifier provided by an embodiment of the present application. Among them, the memory controller sending a first read command to the memory can be understood as: the memory controller reads the compression identifier from the memory into the cache.

[0125] Or rather, the memory controller can first attempt to update the compression identifier corresponding to the first storage address in the cache, and when it determines that the compression identifier is not stored in the cache, then read the compression identifier from the memory into the cache for update. Specifically, the memory controller can determine whether the compression identifier is stored in the cache. For example, the memory controller can determine whether the compression identifier is stored in the cache according to the first storage address. Further, if the memory controller determines that the compression identifier is not stored in the cache according to the first storage address, then the memory controller can send a first read command to the memory, and this first read command can be used to read the compression identifier from the memory into the cache and update the compression identifier in the cache. Or if the memory controller determines that the compression identifier is stored in the cache according to the first storage address, then the memory controller can update the compression identifier in the cache. Among them, the memory controller sending a first read command to the memory can be understood as: the memory controller reads the compression identifier from the memory into the cache.

[0126] Mode 3: The memory controller updates the compression identifier corresponding to the first storage address in the second storage space.

[0127] If the compression identifier is not stored in the cache, the memory controller can update the compression identifier corresponding to the first storage address in the second storage space. Exemplarily, the memory controller determines that the compression identifier is stored in the second storage space according to the first storage address, and updates the compression identifier in the second storage space. For example, the memory controller can determine a full-space search according to the first storage address, and the search result is that the compression identifier is stored in the second storage space. Optionally, this second storage space can belong to the memory, or it can also not belong to the memory, without limitation.

[0128] The memory controller can generate the compression identifier corresponding to the first storage address through any of the above methods. In S204, the memory controller generates the compression identifier corresponding to the first storage address to identify whether the data stored in the first storage space indicated by the first storage address is compressed data, so that the memory controller can send a corresponding read command to the memory according to this compression identifier during the data reading process to correctly read the data.

[0129] In one implementation, the memory controller may determine whether the first data supports (or can be) compressed. For example, before S202, the memory controller may determine whether the first data supports compression. If the memory controller determines that the first data supports compression, then the memory controller executes the content of S202 to S204 in Figure 2 . Or if the memory controller determines that the first data does not support compression, then the memory controller may directly write the first data into the memory, Figure 2 which is not shown. For example, the memory controller may not compress the first data and send a third write command to the memory, and the third write command may be used to write the first data into the first storage space. Optionally, the memory controller may also generate a compression flag corresponding to the first storage address, and the compression flag indicates that the data stored in the first storage space indicated by its corresponding first storage address is not compressed data. For specific details, please refer to the foregoing content and will not be elaborated here. Among them, the memory controller sending the third write command to the memory can be understood as: the memory controller writing the first data into the first storage space. Optionally, the third write command may be a 64-byte write command. For specific details, please refer to the foregoing content and will not be elaborated here.

[0130] The compression flag is used to indicate that the data stored in the first storage space indicated by its corresponding first storage address is not compressed data can be replaced with: The compression flag is used to indicate that the first data stored in the first storage space indicated by its corresponding first storage address is not compressed data; or it can also be replaced with: The compression flag is used to indicate that the data (or the first data) stored in the first storage space is not compressed data; or it can also be replaced with: The compression flag is used to indicate that the corresponding data (or the first data) is not compressed data; or it can also be replaced with: The compression flag is used to indicate that the first data is not compressed data; or it can also be replaced with: The compression flag is used to indicate that the first data is not compressed.

[0131] It should be noted that the specific implementation manner for the memory controller to determine whether the first data supports compression is not limited in the embodiments of the present application.

[0132] It should be noted that Figure 2 The execution order of the steps shown is taken as an example and is not limited thereto. For example, the memory controller may first send a second write command to the memory and then generate a compression flag corresponding to the first storage address; or the memory controller may first generate a compression flag corresponding to the first storage address and then send a second write command to the memory; or, the memory controller may send a second write command to the memory while generating a compression flag corresponding to the first storage address.

[0133] Figure 4A flowchart of a data processing method provided by an embodiment of the present application is exemplarily shown. In this embodiment, when the code pattern of the first data is a special code pattern (denoted as the first code pattern), the memory controller does not write the first data into the memory. As Figure 4 shown, the method may include the following content.

[0134] S401: The memory controller receives a first write command.

[0135] The first write command can be used to write the first data into the first storage space indicated by the first storage address, and the first storage space belongs to the memory. In other words, the first write command can be used to write the first data into the memory, and the storage address of the first data is the first storage address. The first write command can come from a user, or can also be generated by an internal task, etc. The specific implementation form of the sending end of the first write command in the embodiment of the present application is not limited. The first data can be image data, or can also be audio data, or can also be text, etc. The specific implementation form of the first data in the embodiment of the present application is not limited. Exemplarily, the data volume of the first data can be 64 bytes or 32 bytes, without limitation. Optionally, in this embodiment, the first write command can be a 64-byte write command or can also be a 32-byte write command. For specific reference, please refer to the foregoing content and will not be elaborated here.

[0136] S402: The memory controller determines that the code pattern of the first data is the first code pattern.

[0137] The code pattern of the first data can be understood as: the value of the first data; or can also be understood as: the bit value of the first data; or can also be understood as: the binary expression of the first data, etc. The first code pattern can be all 0s, or can also be all 1s, or can also be a preset code pattern, without limitation. Among them, the descriptions of all 0s and all 1s can refer to the foregoing content and will not be elaborated here.

[0138] S403: The memory controller determines not to store the first data in the memory (or the first storage space) according to the code pattern of the first data.

[0139] Or S403 can also be described as: The memory controller determines not to write the first data into the memory (or the first storage space) according to the code pattern of the first data; or S403 can also be described as: The memory controller does not write the first data into (or store it in) the memory (or the first storage space) according to the code pattern of the first data.

[0140] S404: The memory controller generates a compression identifier corresponding to the first storage address.

[0141] In this embodiment, the compression identifier generated by the memory controller is the compression identifier corresponding to the first code pattern. The compression identifier corresponding to the first code pattern can be used to generate the first data, or in other words, the compression identifier corresponding to the first code pattern can be used to generate the first data corresponding to the first code pattern. Here, "generate" can be understood as create, update, modify, determine, etc., without limitation. For example, the memory controller can generate or create the compression identifier corresponding to the first storage address, and this compression identifier is used to generate the first data. For another example, the memory controller can update the compression identifier corresponding to the first storage address, and the updated compression identifier is used to generate the first data. Here, updating the compression identifier can be understood as: updating (or modifying) the value (or status value, or bit value, etc.) of the compression identifier corresponding to the first storage address. Optionally, the compression identifier corresponding to the first code pattern can also be used to indicate that the code pattern of the data originally to be stored at its corresponding first storage address is the first code pattern. There is a corresponding relationship between the first code pattern and the compression identifier. For specific details, reference can be made to the foregoing content, which will not be elaborated here.

[0142] In one implementation, the memory controller can store the compression identifier in the cache, which can improve the efficiency of the memory controller in scheduling the compression identifier. Alternatively, the memory controller can also store the compression identifier in the second storage space. The second storage space may or may not belong to the memory, without limitation. In other words, the compression identifier can be stored in the cache, or it can also be stored in the second storage space. For specific details, please refer to the content of S204, which will not be elaborated here.

[0143] Optionally, after the memory controller stores the compression identifier in the cache, when the condition is met (such as the expiration of the valid duration of the compression identifier in the cache or being periodically cleared, etc.), the memory controller can migrate the compression identifier from the cache to the memory, without limitation.

[0144] In S404, the specific way for the memory controller to generate the compression identifier of the first storage address can be: the memory controller directly generates or creates the compression identifier corresponding to the first storage address; or, the memory controller updates the compression identifier corresponding to the first storage address in the cache; or, the memory controller updates the compression identifier corresponding to the first storage address in the second storage space. For specific implementation methods, reference can be made to the relevant content of S204, which will not be elaborated here.

[0145] It should be noted that Figure 2 the meaning of the compression identifier generated by the memory controller in the illustrated embodiment is different from Figure 4 the meaning of the compression identifier generated by the memory controller in the illustrated embodiment. Both can be referred to as compression identifiers, or different terms can be used to represent them respectively. For example, the first compression identifier is used to indicate that the data stored in its corresponding first storage space is compressed data, and the second compression identifier is used to generate the first data, without limitation.

[0146] It should be noted that Figure 4 The execution order of the steps shown is taken as an example and is not limited thereto. For example, the memory controller may first determine not to store the first data in the memory, and then generate a compression identifier corresponding to the first storage address; or the memory controller may first generate a compression identifier corresponding to the first storage address, and then determine not to store the first data in the memory; or, the memory controller may determine not to store the first data in the memory while generating a compression identifier corresponding to the first storage address.

[0147] The above Figure 4 In the embodiment shown, when the code pattern of the first data is the first code pattern, the memory controller may not store the first data in the memory, and thus there is no need to access the memory. Therefore, the access bandwidth of the memory during the data writing process can be reduced, and the power consumption of the memory can be lowered. Moreover, the memory controller generates a compression identifier corresponding to the first storage address, and this compression identifier is the compression identifier corresponding to the first code pattern. In this way, when the first data needs to be read, the memory controller can generate the first data according to the compression identifier corresponding to the first code pattern.

[0148] In one implementation manner Figure 2 The embodiment shown and Figure 4 The embodiment shown can be implemented separately or in combination. For example, the memory controller may determine whether the code pattern of the first data is the first code pattern. Further, if the memory controller determines that the code pattern of the first data is not the first code pattern, then the memory controller may execute the content of S202 to S204; or if the memory controller determines that the code pattern of the first data is the first code pattern, then the memory controller may execute the content of S403 and S404, as Figure 5 shown. This Figure 5 exemplarily shows a schematic flowchart of a data processing method provided by an embodiment of the present application. As Figure 5 shown, the method may include the following content.

[0149] S501: The memory controller receives a first write command. This first write command may be used to write the first data into a first storage space indicated by the first storage address, and this first storage space belongs to the memory. Among them, the specific implementation process of S501 may refer to the content of S201 or S401 and will not be elaborated here.

[0150] S502: The memory controller determines whether the code pattern of the first data is the first code pattern. If the memory controller determines that the code pattern of the first data is the first code pattern, then execute the content of S503; or if the memory controller determines that the model of the first data is not the first code pattern, then execute S506.

[0151] S503: The memory controller determines not to store the first data in the memory according to the code pattern of the first data.

[0152] S504: The memory controller obtains the compression flag corresponding to the first storage address. For example, the memory controller can obtain the compression flag from the cache or the memory.

[0153] S505: The memory controller updates the compression flag to obtain a compression flag 1. The compression flag 1 is the compression flag corresponding to the first code pattern and can be used to generate or determine the first data.

[0154] For the sake of simplicity, in this embodiment, the compression flag corresponding to the first code pattern is denoted as the compression flag 1, the compression flag used to indicate that the data stored in the first storage space is compressed data is denoted as the compression flag 2, and the compression flag used to indicate that the data stored in the first storage space is not compressed data is denoted as the compression flag 3 as an example for illustration.

[0155] For the specific implementation processes of the above S502 to S505, please refer to the relevant content of the Figure 4 illustrated embodiment, which will not be elaborated here. It should be understood that S504 and S505 can be replaced with: The memory controller generates the compression flag 1.

[0156] S506: The memory controller determines whether the first data supports compression. If the memory controller determines that the first data supports compression, then execute S507; or if the memory controller determines that the first data does not support compression, then execute S511.

[0157] S507: The memory controller compresses the first data to obtain second data. The data volume of the second data is smaller than that of the first data.

[0158] S508: The memory controller sends a second write command to the memory. The second write command can be used to write the second data into the first storage space.

[0159] S509: The memory controller obtains the compression flag corresponding to the first storage address. For example, the memory controller can obtain the compression flag from the cache or the memory.

[0160] S510: The memory controller updates the compression flag to obtain a compression flag 2. The compression flag 2 can be used to indicate that the data stored in the first storage space is compressed data.

[0161] It should be understood that S509 and S510 can be replaced with: The memory controller generates the compression flag 2.

[0162] S511: The memory controller sends a third write command to the memory. The third write command can be used to write the first data into the first storage space.

[0163] S512: The memory controller obtains the compression flag corresponding to the first storage address. For example, the memory controller may obtain the compression flag from a cache or memory.

[0164] S513: The memory controller updates the compression flag to obtain a compression flag 3. The compression flag 3 can be used to indicate that the data stored in the first storage space is not compressed data.

[0165] S512 and S513 are optional steps, Figure 5 and are represented by a dashed line.

[0166] It should be understood that S512 and S513 can be replaced by: The memory controller generates a compression flag 3.

[0167] For the specific implementation processes of the above S506 to S513, please refer to the relevant content of the Figure 2 illustrated embodiments correspondingly, which will not be elaborated here.

[0168] It should be noted that Figure 5 The execution order of the illustrated steps is taken as an example and is not limited thereto. For example, the memory controller may first determine whether the code pattern of the first data is the first code pattern, and then determine whether the first data supports compression; or the memory controller may first determine whether the first data supports compression, and then determine whether the code pattern of the first data is the first code pattern; or the memory controller may also simultaneously determine whether the first data supports compression and whether the code pattern of the first data is the first code pattern.

[0169] The data processing method in the data writing process was introduced above. Next, the data processing method in the data reading process will be introduced.

[0170] Figure 6 Exemplarily shown is a flowchart of another data processing method provided by an embodiment of the present application. In this embodiment, the memory controller responds to a second read command for reading the first data, and reads the compressed data of the first data from the memory according to the compression flag corresponding to the first storage address. As Figure 6 shown, the method may include the following.

[0171] S601: The memory controller receives the second read command.

[0172] The second read command can be used to read the first data from the first storage space indicated by the first storage address, and the first storage space belongs to the memory. In other words, the second read command can be used to read the first data from the memory, and the storage address of the first data is the first storage address. The second read command can come from the user, or can also be generated by an internal task, etc. The specific implementation form of the sending end of the second read command in the embodiments of the present application is not limited. Exemplarily, the data volume of the first data can be 64 bytes, without limitation. The description of the first data can refer to S201 and will not be elaborated here. Optionally, in this embodiment, the second read command can be a 64-byte read command. For specific details, please refer to the foregoing content and will not be elaborated here.

[0173] S602: The memory controller obtains the compression flag corresponding to the first storage address.

[0174] The compression flag can be used to indicate that the data stored in the first storage space is compressed data. The description of the compression flag can refer to the relevant content of S204 and will not be elaborated here. The compression flag can be stored in the cache; or the compression flag can also be stored in the second storage space. For example, the second storage space can belong to the memory, and the second storage space and the first storage space belong to different banks, or the second storage space is the SRAM in the memory. For specific details, please refer to the relevant content of S204 and will not be elaborated here.

[0175] In one implementation, the memory controller can obtain the compression flag according to the first storage address. As an example, the memory controller can first try to obtain the compression flag from the cache, and then obtain the compression flag from the memory when it is determined that the compression flag is not stored in the cache. Specifically, the memory controller can determine whether the compression flag is stored in the cache. For example, the memory controller can determine whether the compression flag is stored in the cache according to the first storage address. Further, if the memory controller determines that the compression flag is not stored in the cache according to the first storage address, then the memory controller can send a fourth read command to the memory. The fourth read command can be used to read the compression flag from the memory (such as the second storage space or SRAM) into the cache, and obtain the compression flag from the cache. Or if the memory controller determines that the compression flag is stored in the cache according to the first storage address, then the memory controller can obtain the compression flag from the cache. The memory controller's obtaining of the compression flag can refer to the Figure 3 embodiment shown. Among them, the memory controller sending the fourth read command to the memory can be understood as: the memory controller reads the compression flag from the memory into the cache.

[0176] Another example is that the memory controller can determine that the compression identifier is stored in the second storage space according to the first storage space, and obtain the compression identifier from the second storage space. For example, the memory controller can perform a full-space search based on the first storage address, and the search result is that the compression identifier is stored in the second storage space, and obtain the compression identifier from the second storage space. For the description of the second storage space, please refer to the foregoing content and will not be elaborated here.

[0177] S603: The memory controller sends a third read command to the memory according to the compression identifier.

[0178] This third read command can be used to read the second data from the first storage space, that is, read the second data from the memory. The second data is the data obtained after compressing the first data. The data volume of the second data is smaller than that of the first data. Among them, the memory controller sending the third read command to the memory can be understood as: the memory controller reads the second data from the first storage space (or memory). Optionally, in this embodiment, the third read command can be a 32-byte read command. For specific details, please refer to the foregoing content and will not be elaborated here.

[0179] Optionally, the memory controller can also perform decompression processing on the second data to obtain the first data, that is, execute the content of S604.

[0180] S604: The memory controller performs decompression processing on the second data to obtain the first data.

[0181] S604 is an optional step Figure 6 and is indicated by a dotted line. The memory controller can decompress the second data to obtain the first data.

[0182] Optionally, the memory controller can also send the first data. For example, after S604, the memory controller sends the first data.

[0183] In one implementation, the memory controller obtains the compression flag corresponding to the first storage address, and can determine whether the data stored in the first storage space indicated by the first storage address is compressed data according to the compression flag corresponding to the first storage address. For example, the memory controller determines that the data stored in the first storage space indicated by the first storage address is compressed data according to the compression flag corresponding to the first storage address, and sends a third read command to the memory. For another example, the memory controller determines that the data stored in the first storage space indicated by the first storage address is not compressed data according to the compression flag corresponding to the first storage address, and sends a fifth read command to the memory. The fifth read command can read the first data from the first storage space (or the memory). Herein, the memory controller sending the fifth read command to the memory can be understood as: the memory controller reads the first data from the first storage space (or the memory). Optionally, the fifth read command can be a 64-byte read command. For specific reference, please refer to the foregoing content and details are not repeated here.

[0184] In Figure 6 In the illustrated embodiment, the memory controller determines that the data stored in the first storage space indicated by the first storage address is compressed data according to the compression flag corresponding to the first storage address, and sends a third read command for reading the second data to the memory, which can reduce the access bandwidth during the data reading process, thereby reducing the power consumption of the memory.

[0185] Figure 7 Exemplarily, a flowchart of another data processing method provided by an embodiment of the present application is shown. In this embodiment, the memory controller generates the first data according to the compression flag corresponding to the first storage address. As Figure 7 shown, the method may include the following content.

[0186] S701: The memory controller receives a second read command.

[0187] The second read command can be used to read the first data from the first storage space indicated by the first storage address, and the first storage space belongs to the memory. In other words, the second read command can be used to read the first data from the memory, and the storage address of the first data is the first storage address. The second read command can come from a user, or can also be generated by an internal task, etc. The specific implementation form of the sending end of the second read command in the embodiment of the present application is not limited. Exemplarily, the data volume of the first data can be 64 bytes or 32 bytes, without limitation. The description of the first data can refer to S201 and details are not repeated here. Optionally, in this embodiment, the second read command can be a 64-byte read command or a 32-byte read command. For specific reference, please refer to the foregoing content and details are not repeated here.

[0188] S702: The memory controller determines that the compression identifier corresponding to the first storage address is the compression identifier corresponding to the first code pattern.

[0189] Alternatively, S702 can also be described as: The memory controller obtains the compression identifier corresponding to the first storage address, and this compression identifier is the compression identifier corresponding to the first code pattern.

[0190] The compression identifier corresponding to the first code pattern can be used to generate or determine the first data; or, the compression identifier corresponding to the first code pattern can be used to generate or determine the data corresponding to the first code pattern, that is, the first data. This compression identifier can be stored in the cache; or this compression identifier can also be stored in the second storage space. For specific details, please refer to the relevant content of S404 and will not be elaborated here. Among them, the first code pattern can be all 0, or can also be all 1, or can also be a preset code pattern. For specific details, please refer to the foregoing content and will not be elaborated here.

[0191] In one implementation, the memory controller obtains the compression identifier corresponding to the first storage address and determines that the compression identifier corresponding to the first storage address is the compression identifier corresponding to the first code pattern. For example, the memory controller can determine that the compression identifier corresponding to the first storage address is the compression identifier corresponding to the first code pattern according to the correspondence between the compression identifier and the first code pattern.

[0192] In one implementation, the memory controller can obtain the compression identifier according to the first storage address. As an example, the memory controller can first attempt to obtain the compression identifier from the cache, and when it determines that the compression identifier is not stored in the cache, then obtain the compression identifier from the memory. Specifically, the memory controller can determine whether the compression identifier is stored in the cache. For example, the memory controller can determine whether the compression identifier is stored in the cache according to the first storage address. Further, if the memory controller determines according to the first storage address that the compression identifier is not stored in the cache, then the memory controller can send a fourth read command to the memory, and this fourth read command can be used to read the compression identifier from the memory (such as the second storage space or SRAM) into the cache and obtain the compression identifier from the cache. Or if the memory controller determines according to the first storage address that the compression identifier is stored in the cache, then the memory controller can obtain the compression identifier from the cache. The memory controller's obtaining of the compression identifier can refer to the Figure 3 illustrated embodiment. Among them, the memory controller sending a fourth read command to the memory can be understood as: The memory controller reads the compression identifier from the memory into the cache.

[0193] Another example is that the memory controller can determine that the compression identifier is stored in the second storage space according to the first storage space, and obtain the compression identifier from the second storage space. For example, the memory controller can perform a full-space search based on the first storage address, and the search result is that the compression identifier is stored in the second storage space, and the compression identifier is obtained from the second storage space. For the description of the second storage space, please refer to the foregoing content and will not be elaborated here.

[0194] S703: The memory controller generates the first data according to the compression identifier.

[0195] The memory controller can generate or determine the first data according to the compression identifier. For example, the memory controller can determine the first data according to the correspondence between the first code pattern and the compression identifier. The specific implementation process of the memory controller generating the first data according to the compression identifier in the embodiments of the present application is not limited.

[0196] Optionally, the memory controller can also send the first data. For example, after S703, the memory controller sends the first data.

[0197] In Figure 7 In the shown embodiment, the memory controller determines that the compression identifier corresponding to the first storage address is the compression identifier of the first code pattern, and generates the first data according to the compression identifier, so there is no need to access the memory, thus reducing the access bandwidth of the memory during the data reading process and reducing the power consumption of the memory.

[0198] In one implementation manner, Figure 6 the shown embodiment and Figure 7 the shown embodiment can be implemented separately or in combination. For example, the memory controller can determine whether the compression identifier corresponding to the first storage address is the compression identifier corresponding to the first code pattern. Further, if the memory controller determines that the compression identifier of the first storage address is not the compression identifier corresponding to the first code pattern, then the memory controller can execute the content of S603 and S604; or if the memory controller determines that the compression identifier of the first storage address is the compression identifier corresponding to the first code pattern, then the memory controller can execute the content of S703, as Figure 8 shown. The Figure 8 exemplarily shows a schematic flowchart of a data processing method provided by the embodiments of the present application. As Figure 8 shown, the method may include the following content.

[0199] S801: The memory controller receives a second read command. The second read command can be used to read the first data from the first storage space indicated by the first storage address, and the first storage space belongs to the memory. The specific implementation process of S801 can refer to S601 or S701 and will not be elaborated here.

[0200] S802: The memory controller obtains the compression flag corresponding to the first storage address. For example, the memory controller may obtain the compression flag corresponding to the first storage address from a cache or a second storage space. Specifically, reference may be made to the content of S602, which will not be elaborated here.

[0201] S803: The memory controller determines whether the compression flag corresponding to the first storage address is compression flag 1. For example, the memory controller may determine whether the compression flag corresponding to the first storage address is the compression flag corresponding to the first code pattern according to the correspondence between the compression flag and the first code pattern. If the memory controller determines that the compression flag corresponding to the first storage address is the compression flag corresponding to the first code pattern, then S804 is executed; or if the memory controller determines that the compression flag corresponding to the first storage address is not the compression flag corresponding to the first code pattern, then S805 is executed.

[0202] For simplicity, in this embodiment, the compression flag corresponding to the first code pattern is denoted as compression flag 1, the compression flag used to indicate that the data stored in the first storage space is compressed data is denoted as compression flag 2, and the compression flag used to indicate that the data stored in the first storage space is not compressed data is denoted as compression flag 3 for illustration. Correspondingly, compression flag 1 can be used to generate the first data.

[0203] S804: The memory controller generates the first data according to compression flag 1.

[0204] The specific implementation processes of the above S803 and S804 can refer to Figure 7 the description in the illustrated embodiment and will not be elaborated here.

[0205] S805: The memory controller determines whether the data stored in the first storage space is compressed data. Exemplarily, the memory controller may determine whether the data stored in the first storage space is compressed data according to the compression flag corresponding to the first storage address. For example, if the compression flag corresponding to the first storage address is compression flag 2, the memory controller may determine that the data stored in the first storage space is compressed data, that is, the first storage space stores the second data. Another example is that if the compression flag corresponding to the first storage address is compression flag 3, the memory controller may determine that the data stored in the first storage space is not compressed data, that is, the first storage space stores the first data. If the memory controller determines that the data stored in the first storage space is compressed data, then the content of S806 is executed; or if the memory controller determines that the data stored in the first storage space is not compressed data, then the content of S808 is executed.

[0206] S806: The memory controller sends a third read command to the memory according to the compression flag 2. The third read command can be used to read second data from the first storage space or the memory. The second data is the data obtained by compressing the first data. The amount of the second data is smaller than that of the first data. The compression flag 2 can be used to indicate that the data stored in the first storage space is compressed data.

[0207] S807: The memory controller decompresses the second data to obtain the first data.

[0208] S808: The memory controller sends a fifth read command to the memory according to the compression flag 3. The fifth read command can be used to read the first data from the first storage space or the memory. The compression flag 3 can be used to indicate that the data stored in the first storage space is not compressed data.

[0209] The specific implementation processes of the above S805 to S808 can refer to Figure 6 the description in the illustrated embodiment and will not be elaborated here.

[0210] It should be noted that Figure 8 the execution order of the illustrated steps is taken as an example and is not limited thereto. For example, the memory controller may first determine whether the compression flag corresponding to the first storage address is the compression flag 1, and then determine whether the data stored in the first storage space is compressed data; or the memory controller may also determine simultaneously whether the compression flag corresponding to the first storage address is the compression flag 1 and whether the data stored in the first storage space is compressed data, without limitation.

[0211] In one implementation manner, Figure 2 the illustrated embodiment and Figure 6 the illustrated embodiment can be implemented separately or in combination. For example, after S204, the memory controller may further receive a second read command, obtain the compression flag corresponding to the first storage address, and according to the compression flag, send a third read command to the memory. Another example is that before S601, the memory controller may further receive a first write command, compress the first data to obtain the second data, send a second write command to the memory, and generate the compression flag corresponding to the first storage address. The specific implementation process can refer to Figure 2 and Figure 6 the relevant content and will not be elaborated here.

[0212] In one implementation manner, Figure 4 the illustrated embodiment and Figure 7The illustrated embodiments can be implemented separately or in combination. For example, after S403 or S404, the memory controller can also receive a second read command, determine that the compression identifier corresponding to the first storage address is the compression identifier corresponding to the first code pattern, and generate first data according to the compression identifier. For another example, before S701, the memory controller can also receive a first write command, determine that the code pattern of the first data is the first code pattern, determine not to store the first data in the memory according to the code pattern of the first data, and generate a compression identifier corresponding to the first storage address, where the compression identifier is the compression identifier corresponding to the first code pattern. The specific implementation process can refer to Figure 4 and Figure 7 for relevant content, which will not be elaborated here.

[0213] It can be understood that Figure 5 the illustrated embodiments can also be implemented in combination with any of the embodiments illustrated in Figures 6 to 8 . Similarly, Figure 8 the illustrated embodiments can also be implemented in combination with any of the embodiments illustrated in Figure 2 or Figure 4 . The specific implementation process can refer to the foregoing content and will not be elaborated here.

[0214] In the embodiments provided in this application, the method provided in the embodiments of this application is introduced from the perspective of the memory controller. Among them, the steps executed by the memory controller can be implemented by different functional entities that make up the memory controller. The memory controller can include a hardware structure and / or software module, and implement the above various functions in the form of a hardware structure, a software module, or a combination of a hardware structure and a software module. Whether a certain function among the above various functions is executed in the form of a hardware structure, a software module, or a combination of a hardware structure and a software module depends on the specific application and design constraints of the technical solution.

[0215] Next, the data processing device used to implement the above method in the embodiments of this application will be introduced in conjunction with the accompanying drawings. Therefore, the content in the foregoing can be used in subsequent embodiments, and the repeated content will not be elaborated.

[0216] Figure 9 The structural schematic diagram of a data processing device 900 is exemplarily shown. The data processing device 900 can implement the functions or steps implemented by the memory controller in the above various method embodiments.

[0217] In one implementation, the data processing device 900 may include a processing module 901 and a transceiver module 902. Among them, the processing module 901 may be used for data processing, such as performing the steps executed by the memory controller in any of the above method embodiments. The transceiver module 902 may be used to implement corresponding communication functions, such as receiving or sending relevant data, commands or messages. The transceiver module 902 may also be referred to as a communication interface, or a communication module, or a transceiver unit, etc.

[0218] It should be noted that the data processing device 900 may include the processing module 901 but not the transceiver module 902. Or, the data processing device 900 may include the transceiver module 902 but not the processing module 901. Specifically, it depends on whether the above scheme executed by the data processing device 900 includes processing actions and transceiver actions.

[0219] Optionally, the data processing device 900 may further include a storage module, Figure 9 not shown in the figure. The storage module may be used to store instructions and / or data. The processing module 901 may read the instructions and / or data in the storage module so that the data processing device 900 implements the foregoing method embodiments. Optionally, the storage module may also be used to store compression identifiers.

[0220] Optionally, the transceiver module 902 may include a sending module and a receiving module. The sending module is used to perform the sending operation in the above method embodiments. The receiving module is used to perform the receiving operation in the above method embodiments.

[0221] It should be noted that the data processing device 900 may include the sending module but not the receiving module. Or, the data processing device 900 may include the receiving module but not the sending module. Specifically, it depends on whether the above scheme executed by the data processing device 900 includes sending actions and receiving actions.

[0222] Exemplarily, the data processing device 900 may implement the functions or steps implemented by the memory controller in any of the above method embodiments. The data processing device 900 may be a memory controller or may also be a component configured in the memory controller. The processing module 901 is used to perform the processing-related operations of the memory controller in the above method embodiments. The transceiver module 902 is used to perform the transceiver-related operations of the memory controller in the above method embodiments.

[0223] In one implementation, the data processing device 900 may be used to perform the above Figure 2 or Figure 5 actions executed by the memory controller in the shown embodiments. Specifically, reference may be made to the above Figure 2 or Figure 5The relevant introductions in the embodiments shown are not elaborated here. For example, the data processing device 900 may execute the following solution: The transceiver module 902 may be configured to receive a first write command for writing first data into a first storage space indicated by a first storage address, where the first storage space belongs to the memory; the processing module 901 may be configured to compress the first data to obtain second data, and the data volume of the second data is smaller than that of the first data; the transceiver module 902 is further configured to send a second write command to the memory, where the second write command is used to write the second data into the first storage space; the processing module 901 is further configured to generate a compression identifier corresponding to the first storage address, where the compression identifier is used to indicate that the data stored in the first storage space is compressed data.

[0224] In one implementation, the data processing device 900 may be used to execute the above Figure 4 or Figure 5 the actions performed by the memory controller in the embodiments shown. Specifically, reference may be made to the relevant introductions in the above Figure 4 or Figure 5 The relevant introductions in the embodiments shown are not elaborated here. For example, the data processing device 900 may execute the following solution: The transceiver module 902 may be configured to receive a first write command for writing first data into a first storage space indicated by a first storage address, where the first storage space belongs to the memory; the processing module 901 may be configured to determine that the code pattern of the first data is a first code pattern; determine not to store the first data in the memory according to the code pattern of the first data, and generate a compression identifier corresponding to the first storage address, where the compression identifier is the compression identifier corresponding to the first code pattern, and the compression identifier corresponding to the first code pattern may be used to generate the first data.

[0225] In one implementation, the data processing device 900 may be used to execute the above Figure 6 or the actions performed by the memory controller in the embodiment shown in 8. Specifically, reference may be made to the relevant introductions in the above Figure 6 or Figure 8 The relevant introductions in the embodiments shown are not elaborated here. For example, the data processing device 900 may execute the following solution: The transceiver module 902 may be configured to receive a second read command for reading first data from a first storage space indicated by a first storage address, where the first storage space belongs to the memory; the processing module 901 may be configured to obtain a compression identifier corresponding to the first storage address, where the compression identifier is used to indicate that the data stored in the first storage space is compressed data; the transceiver module 902 is further configured to send a third read command to the memory according to the compression identifier, where the third read command is used to read second data from the first storage space, and the second data is the compressed first data, and the data volume of the second data is smaller than that of the first data.

[0226] In one embodiment, the data processing device 900 can be used to execute the actions performed by the memory controller in the above Figure 7 or Figure 8 illustrated embodiments. Specifically, reference can be made to the relevant descriptions in the above Figure 7 or Figure 8 illustrated embodiments, which will not be elaborated here. For example, the data processing device 900 can execute the following solution: a transceiver module 902, which can be used to receive a second read command for reading first data from a first storage space indicated by a first storage address, where the first storage space belongs to the memory; a processing module 901, which can be used to determine that the compression identifier corresponding to the first storage address is the compression identifier corresponding to a first code pattern, where the compression identifier corresponding to the first code pattern is used to generate the first data, and generate the first data according to the compression identifier.

[0227] It should be understood that a more detailed description of each module performing the corresponding process can be directly obtained by referring to the relevant descriptions in any of the Figures 2 to 8 illustrated method embodiments. For the sake of brevity, it will not be elaborated here.

[0228] In the above embodiments, the processing module 901 can be implemented by at least one processor or processor-related circuit. The transceiver module 902 can be implemented by a transceiver or transceiver-related circuit. The storage module can be implemented by at least one memory.

[0229] As Figure 10 illustrated, an embodiment of the present application provides a schematic structural diagram of a data processing device 1000. The data processing device 1000 can include a processor 1020, which is used to implement or support the data processing device 1000 in implementing the functions of the memory controller in any method embodiment of the present application. Specifically, reference can be made to the detailed descriptions in the foregoing method embodiments, which will not be elaborated here. For example, the processor 1020 is used to read and execute program instructions through a communication interface, so that the data processing device 1000 implements the corresponding method. The processor 1020 can include one or more processors, without limitation.

[0230] Specifically, the data processing device 1000 can be a memory controller or a functional module located in the memory controller, and can implement the functions of the memory controller in any method embodiment of the present application.

[0231] It should be noted that the above-mentioned functional modules can be implemented by hardware, or can be implemented by a combination of hardware and software, without limitation. And when the data processing device 1000 only includes the processor 1020, the data processing device 1000 can be a chip, or can also be a chip system.

[0232] For example, the data processing device 1000 can be a chip system. Among them, the chip system can be composed of chips, or can include chips and other discrete devices, without limitation.

[0233] Optionally, the data processing device 1000 may further include a memory 1030 for storing program instructions and / or data. The memory 1030 is coupled to the processor 1020. Among them, the coupling can be understood as an indirect coupling or communication connection between devices, units or modules, which can be electrical, mechanical or other forms for information interaction between devices, units or modules. The processor 1020 may cooperate with the memory 1030. The processor 1020 and the memory 1030 may be integrated together or may be separately provided.

[0234] Further, the processor 1020 is configured to execute the program instructions stored in the memory 1030 so that the data processing device 1000 implements the corresponding method.

[0235] Among them, one or more memories in the memory 1030 may be included in the processor, or the memory 1030 may exist independently, such as an off-chip memory, and is connected to the processor 1020 through a communication bus ( Figure 10 represented by the thick line 1040). The memory 1030 and the processor 1020 may also be integrated together.

[0236] Optionally, the data processing device 1000 further includes a communication interface 1010 ( Figure 10 represented by a dotted line) for communicating with other devices through a transmission medium, so that the devices in the data processing device 1000 can communicate with other devices (such as a memory). The processor 1020 may use the communication interface 1010 to receive and transmit data, commands, etc. For example, the processor 1020 may be configured to control the communication interface 1010 to receive and / or transmit data.

[0237] Among them, the communication interface 1010 may specifically be a transceiver. In terms of hardware implementation, the transceiver may be used to implement the functions of the above-mentioned transceiver module 902, and the transceiver is integrated in the data processing device 1000 to form the communication interface 1010.

[0238] It should be noted that the communication interface 1010 may have a sending function and a receiving function, and can implement data reception and transmission; or it may have a sending function and no receiving function for data sending; or, it may also have a receiving function and no sending function for data reception.

[0239] It should be noted that in the embodiments of the present application, the specific connection medium between the communication interface 1010, the processor 1020, and the memory 1030 is not limited. Figure 10In the middle, the memory 1030, the processor 1020, and the communication interface 1010 are connected through the communication bus 1040. The connection manners between other components are only for illustrative purposes and are not limited thereto. The communication bus 1040 can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, Figure 10 only a thick line is used to represent it in the middle, but it does not mean that there is only one communication bus or one type of communication bus.

[0240] In the embodiments of the present application, the processor 1020 can be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor, etc. The method disclosed in combination with the embodiments of the present application can be completed by the hardware in the processor, or completed by the combination of the hardware and software in the processor.

[0241] In the embodiments of the present application, the memory 1030 can be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), etc., and can also be a volatile memory, such as a random-access memory (RAM). The memory can also be any other medium that is used to carry or store program code in the form of instructions or data structures and can be accessed by a computer; or, it is a circuit or any other device capable of implementing a storage function for storing program instructions and / or data.

[0242] Based on the same concept, refer to Figure 11 , the embodiments of the present application further provide another data processing device 1100, including: an input / output interface 1110 and a logic circuit 1120; the input / output interface 1110 is used to receive code instructions and transmit them to the logic circuit 1120; the logic circuit 1120 is used to run the code instructions to execute the method executed by the memory controller in any of the above embodiments.

[0243] In an optional implementation manner, the data processing device 1100 can be applied to a memory controller to execute the method executed by the memory controller, specifically, for example, the method executed by the memory controller in any of the embodiments shown in the foregoing Figures 2 to 8 in any of the embodiments.

[0244] For example, the data processing device 1100 can receive a first write command for writing first data into a first storage space indicated by a first storage address. The first storage space belongs to the memory. Compress the first data to obtain second data, where the data volume of the second data is smaller than that of the first data. Send a second write command to the memory, where the second write command is used to write the second data into the first storage space. And generate a compression identifier corresponding to the first storage address, where the compression identifier is used to indicate that the data stored in the first storage space is compressed data.

[0245] For another example, the data processing device 1100 can receive a first write command for writing first data into a first storage space indicated by a first storage address. The first storage space belongs to the memory. Determine that the code pattern of the first data is a first code pattern. Determine not to store the first data in the memory according to the code pattern of the first data, and generate a compression identifier corresponding to the first storage address, where the compression identifier is the compression identifier corresponding to the first code pattern. Here, the compression identifier corresponding to the first code pattern can be used to generate the first data.

[0246] For another example, the data processing device 1100 can receive a second read command for reading first data from a first storage space indicated by a first storage address. The first storage space belongs to the memory. Obtain a compression identifier corresponding to the first storage address, where the compression identifier is used to indicate that the data stored in the first storage space is compressed data. And according to the compression identifier, send a third read command to the memory, where the third read command is used to read second data from the first storage space. The second data is the compressed first data, and the data volume of the second data is smaller than that of the first data.

[0247] For yet another example, the data processing device 1100 can receive a second read command for reading first data from a first storage space indicated by a first storage address. The first storage space belongs to the memory. Determine that the compression identifier corresponding to the first storage address is the compression identifier corresponding to the first code pattern, where the compression identifier corresponding to the first code pattern is used to generate the first data, and generate the first data according to the compression identifier.

[0248] Since the data processing device 1100 provided in this embodiment can be applied to a memory controller to complete the methods executed by the above memory controller. Therefore, the technical effects that can be obtained can refer to the above method embodiments and will not be elaborated here.

[0249] An embodiment of the present application also provides a computer-readable storage medium, including program instructions, which when running on a computer, cause the computer to execute the methods or steps in the above various embodiments.

[0250] In an embodiment of the present application, a computer program product is further provided, including program instructions that, when running on a computer, cause the computer to execute the methods or steps in the foregoing various embodiments.

[0251] An embodiment of the present application provides a chip system, which includes a processor for implementing the functions of a memory controller in the foregoing various methods (for example, executing corresponding methods or steps). The chip system may be composed of chips or may include chips and other discrete devices.

[0252] Optionally, the chip system further includes a memory for storing program instructions for the foregoing processor to read and execute to implement corresponding methods.

[0253] It should be understood that in various embodiments of the present application, the magnitudes of the serial numbers of the foregoing processes do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0254] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0255] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be repeated here.

[0256] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in an electrical, mechanical, or other form.

[0257] The unit described as a separation component may or may not be physically separated. The component shown as a unit may or may not be a physical unit, that is, it may be located in one place or may be distributed across multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0258] In addition, each functional unit in various embodiments of the present application may be integrated in a processing unit, may exist physically separately for each unit, or two or more units may be integrated in one unit.

[0259] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the part that essentially contributes to the technical solution of the present application or a part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc that can store program codes.

[0260] The above is only the specific implementation manner of the present application, but the protection scope of the embodiments of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the embodiments of the present application, and all should be covered by the protection scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application should be subject to the protection scope of the claims.

Claims

1. A data processing method, characterized in that, the method includes: receiving a first write command for writing first data into a first storage space indicated by a first storage address, the first storage space belonging to a memory; compressing the first data to obtain second data, wherein the data volume of the second data is smaller than that of the first data; sending a second write command to the memory and generating a compression identifier corresponding to the first storage address, wherein the second write command is used to write the second data into the first storage space, and the compression identifier is used to indicate that the data stored in the first storage space is compressed data.

2. The method according to claim 1, characterized in that, generating a compression identifier corresponding to the first storage address includes: determining that the compression identifier is stored in a cache according to the first storage address; updating the compression identifier in the cache.

3. The method according to claim 1, characterized in that, generating a compression identifier corresponding to the first storage address includes: determining that the compression identifier is not stored in the cache according to the first storage address; sending a first read command for reading the compression identifier from the memory into the cache; updating the compression identifier in the cache.

4. The method according to claim 1, characterized in that, generating a compression identifier corresponding to the first storage address includes: determining that the compression identifier is stored in a second storage space, the second storage space belonging to the memory, according to the first storage address; updating the compression identifier in the second storage space.

5. The method according to any one of claims 1, 3, and 4, characterized in that, the compression identifier is stored in a second storage space in the memory, and the second storage space and the first storage space belong to different memory banks in the memory.

6. The method according to any one of claims 1, 3, and 4, characterized in that, the compression identifier is stored in a static random access memory (SRAM) in the memory.

7. The method according to any one of claims 1 to 6, characterized in that, the method further includes: storing the compression identifier into the cache.

8. The method according to any one of claims 1 to 7, characterized in that, the method further includes: determining that the code pattern of the first data is not a first code pattern, the first code pattern being used to make it unnecessary to store the first data in the memory, and the compression identifier corresponding to the first code pattern being used to generate the first data.

9. The method according to claim 8, characterized in that, the first code pattern is all 0, or the first code pattern is all 1, or the first code pattern is a preset code pattern.

10. A data processing method, characterized in that, the method includes: receiving a second read command for reading first data from a first storage space indicated by a first storage address, the first storage space belonging to a memory; Obtain the compression identifier corresponding to the first storage address, where the compression identifier is used to indicate that the data stored in the first storage space is compressed data; According to the compression identifier, send a third read command to the memory, where the third read command is used to read second data from the first storage space, and the second data is the compressed first data, and the data volume of the second data is smaller than the data volume of the first data.

11. The method according to claim 10, wherein, the obtaining the compression identifier corresponding to the first storage address includes: Determine that the compression identifier is stored in the cache according to the first storage address; Obtain the compression identifier from the cache.

12. The method according to claim 10, wherein, the obtaining the compression identifier corresponding to the first storage address includes: Determine that the compression identifier is not stored in the cache according to the first storage address; Send a fourth read command, where the fourth read command is used to read the compression identifier from the memory into the cache; Obtain the compression identifier from the cache.

13. The method according to claim 10, wherein, the obtaining the compression identifier corresponding to the first storage address includes: Determine that the compression identifier is stored in a second storage space according to the first storage address, and the second storage space belongs to the memory; Obtain the compression identifier from the second storage space.

14. The method according to any one of claims 10, 12, and 13, wherein, the compression identifier is stored in a second storage space in the memory, and the second storage space and the first storage space belong to different banks in the memory.

15. The method according to any one of claims 10, 12, and 13, wherein, the compression identifier is stored in SRAM in the memory.

16. The method according to any one of claims 10 to 15, wherein, the method further includes: Determine that the compression identifier is not the compression identifier corresponding to the first code pattern, and the compression identifier corresponding to the first code pattern is used to generate the first data.

17. The method according to claim 16, wherein, the first code pattern is all 0, or the first code pattern is all 1, or the first code pattern is a preset code pattern.

18. The method according to any one of claims 10 to 17, wherein, the method further includes: Perform decompression processing on the second data to obtain the first data.

19. A data processing device, wherein, It includes a module for executing the method according to any one of claims 1 to 18.

20. A data processing device, wherein, It includes at least one processor, and the at least one processor is used to execute the method according to any one of claims 1 to 18.

21. A data processing device, wherein, It includes at least one processor and a communication interface, and the at least one processor is used to read and execute instructions through the communication interface, so that the data processing device executes the method according to any one of claims 1 to 18.

22. A computer-readable storage medium, characterized in that, it stores a computer program or instructions, and the computer program or instructions are used to implement the method described in any one of claims 1 to 18.

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