Anti-aliasing downsampling circuit, circuit module, chip and signal processing device

Abstract

The present application provides an anti-aliasing downsampling circuit, a circuit module, a chip and a signal processing device, wherein the circuit includes a first multiplication-accumulation module, at least one second multiplication-accumulation module, a third multiplication-accumulation module, a module I counter and latch register; the first input terminals of the first to third multiplication-accumulation modules are connected together, the second input terminal of the first multiplication-accumulation module inputs data 0, the output terminal is connected to the second input terminal of the second multiplication-accumulation module, the output terminal of the second multiplication-accumulation module is connected to the second input terminal of the third multiplication-accumulation module, and the output terminal of the third multiplication-accumulation module is connected to the latch register; module I The counter is connected to the control input of the first to third multiplication and accumulation modules and the latch register, and the first to third multiplication and accumulation modules perform multiplication and accumulation operations; the latch register outputs I The number of the second multiplication and accumulation modules depends on the filter order and the module I modulus of the counter I Sure.

Description

Technical Field

[0001] The present application relates to the field of digital signal processing, and in particular to an anti-aliasing downsampling circuit, circuit module, chip and signal processing device. Background Art

[0002] In the field of digital signal processing, downsampling, a common technique for reducing signal sampling rates, has significant application value. However, direct downsampling can easily cause high-frequency components in the signal spectrum to fold into the low-frequency portion, causing aliasing and severely impacting signal quality. To effectively address this issue, anti-aliasing filters are typically used before downsampling to remove high-frequency components above the Nyquist frequency. Currently, anti-aliasing filters are typically FIR filters. As non-recursive filters, their output depends solely on the input, offering advantages such as linear phase and stability.

[0003] However, existing downsampling technology has certain drawbacks. Implementing the anti-aliasing filter and the downsampling decimation circuit separately in the downsampling circuit generates a large number of redundant operations. These redundant operations not only increase processing complexity but also significantly increase the power consumption of the downsampling circuit. This is detrimental to the energy efficiency and efficient operation of digital signal processing equipment, limiting its application in power-demanding scenarios. Therefore, a new anti-aliasing downsampling circuit is urgently needed to reduce redundant operations. Summary of the Invention

[0004] Based on the above situation, the main purpose of this application is to provide an anti-aliasing downsampling circuit, circuit module, chip and signal processing device to reduce redundant operations.

[0005] To achieve the above objectives, the technical solutions adopted in this application are as follows:

[0006] An anti-aliasing downsampling circuit includes: a first multiplication-accumulation module, at least one second multiplication-accumulation module, a third multiplication-accumulation module, I counter and latch registers;

[0007] The first input terminal of the first multiplication-accumulation module, the first input terminal of the second multiplication-accumulation module, and the first input terminal of the third multiplication-accumulation module are connected together, the second input terminal of the first multiplication-accumulation module inputs data 0, the output terminal of the first multiplication-accumulation module is connected to the second input terminal of the second multiplication-accumulation module, the output terminal of the second multiplication-accumulation module is connected to the second input terminal of the third multiplication-accumulation module, and the output terminal of the third multiplication-accumulation module is connected to the latch register;

[0008] The mold I The counter is connected to the control input end of the first multiplication and accumulation module, the second multiplication and accumulation module, the third multiplication and accumulation module and the latch register.I The value of the count variable of the counter increases as the clock cycle changes. Under the control of the value of the count variable, the first multiplication and accumulation module selects the corresponding filter coefficient and 0 or the accumulation result of the first multiplication and accumulation module, the second multiplication and accumulation module selects the corresponding filter coefficient and the output result of the first multiplication and accumulation module or the accumulation result of the second multiplication and accumulation module, and the third multiplication and accumulation module selects the corresponding filter coefficient and the output result of the second multiplication and accumulation module or the accumulation result of the third multiplication and accumulation module to perform multiplication and accumulation operations;

[0009] According to the value of the count variable, the latch register outputs I Downsampling results;

[0010] The number of the second multiplication-accumulation modules is determined by the filter order and the module I modulus of the counter I Sure.

[0011] As an option, depending on the filter order M and model I modulus of the counter I , set the second multiplication-accumulation module to indivual.

[0012] Optionally, the first input ends of each second multiplication-accumulation module are connected together, the second input end is connected to the output end of the adjacent first multiplication-accumulation module or the output end of the adjacent previous second multiplication-accumulation module, and the output end of each second multiplication-accumulation module is connected to the second input end of the adjacent next second multiplication-accumulation module or the input end of the adjacent third multiplication-accumulation module.

[0013] Optionally, the first multiplication-accumulation module includes a first multiplier, a first adder, a first multiplexer, and a first accumulation register, and the filter coefficients and input data corresponding to the first multiplication-accumulation module are input into the first multiplier for multiplication operation;

[0014] The first multiplexer is in the module I Under the numerical control of the counting variable of the counter, the first adder selects to output 0 or the output result of the first accumulator register, and performs an addition operation on the output result of the first multiplier and the output result selected by the first multiplexer;

[0015] The first accumulation register stores the output result of the first adder, and uses the stored result as the input of the second multiplication-accumulation module, and inputs the stored result into the first adder through the first multiplexer.

[0016] Optionally, the second multiplication-accumulation module includes a second multiplier, a second adder, a second multiplexer, and a second accumulation register, and the filter coefficient and input data corresponding to the second multiplication-accumulation module are input into the second multiplier for multiplication operation;

[0017] The second multiplexer is in the module I Under the numerical control of the counting variable of the counter, the output result of the first accumulator register or the output result of the second accumulator register is selected for output, and the second adder performs an addition operation on the output result of the second multiplier and the output result selected by the second multiplexer;

[0018] The second accumulation register stores the output result of the second adder, and uses the stored result as the input of the third multiplication-accumulation module, and inputs the stored result into the second adder through the second multiplexer.

[0019] Optionally, the third multiplication-accumulation module includes a third multiplier, a third adder, a third multiplexer, and a third accumulation register, and the filter coefficients and input data corresponding to the third multiplication-accumulation module are input into the third multiplier for multiplication operation;

[0020] The third multiplexer is in the module I Under the numerical control of the counting variable of the counter, the output result of the second accumulator register or the output result of the third accumulator register is selected for output, and the third adder performs an addition operation on the output result of the third multiplier and the output result selected by the third multiplexer;

[0021] The third accumulator register stores the output result of the third adder, inputs the stored result into the latch register for latching, and inputs the stored result into the third adder through the third multiplexer.

[0022] As an option, depending on the filter order M and model I modulus of the counter I ,Will M +1 filter coefficient written coefficient tables, each of which has I filter coefficients.

[0023] As an option, when M +1 Not I When the value is an integer multiple of Some filter coefficients in the coefficient table are padded with 0.

[0024] As an option, the value of the count variable ranges from 0 to I -1.

[0025] Optionally, when the value of the counter variable is 0:

[0026] The first multiplexer selects to output 0, the first adder performs an addition operation on 0 and the output result of the first multiplier, and the output result of the first adder is stored in the first accumulator register; the second multiplexer selects to output the output result of the first accumulator register, the second adder performs an addition operation on the output result of the first accumulator register and the output result of the second multiplier, and the output result of the second adder is stored in the second accumulator register; the third multiplexer selects to output the output result of the second accumulator register, the third adder performs an addition operation on the output result of the second accumulator register and the output result of the third multiplier, and the output result of the third adder is stored in the third accumulator register, and the output result of the third accumulator register is input into the latch register for latching.

[0027] As an option, the value of the count variable is 1~ I -1 hour:

[0028] The first multiplexer selects to output the output result of the first accumulator register in the previous clock cycle, the first adder performs an addition operation on the output result of the first accumulator register in the previous clock cycle and the output result of the first multiplier, and the output result of the first adder is stored in the first accumulator register; the second multiplexer selects to output the output result of the second accumulator register in the previous clock cycle, the second adder performs an addition operation on the output result of the second accumulator register in the previous clock cycle and the output result of the second multiplier, and the output result of the second adder is stored in the second accumulator register; the third multiplexer selects to output the output result of the third accumulator register in the previous clock cycle, the third adder performs an addition operation on the output result of the third accumulator register in the previous clock cycle and the output result of the third multiplier, and the output result of the third adder is stored in the third accumulator register, and the output result of the third accumulator register is input into the latch register for latching.

[0029] Optionally, the value of the counter variable is I -1, the third accumulator register stores the result as I The down-sampling result is input into the latch register for latching.

[0030] An embodiment of the present application further provides a circuit module, comprising any of the above-mentioned anti-aliasing downsampling circuits.

[0031] An embodiment of the present application further provides a chip comprising any of the above-mentioned anti-aliasing downsampling circuits.

[0032] An embodiment of the present application also provides a signal processing device, including the above-mentioned circuit module or chip.

[0033] The present application provides a first multiplication-accumulation module, at least one second multiplication-accumulation module, a third multiplication-accumulation module, a module I Counters and latch registers distribute multiplication and addition operations evenly across I In a clock cycle, the multipliers and adders in the first multiplication-accumulation module, the second multiplication-accumulation module and the third multiplication-accumulation module are I Multiplexing eliminates redundant operations, saving significant computation time. Calculations that would normally require multiple clock cycles can be completed in a shorter timeframe, thereby improving the overall computational speed of the circuit system. Redundant operations typically occupy logic resources such as multipliers and adders within a circuit. Eliminating these redundant operations frees up these resources, improving resource utilization. Intermediate results generated by redundant operations typically need to be stored in registers. Eliminating these redundant operations saves storage resources.

[0034] The circuit module provided in the embodiment of the present application has excellent anti-aliasing performance and flexible downsampling capability, while integrating other practical functions to meet the diverse signal processing requirements of different applications.

[0035] The chip provided in the embodiment of the present application integrates the above-mentioned anti-aliasing downsampling circuit, which can prevent spectrum aliasing and ensure the integrity of the sampled signal spectrum; improve signal quality and filter out high-frequency noise interference; reduce sampling rate requirements and reduce hardware costs and power consumption.

[0036] Other beneficial effects of the present application will be explained through the introduction of specific technical features and technical solutions in the specific implementation methods. Through the introduction of these technical features and technical solutions, those skilled in the art should be able to understand the beneficial technical effects brought about by the technical features and technical solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Preferred embodiments of the present application will be described below with reference to the accompanying drawings.

[0038] Figure 1 It is a structural block diagram of the anti-aliasing downsampling module in the prior art;

[0039] Figure 2 for Figure 1 The specific implementation structure block diagram of the anti-aliasing downsampling module;

[0040] Figure 3 This is a structural block diagram of an anti-aliasing downsampling circuit according to a preferred embodiment of the present application.

[0041] In the picture:

[0042] 10. First multiplication and accumulation module; 101. First multiplier; 102. First adder; 103. First multiplexer; 104. First accumulation register;

[0043] 20. Second multiplication and accumulation module; 201. Second multiplier; 202. Second adder; 203. Second multiplexer; 204. Second accumulation register;

[0044] 30. Third multiplication and accumulation module; 301. Third multiplier; 302. Third adder; 303. Third multiplexer; 304. Third accumulation register;

[0045] 40. Model I counter;

[0046] 50. Latch register. DETAILED DESCRIPTION

[0047] The present application is described below based on examples, but the present application is not limited to these examples. In the detailed description of the present application below, some specific details are described in detail. In order to avoid obscuring the essence of the present application, well-known methods, processes, procedures, and components are not described in detail.

[0048] Furthermore, persons of ordinary skill in the art will appreciate that the figures provided herein are for illustration purposes only and are not necessarily drawn to scale.

[0049] Unless the context clearly requires otherwise, throughout the specification and claims, the words "include," "comprising," and similar words should be construed in an inclusive sense rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to."

[0050] In the description of this application, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance. In addition, in the description of this application, unless otherwise specified, "plurality" means two or more.

[0051] In digital signal processing systems, it's sometimes necessary to reduce the signal's sampling rate, known as downsampling. Before downsampling, the digital signal must be filtered using an anti-aliasing filter. This is because downsampling changes the signal's spectrum. If components with frequencies above half the new sampling rate (the Nyquist frequency) are not pre-filtered, aliasing will occur. For example, in video processing, when downsampling a high-frame-rate video to a lower frame rate, the video signal is first processed using a digital anti-aliasing filter to remove high-frequency components before downsampling to prevent aliasing distortion.

[0052] Since FIR (Finite Impulse Response) filters can accurately control the frequency response and achieve good low-pass characteristics by designing appropriate filter coefficients, FIR filters are often used as anti-aliasing filters.

[0053] like Figure 1 As shown, the anti-aliasing downsampling module in the prior art mainly includes an anti-aliasing filter and I The output of the downsampling decimator and the anti-aliasing filter are connected to I The input of the downsampling decimator is connected to I The downsampling decimator is used to output the downsampled result. Assume that the anti-aliasing filter adopts Figure 2 shown M The unit impulse response of the FIR filter is Indicates that the input of the FIR filter is , the output is .

[0054] in, M Unit impulse response of an FIR filter of order Expressed as:

[0055] (1)

[0056] It has the generalized linear phase characteristic condition, namely:

[0057] ,or .

[0058] Output of the FIR filter for:

[0059] (2)

[0060] In formula (2), h ( k ) represents the first kcoefficients, x ( n − k ) represents the input signal x ( n )Delay k signal after a clock cycle.

[0061] I Downsampling decimator every I Output 1 valid result per clock cycle :

[0062] (3)

[0063] In formula (3), x ( rI − k ) represents the input signal x ( n ) at discrete moments rI − k The value of rI represents the current discrete moment, r Indicates the index of the downsampled data.

[0064] from Figure 2 and the output of the FIR filter From the expression, we can see that in the existing anti-aliasing downsampling module based on two discrete modules, the transposed FIR filter and the decimator, when the FIR filter is used to remove the high-frequency components, multiplication and addition operations are required for each sample of the input signal. M +1 multiplier and M Adders. In the order of the filter M Higher, or a multiple of the sampling rate reduction I When the number of samples is large, a large number of operations are generated. In fact, there is a certain degree of redundancy in these operations. For example, for some adjacent samples, their multiplication operations during the filtering process may have some identical coefficients. However, because traditional implementation methods fail to effectively optimize these redundant operations, each sample needs to undergo a complete multiplication operation during the operation. This undoubtedly increases the number of multipliers used and, accordingly, the number of adders.

[0065] The anti-aliasing downsampling circuit provided by this application is implemented based on the circuit structure of a transposed FIR filter. The anti-aliasing downsampling circuit obtained through theoretical analysis and circuit structure design can effectively eliminate redundant operations. By evenly distributing multiplication and addition operations and sharing multipliers and adders, the problem of excessive local computation can be effectively avoided. At the same time, this application reduces the number of multipliers and adders by multiples. This application can effectively solve the redundant computation problem existing in the prior art, significantly reduce power consumption while reducing circuit scale, and effectively improve circuit performance.

[0066] Decompose and transform Equation (3), assuming M +1 for I An integer multiple of (if it is not an integer multiple, this condition can be met by padding the filter coefficients with zeros), that is, M +1= KI , then z ( r ) is calculated as K Step by step I After each step is completed, it will proceed to the next step of data calculation.

[0067] Specifically, formula (3) can be decomposed and transformed into:

[0068]

[0069] Based on the above decomposition and deformation process, the number of multipliers can be obtained from M +1 is reduced to The number of adders can be obtained from M Reduced to indivual.

[0070] Based on the above theoretical analysis, multiplication and addition operations can be evenly distributed in I In one clock cycle, the multiplier and adder are I Multiplexing only requires multipliers and adders, which can be realized M +1 addition of the multiplication results.

[0071] Based on the above theoretical analysis results, the anti-aliasing downsampling circuit provided in the embodiment of the present application can be designed. The anti-aliasing downsampling circuit provided in the embodiment of the present application is described in detail below with reference to the accompanying drawings.

[0072] Figure 3 A schematic diagram of the structure of an anti-aliasing downsampling circuit provided in an embodiment of the present application is shown in FIG. Figure 3As shown, the anti-aliasing downsampling circuit includes: a first multiplication-accumulation module 10, at least one second multiplication-accumulation module 20, a third multiplication-accumulation module 30, I Counter 40 and latch register 50.

[0073] Among them, the first input end of the first multiplication and accumulation module 10, the first input end of the second multiplication and accumulation module 20 and the first input end of the third multiplication and accumulation module 30 are connected together, the second input end of the first multiplication and accumulation module 10 inputs data 0, the output end of the first multiplication and accumulation module 10 is connected to the second input end of the second multiplication and accumulation module 20, the output end of the second multiplication and accumulation module 20 is connected to the second input end of the third multiplication and accumulation module 30, and the output end of the third multiplication and accumulation module 30 is connected to the latch register 50.

[0074] mold I The counter 40 is connected to the control input terminals of the first multiplication and accumulation module 10, the second multiplication and accumulation module 20, the third multiplication and accumulation module 30 and the latch register 50. I The value of the counting variable of the counter 40 increases with the change of the clock cycle. Under the control of the value of the counting variable, the first multiplication and accumulation module 10 selects the corresponding filter coefficient and 0 or the accumulation result of the first multiplication and accumulation module 10, the second multiplication and accumulation module 20 selects the corresponding filter coefficient and the output result of the first multiplication and accumulation module 10 or the accumulation result of the second multiplication and accumulation module 20, and the third multiplication and accumulation module 30 selects the corresponding filter coefficient and the output result of the second multiplication and accumulation module 20 or the accumulation result of the third multiplication and accumulation module 30 to perform multiplication and accumulation operations.

[0075] According to the value of the count variable, the latch register 50 outputs I Downsampling results.

[0076] The number of the second multiplication-accumulation modules 20 is determined by the filter order and the module I Modulus value of counter 40 I Sure.

[0077] It should be noted that the digital signal data to be processed can be input into the first multiplication and accumulation module 10, the second multiplication and accumulation module 20 and the third multiplication and accumulation module 30 through the first input end of the first multiplication and accumulation module 10, the first input end of the second multiplication and accumulation module 20 and the first input end of the third multiplication and accumulation module 30 for parallel multiplication and accumulation operations.

[0078] According to the model IThe value of the count variable of counter 40 selects the filter coefficients from the preset coefficient table corresponding to each multiplication and accumulation module, and performs a multiplication operation using the input digital signal data and the filter coefficients in the corresponding coefficient table. The coefficient table can be a set of pre-set values, which are determined according to specific computational requirements. A multiplication operation is the multiplication of the input digital signal data with the corresponding filter coefficients in the coefficient table. For example, in digital signal processing, in order to filter or transform a signal, it is necessary to multiply the input signal data with the filter coefficients (stored in the coefficient table) to achieve a specific signal processing function. The result of the multiplication operation is then accumulated.

[0079] In the embodiment of the present application, according to the filter order M and model I Modulus value of counter 40 I , set the second multiplication-accumulation module 20 to indivual.

[0080] For example, when the filter order is 14, the modulus I Modulus value of counter 40 I When the value is 3 (ie, the anti-aliasing downsampling circuit can achieve 3 times downsampling output), a first multiplication-accumulation module 10 , three second multiplication-accumulation modules 20 and one third multiplication-accumulation module 30 may be provided.

[0081] In an embodiment of the present application, the first input ends of each second multiplication-accumulation module 20 are connected together, the second input end is connected to the output end of the adjacent first multiplication-accumulation module 10 or the output end of the adjacent previous second multiplication-accumulation module 20, and the output end of each second multiplication-accumulation module 20 is connected to the second input end of the adjacent next second multiplication-accumulation module 20 or the input end of the adjacent third multiplication-accumulation module 30.

[0082] For example, when there is a first multiplication-accumulation module 10, three second multiplication-accumulation modules 20 and a third multiplication-accumulation module 30, the three second multiplication-accumulation modules 20 are respectively S 21 Module, S 22 Module and S 23 When the module is displayed, S 21 Module, S 22 Module and S 23 The first input terminals of the modules are connected to the first input terminals of the first multiplication-accumulation module 10 and the third multiplication-accumulation module 30. 21 The second input terminal of the module is connected to the output terminal of the first multiplication and accumulation module 10, S 22 The second input terminal of the module is connected to S 21 The output terminal of the module is connected to S 23The second input terminal of the module is connected to S 22 The output terminal of the module is connected to the second input terminal of the third multiplication and accumulation module 30 and S 23 Output connection of the module.

[0083] In the embodiment of the present application, the first multiplication-accumulation module 10 includes a first multiplier 101, a first adder 102, a first multiplexer (MUX) 103, and a first accumulation register 104. The filter coefficients and input data of the first multiplication-accumulation module 10 are input into the first multiplier 101 for multiplication operation.

[0084] The first multiplexer 103 is configured in the module I Under the control of the numerical value of the count variable of the counter 40, the first adder 102 selects to output 0 or the output result of the first accumulator register 104, and performs an addition operation on the output result of the first multiplier 101 and the result selected by the first multiplexer 103;

[0085] The first accumulator register 104 stores the output result of the first adder 102 and uses the stored result as the input of the second multiplication-accumulation module 20 , and inputs the stored result into the first adder 102 through the first multiplexer 103 .

[0086] Specifically, the first multiplier 101 receives the filter coefficient and input data corresponding to the first multiplication and accumulation module 10 as input, and performs a multiplication operation on the two data. The filter coefficient can be a pre-set fixed value used to filter the input data. The input data is a real-time input signal to be processed. The first multiplexer 103 has two inputs, one is a fixed value 0, and the other is the output result of the first accumulation register 104; its output is determined by the module I The counter 40 controls the value of the count variable. When the count variable satisfies a preset condition, it outputs 0; when the preset condition is not met, it outputs the output of the first accumulator register 104. For example, when the value of the count variable is 0, the first multiplexer 103 outputs 0; when the value of the count variable is not 0, the first multiplexer 103 outputs the output of the first accumulator register 104.

[0087] The first adder 102 adds the output of the first multiplier 101 and the output of the first multiplexer 103. If the output of the first multiplexer 103 is 0, the output of the first adder 102 is equal to the output of the first multiplier 101. If the output of the first multiplexer 103 is the output of the first accumulator 104, the output of the first adder 102 is the sum of the multiplication result of the first multiplier 101 and the output of the first accumulator 104.

[0088] The first accumulator register 104 is used to store the output result of the first adder 102. During each clock cycle, the output result of the first adder 102 is written to the first accumulator register 104, replacing the previously stored result. Simultaneously, the first accumulator register 104 uses the stored result as the input of the second multiplication-accumulation module 20 and feeds it back to the first adder 102 via the first multiplexer 103 for the next accumulation operation.

[0089] In the embodiment of the present application, the second multiplication-accumulation module 20 includes a second multiplier 201, a second adder 202, a second multiplexer 203, and a second accumulation register 204. The filter coefficients and input data of the second multiplication-accumulation module 20 are input into the second multiplier 201 for multiplication operation.

[0090] The second multiplexer 203 is configured in the module I Under the control of the numerical value of the count variable of the counter 40, the output result of the first accumulator register 104 or the output result of the second accumulator register 204 is selected for output, and the second adder 202 performs an addition operation on the output result of the second multiplier 201 and the result selected by the second multiplexer 203;

[0091] The second accumulator register 204 stores the output result of the second adder 202 and uses the stored result as the input of the third multiplication-accumulation module 30 , and inputs the stored result into the second adder 202 through the second multiplexer 203 .

[0092] Specifically, the second multiplier 201 receives the filter coefficient and input data corresponding to the second multiplication and accumulation module 20 as input, and performs a multiplication operation on the two data. The filter coefficient can be a pre-set fixed value used to filter the input data. The input data is a real-time input signal to be processed. The second multiplexer 203 has two inputs, one is the output result of the first accumulation register 104, and the other is the output result of the second accumulation register 204; its output is determined by the module IThe counter 40 controls the value of the count variable. When the count variable satisfies a preset condition, the output result of the first accumulator 104 is selected for output; when the preset condition is not satisfied, the output result of the second accumulator 204 is selected for output. For example, when the value of the count variable is 0, the second multiplexer 203 selects to output the output result of the first accumulator 104; when the value of the count variable is not 0, the second multiplexer 203 selects to output the output result of the second accumulator 204.

[0093] The second adder 202 performs an addition operation on the output result of the second multiplier 201 and the result selected by the second multiplexer 203. If the second multiplexer 203 outputs the output result of the first accumulator 104, the output of the second adder 202 is equal to the sum of the output result of the first accumulator 104 and the multiplication result output by the second multiplier 201. If the second multiplexer 203 outputs the output result of the second accumulator 204, the output of the second adder 202 is equal to the sum of the multiplication result output by the second multiplier 201 and the output result of the second accumulator 204.

[0094] The second accumulator register 204 is used to store the output result of the second adder 202. During each clock cycle, the output result of the second adder 202 is written to the second accumulator register 204, replacing the previously stored result. Simultaneously, the second accumulator register 204 uses the stored result as the input of the third multiplication-accumulation module 30 and feeds it back to the second adder 202 via the second multiplexer 203 for the next accumulation operation.

[0095] In the embodiment of the present application, the third multiplication-accumulation module 30 includes a third multiplier 301, a third adder 302, a third multiplexer 303, and a third accumulation register 304. The filter coefficients and input data corresponding to the third multiplication-accumulation module 30 are input into the third multiplier 301 for multiplication operation.

[0096] The third multiplexer 303 is in the module I Under the control of the numerical value of the count variable of the counter 40, the output result of the second accumulator register 204 or the output result of the third accumulator register 304 is selected for output, and the third adder 302 performs an addition operation on the output result of the third multiplier 301 and the result selected by the third multiplexer 303;

[0097] The third accumulator register 304 stores the output result of the third adder 302 , inputs the stored result into the latch register 50 for latching, and inputs the stored result into the third adder 302 through the third multiplexer 303 .

[0098] Specifically, the third multiplier 301 receives the filter coefficient and input data corresponding to the third multiplication and accumulation module 30 as input, and performs a multiplication operation on the two data. The filter coefficient can be a pre-set fixed value used to filter the input data. The input data is a real-time input signal to be processed. The third multiplexer 303 has two inputs, one is the output result of the second accumulation register 204, and the other is the output result of the third accumulation register 304; its output is determined by the module I The counter 40 controls the value of the count variable. When the count variable satisfies a preset condition, the output result of the second accumulator register 204 is selected for output; when the preset condition is not satisfied, the output result of the third accumulator register 304 is selected for output. For example, when the value of the count variable is 0, the third multiplexer 303 selects to output the output result of the second accumulator register 204; when the value of the count variable is not 0, the third multiplexer 303 selects to output the output result of the third accumulator register 304.

[0099] The third adder 302 performs an addition operation on the output result of the third multiplier 301 and the result selected by the third multiplexer 303. If the third multiplexer 303 outputs the output result of the first accumulator register 104, the output of the third adder 302 is equal to the sum of the output result of the second accumulator register 204 and the multiplication result output by the third multiplier 301. If the third multiplexer 303 outputs the output result of the third accumulator register 304, the output of the third adder 302 is equal to the sum of the multiplication result output by the third multiplier 301 and the output result of the third accumulator register 304.

[0100] The third accumulator register 304 is used to store the output result of the third adder 302. During each clock cycle, the output result of the third adder 302 is written into the third accumulator register 304, replacing the previously stored result. Simultaneously, the third accumulator register 304 uses the stored result as the input of the third multiplication-accumulation module 30 and feeds it back to the third adder 302 via the third multiplexer 303 for the next accumulation operation.

[0101] In the embodiment of the present application, according to the filter order M and model I Modulus value of counter 40 I ,Will M +1 filter coefficient written coefficient tables, each of which has I filter coefficients. The filter coefficients in each coefficient table can be I The value of the count variable of the counter 40 is selected.

[0102] It should be noted that when M +1 Not I When the value is an integer multiple of Some filter coefficients in the coefficient table are padded with 0.

[0103] For example, when M is 14, I When is 3, there are 15 filter coefficients, which can be written into 5 coefficient tables, each of which has 3 filter coefficients, and each coefficient table corresponds to a multiplication and accumulation module. M is 13, I When is 3, there are 14 filter coefficients, which can be written into 5 coefficient tables. The first to fourth coefficient tables each contain 3 filter coefficients, and the fifth coefficient table contains 2 filter coefficients. The other filter coefficient in the fifth coefficient table can be padded with 0.

[0104] In the embodiment of the present application, the range of the value of the counting variable is 0~ I -1, that is, the value of the counting variable can be 0, 1, 2, 3, ..., I -1. When I When is 3, the value of the count variable can be 0, 1, or 2. Each value of the count variable corresponds to a corresponding filter coefficient.

[0105] In the above embodiment, when the value of the count variable is 0:

[0106] The first multiplexer 103 selects to output 0, the first adder 102 adds 0 to the output result of the first multiplier 101, and the output result of the first adder 102 is stored in the first accumulator register 104; the second multiplexer 203 selects to output the output result of the first accumulator register 104, the second adder 202 adds the output result of the first accumulator register 104 and the output result of the second multiplier 201, and the output result of the second adder 202 is stored in the second accumulator register 204; the third multiplexer 303 selects to output the output result of the second accumulator register 204, the third adder 302 adds the output result of the second accumulator register 204 and the output result of the third multiplier 301, and the output result of the third adder 302 is stored in the third accumulator register 304, and the output result of the third accumulator register 304 is input into the latch register 50 for latching.

[0107] In the above embodiment, when the value of the counting variable is 1~ I -1 hour:

[0108] The first multiplexer 103 selects to output the output result of the first accumulator register 104 in the previous clock cycle, the first adder 102 adds the output result of the first accumulator register 104 in the previous clock cycle and the output result of the first multiplier 101, and the output result of the first adder 102 is stored in the first accumulator register 104; the second multiplexer 203 selects to output the output result of the second accumulator register 204 in the previous clock cycle, the second adder 202 adds the output result of the second accumulator register 204 in the previous clock cycle and the output result of the second multiplier 101. The output results of the adder 201 are added, and the output result of the second adder 202 is stored in the second accumulator register 204; the third multiplexer 303 selects to output the output result of the third accumulator register 304 in the previous clock cycle, and the third adder 302 adds the output result of the third accumulator register 304 in the previous clock cycle and the output result of the third multiplier 301, and the output result of the third adder 302 is stored in the third accumulator register 304, and the output result of the third accumulator register 304 is input into the latch register 50 for latching.

[0109] In the above embodiment, when the value of the counting variable is I -1, the result stored in the third accumulator register 304 (ie, the output result of the third accumulator register 304 in the previous clock cycle) is used as I The down-sampling result is input into the latch register 50 for latching. I Under the numerical control of the counting variable of the counter 40, the latch register 50 outputs the corresponding clock cycle. I The result of downsampling. When the value of the count variable is 0~ I When the latch value of the latch register 50 is -2, the latch value remains unchanged and the output also remains unchanged.

[0110] It is understandable that in actual circuits, I -1 clock cycle calculation result, on the rising edge of the clock when the value of the count variable is 0, I The down-sampling result is latched by the latch register 50 and output.

[0111] When the next clock cycle arrives, the value of the count variable is I -1 becomes 0 again.

[0112] Assume that the anti-aliasing downsampling circuit provided in the embodiment of the present application is n Clock cycle output , one data is input per clock cycle, and M +1 Yes I An integer multiple of M +1= KIAmong them, there is a first multiplication and accumulation module, K -2 second multiplication and accumulation modules, one third multiplication and accumulation module. The output results of the anti-aliasing downsampling circuit at each clock cycle are described below.

[0113] No. clock cycles to Clock cycle calculation ,point I The calculation is completed in clock cycles:

[0114] (4)

[0115] According to the order of data input, I Calculate the clock cycles separately of I Multiplications and accumulations:

[0116] The product is calculated in the 0th clock cycle , the first multiplexer 103 selects output 0, and the addition result of the first adder 102 is stored in the accumulator register In the first calculation, the product is directly multiplied Stored in the accumulator register middle:

[0117] ,

[0118] ;

[0119] The first clock cycle calculates the product , the first multiplexer 103 selects the output accumulation register The addition result of the first adder 102 is stored in the accumulator register middle:

[0120] ,

[0121] ;

[0122] …

[0123] No. I -1 clock cycle to calculate the product , the first multiplexer 103 selects the output accumulation register The addition result of the first adder 102 is stored in the accumulator register In, get :

[0124] ,

[0125] ;

[0126] No. clock cycles to Clock cycle calculation ,point I The calculation is completed in clock cycles:

[0127] (5)

[0128] According to the order of data input, I Calculate the clock cycles separately of I Multiplications and accumulation into the accumulator register :

[0129] The product is calculated in the 0th clock cycle , the second multiplexer 203 selects the output accumulation register The value of the accumulation register The output result is completed I Multiplication and accumulation The addition result of the second adder 202 is stored in the accumulator register middle:

[0130] ,

[0131] ;

[0132] The first clock cycle calculates the product , the second multiplexer 203 selects the output accumulation register The addition result of the second adder 202 is stored in the accumulator register middle:

[0133] ,

[0134] ;

[0135] …

[0136] No. I -1 clock cycle to calculate the product , the second multiplexer 203 selects the output accumulation register The addition result of the second adder 202 is stored in the accumulator register In, get :

[0137] ,

[0138] ;

[0139] …

[0140] No. clock cycles to n Clock cycle calculation ,point I The calculation is completed in clock cycles and the final result is output :

[0141] (6)

[0142] According to the order of data input, I Calculate the clock cycles separately of I Multiplications and accumulation into the accumulator register :

[0143] The product is calculated in the 0th clock cycle , No. K - 1 multiplexer to select the output accumulation register The value of the accumulation register The value is completed I Multiplication and accumulation , the addition result is stored in the accumulator register middle:

[0144] ,

[0145] ;

[0146] The first clock cycle calculates the product , No. K - 1 multiplexer to select the output accumulation register The result of the addition is stored in the accumulator register. middle:

[0147] ,

[0148] ;

[0149] …

[0150] No. I -1 clock cycle to calculate the product , No. K Multiplexer selects the output accumulation register The result of the addition is stored in the accumulator register. ,get :

[0151] ,

[0152] .

[0153] Every I Input data, the calculation is transferred to the next multiplication and accumulation module to continue the operation. Each multiplication and accumulation module includes an independent multiplier, adder, accumulation register and coefficient table. Step operation to get the final result And output 1 downsampling result.

[0154] It should be noted that Figure 3 It is a pipeline-like structure based on the attached Figure 3 The above During the calculation process, The outputs before and after are also being calculated, e.g. of hour, of is also being calculated and stored in the accumulator register middle.

[0155] The following example takes the filter order as 14 and the need to achieve 3 times downsampling output (i.e. M is 14, I 3), the structure and working principle of the anti-aliasing downsampling circuit provided in the embodiment of the present application are described.

[0156] One first multiplication-accumulator module, three second multiplication-accumulator modules, and one third multiplication-accumulator module are provided. 15 filter coefficients are written into five coefficient tables, each of which contains three filter coefficients.

[0157] mold I The counter 40 is a modulo 3 counter, and the values ​​of its counting variable are 0, 1 and 2. When the value of the counting variable is 0, the corresponding filter coefficients in each coefficient table are h (14) h (11) h (8) h (5) and h (2). When the value of the count variable is 1, the corresponding filter coefficients in each coefficient table are h (13) h (10) h (7) h (4) and h (1). When the value of the counting variable is 2, the corresponding filter coefficients in each coefficient table are h (12)h (9) h (6) h (3) and h (0). The corresponding filter coefficients in different coefficient tables can be selected according to the value of the count variable.

[0158] Assume that the output is at the 15th clock cycle ,but The calculation content in each clock cycle is broken down as follows:

[0159] Calculation from the 1st clock cycle to the 3rd clock cycle , calculated in 3 clock cycles:

[0160] .

[0161] According to the data input order, the three clock cycles are calculated separately 3 multiplications and accumulation together:

[0162] The product is calculated in the 0th clock cycle , the first multiplexer 103 selects output 0, and the addition result of the first adder 102 is stored in the accumulator register In the first calculation, the product is directly multiplied Stored in the accumulator register middle:

[0163] ,

[0164] ;

[0165] The first clock cycle calculates the product , the first multiplexer 103 selects the output accumulation register The addition result of the first adder 102 is stored in the accumulator register middle:

[0166] ,

[0167] ;

[0168] The second clock cycle calculates the product , the first multiplexer 103 selects the output accumulation register The addition result of the first adder 102 is stored in the accumulator register In, get :

[0169] ,

[0170] .

[0171] Calculation from the 4th to the 6th clock cycle , calculated in 3 clock cycles:

[0172] .

[0173] According to the data input order, the three clock cycles are calculated separately 3 multiplications and accumulation into the accumulator register :

[0174] The product is calculated in the 0th clock cycle , the second multiplexer 203 selects the output accumulation register The value of the accumulation register The output result is that 3 multiplications and accumulations have been completed. The addition result of the second adder 202 is stored in the accumulator register middle:

[0175] ,

[0176] ;

[0177] The first clock cycle calculates the product , the second multiplexer 203 selects the output accumulation register The addition result of the second adder 202 is stored in the accumulator register middle:

[0178] ,

[0179] ;

[0180] The second clock cycle calculates the product , the second multiplexer 203 selects the output accumulation register The addition result of the second adder 202 is stored in the accumulator register In, get :

[0181] ,

[0182] .

[0183] Calculation from the 7th clock cycle to the 9th clock cycle , calculated in 3 clock cycles:

[0184] .

[0185] According to the data input order, the three clock cycles are calculated separately 3 multiplications and accumulation into the accumulator register :

[0186] The product is calculated in the 0th clock cycle , the third multiplexer selects the output accumulation register The value of the accumulation register The value of has completed 3 multiplications and accumulations , the addition result is stored in the accumulator register middle:

[0187] ,

[0188] ;

[0189] The first clock cycle calculates the product , the third multiplexer selects the output accumulation register The result of the addition is stored in the accumulator register. middle:

[0190] ,

[0191] ;

[0192] The second clock cycle calculates the product , the third multiplexer selects the output accumulation register The result of the addition is stored in the accumulator register. ,get :

[0193] ,

[0194] .

[0195] Calculation from the 10th clock cycle to the 12th clock cycle , calculated in 3 clock cycles:

[0196] .

[0197] According to the data input order, the three clock cycles are calculated separately 3 multiplications and accumulation into the accumulator register :

[0198] The product is calculated in the 0th clock cycle , the 4th multiplexer selects the output accumulation register The value of the accumulation register The value of has completed 3 multiplications and accumulations , the addition result is stored in the accumulator register middle:

[0199] ,

[0200] ;

[0201] The first clock cycle calculates the product , the 4th multiplexer selects the output accumulation register The result of the addition is stored in the accumulator register. middle:

[0202] ,

[0203] ;

[0204] The second clock cycle calculates the product , the 4th multiplexer selects the output accumulation register The result of the addition is stored in the accumulator register. ,get :

[0205] ,

[0206] .

[0207] Calculation from the 13th clock cycle to the 15th clock cycle , the calculation is completed in 3 clock cycles and the final result is output :

[0208] .

[0209] According to the data input order, the three clock cycles are calculated separately 3 multiplications and accumulation into the accumulator register :

[0210] The product is calculated in the 0th clock cycle , the 5th multiplexer selects the output accumulation register The value of the accumulation register The value of has completed 3 multiplications and accumulations , the addition result is stored in the accumulator register middle:

[0211] ,

[0212] ;

[0213] The first clock cycle calculates the product , the 5th multiplexer selects the output accumulation register The result of the addition is stored in the accumulator register. middle:

[0214] ,

[0215] ;

[0216] The second clock cycle calculates the product , the 5th multiplexer selects the output accumulation register The result of the addition is stored in the accumulator register. ,get :

[0217] ,

[0218] .

[0219] Assuming that the 15 filter coefficients are as shown in Table 1, the coefficients in the 5 coefficient tables are as shown in Table 2.

[0220] Table 1 Filter coefficients

[0221]

[0222] Table 2 Coefficient table

[0223]

[0224] When input When the theoretical anti-aliasing filter output , the anti-aliasing downsampling circuit output As shown in Table 3. Compared with the anti-aliasing downsampling module in the prior art, the output end of the anti-aliasing downsampling circuit provided by the embodiment of the present application has an additional latch register 50, so Output later than One clock cycle.

[0225] Table 3 Anti-aliasing downsampling circuit output table

[0226]

[0227] The present application also provides a circuit module including the aforementioned anti-aliasing downsampling circuit. This circuit module integrates the anti-aliasing downsampling circuit provided in the present application. This circuit module can be expanded and optimized to provide efficient and reliable signal preprocessing solutions for a variety of digital signal processing scenarios. This circuit module offers excellent anti-aliasing performance and flexible downsampling capabilities, while also integrating other practical functions to meet the diverse signal processing requirements of different applications.

[0228] For example, in the field of audio processing, in audio recording, playback, and editing devices, the circuit module provided by the embodiments of the present application can be used to downsample high-sampling-rate audio signals while effectively suppressing ambient noise and noise generated by the device itself, ensuring high-quality audio signal output. Specifically, in a portable audio player, this circuit module can downsample high-sampling-rate audio files to a sampling rate suitable for device processing, while optimizing the quality of the audio signal and enhancing the user's listening experience.

[0229] In wireless and wired communication systems, the circuit modules provided by the embodiments of the present application can be used to preprocess received signals. Through functions such as anti-aliasing downsampling and noise suppression, signal reliability and transmission efficiency are improved, and bit error rates are reduced. Furthermore, the signal format conversion function enables compatibility with different communication protocols and devices, meeting the diverse needs of communication systems.

[0230] In industrial automation and sensor signal processing, the circuit module provided in the embodiment of the present application can perform operations such as anti-aliasing downsampling, gain adjustment, and noise suppression on sensor signals, converting the original signals into a format suitable for processing by industrial control systems, and providing reliable data support for monitoring and control of production processes.

[0231] In medical devices such as electrocardiographs and electroencephalographs, the circuit module provided in the embodiments of the present application can effectively remove noise interference in physiological signals, downsample the signals to reduce the amount of data, and at the same time ensure the integrity and accuracy of the signals, providing a reliable basis for medical diagnosis.

[0232] The present application also provides a chip including the aforementioned anti-aliasing downsampling circuit. The anti-aliasing downsampling circuit is configured to reduce the sampling rate of a signal while avoiding aliasing distortion, thereby reducing the amount of data. The anti-aliasing downsampling circuit eliminates redundant computations and has advantages such as small circuit size and low power consumption.

[0233] The chip provided in the embodiments of the present application can be used in consumer electronic products such as smartphones, tablet computers, and smart speakers to process audio and video signals. For example, during audio recording and playback on a smartphone, the chip can perform anti-aliasing downsampling on the audio signal collected by the microphone, while optimizing the audio quality and providing a clear and realistic sound quality experience. In terms of video capture and playback, the chip can efficiently process the video signal output by the camera, achieving video downsampling and format conversion to meet different storage and transmission requirements.

[0234] In industrial automation production lines, this chip can be used to process signals collected by various sensors, such as temperature sensors, pressure sensors, and accelerometers. By downsampling and optimizing sensor signals to prevent aliasing, it can accurately capture various parameters in the production process, providing reliable data support for industrial control systems. In the Internet of Things (IoT), this chip can be applied to various smart devices and sensor nodes, enabling efficient processing and transmission of massive amounts of data, improving the performance and reliability of IoT systems.

[0235] In medical devices such as electrocardiographs, electroencephalograms, and ultrasound machines, this chip effectively removes noise interference from biomedical signals and performs precise anti-aliasing and downsampling processing on the signals, ensuring that doctors receive accurate diagnostic information. Furthermore, the chip's multi-channel processing capabilities enable simultaneous processing of multiple biomedical signals, improving the efficiency of medical equipment.

[0236] In communications systems, this chip can be used to process both wireless and wired signals. For example, in base station equipment, it can perform anti-aliasing and downsampling on received RF signals, improving signal quality and transmission efficiency. In network equipment, the chip can process data signals, downsampling and format conversion to accommodate different network transmission protocols and bandwidth requirements.

[0237] The present application also provides a signal processing device comprising the aforementioned circuit module or chip. The signal processing device can be used in smart home systems, intelligent transportation systems, aerospace systems, and financial transaction systems, providing reliable solutions for various complex signal processing tasks.

[0238] It will be appreciated by those skilled in the art that, under the premise of no conflict, the above-mentioned preferred embodiments can be freely combined and superimposed. Among them, the flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the system according to the various embodiments disclosed in this application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment, or a part of a code, and the module, program segment, or a part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions. The numbering of each step in this article is only for the convenience of description and reference, and is not used to limit the order of execution. The specific execution order is determined by the technology itself, and those skilled in the art can determine various allowable and reasonable orders based on the technology itself.

[0239] Those skilled in the art will appreciate that, provided there is no conflict, the above preferred solutions can be freely combined and superimposed.

[0240] It should be understood that the above-mentioned embodiments are merely illustrative and not restrictive. Without departing from the basic principles of the present application, various obvious or equivalent modifications or substitutions that can be made by those skilled in the art to the above-mentioned details will be included in the scope of the claims of the present application.

Claims

1. An anti-aliasing downsampling circuit, characterized in that: include: A first multiplication-accumulation module, at least one second multiplication-accumulation module, a third multiplication-accumulation module, a module I counter and latch registers; The first input terminal of the first multiplication-accumulation module, the first input terminal of the second multiplication-accumulation module, and the first input terminal of the third multiplication-accumulation module are connected together, the second input terminal of the first multiplication-accumulation module inputs data 0, the output terminal of the first multiplication-accumulation module is connected to the second input terminal of the second multiplication-accumulation module, the output terminal of the second multiplication-accumulation module is connected to the second input terminal of the third multiplication-accumulation module, and the output terminal of the third multiplication-accumulation module is connected to the latch register; The mold I The counter is connected to the control input end of the first multiplication and accumulation module, the second multiplication and accumulation module, the third multiplication and accumulation module and the latch register. I The value of the count variable of the counter increases as the clock cycle changes. Under the control of the value of the count variable, the first multiplication and accumulation module selects the corresponding filter coefficient and 0 or the accumulation result of the first multiplication and accumulation module, the second multiplication and accumulation module selects the corresponding filter coefficient and the output result of the first multiplication and accumulation module or the accumulation result of the second multiplication and accumulation module, and the third multiplication and accumulation module selects the corresponding filter coefficient and the output result of the second multiplication and accumulation module or the accumulation result of the third multiplication and accumulation module to perform multiplication and accumulation operations; According to the value of the count variable, the latch register outputs I Downsampling results; The number of the second multiplication-accumulation modules is determined by the filter order and the module I modulus of the counter I Determine that the number of the second multiplication-accumulation modules is Among them, M Indicates the filter order.

2. The anti-aliasing downsampling circuit according to claim 1, wherein: The first input ends of each second multiplication-accumulation module are connected together, the second input end is connected to the output end of the adjacent first multiplication-accumulation module or the output end of the adjacent previous second multiplication-accumulation module, and the output end of each second multiplication-accumulation module is connected to the second input end of the adjacent next second multiplication-accumulation module or the input end of the adjacent third multiplication-accumulation module.

3. The anti-aliasing downsampling circuit according to claim 1, wherein: The first multiplication-accumulation module includes a first multiplier, a first adder, a first multiplexer, and a first accumulation register, and the filter coefficients and input data corresponding to the first multiplication-accumulation module are input into the first multiplier for multiplication operation; The first multiplexer is in the module I Under the numerical control of the counting variable of the counter, the first adder selects to output 0 or the output result of the first accumulator register, and performs an addition operation on the output result of the first multiplier and the output result selected by the first multiplexer; The first accumulation register stores the output result of the first adder, and uses the stored result as the input of the second multiplication-accumulation module, and inputs the stored result into the first adder through the first multiplexer.

4. The anti-aliasing downsampling circuit according to claim 3, characterized in that: The second multiplication-accumulation module includes a second multiplier, a second adder, a second multiplexer, and a second accumulation register, and the filter coefficients and input data corresponding to the second multiplication-accumulation module are input into the second multiplier for multiplication operation; The second multiplexer is in the module I Under the numerical control of the counting variable of the counter, the output result of the first accumulator register or the output result of the second accumulator register is selected for output, and the second adder performs an addition operation on the output result of the second multiplier and the result selected and output by the second multiplexer; The second accumulation register stores the output result of the second adder, and uses the stored result as the input of the third multiplication-accumulation module, and inputs the stored result into the second adder through the second multiplexer.

5. The anti-aliasing downsampling circuit according to claim 4, characterized in that: The third multiplication-accumulation module includes a third multiplier, a third adder, a third multiplexer, and a third accumulation register, and the filter coefficients and input data corresponding to the third multiplication-accumulation module are input into the third multiplier for multiplication operation; The third multiplexer is in the module I Under the numerical control of the counting variable of the counter, the output result of the second accumulator register or the output result of the third accumulator register is selected for output, and the third adder performs an addition operation on the output result of the third multiplier and the output result selected by the third multiplexer; The third accumulator register stores the output result of the third adder, inputs the stored result into the latch register for latching, and inputs the stored result into the third adder through the third multiplexer.

6. The anti-aliasing downsampling circuit according to claim 5, characterized in that: According to the filter order M and model I modulus of the counter I ,Will M +1 filter coefficient written coefficient tables, each of which has I filter coefficients.

7. The anti-aliasing downsampling circuit according to claim 6, characterized in that: when M +1 Not I When the value is an integer multiple of Some filter coefficients in the coefficient table are padded with 0.

8. The anti-aliasing downsampling circuit according to claim 6, wherein: The range of the value of the counting variable is 0~ I -1.

9. The anti-aliasing downsampling circuit according to claim 8, characterized in that: When the value of the counter variable is 0: The first multiplexer selects to output 0, the first adder performs an addition operation on 0 and an output result of the first multiplier, and the output result of the first adder is stored in the first accumulator register; The second multiplexer selects and outputs the output result of the first accumulator register, the second adder performs an addition operation on the output result of the first accumulator register and the output result of the second multiplier, and the output result of the second adder is stored in the second accumulator register; The third multiplexer selects and outputs the output result of the second accumulator register, the third adder performs an addition operation on the output result of the second accumulator register and the output result of the third multiplier, the output result of the third adder is stored in the third accumulator register, and the output result of the third accumulator register is input into the latch register for latching.

10. The anti-aliasing downsampling circuit according to claim 8, characterized in that: The value of the counting variable is 1~ I -1 hour: The first multiplexer selects and outputs an output result of the first accumulator register in a previous clock cycle, the first adder performs an addition operation on the output result of the first accumulator register in the previous clock cycle and an output result of the first multiplier, and the output result of the first adder is stored in the first accumulator register; The second multiplexer selects and outputs an output result of the second accumulator register in a previous clock cycle, the second adder performs an addition operation on the output result of the second accumulator register in the previous clock cycle and the output result of the second multiplier, and the output result of the second adder is stored in the second accumulator register; The third multiplexer selects and outputs the output result of the third accumulator register in the previous clock cycle, the third adder performs an addition operation on the output result of the third accumulator register in the previous clock cycle and the output result of the third multiplier, the output result of the third adder is stored in the third accumulator register, and the output result of the third accumulator register is input into the latch register for latching.

11. The anti-aliasing downsampling circuit according to claim 10, characterized in that: The value of the count variable is I -1, the third accumulator register stores the result as I The down-sampling result is input into the latch register for latching.

12. A circuit module, characterized in that: The method comprises the anti-aliasing downsampling circuit according to any one of claims 1 to 11.

13. A chip, characterized in that: The method comprises the anti-aliasing downsampling circuit according to any one of claims 1 to 11.

14. A signal processing device, characterized in that: Comprising the circuit module according to claim 12 or the chip according to claim 13.

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