Rapid line resistance network analysis method for nonvolatile memory array

Abstract

The invention belongs to the technical field of line resistance network analysis, and discloses a fast line resistance network analysis method for a nonvolatile memory array, which comprises the following steps of: establishing electrode KCL equations of all rows and columns in a line resistance network of the nonvolatile memory array; a voltage line and a coefficient matrix in the KCL equation are transformed and decomposed, a fixed point iterative algorithm is introduced, and voltage distribution of nodes at the top and the bottom of the array is iteratively calculated. An original complex large-scale linear equation set problem is converted into two small-scale sub-problems. And solving is carried out through mutual iteration of the two sub-problems, so that the calculation complexity and the calculation memory are reduced. According to the method, the influence of IR-drop on neural network calculation acceleration can be predicted and evaluated in the design stage. The method has the advantages that the accuracy is high, and the influence of IR-drop can be simulated with the accuracy exceeding 95%; the calculation complexity is low, and the calculation complexity is reduced from O ((2mn) 2) to O (mn); the memory load is small, and the use of the memory is minimized while high accuracy is kept.

Description

Technical Field

[0001] The present invention belongs to the technical field of wire resistance network analysis, and more specifically, relates to a fast wire resistance network analysis method for a non-volatile memory array. Background Art

[0002] With the rapid development of artificial intelligence technology, especially driven by deep learning algorithms, computing hardware is facing increasing performance requirements. The Computing-In-Memory (CIM) technology has attracted much attention because it integrates storage and computing in the same location. Due to its significant advantages in providing high computing power, high energy efficiency, and low latency, it has become one of the key technologies to solve the AI computing power demand. Non-volatile storage devices have the dual functions of storage and computing, and their unique physical characteristics make them show great potential in CIM applications.

[0003] However, with the expansion of the scale of non-volatile memory arrays, considering the existence of the mutual connection resistance between wires, the voltage drop (IR-Drop) between the memory array nodes accumulates continuously, and its influence on the voltage distribution in the array becomes more and more obvious, hindering the application of in-memory computing technology. Therefore, generally, the wire resistance network of the non-volatile memory array is analyzed to obtain the voltage distribution of the array nodes, so as to evaluate the influence of IR-Drop in large-scale neural networks, and then correct the error caused by IR-drop to the neural network.

[0004] In the existing technology, directly solving the node voltage distribution of the array involves the inversion of a large-scale matrix, which requires extremely large computational amount and computational memory. There are also two other methods: one is to use a first-order iterative model to correct the conductance of memristors, but there are non-negligible accuracy problems; the other is to use the gamma iterative algorithm in the correction model to alleviate the accuracy problems, which is essentially a second-order correction of the conductance of non-volatile memory cells, and will bring a relatively large computational amount (O(2mn) 2 , where m and n represent the number of rows and columns of the non-volatile memory array respectively) and memory load. Summary of the Invention

[0005] Aiming at the above defects or improvement requirements of the existing technology, the present invention provides a fast wire resistance network analysis method for a non-volatile memory array, aiming to improve the calculation accuracy of the voltage distribution of the non-volatile memory array nodes and reduce the computational amount and memory load of the voltage distribution of the nodes.

[0006] To achieve the above object, the present invention provides a fast wire resistance network analysis method for a non-volatile memory array, including:

[0007] Establish the electrode KCL equations for all rows and columns in the non-volatile memory array line resistance network: A·Vt′ = Vb′ + b, B·Vb″ = Vt″; where A and B are both tridiagonal matrices, representing the coefficient matrices of the upper electrode voltages of all rows and columns in the line resistance network respectively; Vt′ and Vt″ are the upper electrode voltage vectors of all rows and columns respectively; Vb′ and Vb″ are the lower electrode voltage vectors of all rows and columns respectively; b is the vector composed of the input voltages of all rows.

[0008] Transform the voltage vector Vb″ using Vb′ and the orthonormal transformation matrix M, transform the voltage vector Vt″ using Vt′ and the orthonormal transformation matrix M, and decompose the coefficient matrices A and B according to the properties of tridiagonal matrices; substitute the transformed Vb″, Vt″ and the decomposed coefficient matrices A and B into the corresponding electrode KCL equations, and after transposing the equations, obtain the corresponding matrix equations based on fixed-point iteration.

[0009] Substitute the initial values of the upper and lower electrode voltages of all rows into the matrix equations based on fixed-point iteration for iteration to obtain the upper and lower electrode voltage vectors Vt′ and Vb′ of all rows; and based on the transformation relationship between the voltage vectors Vt′, Vb′ and the orthonormal transformation matrix M, obtain the upper and lower electrode voltage vectors Vt″ and Vb″ of all columns.

[0010] Further, the transformation of the voltage vector Vb″ using Vb′ and the orthonormal transformation matrix M, and the transformation of the voltage vector Vt″ using Vt′ and the orthonormal transformation matrix M, the corresponding transformation relationships are: M·Vb′ = Vb″, M·Vt′ = Vt″;

[0011] After substituting the transformed Vb″, Vt″ and the decomposed coefficient matrices A and B into the corresponding electrode KCL equations, the transformed electrode KCL equations obtained are:

[0012] (G A ·H A + I)·Vt′ = Vb′ + b

[0013] (G B ·H B + I)·M·Vb′ = M·Vt′

[0014] Where, (G A ·H A + I) and (G B ·H B + I) represent the decomposed coefficient matrices A and B respectively; G A is a diagonal matrix composed of the ratios of the row line conductances G BL of the non-volatile memory array to the storage cell conductances G m ; GB is the column-line conductance G SL and the ratio of the conductance of the storage cell G m to form a diagonal matrix; H A and H B are respectively the standard tridiagonal matrices corresponding to the coefficient matrices A and B; I is the identity matrix.

[0015] Furthermore, the matrix equation based on fixed-point iteration is:

[0016] Vt′ (k+1) =(G A ·H A ) -1 (Vb′ (k) +b - Vt′ (k) )

[0017] Vb′ (k+1) =M -1 (G B ·H B ) -1 ·(M·Vt′ (k) -M·Vb′ (k) )

[0018] In the formula, M -1 is the inverse matrix of M; k represents the number of iterations, k≥0, when k = 0, Vt′ (0) , Vb′ (0) are respectively the initial values of the upper and lower electrode voltages of all rows; Vt′ (k) , Vb′ (k) respectively represent Vt′ and Vb′ after the k-th iteration;

[0019] In each iteration process, the calculation method of (G·H) -1 ·V is:

[0020] Transform (G·H) -1 into: G -1 ·H -1 ; where, G represents G A or G B , which is a diagonal matrix, and H represents H A or H B ;

[0021] Decompose H -1 by LU decomposition into the product of the corresponding L matrix and U matrix, and then convert the product of H -1 and the vector V into the product of the L matrix and U matrix and the vector V; where, the vector V is (Vb′ (k) +b - Vt′ (k) ) or (M·Vt′ (k) -M·Vb′(k) )。

[0022] Further, the calculation method for the initial values of the upper electrode and lower electrode voltages of all rows and columns is as follows:

[0023] Set the lower electrode line resistance of the wire resistance network to 0 Ω to reduce the two-dimensional wire resistance network to a one-dimensional wire resistance network; establish a second-order homogeneous linear difference equation satisfied by the upper electrode voltage in the one-dimensional wire resistance network, and solve the second-order homogeneous linear difference equation, and use the obtained analytical solution as the initial value Vt′ of the upper electrode voltages of all rows (0) ;

[0024] Set the upper electrode line resistance of the wire resistance network to 0 Ω to reduce the two-dimensional wire resistance network to a one-dimensional wire resistance network; establish a second-order homogeneous linear difference equation satisfied by the lower electrode voltage in the one-dimensional wire resistance network, and solve the second-order homogeneous linear difference equation, and use the obtained analytical solution as the initial value Vb′ of the lower electrode voltages of all rows (0) 。

[0025] Further, iterate the matrix equation based on fixed-point iteration, and the iteration termination condition is:

[0026] According to the upper electrode voltage vector Vt′ of all rows in the current iteration (k) , the lower electrode voltage vector Vb′ (k) Calculate the output currents of all columns of the wire resistance network, and determine whether the column output currents meet the preset accuracy requirements; if not, perform the next iteration, if so, terminate the iteration to obtain the corresponding upper electrode and lower electrode voltage vectors.

[0027] Further, it further includes: evaluating the impact of the voltage drop between the nodes of the non-volatile memory array on the large-scale neural network based on the column output currents that meet the preset accuracy requirements.

[0028] Further, the storage unit in the non-volatile memory array is a memristor.

[0029] The present invention also provides a fast wire resistance network analysis system for a non-volatile memory array, including a computer-readable storage medium and a processor;

[0030] The computer-readable storage medium is used to store executable instructions;

[0031] The processor is used to read the executable instructions stored in the computer-readable storage medium and execute the fast wire resistance network analysis method for the non-volatile memory array described in any one of the above.

[0032] The present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, it implements the fast wire resistance network analysis method of the non-volatile memory array as described in any one of the above.

[0033] The present invention also provides a computer program product, including a computer program, and when the computer program runs on a computer, it enables the computer to execute the fast wire resistance network analysis method of the non-volatile memory array as described in any one of the above.

[0034] Generally speaking, through the above technical solutions conceived by the present invention, the following beneficial effects can be achieved:

[0035] (1) In the fast wire resistance network analysis method of the non-volatile memory array of the present invention, the large-scale non-homogeneous linear equations for directly solving the node voltages of the array are separated and converted into two smaller-scale sub-problems for respectively solving the upper and lower node (upper and lower electrode) voltages, thereby reducing the computational complexity and computational memory. Specifically, by establishing the electrode KCL equations for all rows and columns in the wire resistance network, transforming and decomposing the voltage matrix and coefficient matrix in the equations based on the standard orthogonal transformation matrix transformation and the properties of the tridiagonal matrix, and introducing a fixed-point iteration algorithm to iterate the electrode KCL equations for rows and columns, the solution of the node voltages of the storage array is realized. Since the method of the present invention does not involve the inversion of large-scale matrices, the computational amount and computational memory are reduced; and the method of the present invention solves the node voltages starting from the physical eigen-equations of the wire resistance network of the non-volatile memory array, rather than establishing an approximate model for solution, so it has high accuracy.

[0036] (2) Further, in the fast wire resistance network analysis method of the non-volatile memory array of the present invention, based on the constructed matrix equation based on fixed-point iteration, when performing fixed-point iteration, the LU matrix decomposition is used to decompose the coefficient matrix in the matrix equation of the fixed-point iteration, so as to convert the large-scale matrix operation into the transfer and accumulation of data. For a non-volatile memory array with a scale of m*n, the original computational complexity is reduced from O((2mn) 2 ) to O(mn), and the computational memory also becomes O(mn), greatly reducing the computational amount and computational memory.

[0037] (3) Preferably, a dimension reduction method is adopted to solve the one-dimensional approximate initial solutions of the upper electrode and the lower electrode, so as to reduce the number of iterations of the fixed-point iteration algorithm and further reduce the computational amount.

[0038] (4) Preferably, the storage unit in the non-volatile memory array is a memristor; by combining data storage and processing operations at the same location, the memristor can significantly reduce the data transmission distance, reduce power consumption, and improve computational efficiency.

[0039] In summary, the analysis method of the present invention decomposes the top node network and the bottom node network and is based on the fixed-point iteration algorithm, reducing the computational complexity from the traditional O((2mn) 2 ) to O(mn); moreover, the computational memory is small, only O(mn) variables need to be stored, and the storage space required for the calculation is small, which is conducive to quickly solving the voltage distribution of a large-scale memristor array. Description of the Drawings

[0040] Figure 1 Schematic diagram of the fast line resistance network analysis method for the non-volatile memory array in the embodiment of the present invention.

[0041] Figure 2 Schematic diagram of the non-volatile memory array and the corresponding KCL equations of the upper and lower electrodes in the embodiment of the present invention; (a) is a schematic diagram of the line resistance network and the corresponding KCL equation of the upper electrode voltage, and (b) is a schematic diagram of the line resistance network and the corresponding KCL equation of the lower electrode voltage.

[0042] Figure 3 Schematic diagram of the pseudo-code for optimizing the matrix-vector multiplication problem by using matrix LU decomposition in the embodiment of the present invention.

[0043] Figure 4 Schematic diagram of reducing the dimension to solve the approximate initial solution in the embodiment of the present invention; (a) is the voltage distribution of the upper electrode obtained by solving, (b) is the line resistance network after dimension reduction by setting the lower electrode line resistance to 0Ω, (c) is the voltage distribution of the lower electrode obtained by solving, and (d) is the line resistance network after dimension reduction by setting the upper electrode line resistance to 0Ω.

[0044] Figure 5 Schematic diagram of the simulation results in the case of an array scale of 128 rows × 128 columns in the embodiment of the present invention; (a) is the output current error obtained by one fixed-point iteration and two fixed-point iterations when the line resistance is 2Ω, (b) is the current accuracy obtained under different line resistances, (c) is the current accuracy of the line resistance network output for different scales when the line resistance is 0.2Ω, and (d) is the current accuracy of the line resistance network output under different input excitations. Detailed Embodiments

[0045] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0046] Embodiment 1

[0047] As Figure 1 shown, in an embodiment of the present invention, a fast wire resistance network analysis method for a non-volatile memory array is provided, which mainly includes:

[0048] Establish the electrode KCL equations for all rows in the wire resistance network of the non-volatile memory array: A·Vt′ = Vb′ + b; where A is a tridiagonal matrix representing the coefficient matrix of the upper electrode voltages of all rows in the wire resistance network; Vt′ is a vector composed of the upper electrode voltages of all rows, used to characterize the upper electrode voltage distribution of all rows; Vb′ is a vector composed of the lower electrode voltages of all rows, used to characterize the lower electrode voltage distribution of all rows; b is a vector composed of the input voltages of all rows.

[0049] Establish the electrode KCL equations for all columns in the wire resistance network of the non-volatile memory array: B·Vb″ = Vt″; where B is a tridiagonal matrix representing the coefficient matrix of the lower electrode voltages of all columns in the wire resistance network; Vt″ is a vector composed of the upper electrode voltages of all columns, used to characterize the upper electrode voltage distribution of all columns; Vb″ is a vector composed of the lower electrode voltages of all columns, used to characterize the lower electrode voltage distribution of all columns.

[0050] Transform Vb″ using Vb′ and the orthonormal transformation matrix M, transform Vt″ using Vt′ and the orthonormal transformation matrix M, and decompose the matrices A and B according to the properties of the tridiagonal matrix; substitute the transformed Vb″, Vt″ and the decomposed matrices A and B into the corresponding electrode KCL equations, and after transposing the equations, obtain the corresponding matrix equations based on fixed-point iteration;

[0051] Substitute the initial values of the upper and lower electrode voltages of all rows in the wire resistance network into the matrix equations based on fixed-point iteration for iteration, and iteratively obtain the upper and lower electrode voltage vectors Vt′, Vb′ of all rows; and based on the transformation relationship between the voltage vectors Vt′, Vb′ and the orthonormal transformation matrix M, obtain the upper and lower electrode voltage vectors Vt″, Vb″ of all columns.

[0052] The fast wire resistance network analysis method for the non-volatile memory array of the present invention separates the large-scale non-homogeneous linear equations for directly solving the node voltages of the array and converts them into two smaller-scale sub-problems for separately solving the upper and lower node (upper and lower electrodes) voltages, thereby reducing the computational complexity and computational memory. Specifically, by establishing the electrode KCL equations for all rows and columns in the wire resistance network, transforming and decomposing the voltage matrix and coefficient matrix in the equations based on the standard orthogonal transformation matrix transformation and the properties of the tridiagonal matrix, and introducing a fixed-point iteration algorithm to iterate the electrode KCL equations for rows and columns, the solution of the node voltages of the storage array is realized. Since the method of the present invention does not involve the inversion of large-scale matrices, the computational amount and computational memory are reduced; and the method of the present invention solves the node voltages starting from the physical eigen-equations of the wire resistance network of the non-volatile memory array, rather than establishing an approximate model for solution, which has high accuracy.

[0053] In the embodiments of the present invention, establishing the electrode KCL equations for all rows and columns in the wire resistance network of the non-volatile memory array includes:

[0054] Constructing the upper and lower electrode KCL equations for the storage unit at the i-th row and j-th column in the wire resistance network of the non-volatile memory array:

[0055] Ip(i, j) = Im(i, j) + Ip(i, j + 1) (1)

[0056] In(i - 1, j) = Im(i, j) + In(i, j) (2)

[0057] Where, Ip(i, j) is the current value flowing through the wire resistance of the upper electrode of the storage unit at the i-th row and j-th column; In(i, j) is the current value flowing through the wire resistance of the lower electrode of the storage unit at the i-th row and j-th column; Im(i, j) is the current value flowing through the storage unit at the i-th row and j-th column; correspondingly, Ip(i, j + 1) is the current value flowing through the wire resistance of the upper electrode of the storage unit at the i-th row and j + 1-th column, and In(i - 1, j) is the current value flowing through the wire resistance of the lower electrode of the storage unit at the (i - 1)-th row and j-th column. As Figure 2 shown, Figure 2 (a) in represents the schematic diagram of the wire resistance network and the corresponding upper electrode voltage KCL equation of the m-row and n-column non-volatile memory array in the embodiments of the present invention, and the arrow indicates the current direction; Figure 2 (b) in represents the schematic diagram of the wire resistance network and the corresponding lower electrode voltage KCL equation of the m-row and n-column non-volatile memory array in the embodiments of the present invention. By applying a voltage excitation to the BL (bit line) at the left end of the cross array, and then clamping the SL (source line) at the lower end of the array to the ground gnd. According to Kirchhoff's theorem, perform matrix multiplication in the analog domain, and the output result of the non-volatile memory array is the output current at the SL end.

[0058] Convert the current in the KCL equation of the upper and lower electrodes of the storage unit in the \(i\)-th row and \(j\)-th column into the form of conductance multiplied by the corresponding electrode voltage (node voltage), and combine the KCL equations of all electrodes of the storage units in the \(i\)-th row to list the row linear equations composed of the KCL equations of all electrodes of the storage units in the \(i\)-th row:

[0059] A i ·V i ′=Vb i ′+b i (3)

[0060] Among them, A i is the coefficient matrix of the upper electrode voltage \(V_t\) i ′ of the storage unit in the \(i\)-th row; \(V_b\) i ′ is the lower electrode voltage of the storage unit in the \(i\)-th row; b i is the bias term considering the input voltage \(V\) in(i) in the \(i\)-th row.

[0061] Combine the row linear equations of all row storage units to obtain the KCL equations of all electrodes of all rows in the non-volatile memory array line resistance network:

[0062] A·Vt′=Vb′+b (4)

[0063] Model the storage units in the \(j\)-th column in the same way to obtain the KCL equations of all electrodes of all columns in the non-volatile memory array line resistance network:

[0064] B·Vb″=Vt″ (5)

[0065] As a preferred implementation, each storage unit in the non-volatile memory array is a memristor.

[0066] As a preferred implementation, based on the fact that \(V_b'\) and \(V_b''\), \(V_t'\) and \(V_t''\) are vectors expanded in the row and column directions respectively, use the standard orthogonal transformation matrix \(M\) to transform the voltage vector (\(V_b'\) and \(V_b''\), \(V_t'\) and \(V_t''\)):

[0067] M·Vb′=Vb″,M·Vt′=Vt″ (6)

[0068] Decompose matrices \(A\) and \(B\) according to the properties of the tridiagonal matrix: \(A = G A ·H A +I, B = G B ·H B +I, where \(G A is the diagonal matrix composed of the ratio of the row line conductance \(G BL of the non-volatile memory array to the storage unit conductance \(G m , and \(G Bis the column conductance G SL and the conductance G of the storage cell m to form a diagonal matrix; H A and H B are the standard tridiagonal matrices corresponding to matrices A and B respectively; I is the identity matrix.

[0069] Substitute the transformed Vb″ and Vt″, and the decomposed matrices A and B into formulas (4) and (5) to obtain:

[0070] (G A ·H A +I)·Vt′ = Vb′ + b (7)

[0071] (G B ·H B +I)·M·Vb′ = M·Vt′ (8)

[0072] After transposing (G A ·H A +I) and (G B ·H B +I), the matrix equation based on fixed-point iteration is obtained:

[0073] Vt′ (k+1) =(G A ·H A ) -1 (Vb′ (k) +b - Vt′ (k) ) (9)

[0074] Vb′ (k+1) =M -1 (G B ·H B ) -1 ·(M·Vt′ (k) -M·Vb′ (k) ) (10)

[0075] In the formula, M -1 is the inverse matrix of the orthogonal transformation matrix; k represents the number of iterations, k ≥ 0; Vt′ (k) represents Vt′ after the k-th iteration; Vb′ (k) represents Vb′ after the k-th iteration; among them, the coefficient matrices (G A ·H A ) -1 and (G B ·H B ) -1 can be transformed as follows:

[0076] (G A ·H A )-1 = H A -1 ·G A -1 (11)

[0077] (G B ·H B ) -1 = H B -1 ·G B -1 (12)

[0078] Since G A and G B are diagonal matrices, it is easy to find their corresponding inverse matrices according to the properties of diagonal matrices. While H A -1 and H B -1 can be decomposed into the product of the corresponding L matrix and U matrix by LU matrix decomposition.

[0079] For a matrix H, its corresponding LU decomposition is as follows:

[0080]

[0081] Since the L matrix is a strictly lower triangular matrix and the U matrix is a strictly upper triangular matrix, the multiplication of the L matrix, U matrix and the vector V can be realized by shifting and accumulating the elements in the vector V. In the embodiment of the present invention, the vector V is (Vb′ (k) + b - Vt′ (k) ) or (M·Vt′ (k) - M·Vb′ (k) ). Thus, the product of (G A ·H A ) -1 and (Vb′ (k) + b - Vt′ (k) ), and the product of (G B ·H B ) -1 and (M·Vt′ (k) - M·Vb′ (k) ) can be transformed into the corresponding L matrix and U matrix to perform shifting and accumulation on the elements in (Vb′ (k) + b - Vt′ (k) ) or (M·Vt′ (k) - M·Vb′ (k) ), and the computational complexity is O(mn), which is significantly lower than the complexity O(2mn) required for direct matrix solution 2 .

[0082] As shown in Figure 3 the figure, it is a schematic diagram of pseudocode for optimizing the matrix-vector multiplication problem using matrix LU decomposition in the embodiment of the present invention. By performing LU decomposition on H A -1 and H B -1 the result is an upper triangular matrix and a lower triangular matrix. Therefore, the multiplication of the original coefficient matrix and the vector V can be converted into multiplication with the upper triangular matrix U and the lower triangular matrix L respectively. Since all the elements in the L and U matrices are 1, by shifting and accumulating the elements in the vector V, the large-scale multiplication of the coefficient matrix and the vector V is completely avoided, thus reducing the original matrix operation with a computational complexity of O(2mn) 2 to O(mn), achieving a reduction in the computational complexity, and the memory required for the calculation also decreases from O(2mn) 2 to O(mn).

[0083] Substitute the initial values Vb′ (0) and Vt′ (0) of the lower electrode voltages of all rows and the upper electrode voltages of all rows into the matrix equations based on fixed-point iteration shown in formulas (9) and (10), and iteratively obtain the final lower electrode voltage distribution Vb′ and upper electrode voltage distribution Vt′ of all rows; obtain the upper electrode voltage distribution Vt″ and lower electrode voltage distribution Vb″ of all columns through formula (6).

[0084] In the embodiment of the present invention, the iteration termination condition is:

[0085] According to the lower electrode voltages Vb′ (k) of all rows and the upper electrode voltages Vt′ (k) obtained in the current iteration, calculate the output currents of all columns of the line resistance network, and determine whether the output current of this column meets the accuracy requirement. If so, stop the iteration; if not, perform the next iteration until the output current of the column meets the accuracy requirement.

[0086] For the fast line resistance network analysis method of the non-volatile memory array of the present invention, based on the constructed matrix equation based on fixed-point iteration, when performing fixed-point iteration, LU matrix decomposition is used to decompose the coefficient matrix in the matrix equation of fixed-point iteration, thereby converting large-scale matrix operations into data shifting and accumulation, greatly reducing the computational complexity and the memory required for calculation.

[0087] As a preferred implementation, in the embodiment of the present invention, a dimensionality reduction method is used to solve the one-dimensional approximate initial solution of the upper electrode and the lower electrode, thereby reducing the number of iterations of the fixed-point iteration algorithm and reducing the computational complexity. Specifically, it includes:

[0088] Set the lower electrode line resistance of the line resistance network to 0 Ω to reduce the original two-dimensional line resistance network to a one-dimensional π-type network model; at this time, the reduced line resistance network is only affected by the row line resistance R BL and the memristor conductance G m .

[0089] Based on the reduced line resistance network, write the second-order homogeneous linear difference equation satisfied by the upper electrode voltage, and solve this second-order homogeneous linear difference equation to obtain the initial value Vt′ of the upper electrode voltage (0) .

[0090] Similarly, set the upper electrode line resistance of the line resistance network to 0 Ω, reduce the line resistance network, write the second-order homogeneous linear difference equation satisfied by the lower electrode voltage based on the reduced line resistance network, and solve this second-order homogeneous linear difference equation to obtain the initial value Vb′ of the lower electrode voltage (0) .

[0091] In the embodiment of the present invention, when the lower electrode line resistance of the line resistance network is 0 Ω, the second-order homogeneous linear difference equation satisfied by the corresponding node voltage is:

[0092] G BL ·(V t (i,j)-V t (i,j - 1)) - G BL ·(V t (i,j)-V t (i,j + 1)) - G mean ·V t (i,j) = 0 (14)

[0093] In the formula, V t (i,j) represents the upper electrode voltage of the memory cell in the i-th row and j-th column of the reduced line resistance network, G BL = 1 / R BL is the row line conductance, and G mean is the average conductance of the memory cell;

[0094] Based on the input voltage, solve the initial solution of the upper electrode voltage:

[0095]

[0096] Among them, F(·) represents the polynomial function of the second-order homogeneous linear difference equation, n is the number of columns of the non-volatile memory array; h is the ratio of the line resistance to the memory cell.

[0097] Similarly, the approximate initial solution of the lower electrode voltage is:

[0098] K·Vb T = Vin T (16)

[0099] Among them, K represents the coefficient matrix of the linear equations in the reduced-dimension line resistance network, and Vb T is the transpose of Vb. Vb is a vector composed of all row bottom electrode voltages, and Vin is a vector composed of all row input voltages V in(i) constitute.

[0100] Verified by the simulation results, the upper and lower electrode voltages calculated from the optimized initial solution have reached an accuracy of more than 70% under different input voltages. Substituting them into the matrix equation based on fixed-point iteration can quickly solve the upper and lower electrode voltage distributions.

[0101] Such as Figure 4 shown, it is a schematic diagram of reducing the dimension to solve the approximate initial solution in the embodiment of the present invention. Figure 4 In (a) is the upper electrode voltage distribution obtained by solving in the embodiment of the present invention, Figure 4 in (b) represents the reduced-dimension line resistance network after setting the bottom electrode line resistance to 0Ω; by setting the bottom electrode line resistance to 0Ω, the original two-dimensional line resistance model is reduced to a one-dimensional π-type network model. By solving the analytical solution of the one-dimensional π-type network, the preliminary solution of the upper electrode voltage distribution is realized. Similarly, Figure 4 in (c) is the lower electrode voltage distribution obtained by solving, Figure 4 in (d) represents the reduced-dimension line resistance network after setting the upper electrode line resistance to 0Ω; by setting the upper electrode line resistance to 0Ω, the two-dimensional line resistance model is reduced to a one-dimensional line resistance model. By solving the linear equations of the one-dimensional model, the initial solution of the lower electrode voltage can be obtained. With the initial solutions of the upper and lower electrode voltages, based on fixed-point iteration, the voltage distributions of the upper and lower electrodes can be iteratively solved faster.

[0102] Such as Figure 5 shown, it is the simulation result in the case of an array scale of 128 rows × 128 columns in the embodiment of the present invention. Such as Figure 5 shown in (a), when the line resistance is 2Ω, the output current calculated from all row bottom electrode voltages Vb′ (k) of all rows and all row upper electrode voltages Vt′ (k) obtained by one fixed-point iteration, compared with the true value, the current error is less than 3.9%; two fixed-point iterations can achieve an output current error of less than 2.2%. Such as Figure 5 shown in (b), under different line resistances, the method of the present invention still has a current accuracy of more than 95%. Such as Figure 5 shown in (c), when the line resistance is 0.2Ω, for line resistance networks of different scales, the method of the present invention all has a current accuracy of more than 95%. Such as Figure 5As shown in (d), under different input excitations, the method of the present invention has a current accuracy of more than 97%.

[0103] It can be seen that for a 128*128 memristor array, the method of the present invention shows a relative error of 2.2% with only 2 iterations. Within the actual lead resistance range, the iteration can quickly reach an accuracy of more than 95%, and has a low computational complexity and a small memory load, which is sufficient to meet the deployment of neural networks.

[0104] The method in the embodiment of the present invention can analyze the voltage distribution caused by wire resistance in the memristor array, evaluate the influence of the array line resistance on the accuracy of the neural network, and thus provide a method for the accuracy compensation and deployment of the neural network.

[0105] Embodiment 2

[0106] The embodiment of the present invention provides a fast line resistance network analysis system for a non-volatile memory array, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the steps of the fast line resistance network analysis method for the non-volatile memory array in the above Embodiment 1.

[0107] The related technical solutions are the same as above and will not be elaborated here.

[0108] Embodiment 3

[0109] The embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps of the fast line resistance network analysis method for the non-volatile memory array in the above Embodiment 1.

[0110] The related technical solutions are the same as above and will not be elaborated here.

[0111] Embodiment 4

[0112] The embodiment of the present application provides a computer program product, including a computer program. When the computer program runs on a computer, it causes the computer to execute the steps of the fast line resistance network analysis method for the non-volatile memory array in the above Embodiment 1.

[0113] The related technical solutions are the same as above and will not be elaborated here.

[0114] Those skilled in the art can easily understand that the above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A fast line resistance network analysis method for a non-volatile memory array, characterized in that: include: The electrode KCL equations of all rows and columns in the line resistance network of the non-volatile memory array are established: A·Vt′=Vb′+b, B·Vb″=Vt″; where A and B are tridiagonal matrices, representing the coefficient matrices of the upper electrode voltages of all rows and columns in the line resistance network; Vt′ and Vt″ are the upper electrode voltage vectors of all rows and columns; Vb′ and Vb″ are the lower electrode voltage vectors of all rows and columns; b is a vector composed of the input voltages of all rows; The voltage vector Vb″ is transformed by Vb′ and the standard orthogonal transformation matrix M, and the voltage vector Vt″ is transformed by Vt′ and the standard orthogonal transformation matrix M, and the coefficient matrices A and B are decomposed according to the properties of the tridiagonal matrix; the transformed Vb″, Vt″ and the decomposed coefficient matrices A and B are substituted into the corresponding electrode KCL equation, and after transposing the equation, the corresponding matrix equation based on fixed point iteration is obtained; The initial values ​​of the upper electrode and lower electrode voltages of all rows are substituted into the matrix equation based on fixed point iteration for iteration to obtain the upper electrode and lower electrode voltage vectors Vt′, Vb′ of all rows; and based on the transformation relationship between the voltage vectors Vt′, Vb′ and the standard orthogonal transformation matrix M, the upper electrode and lower electrode voltage vectors Vt″, Vb″ of all columns are obtained.

2. The fast line resistance network analysis method of the non-volatile memory array according to claim 1, characterized in that: The voltage vector Vb″ is transformed by Vb′ and the standard orthogonal transformation matrix M, and the voltage vector Vt″ is transformed by Vt′ and the standard orthogonal transformation matrix M, and the corresponding transformation relations are: M·Vb′=Vb″, M·Vt′=Vt″; After substituting the transformed Vb″, Vt″ and the decomposed coefficient matrices A and B into the corresponding electrode KCL equation, the transformed electrode KCL equation is obtained as follows: (G A ·H A +I)·Vt′=Vb′+b (G B ·H B +I)·M·Vb′=M·Vt′ Among them, (G A ·H A +I) and (G B ·H B +I) represent the coefficient matrices A and B after decomposition respectively; G A is the row line conductance G of the nonvolatile memory array. BL and the storage cell conductance G m The diagonal matrix composed of the ratios of B is the column line conductance G SL and the storage cell conductance G m A diagonal matrix composed of the ratios of A and H B are the standard tridiagonal matrices corresponding to the coefficient matrices A and B respectively; I is the identity matrix.

3. The fast line resistance network analysis method of the non-volatile memory array according to claim 2, characterized in that: The matrix equation based on fixed point iteration is: Tt′ (k+1) =(G A ·H A ) -1 (Vb′ (k) +b-Vt′ (k) ) Vb′ (k+1) =M -1 (G B ·H B ) -1 ·(M·Vt′ (k) -M·Vb′ (k) ) Where M -1 is the inverse matrix of M; k represents the number of iterations, k≥0, when k=0, Vt′ (0) , Vb′ (0) are the initial values ​​of the upper and lower electrode voltages of all rows respectively; Vt′ (k) , Vb′ (k) Respectively represent Vt′ and Vb′ after the kth iteration; In each iteration, (G·H) -1 V is calculated as: (G·H) -1 Transformed into: G -1 ·H -1 ; Where G represents G A or G B , is a diagonal matrix, H represents H A or H B ; H -1 Use LU decomposition to decompose the corresponding L matrix and U matrix, and then H -1 The product of the matrix L and the matrix U with the vector V is converted into the product of the matrix L and the matrix U with the vector V; where the vector V is (Vb′ (k) +b-Vt′ (k) ) or (M·Vt′ (k) -M·Vb′ (k) ).

4. The fast line resistance network analysis method of a non-volatile memory array according to any one of claims 1 to 3, characterized in that: The initial values ​​of the upper electrode and lower electrode voltages of all rows and columns are calculated as follows: The lower electrode line resistance of the line resistance network is set to 0Ω to reduce the two-dimensional line resistance network to a one-dimensional line resistance network; a second-order homogeneous linear difference equation satisfied by the upper electrode voltage in the one-dimensional line resistance network is established, and the second-order homogeneous linear difference equation is solved, and the analytical solution obtained is used as the initial value Vt′ of the upper electrode voltage of all rows (0) ; The upper electrode line resistance of the line resistance network is set to 0Ω to reduce the two-dimensional line resistance network to a one-dimensional line resistance network; a second-order homogeneous linear difference equation satisfied by the lower electrode voltage in the one-dimensional line resistance network is established, and the second-order homogeneous linear difference equation is solved, and the analytical solution obtained is used as the initial value Vb′ of the lower electrode voltage of all rows (0) .

5. The fast line resistance network analysis method of the non-volatile memory array according to claim 4, characterized in that: The matrix equation based on fixed point iteration is iterated, and the iteration termination condition is: According to the upper electrode voltage vector Vt′ of all rows in the current iteration (k) , the lower electrode voltage vector Vb′ (k) Calculate all column output currents of the line resistance network, and determine whether the column output currents meet the preset accuracy requirements; if not, perform the next iteration, and if so, terminate the iteration to obtain the corresponding upper electrode and lower electrode voltage vectors.

6. The fast line resistance network analysis method of the non-volatile memory array according to claim 5, characterized in that: Also includes: The impact of voltage drop between nodes of nonvolatile memory array on large-scale neural networks is evaluated based on column output current that meets preset accuracy requirements.

7. The fast line resistance network analysis method of a non-volatile memory array according to claim 1, characterized in that: The storage units in the non-volatile memory array are memristors.

8. A fast line resistance network analysis system for a non-volatile memory array, characterized in that: comprising a computer readable storage medium and a processor; The computer-readable storage medium is used to store executable instructions; The processor is used to read the executable instructions stored in the computer-readable storage medium to execute the fast line resistance network analysis method of the non-volatile memory array according to any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the fast line resistance network analysis method of the non-volatile memory array as claimed in any one of claims 1 to 7 is implemented.

10. A computer program product, characterized in that The invention comprises a computer program, which, when being executed on a computer, enables the computer to execute the fast line resistance network analysis method of a non-volatile memory array as claimed in any one of claims 1 to 7.

Images