Method for automatically generating circuit based on AI

Abstract

The invention discloses a method for automatically generating a circuit based on AI, and belongs to the field of circuit design, and the method comprises the steps: obtaining a design index; the method comprises the following steps of: acquiring design indexes, capturing a dependency relationship among the design indexes by utilizing an attention mechanism, extracting features by utilizing a multi-layer Transform structure to obtain an overall structure and advanced feature representation of a circuit, and matching the advanced feature representation with a standard circuit netlist template based on the overall structure of the circuit to obtain a current circuit structure; simulating the current circuit structure to obtain a simulation report, and extracting error information from the simulation report; and correcting the current circuit structure based on the error information, simulating the corrected circuit structure again, circulating until no error exists in the simulation report, and outputting a circuit schematic diagram and a simulation result. The method solves the problems that an existing method generally has limitation, and automatic design of a complex circuit is difficult to quickly and flexibly carry out.

Description

Technical Field

[0001] The present invention belongs to the field of circuit design, and in particular relates to a method for automatically generating circuits based on AI. Background Art

[0002] The traditional circuit design process usually relies on engineers to manually design the corresponding circuit structure, and combine EDA tools (such as Cadence, Hspice) for repeated adjustments, modifications and verifications. Since manual design requires years of experience accumulation, simulation errors need to be manually checked one by one, and circuit performance requires multiple iterations, modifications and simulations, the process has problems such as long design cycle, low debugging efficiency, and high resource consumption. This leads to limitations and problems such as long development cycle in the integrated circuit field, slow product upgrades, and high costs. Although some EDA tools for automated auxiliary design have appeared, they are generally limited and difficult to quickly and flexibly carry out complex designs, especially for analog circuit designs, and lack intelligent automatic design capabilities. Summary of the invention

[0003] In view of the above-mentioned deficiencies in the prior art, the present invention provides a method for automatically generating circuits based on AI, which solves the problem that the prior methods are generally limited and difficult to design complex circuits quickly, automatically and flexibly.

[0004] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention is: a method for automatically generating circuits based on AI, obtaining design indicators, and storing the design indicators as structured data; the design indicators include circuit performance indicators, component indicators, circuit type indicators and component connection methods; The attention mechanism is used to capture the dependencies between various design indicators, and the multi-layer Transformer structure is used to extract features to obtain the overall structure and high-level feature representation of the circuit. Based on the overall structure of the circuit, the high-level feature representation is matched with the standard circuit netlist template to obtain the current circuit structure. Simulate the current circuit structure, obtain a simulation report, and extract error information from the simulation report; The current circuit structure is corrected based on the error information, and the corrected circuit structure is simulated again, and the cycle is repeated several times until there are no errors in the simulation report, and the circuit structure is output.

[0005] The beneficial effects of the present invention are: realizing the automatic generation from functional requirements to circuit netlists, and by introducing a natural language parsing module and a circuit structure embedding coding mechanism, the circuit design target input by the user can be automatically converted into a structured representation, and further a candidate circuit structure can be generated, thereby reducing the manual modeling process and improving the design efficiency. The closed-loop simulation correction mechanism effectively improves the one-time simulation pass rate. After the circuit is initially generated, the grammatical errors and performance deviations in the netlist are automatically identified based on the simulation feedback, and the grammatical repair, parameter optimization or structural adjustment strategy is called according to the error type, effectively improving the availability of the netlist and the convergence speed of the circuit performance. With the help of a multi-layer attention mechanism to extract deep design semantics, the multi-head self-attention module in the Transformer structure captures the structural association and cross-module information in the circuit, and has stronger design transferability and generalization ability, and improves the scope of application in complex circuit scenarios. Provides the compatible adaptation capability of multi-platform netlist output, and automatically maps the internally generated design data to the netlist format (such as HSPICE, NGspice format) supported by the target platform according to the EDA software standard specified by the user, ensuring compatibility with mainstream simulation platforms and improving deployment flexibility. Supporting the expansion of multiple types of design tasks such as analog circuits and integrated circuits, this method can handle complex circuit modules containing continuous time domain behavior and high-frequency signal characteristics through multi-layer feature extraction and template migration mechanisms, and has a wide range of scene adaptation capabilities. Effectively reducing the number of simulations and computing resource overhead, through advanced feature compression expression and template screening strategies, the system can quickly locate potential feasible solutions in the design space, avoid redundant simulations and exhaustive traversal, significantly shorten the circuit development cycle and save computing resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 The figure is a flow chart of the method of the present invention. DETAILED DESCRIPTION

[0007] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

[0008] like Figure 1 As shown, in one embodiment of the present invention, a method for automatically generating a circuit based on AI includes: Obtaining design indicators and storing the design indicators as structured data; the design indicators include circuit performance indicators, component indicators, circuit type indicators, and component connection methods; The attention mechanism is used to capture the dependencies between various design indicators, and the multi-layer Transformer structure is used to extract features to obtain the overall structure and high-level feature representation of the circuit. Based on the overall structure of the circuit, the high-level feature representation is matched with the standard circuit netlist template to obtain the current circuit structure. Simulate the current circuit structure, obtain a simulation report, and extract error information from the simulation report; The current circuit structure is corrected based on the error information, and the corrected circuit structure is simulated again, and the cycle is repeated several times until there are no errors in the simulation report, and the circuit structure is output.

[0009] In this embodiment, design indicators input by the user are received, such as circuit performance indicators (gain, noise, etc.), component indicators (capacitors, resistors, etc.), circuit type indicators (amplifiers, filters, etc.) and component connection methods (series, parallel, etc.). For example, the user needs to design a low-noise amplifier with an operating frequency of 2GHz-6GHz, and the requirements are as follows: "1. Operating frequency band: 2GHz-6GHz; 2. Gain: 10dB±1dB; 3. Noise figure: better than 5dB; 4. Linearity: input 1dB compression point better than -10dBm; 5. Power consumption: 40mW; 6. Circuit stability: kf greater than 1; 7. Input and output impedance: 50 ohms (S11, S22≤-10dB)." The local circuit design model analyzes the user's requirements, splits the input text into subwords through the word segmenter, and uses natural language processing technology to extract key design indicators from the word segmentation results, such as "amplifier", "low noise", "operating frequency band: 2GHz-6GHz", "noise figure: 5dB", "gain: 10dB±1dB", etc. The system then parses these design indicators and converts them into a structured data format, usually expressed in the form of key-value pairs, that is, each indicator corresponds to its specific value, which is convenient for further processing. These structured data include specific values ​​of each design requirement and its corresponding type, such as circuit type, performance requirements and parameter range.

[0010] Get the current circuit structure, specifically: According to the structured data, the relevant weights of each design indicator are calculated using normalization operations:

[0011] in, For the The relevant weights of the design indicators; For the Initial weight scores of design indicators; is the temperature coefficient; For the Initial weight scores of design indicators; The self-attention mechanism is used to calculate the dependencies between the design indicators:

[0012] in, is the dependency relationship between the current design indicator and all design indicators; is the activation function; is the query matrix, which represents the current design index; is the key matrix, which is composed of various design indicators; is the dimension of the key; is the bias term; is a value matrix, representing the weight vector associated with the design indicator; is transposed; According to the dependencies between the design indicators, the multi-layer Transformer structure is used to extract features and obtain the overall structure and high-level feature representation of the circuit; Calculate the matching score between each feature in the advanced feature representation and the embedded representation in the standard circuit netlist template, extract the embedded representation with a matching score greater than a threshold, and obtain a matching template set; Based on the overall structure of the circuit, any one embedding representation is selected from the matching templates of each feature of the high-level feature representation, and the current circuit structure is obtained based on the embedding representation selected corresponding to each feature.

[0013] In this embodiment, the converted structured data is dynamically calculated based on the attention mechanism to calculate the relevant weights of each design indicator to measure the importance and correlation of each parameter. The temperature coefficient is used to control the smoothness of the distribution. This weight is used to guide the model to focus on high-priority design requirements while ensuring that secondary parameters are not ignored. In terms of dependency capture, the self-attention mechanism is mainly used to calculate the dependencies between parameters. Through this mechanism, it is possible to automatically learn which design indicators have strong correlations, such as gain, noise figure, and linearity, which often affect each other in amplifiers, thereby optimizing the design scheme. The captured dependencies will be used to guide the feature extraction process of the Transformer layer to ensure that the network pays attention to the core constraints of the circuit design.

[0014] According to the dependencies between the design indicators, a multi-layer Transformer structure is used to extract features to obtain the overall structure and high-level feature representation of the circuit, including: The first layer Transformer structure is used to extract local parameter relationships based on the dependencies between various design indicators; The second layer Transformer structure is used to extract global features based on local parameter relationships; The third-layer Transformer structure is used to extract the overall structure and high-level feature representation of the circuit based on global features, combined with circuit templates and historical circuit design cases.

[0015] According to the dependency relationship between the design indicators, the local parameter relationship is extracted, which is as follows: The structured data is linearly transformed and positionally encoded to obtain the circuit extraction input data:

[0016] in, extracting a query vector of input data for the circuit; For structured data; , and All are trainable weight matrices; Extracting a key vector of input data for the circuit; extracting a value vector of input data for the circuit; The input data extracted by the circuit is input into the multi-head self-attention mechanism to obtain the local parameter relationship; the bias term of the multi-head self-attention mechanism of the first layer Transformer structure is the dependency relationship between the design indicators.

[0017] The expression of the global feature is:

[0018] in, It is a global feature; It is the layer normalization operation; is the intermediate representation; It is a feed-forward neural network; is the local parameter relationship; , and Both are trainable weight matrices that map data into vectors.

[0019] The overall structure and high-level features of the circuit are expressed as:

[0020] in, is the overall structure of the circuit; Generate functions for structures; is the hidden state of the final fusion; is the activation function; is a structural mapping matrix used to project the high-dimensional feature space into the structural label space; A circuit feature representation that combines the structural semantics of the current circuit state and historical circuit templates; is the bias vector; For connection operation; It is a global feature; Encoding for historical circuits; is the fusion weight matrix; For high-level feature representation; is the hidden state used to obtain the final fusion Extract key design features from high-dimensional feature mapping functions; It is a high-dimensional mapping layer; is global average pooling; is the weight of the high-dimensional mapping layer; is the number of structural units in the circuit; is the final feature sequence after fusion; is the bias of the high-dimensional mapping layer.

[0021] In this embodiment, in the Transformer structure, the input data is a processed circuit design parameter matrix, which is composed of structured design indicators extracted in the early stage, including circuit performance indicators, component indicators, circuit type indicators, and component connection methods, etc. After encoding and normalization, a numerical input format acceptable to the model is formed. Each layer of Transformer blocks consists of a multi-head self-attention mechanism and a feedforward neural network. The output of the previous layer is used as the input of the next layer, so that the model can learn the feature relationships of different levels in depth. The first layer mainly learns local parameter relationships, such as the matching between frequency range and gain.

[0022] The first-layer attention mechanism introduces dependencies between design indicators (such as voltage-current relationship, gain-frequency coupling, etc.) as explicit bias information into the attention score calculation. Specifically, when calculating the attention score, the bias term is composed of the extracted design dependency matrix to strengthen the focus on the intrinsic coupling between key design indicators. Through this mechanism, the attention distribution can be guided to be closer to the circuit design logic during the feature aggregation process, thereby improving the ability to model circuit behavior characteristics.

[0023] The middle layer focuses on global features, including circuit stability and power optimization; after receiving the output of the previous layer After that, this layer processes its input again through the multi-head attention mechanism, and combines residual connection with layer normalization. The data processing flow formula is as follows:

[0024] in, Represents the intermediate feature representation from the previous layer, which encodes the parameter information of the preliminary representation of each circuit component (such as resistors, capacitors, transistors, etc.) and their topological connection structure. , and is the trainable weight matrix in the first layer of attention mechanism, which is used to transform the input features Mapped into query, key, and value vectors. In this task, Query represents the structural requirements or target characteristics of the current circuit element, Key represents the response characteristics of other components, and Value is the actual feature vector used for information aggregation. The attention module calculates the similarity between Query and Key (i.e., the coupling degree between components, such as signal path correlation and electrical parameter influence) to obtain the attention weight, thereby performing weighted aggregation on the Value vector to achieve modeling of the global circuit dependency structure.

[0025] The obtained Attention output and the original input Add (residual connection), and then normalize through LayerNorm to get the intermediate representation , effectively alleviating the problem of gradient vanishing and feature drift. Subsequently, the feed-forward neural network FFN (generally two linear layers + ReLU activation function) is used to further Perform nonlinear transformation to improve the ability to express complex circuit modes (such as feedback structures, coupling paths, etc.), and finally perform LayerNorm again to obtain As the output of the current layer.

[0026] In this process, the Attention layer can explicitly model the physical and structural associations between components, while FFN is used to enhance the nonlinear combination capabilities of local features. The combination of the two helps to unify the expression of circuit structure and behavior modeling. This layer enhances the global semantic understanding capabilities while retaining the original features, such as overall circuit stability, noise sensitivity, and power consumption path.

[0027] Subsequent layers further combine circuit templates and historical circuit design cases to extract the overall structure and high-level feature representation of the circuit. In the initialization stage, the initial feature vector of the task will be extracted based on the user's circuit requirements, including structural dimensions (such as the number of components, coupling relationships), parameter distribution (such as statistical characteristics of voltage, resistance, and capacitance), and performance index requirements (such as frequency response, gain range, etc.). These feature vectors are mapped through a lightweight encoding network and input into a pre-trained circuit family classifier to determine the most likely matching circuit type for the task (such as amplifiers, filters, regulators, etc.), and dynamically set the number of layers of the Transformer network based on the task complexity score (such as nonlinearity, parameter span). In scenarios with complex structures or higher design goals, the number of layers of the Transformer network can be expanded, and the effective modeling of multi-level structures, complex topologies, and long-range dependencies of circuits can be achieved through automatic adjustment of the number of layers. This process uses a multi-layer Transformer network to classify the output features of the previous layer. Historical circuit coding Fusion is performed to enhance the ability to recognize different design styles and typical modules.

[0028] In this embodiment, structure migration and high-level expression generation are achieved by matching the structure encoding (such as topological features, component layout diagram) in the template library with the feature representation state of the current circuit design. The structure generation function is used to extract visual structure information from the high-dimensional representation, such as the topological connection matrix, module boundaries, etc.

[0029] In this embodiment, the fused circuit feature representation combines the structural semantics of the current circuit state and the historical circuit template; It is a structural mapping matrix, which is used to project the high-dimensional feature space into the structural label space; is the bias vector; is an optional activation function (such as softmax or sigmoid) used to generate module belonging probability or edge connection strength; output S Represents a set of structural matrices, including intermediate visualization structural information such as topological connection matrix A and module boundary vector M.

[0030] In this embodiment, The key design features are extracted from the function, which is a specific mapping function designed by combining Transformer output, structural encoding, and historical case representation. Represents the final feature sequence after fusion; GlobalAvgPool averages the feature vectors of all positions to extract the global circuit behavior representation; , is the weight and bias of the high-dimensional mapping layer (MLP); output FRepresents the extracted key design feature vector.

[0031] In this embodiment, Represents the high-level circuit feature vector extracted from the fusion module, covering key design indicators such as noise margin, power stability coefficient, reliability score, etc. The expression for the matching score is:

[0032] in, for and The matching score of Calculate the cosine similarity function; The first Features For the Embedding representation; is the norm of the vector.

[0033] In this embodiment, in order to further determine the degree of matching between the current design and each template in the template library, a matching scoring mechanism based on cosine similarity is introduced. According to the matching results, a group of template structures that are highly relevant to the current design are screened out to form a matching template set. This set not only provides a reference framework for structure generation, but also provides candidate solutions for subsequent circuit topology fine-tuning: on the one hand, a preliminary circuit structure can be quickly generated based on the typical connection mode and component configuration in the matching template; on the other hand, by comparing the structural differences between the matching template and the current design, fine-tuning can be guided at key nodes (such as adjusting module boundaries, inserting or replacing components, optimizing connection paths, etc.), thereby improving the performance and feasibility of the circuit and reducing design risks.

[0034] When the EDA software specified in the user input corresponds to the standard netlist format stored in the knowledge base, the circuit design data (including component types, connection relationships, parameter values, etc.) generated is structured and mapped into a standard netlist representation format that meets the parsing requirements of the target EDA tool based on the circuit template associated with the successfully matched high-level features in the previous text. These successfully matched features have clear structural guidance and parameter settings, so they can be directly used in the netlist generation process. For high-level features that fail to successfully match the template, the backtracking mechanism will be enabled. Based on the experience of similar designs in historical circuit cases, the most likely circuit structure or parameter configuration will be inferred for completion to ensure the correctness and compatibility of subsequent simulation and verification processes. The symbols corresponding to each key entity are extracted from the component symbol library for one-to-one correspondence. The key entity is automatically identified from the circuit template based on the user's circuit design requirements and reasoning model. For example, based on the functional requirements of the design (such as low-noise amplifiers, filters, etc.), the circuit modules involved (such as transistors, operational amplifiers, etc.) are identified. Match the component models required for the design with the process library (PDK) provided by the process manufacturer. The component models required for the design refer to the specific models of each component in the standard component library that meet the circuit design requirements (such as capacitor, resistor, transistor, etc.). These models include the electrical characteristics, behavior models and corresponding physical structures of the components. By matching with the component information in the process library, the specific required process is determined.

[0035] Combined with the circuit templates, component libraries, circuit standard design rules and historical circuit design cases in the knowledge base, the appropriate circuit template (such as common amplifier, filter and other module structures) is automatically selected according to the user's circuit design needs to provide a basic framework for the design. The circuit template includes not only the structure of the function implementation, but also the common module connection method and layout. The component library provides specific component models, parameters and symbols for each circuit module. According to the module defined in the template, the appropriate components are automatically selected from the component library and given appropriate electrical characteristics and symbols to ensure the accuracy and feasibility of the design. The circuit standard design rules ensure that the design meets various constraints (such as netlist writing format, component parameters, etc.), and ensure the validity of the design through automated checks to avoid errors or non-standard situations in the design process. In addition, historical circuit design cases provide successful experiences and failure lessons of similar designs. By comparing the characteristics of the current design with the designs in historical cases, potential design problems can be identified, and successful experiences can be learned or repeated to optimize the current design.

[0036] On this basis, the circuit parameters (such as resistance value, voltage value, frequency, etc.) in the user's requirements are first preprocessed, mainly using normalization, discretization encoding and other methods to convert physical quantities into computable numerical representations to enhance the method's parsability and generalization capabilities. These circuit parameters specifically refer to the technical indicators of each component in the circuit, such as resistance, capacitance, voltage, current frequency, etc. After preprocessing, the data can be scaled to facilitate subsequent reasoning calculations. Subsequently, the model will extract the high-dimensional feature vector of the circuit by calculating key circuit features such as resonant frequency, gain characteristics, and impedance matching parameters. The calculation of the resonant frequency is based on the formula of the LC circuit or RC circuit, the gain characteristics are obtained by the gain calculation formula, and the impedance matching parameters are calculated by calculating the matching degree of the input and output impedances and the load impedance. These key features are used to construct the high-dimensional feature vector of the circuit, representing the electrical performance and behavioral characteristics of the circuit. Then, the high-dimensional feature vector is converted into a compact low-dimensional feature representation through dimensionality reduction methods (such as PCA or autoencoder), which can reduce the computational complexity and improve the matching efficiency. Finally, these compact feature representations are used as query vectors, not only to match the netlist encoding in the structural template library, but also to assist in querying the historical circuit designs in the cache to introduce empirical structures or parameter settings, thereby improving the rationality and convergence speed of the design. The data of historical circuit designs are usually stored in the form of vectors, including component parameters, circuit characteristics, and performance indicators (such as gain, frequency response, stability, etc.). These historical design vectors are matched with the query vector of the current design by calculating similarity (such as cosine similarity or Euclidean distance), so as to find the historical design that is most similar to the current design, and perform recursive reasoning and optimization based on this design.

[0037] When the calculated similarity between the input feature and the key-value pair in the cache exceeds the set threshold, the most relevant circuit pattern (i.e., the circuit structure similar to the current design requirements) is dynamically retrieved, and the neural units related to "symbol recognition, formula matching, and netlist generation" are gradually triggered.

[0038] Among them, the symbol recognition neuron extracts the symbol features of components through self-supervised learning, and combines the graph neural network for pattern matching and connection rule analysis to identify the circuit topology and construct a preliminary circuit diagram representation. In this process, the calculated circuit parameters (such as resistance, voltage, frequency, etc.) and circuit characteristics (such as resonant frequency, gain characteristics, impedance matching parameters, etc.) are used as input data to help understand the electrical behavior and performance indicators of each component. The symbol recognition neuron uses self-supervised learning to extract the symbol features of each component from the circuit template, such as the graphic symbols of components such as resistors, capacitors, and transistors, and constructs a high-dimensional feature representation of the symbol by learning the relationship between the geometry, size and electrical parameters of each symbol. The graph neural network captures the graph structure information of components in the circuit as nodes and electrical connections between components as edges, analyzes the characteristics of nodes and edges, and identifies the relationship between different circuit modules (such as the connection method of gain amplifiers and filters). In the process of pattern matching, not only the relationship between electrical connections is analyzed, but also matching is combined with symbol features to ensure the accurate identification of the layout of circuit modules and electrical connections. Based on the analysis of graph neural networks, symbol recognition neurons can infer the topological structure of the circuit and establish a preliminary circuit diagram representation, which in turn provides a basis for subsequent netlist generation and circuit simulation. This circuit diagram representation includes the specific location of components, connection methods, and the electrical relationship between them. It is not just the arrangement of components, but also a structured representation that includes electrical characteristics, which can provide an accurate preliminary design framework for circuit optimization and verification.

[0039] Formula matching neurons search for optimal circuit equations through the attention mechanism, and calculate and match the extracted feature parameters with these circuit equations to derive key circuit indicators such as resonant frequency, gain, impedance, etc. The calculated circuit parameters (such as resistance, capacitance, voltage, frequency, etc.) and circuit characteristics (such as gain, frequency response, etc.) are used as input to help formula matching neurons accurately find equations suitable for the current circuit design. Specifically, the attention mechanism enables neurons to prioritize the most relevant equations for matching among a large number of possible circuit equations. After matching, neurons further derive circuit performance indicators such as resonant frequency (according to the formula of LC circuit or RC circuit), gain (through gain calculation formula) and impedance (by analyzing the matching degree of input and output impedance and load impedance). Through these calculation results, neurons can optimize and adjust the key parameters of the circuit to ensure that the circuit performance meets the design requirements and standards.

[0040] Based on the first two, the netlist generation neuron uses a multi-layer perceptron to perform nonlinear transformations to convert the symbolic circuit topology (circuit structure obtained through symbol recognition and graph neural networks) into a standardized circuit description language. Specifically, the symbolized circuit topology information includes component types, connection relationships, parameters, etc. The netlist generation neuron processes this information through a multi-layer perceptron, extracts the structure and behavior characteristics of the circuit, and converts it into a netlist format that meets the requirements of the EDA software. This process not only involves the standardization of circuit elements and their parameters, but also ensures that each connection relationship in the circuit complies with the netlist writing specifications. Ultimately, the neuron generates a netlist that meets the parsing requirements of simulation tools and EDA software through these transformed representations, providing a basis for subsequent simulation and verification.

[0041] During the entire reasoning process, a chain thinking prompt method is used to guide oneself to gradually disassemble the problem, generate step-by-step results in the logical order of symbol recognition, circuit parameter calculation, and netlist conversion, and analyze the inherent structure and relationship of the input data to determine whether there is ambiguity when calculating weight distribution, parameter matching results or connection relationships. Specifically, based on the calculated circuit characteristics, component parameters and circuit topology, the rule engine and deep learning model are used to identify potential conflicts or inconsistencies. For example, when performing parameter matching, if the parameters of multiple components in the circuit are inconsistent or cannot meet the predetermined design requirements, this abnormal situation will be detected, and it will be determined whether backtracking is required based on the preset tolerance threshold. Similarly, when there is ambiguity in the connection relationship, if the connection relationship of certain nodes (components) in the circuit diagram is unclear, or does not match the circuit function requirements, the backtracking mechanism will be identified and triggered.

[0042] The core of the backtracking mechanism is to make corrections based on the error type, the current netlist, and the correction suggestions. First, the ambiguous parts will be classified to identify the error type. Common error types include parameter mismatch (for example, inconsistent resistance values ​​and capacitance values), connection relationship errors (for example, signal paths are not connected, or the input and output connections of circuit modules are not appropriate), and circuit function mismatch (such as insufficient gain, frequency response does not meet requirements, etc.). For each error type, correction suggestions are generated based on historical cases, design specifications, and previous calculation results. For example, when it is found that the resistance value is not as expected, it may be recommended to change the value of the resistance, or to select a resistor of a different specification; when a connection relationship error is identified, the connection method will be automatically adjusted according to the circuit topology and functional requirements to ensure the correct signal path.

[0043] Once the error type is identified and classified, the error will be corrected through recursive reasoning based on historical design experience and optimization strategies. Specifically, part of the netlist will be regenerated based on the correction suggestions, and it will be verified whether the corrected circuit parameters and connection relationships meet the design requirements. If there are still problems with the corrected netlist, backtracking will continue to be performed, and different correction solutions will be iterated until the circuit design meets all design specifications and functional requirements.

[0044] In this way, the backtracking mechanism can not only automatically identify potential problems in circuit design, but also perform precise repairs based on error types and correction suggestions, thereby ensuring the accuracy and feasibility of circuit design.

[0045] After all key steps are completed, the complete netlist file is finally output and integrated to meet the standard syntax format requirements of the simulation software.

[0046] The error information includes the error type and error location.

[0047] Based on the error information, the current circuit structure is corrected, specifically: Based on the error location, find the corresponding node and take the preset corrective action based on the error type.

[0048] In this embodiment, the local computer automatically establishes protocol communication with the server, calls the EDA tool installed in the server, and the EDA software in the server performs simulation test on the netlist, returns the generated simulation results to the local computer, automatically creates a log file, and saves the simulation results; Error diagnosis and correction module: First, parse the simulation log to identify the error types in the netlist, including syntax errors (such as missing component parameters and incorrect connection formats), physical constraint violations (such as impedance mismatch and abnormal bias points), and circuit performance deviations (such as gain and noise figure exceeding the design range).

[0049] Then, error information is extracted based on regular expressions and AST parsing. Error information usually includes the following categories: The first is the error type, which is the specific type of problem detected in the circuit design, such as parameter mismatch, connection error, circuit function mismatch, etc. The second is the error location, which indicates the specific location where the error occurred, such as the pin connection error of a specific component, or a signal path is not connected correctly. The error description is a specific description of the problem, such as "the resistance value is out of the allowable range" or "the input port is not connected to a suitable voltage source." In addition, the contextual information of the error is also included, such as the relevant circuit parameters (such as the specific values ​​of resistance and capacitance) and connection status (such as the path of the connection line and the position of the component) when the error occurs.

[0050] The data expression of these error messages is in structured text or digital format. For example, error messages can be converted into JSON format, which contains the following fields: error type, error location, error description, context parameters, etc. Specifically, each component and its connection relationship will be identified by parsing the netlist and graphic information of the circuit design, and then regular expressions will be used to match the formulas or connection expressions in the circuit design to extract potential errors. For example, when analyzing resistors, it may be detected that the value of a resistor does not meet the design specifications, or when connecting two components, the signal line is not correctly connected to the circuit.

[0051] These error messages are extracted and used as input data for further analysis. After receiving these input data, historical design experience and optimization strategies are used to generate correction suggestions, which include but are not limited to adjusting parameters, rearranging circuit connections, replacing components, etc. In this way, errors can be automatically identified and fixed in circuit design, thereby improving the accuracy and efficiency of the design.

[0052] During the iterative correction process, the netlist is dynamically adjusted according to the error category. For syntax errors, the syntax problems in the circuit description are first identified, such as incorrect component connections, incorrect component symbols, or expressions that do not conform to the netlist writing specifications. Syntax errors usually occur when the netlist format is incorrect, for example, the connection expression between components is illegal, or the description of electrical parameters does not conform to the prescribed format (such as parameter unit errors). When correcting these errors, the non-compliant parts will be automatically modified based on the rules of regular expressions and standard netlist formats, and converted into a correct structure that meets the grammatical requirements. The modified netlist will be restored to a valid representation that conforms to the standard netlist format and can continue to be input into the simulation software for subsequent processing.

[0053] For parameter anomalies, this usually refers to physical constraint violations in circuit design, such as component values ​​that exceed the specified tolerance range (for example, the resistance value is too small or the capacitance value is too large), or the electrical characteristics in the circuit design (such as current, voltage) exceed the maximum tolerance of the components. By comparing with historical circuit design cases, common parameter settings in similar designs are analyzed, and the parameters in the current design are adjusted based on these historical data. For example, when it is found that the resistance value exceeds the preset range, the successful design in the historical case may be referred to, and a suitable resistance value that meets the circuit performance requirements may be selected and automatically adjusted. The adjusted parameters will be reflected in the new netlist to ensure that the circuit design is within the physical constraints.

[0054] For circuit performance deviation, this usually refers to the difference between the simulation results and the design goals, such as the failure of parameters such as gain, frequency response, and power consumption to meet the predetermined goals. First, the source and key factors of the deviation are identified by calculating the deviation between the design goals and the simulation results. Based on these deviations, the circuit topology and key parameters (such as component values, bias point settings, etc.) are analyzed and corrected. Specifically, if the simulation results show insufficient gain, the bias point of the gain amplifier may be adjusted or more suitable components may be selected, or if the frequency response does not meet the requirements, the filter parameters will be re-optimized or the component connection method will be adjusted. The correction process will be carried out on the key parts of the circuit, such as optimizing the input and output impedance of the circuit, adjusting the frequency response curve, etc., to ensure that the design can meet the target requirements. Each revised netlist will be re-entered into the simulation software for verification until the simulation results meet the design requirements.

Claims

1. A method for automatically generating circuits based on AI, characterized in that: include: Obtain design indicators and store the design indicators as structured data; The design indicators include circuit performance indicators, component indicators, circuit type indicators and component connection methods; The attention mechanism is used to capture the dependencies between various design indicators, and the multi-layer Transformer structure is used to extract features to obtain the overall structure and high-level feature representation of the circuit. Based on the overall structure of the circuit, the high-level feature representation is matched with the standard circuit netlist template to obtain the current circuit structure. Simulate the current circuit structure, obtain a simulation report, and extract error information from the simulation report; The current circuit structure is corrected based on the error information, and the corrected circuit structure is simulated again, and the cycle is repeated several times until there are no errors in the simulation report, and the circuit structure is output.

2. The method for automatically generating circuits based on AI according to claim 1, characterized in that: The current circuit structure is obtained as follows: According to the structured data, the relevant weights of each design indicator are calculated using normalization operations: in, For the The relevant weights of the design indicators; For the Initial weight scores of design indicators; is the temperature coefficient; For the Initial weight scores of design indicators; The self-attention mechanism is used to calculate the dependencies between the design indicators: in, is the dependency relationship between the current design indicator and all design indicators; is the activation function; is the query matrix, which represents the current design index; is the key matrix, which is composed of various design indicators; is the dimension of the key; is the bias term; is a value matrix, representing the weight vector associated with the design indicator; is transposed; According to the dependencies between the design indicators, the multi-layer Transformer structure is used to extract features and obtain the overall structure and high-level feature representation of the circuit; Calculate the matching score between each feature in the advanced feature representation and the embedded representation in the standard circuit netlist template, extract the embedded representation with a matching score greater than a threshold, and obtain a matching template set; Based on the overall structure of the circuit, any one embedding representation is selected from the matching templates of each feature of the high-level feature representation, and the current circuit structure is obtained based on the embedding representation selected corresponding to each feature.

3. The method for automatically generating circuits based on AI according to claim 2, characterized in that: According to the dependency relationship between the design indicators, the multi-layer Transformer structure is used to extract features to obtain the overall structure and high-level feature representation of the circuit, which specifically includes: The first layer Transformer structure is used to extract local parameter relationships based on the dependencies between various design indicators; The second layer Transformer structure is used to extract global features based on local parameter relationships; The third-layer Transformer structure is used to extract the overall structure and high-level feature representation of the circuit based on global features, combined with circuit templates and historical circuit design cases.

4. The method for automatically generating circuits based on AI according to claim 3, characterized in that: The local parameter relationship is extracted according to the dependency relationship between the design indicators, specifically: The structured data is linearly transformed and positionally encoded to obtain the circuit extraction input data: in, extracting a query vector of input data for the circuit; For structured data; , and All are trainable weight matrices; Extracting a key vector of input data for the circuit; extracting a value vector of input data for the circuit; The input data extracted by the circuit is input into the multi-head self-attention mechanism to obtain the local parameter relationship; the bias term of the multi-head self-attention mechanism of the first layer Transformer structure is the dependency relationship between the design indicators.

5. The method for automatically generating circuits based on AI according to claim 3, characterized in that: The expression of the global feature is: in, It is a global feature; It is the layer normalization operation; is the intermediate representation; It is a feed-forward neural network; is the local parameter relationship; , and Both are trainable weight matrices that map data into vectors.

6. The method for automatically generating circuits based on AI according to claim 3, characterized in that: The overall structure and high-level features of the circuit are expressed as: in, is the overall structure of the circuit; Generate functions for structures; is the hidden state of the final fusion; is the activation function; is a structural mapping matrix used to project the high-dimensional feature space into the structural label space; A circuit feature representation that combines the structural semantics of the current circuit state and historical circuit templates; is the bias vector; For connection operation; It is a global feature; Encoding for historical circuits; is the fusion weight matrix; For high-level feature representation; is the hidden state used to obtain the final fusion Extract key design features from high-dimensional feature mapping functions; It is a high-dimensional mapping layer; is global average pooling; is the weight of the high-dimensional mapping layer; is the number of structural units in the circuit; is the final feature sequence after fusion; is the bias of the high-dimensional mapping layer.

7. The method for automatically generating circuits based on AI according to claim 2, characterized in that: The expression of the matching score is: in, for and The matching score of Calculate the cosine similarity function; The first Features For the Embedding representation; is the norm of the vector.

8. The method for automatically generating circuits based on AI according to claim 1, characterized in that: The error information includes an error type and an error location.

9. The method for automatically generating circuits based on AI according to claim 8, characterized in that: Based on the error information, the current circuit structure is corrected, specifically: Based on the error location, find the corresponding node and take the preset corrective action based on the error type.

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