Design method of high-efficiency power amplifier

Abstract

The invention relates to the technical field of power amplifiers, and discloses a design method of a high-efficiency power amplifier, which comprises the following steps of: constructing a drain voltage and a drain current of a high-efficiency power amplifier for expanding a continuous GF-1 type mode, expanding a load admittance space and limiting a drain current peak value according to the GF-1 type mode and the continuous GF-1 type mode; according to the design method of the high-efficiency power amplifier, on the basis of GF-1 type and continuous GF-1 type high-efficiency modes, a fundamental wave load admittance design space is expanded, meanwhile, a second harmonic load admittance space is further expanded to a real part-imaginary part space, and the second harmonic load admittance space and the fundamental wave load admittance space are partially overlapped. The extended continuous GF-1 type mode high-efficiency power amplifier can span two or more frequency-doubled working bandwidths, breaks through the theoretical limitation that the continuous GF-1 type mode high-efficiency power amplifier cannot reach two frequency-doubled bandwidths, and meanwhile overcomes the problem that the drain current peak value of a continuous GF-1 type mode high-efficiency power amplifier transistor is too large.

Description

Technical Field

[0001] The present invention relates to the technical field of power amplifiers, and specifically to a design method for a high-efficiency power amplifier. Background Art

[0002] As mobile communication continues to evolve towards the new generation of wireless communication technologies, the situation of coexistence of multiple systems and standards has long existed, resulting in a large increase in the number of operating frequency bands supported by mobile communication systems. Since these operating frequency bands are discretely distributed and the frequencies of the newly added operating frequency bands are continuously increasing, the new generation of mobile communication systems must be able to operate in a wide frequency band range covering multiple octaves, which poses unprecedented challenges to the power amplifiers in mobile communication systems.

[0003] In order for a mobile communication system to have the ability to support multiple operating frequency bands, multiple narrowband power amplifiers operating in different frequency bands can be designed in a mobile communication device. However, this design method greatly increases the number of power amplifiers, system complexity, and product cost. Designing a single broadband power amplifier that can cover an extremely wide frequency range can effectively solve these problems. In addition, the power amplifier is the main energy-consuming component of the entire mobile communication system. Improving the efficiency of the power amplifier can effectively save the operating cost of the system. Therefore, exploring a design method for a single broadband high-efficiency power amplifier has broad application prospects.

[0004] For a long time, various design theories and methods for single broadband high-efficiency power amplifiers have been successively proposed and have been continuously developing. In 2018, Tushar Sharma et al. from the University of Calgary in Canada proposed a new type of GF -1 class high-efficiency mode power amplifier design method, but this mode requires unique specific fundamental and harmonic load impedances, and thus can only be applied to the design of single-frequency power amplifiers. A single-frequency high-efficiency power amplifier operating at 2.6 GHz was designed and verified. In 2021, Sina Eskandari et al. proposed a continuous GF -1 class high-efficiency mode, which greatly expands the design space of the fundamental and second-harmonic load impedances, and thus a broadband high-efficiency power amplifier with a relative bandwidth of 23.3% was designed. However, the second-harmonic load impedance of this mode must be distributed on the pure imaginary part of the Smith chart, which theoretically limits this mode from realizing a broadband high-efficiency power amplifier spanning two octaves or more. Moreover, the power amplifier designed using the continuous GF -1 class high-efficiency mode has the problem of current overshoot, that is, the peak value of the drain current of the transistor in the power amplifier may significantly exceed the maximum drain current it can withstand, resulting in unstable operation or damage of the transistor. Summary of the Invention

[0005] To solve the problem that the power amplifiers in the above existing modes cannot achieve broadband operation across more than two octaves, and that the power amplifiers designed in the continuous class-GF -1 class high-efficiency mode have the problem of current overshoot, the present invention is realized through the following technical solutions: A design method for a high-efficiency power amplifier, comprising:

[0006] S1. Construct the normalized drain voltage and drain current of the extended continuous class-GF -1 class mode power amplifier according to the class-GF -1 class mode and the continuous class-GF -1 class mode;

[0007] S2. Analyze the variation law of the normalized drain current waveform with ξ and γ according to the drain current obtained in S1. In order to limit the peak value of the drain current, initially determine the value ranges of ξ and γ; where ξ is a parameter factor in the resistance term of the drain current expression, and γ is the ratio of the second harmonic voltage to the fundamental voltage of the transistor gate;

[0008] S3. Obtain the fundamental output power and drain efficiency of the extended continuous class-GF -1 class mode power amplifier, select a GaN transistor suitable for the fundamental output power of the power amplifier, set the target drain efficiency, and further determine the ranges of ξ and γ;

[0009] S4. Obtain the fundamental load admittance, second harmonic load admittance, and third harmonic load admittance of the extended continuous class-GF -1 class mode power amplifier, and determine the load admittance design space in the Smith chart according to the ranges of ξ and γ;

[0010] S5. According to the target operating frequency band, design the output matching circuit of the power amplifier, and then convert it into a microstrip circuit. Through electromagnetic layout simulation, ensure that the circuit composed of the transistor drain parasitic parameter equivalent circuit and this microstrip circuit satisfies that the fundamental load admittance, second harmonic load admittance, and third harmonic load admittance in the operating frequency band are distributed within the load admittance design space; if not satisfied, redesign the output matching circuit;

[0011] S6. According to the target operating frequency band, design the stability circuit at the input end of the power amplifier and convert it into a microstrip circuit;

[0012] S7. Select multiple frequency points according to the target operating frequency band, obtain the optimal source impedance at each frequency point, design the input matching circuit using broadband matching technology, and convert it into a microstrip circuit;

[0013] S8. Select multiple frequency points within the operating frequency band, perform electromagnetic layout simulation on the designed power amplifier, simulate the gate voltage waveform inside the transistor, and compare it with the theoretical continuous class-GF -1Compare the gate voltage waveforms of different γ ranges in the class mode to obtain the γ range of the designed power amplifier, and determine that this range includes the γ range obtained in S3; otherwise, return to S6 to redesign the stabilization circuit and the input matching circuit;

[0014] S9. Select multiple frequency points within the operating frequency band, perform electromagnetic layout simulation on the designed power amplifier, and determine that the drain voltage and drain current waveforms on the drain current surface of the transistor are the same as those of the GF -1 class mode and continuous GF -1 class mode, and the peak value of the drain current is near the maximum limit current of the transistor; otherwise, return to S5 to redesign the output matching circuit, the stabilization circuit and the input matching circuit.

[0015] Furthermore, the extended continuous GF in S1 -1 The normalized drain voltage of the class mode power amplifier follows that of the GF -1 class mode, continuous GF -1 class mode, specifically:

[0016]

[0017] Extended continuous GF -1 The drain current of the class mode power amplifier is obtained by adding an additional resistance term to the drain current of the continuous GF -1 class mode, and the resistance term is 1 + ξcosθ. The drain current of the extended continuous GF -1 class mode power amplifier is specifically:

[0018]

[0019] In the formula, θ is the angular frequency, α is the conduction angle, β is the zero-crossing cut-off angle, γ is the ratio of the second harmonic voltage to the fundamental voltage of the transistor gate, I m is the peak drain current, i r2 is the real part of the second harmonic drain current; δ takes values between -1 and 1, and ξ takes values between -1 and 1.

[0020] Furthermore, determining the initial value ranges of γ and ξ is also included in S2, specifically including:

[0021] By analyzing the variation law of the normalized drain current waveform of the extended GF -1 class mode with respect to γ and ξ, considering the peak value of the restricted drain current, initially determine the ranges of γ and ξ, that is, γ ≤ 0 and ξ ≤ 0;

[0022] Furthermore, S3 is specifically:

[0023] Utilize the GF -1The approximate form of the class-mode drain current expanded as a Fourier series of the third harmonic is used to extend the continuous GF -1 Calculate the drain current of the class-mode power amplifier:

[0024]

[0025] where is the DC component of the GF -1 class-mode drain current, is the fundamental component of this drain current, is the second harmonic component of this drain current, is the third harmonic component of this drain current;

[0026] After performing Fourier series expansion and combining like terms on the calculated drain current, the extended continuous GF -1 The DC component, the real and imaginary parts of the fundamental component, the real and imaginary parts of the second harmonic component of the class-mode drain current are respectively:

[0027]

[0028]

[0029] where is the DC component of the extended continuous GF -1 class-mode drain current, is the real part of the fundamental component of this drain current, is the imaginary part of the fundamental component of this drain current, is the real part of the second harmonic component of this drain current, is the imaginary part of the second harmonic component of this drain current;

[0030] Using the DC component and the real part of the fundamental component in the drain voltage of the extended continuous GF -1 class-mode power amplifier and the extended continuous GF -1 Derive the real part of the class-mode drain current, and the fundamental output power and drain efficiency of the extended continuous GF -1 class-mode power amplifier are respectively:

[0031]

[0032] where V dc and V knee are the transistor drain supply voltage and the knee voltage respectively, is the fundamental output power of the extended continuous GF -1 class-mode power amplifier, is the drain efficiency of this mode power amplifier;

[0033] Select a GaN transistor suitable for the fundamental output power of the power amplifier. Based on the supply voltage, maximum peak drain current, and knee voltage of the transistor, establish a three-dimensional surface plot of the fundamental output power and drain efficiency varying with γ and ξ. According to the set range of the condition of the drain efficiency, further determine the value ranges of γ and ξ.

[0034] Further, in step S4, determine the optimal load admittance design space in the Smith chart, specifically as follows:

[0035] Utilize the extended continuous GF -1 The drain voltage of the class-F mode power amplifier and the extended continuous GF -1 The DC component, real and imaginary parts of the fundamental component, and real and imaginary parts of the second harmonic component of the drain current of the class-F mode, and derive the extended continuous GF -1 The fundamental load admittance and second harmonic load admittance of the class-F mode:

[0036]

[0037] In the formula, V dc and V knee are respectively the supply voltage of the transistor drain and the knee voltage. is the fundamental load admittance. is the second harmonic load admittance. is the third harmonic load admittance. The extended continuous GF -1 The establishment of the third harmonic load admittance of the class-F mode takes into account that the drain-source capacitance inside the transistor is short-circuited at the frequency of the third harmonic.

[0038] By setting ξ = 0, the fundamental load admittance, second harmonic load admittance, and third harmonic load admittance of the extended continuous GF -1 class-F mode can be determined. The theoretical results of the fundamental load admittance, second harmonic load admittance, and third harmonic load admittance of the class-F mode are consistent with those of the typical continuous GF -1 class-F mode, thereby verifying the accuracy of the real and imaginary parts of the fundamental component and second harmonic component of the drain current of the derived extended continuous GF -1 class-F mode, fundamental load admittance, second harmonic, and third harmonic load admittances.

[0039] According to the extended continuous GF -1 class-F mode second harmonic load admittance, if ξ > 0, the real part of the second harmonic load admittance is negative, which is impossible in the actual power amplifier design. Determine that the value of ξ must be less than or equal to 0.

[0040] According to the value ranges of ξ and γ obtained in step S3, and -1 ≤ δ ≤ 1, from the extended continuous GF-1 The fundamental harmonic load admittance, second harmonic load admittance, and third harmonic load admittance of the class mode jointly determine the load admittance design space in the Smith chart, including the fundamental harmonic load admittance space, second harmonic load admittance space, and third harmonic load admittance space.

[0041] Furthermore, the specific content of S5 is as follows:

[0042] According to the target operating frequency band, select an appropriate broadband matching technology and high-frequency circuit substrate to design the output matching microstrip circuit of the power amplifier. At the same time, combine the transistor drain parasitic parameter equivalent circuit and the output matching microstrip circuit for electromagnetic simulation to ensure that the fundamental harmonic load admittance and second harmonic load admittance obtained on the transistor current surface are distributed within the load admittance design space, and the third harmonic load admittance is located within the range set near the short-circuit point determined by the third harmonic load admittance space in the load admittance space; if not satisfied, redesign the output matching circuit.

[0043] Furthermore, the specific content of S6 is as follows:

[0044] According to the target operating frequency band, design the stability circuit at the input end of the power amplifier and convert it into a microstrip circuit. The selected high-frequency circuit substrate is the same as that in S5. Ensure that the stability factor including the stability circuit, transistor, and output matching circuit is greater than 1 within the operating frequency band through electromagnetic layout simulation.

[0045] Furthermore, the specific content of S7 is as follows:

[0046] Reasonably select multiple frequency points according to the operating frequency band, perform source pulling on the input end of the power amplifier including the stability circuit, transistor, and output matching circuit. After obtaining the optimal source impedance at each frequency point, use broadband matching technology to design the input matching circuit and convert it into a microstrip circuit on the same high-frequency circuit substrate as S5; ensure that the gain, fundamental harmonic output power, and drain efficiency of the designed power amplifier meet the target requirements within the operating frequency band through electromagnetic layout simulation and adjusting the parameters of the input matching circuit.

[0047] Compared with the prior art, the present invention has the following beneficial effects:

[0048] 1. The design method of this high-efficiency power amplifier expands the fundamental harmonic load impedance design space on the basis of the GF -1 class and continuous GF -1 class high-efficiency modes. At the same time, further expand the second harmonic load impedance space to the real part - imaginary part space and partially overlap it with the fundamental harmonic load impedance space. Based on this, the designed extended continuous GF -1 class mode broadband high-efficiency power amplifier can span a working bandwidth of more than two octaves, breaking through the continuous GF -1The second harmonic load admittance of the class-mode high-efficiency power amplifier must be distributed on the pure imaginary part of the Smith chart and cannot reach the theoretical limit of two octave bandwidths.

[0049] 2. The design method of this high-efficiency power amplifier can effectively limit the peak value of the drain current of the power amplifier transistor, solve the problem of current overshoot in the class-mode high-efficiency power amplifier, and maintain the long-term stable operation of the transistor. -1 The high-efficiency power amplifier in class mode has a problem of current overshoot, and maintaining the long-term stable operation of the transistor.

[0050] 3. The design method of this high-efficiency power amplifier designs an extended continuous class-mode power amplifier that can maintain the same level of operating bandwidth, gain, output power, and drain efficiency as the most advanced power amplifiers designed using other extended continuous class-mode designs. -1 The class-mode power amplifier can maintain the same level of operating bandwidth, gain, output power, and drain efficiency as the most advanced power amplifiers designed using other extended continuous class-mode designs. Brief Description of the Drawings

[0051] Figure 1 Schematic diagram of the normalized drain voltage and current waveforms of the extended continuous class of the present invention; -1

[0052] Figure 2 Schematic diagrams showing the relationship between the fundamental output power and γ and ξ, and the relationship between the drain efficiency and γ and ξ in the embodiments of the present invention;

[0053] Figure 3 Schematic diagram of the load admittance design space of the extended continuous class mode on the transistor current plane in the embodiments of the present invention; -1

[0054] Figure 4 Schematic diagram of the load admittance trajectory of the circuit composed of the transistor parasitic parameter equivalent circuit and the output matching circuit on the transistor current plane in the embodiments of the present invention;

[0055] Figure 5 Schematic diagram and physical diagram in the embodiments of the present invention;

[0056] Figure 6 Schematic diagram of the trajectory of the internal gate-source impedance of the simulated transistor varying with frequency and the internal gate voltage waveform of the transistor at 0.6 and 3.2 GHz in the embodiments of the present invention;

[0057] Figure 7 Schematic diagrams showing the relationship between the simulated and tested gain, output power, and drain efficiency varying with frequency in the embodiments of the present invention;

[0058] Figure 8 Schematic diagrams of the simulated drain voltage and current waveforms at 0.6 GHz and the simulated drain voltage and current waveforms at 3.2 GHz in the embodiments of the present invention;

[0059] Figure 9 Schematic diagrams showing the relationships between the output power, gain, and drain efficiency in simulation and in testing of the present invention's embodiment as functions of the input power. Detailed implementation manners

[0060] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0061] An embodiment of the design method of the high-efficiency power amplifier is as follows:

[0062] Please refer to Figures 1-9 , a design method of a high-efficiency power amplifier, including:

[0063] S1. Construct the normalized drain voltage and drain current of the extended continuous Class-GF mode power amplifier according to the Class-GF mode and the continuous Class-GF mode: -1 The Class-GF mode, continuous Class-GF -1 The normalized drain voltage of the extended continuous Class-GF -1 mode power amplifier follows that of the Class-GF mode and the continuous Class-GF mode. Specifically:

[0064] The normalized drain voltage of the extended continuous Class-GF -1 mode power amplifier is the same as that of the Class-GF mode and the continuous Class-GF mode. Specifically: -1 The Class-GF mode, continuous Class-GF -1 mode. Specifically:

[0065]

[0066] The drain current of the extended continuous Class-GF -1 mode power amplifier is obtained by adding an additional resistance term to the drain current of the continuous Class-GF -1 mode. The resistance term is 1 + ξcosθ. The drain current of the extended continuous Class-GF -1 mode power amplifier is specifically:

[0067]

[0068] In the formula, θ is the angular frequency, α is the conduction angle, β is the zero-crossing cut-off angle, γ is the ratio of the second harmonic voltage to the fundamental voltage of the transistor gate, I m is the drain peak current, and i r2 is the real part of the second harmonic drain current; δ takes values between -1 and 1, and ξ takes values between -1 and 1. When δ = ξ = 0, this drain current expression is the same as that of the typical Class-GF -1The drain currents of the class modes are the same. In addition, the resistance term 1 + ξcosθ in Equation (2) can change the amplitude of the drain current.

[0069] S2. Analyze the variation law of the normalized drain current waveform with ξ and γ based on the drain current obtained in S1. To limit the peak value of the drain current, preliminarily determine the value ranges of ξ and γ. Here, ξ is a parameter factor in the resistance term of the drain current expression, and γ is the ratio of the second harmonic voltage to the fundamental voltage of the transistor gate; from Figure 1 it can be seen that when keeping δ unchanged and γ > 0, the drain current will increase significantly as γ increases. Especially when δ = ±1, the peak value of the drain current is the largest. Figure 1 The waveforms of (b), (e), and (h) in -1 are consistent with the waveforms of the continuous GF Figure 1 class mode. When γ > 0, the current overshoot problem may occur. According to -1 in (c), (f), and (i), it can be found that when ξ > 0, the significantly increased peak value of the drain current will inevitably cause the current overshoot problem. Therefore, choosing the ranges of ξ ≤ 0 and γ ≤ 0 can effectively prevent the current overshoot problem from occurring in the power amplifier of the extended continuous GF

[0070] Set the ranges of ξ and γ. Here, Figure 1 in the extended continuous GF -1 class, γ = -0.5 in (a)-(c) of the normalized drain voltage and current waveforms, γ = 0 in (d)-(f), and γ = 0.5 in (g)-(i). By analyzing the variation law of the normalized drain current waveform of the extended GF -1 class mode with γ and ξ, considering limiting the peak value of the drain current, preliminarily determine the ranges of γ and ξ, that is, γ ≤ 0 and ξ ≤ 0.

[0071] S3. Obtain the fundamental output power and drain efficiency of the power amplifier of the extended continuous GF -1 class mode. Select a GaN transistor suitable for the fundamental output power of the power amplifier, set the target drain efficiency, and further determine the ranges of ξ and γ, specifically including:

[0072] Since it is difficult to directly perform Fourier series expansion on Equation (2), use the approximate form of the Fourier series of the drain current of the GF -1 class mode expanded into the third harmonic to calculate the drain current of the power amplifier of the extended continuous GF -1 class mode:

[0073]

[0074] In the formula, is the DC component of the drain current of the GF -1 class mode, is the fundamental component of the drain current, is the second harmonic component of the drain current, is the third harmonic component of the drain current.

[0075] After performing Fourier series expansion and combining like terms on the calculated drain current, the DC component, the real and imaginary parts of the fundamental component, and the real and imaginary parts of the second harmonic component of the extended continuous GF -1 class mode drain current are respectively:

[0076]

[0077] In the formula, is the DC component of the extended continuous GF -1 class mode drain current, is the real part of the fundamental component of the drain current, is the imaginary part of the fundamental component of the drain current,

[0078] is the real part of the second harmonic component of the drain current, is the imaginary part of the second harmonic component of the drain current.

[0079] Using the drain voltage of the extended continuous GF -1 class mode power amplifier and the DC component and the real part of the fundamental component in the extended continuous GF -1 class mode drain current for derivation, the fundamental output power and drain efficiency of the extended continuous GF -1 class mode power amplifier are respectively:

[0080]

[0081] In the formula, V dc and V knee are respectively the drain supply voltage and the knee voltage of the transistor, is the fundamental output power of the extended continuous GF -1 class mode power amplifier, is the drain efficiency of this mode power amplifier.

[0082] Select a GaN transistor suitable for the fundamental output power of the power amplifier. According to the supply voltage, the maximum peak drain current, and the knee voltage of the transistor, establish a three-dimensional surface diagram of the fundamental output power and drain efficiency varying with γ and ξ. According to the set condition range of the drain efficiency (such as greater than or equal to 70%), further determine the value ranges of γ and ξ.

[0083] S4. Obtain the extended continuous GF -1The fundamental load admittance, second harmonic load admittance, and third harmonic load admittance of the class mode power amplifier determine the load admittance design space in the Smith chart according to the ranges of ξ and γ, specifically as follows:

[0084] Using the extended continuous GF -1 The drain voltage of the class mode power amplifier and the extended continuous GF -1 The DC component, real and imaginary parts of the fundamental component, and real and imaginary parts of the second harmonic component of the class mode drain current are derived to obtain the extended continuous GF -1 The fundamental load admittance and second harmonic load admittance of the class mode:

[0085]

[0086]

[0087] In the formula, V dc and V knee are the transistor drain supply voltage and knee voltage respectively, is the fundamental load admittance, is the second harmonic load admittance, is the third harmonic load admittance, and the extended continuous GF -1 The establishment of the third harmonic load admittance of the class mode is considered because the drain-source capacitance inside the transistor is short-circuited at the frequency of the third harmonic.

[0088] By setting ξ = 0, the extended continuous GF can be determined -1 The theoretical results of the fundamental load admittance, second harmonic load admittance, and third harmonic load admittance of the class mode are consistent with those of the typical continuous GF -1 The expressions of the fundamental load admittance, second harmonic load admittance, and third harmonic load admittance of the class mode are consistent, further verifying the accuracy of the derived extended continuous GF -1 The real and imaginary parts of the fundamental component and the real and imaginary parts of the second harmonic component of the class mode drain current, and the accuracy of the fundamental load admittance, second harmonic, and third harmonic load admittances.

[0089] According to the extended continuous GF -1 For the second harmonic load admittance of the class mode, if ξ > 0, the real part of the second harmonic admittance is negative, which is impossible in the actual power amplifier design. It is determined that the value of ξ must be less than or equal to 0.

[0090] Since when γ ≤ 0, it can be calculated through equations (11)-(12) that the influence of the value of γ on the fundamental admittance and second harmonic admittance can be basically ignored, which is the same as that of the continuous GF -1The conclusion is consistent with that of the class-mode power amplifier. According to the value ranges of ξ and γ obtained in step S3, and -1 ≤ δ ≤ 1, from the extended continuous GF -1 The fundamental load admittance, second-harmonic load admittance, and third-harmonic load admittance of the class-mode jointly determine the load admittance design space in the Smith chart, including the fundamental load admittance space, second-harmonic load admittance space, and third-harmonic load admittance space. It should be noted that the calculated fundamental admittance space and second-harmonic admittance space will have an overlapping area, which provides a theoretical basis for the realization of a bandwidth spanning more than two octaves.

[0091] S5. According to the target operating frequency band, select an appropriate broadband matching technique and high-frequency circuit substrate to design the output matching microstrip circuit of the power amplifier. At the same time, combine the equivalent circuit of the transistor drain parasitic parameters and the output matching microstrip circuit for electromagnetic simulation to ensure that the fundamental load admittance and second-harmonic load admittance obtained on the transistor current surface are distributed within the load admittance design space, and the third-harmonic load admittance is located within the range set near the short-circuit point determined by the third-harmonic load admittance space in the load admittance space; if not satisfied, redesign the output matching circuit.

[0092] S6. According to the target operating frequency band, design the stability circuit at the input end of the power amplifier and convert it into a microstrip circuit. The selected high-frequency circuit substrate is the same as that in S5. Ensure that the stability factor including the stability circuit, transistor, and output matching circuit is greater than 1 within the operating frequency band through electromagnetic layout simulation.

[0093] S7. To ensure that the condition of γ ≤ 0 is satisfied, reasonably select multiple frequency points according to the operating frequency band, perform source pulling on the input end of the power amplifier including the stability circuit, transistor, and output matching circuit. After obtaining the optimal source impedance at each frequency point, use the broadband matching technique to design the input matching circuit and convert it into a microstrip circuit with the same high-frequency circuit substrate as in S5; through electromagnetic layout simulation and adjustment of the input matching circuit parameters, ensure that the gain, fundamental output power, and drain efficiency of the designed power amplifier meet the target requirements within the operating frequency band.

[0094] S8. Select multiple frequency points within the operating frequency band, perform electromagnetic layout simulation on the designed power amplifier, simulate the gate voltage waveform inside the transistor, and compare it with the gate voltage waveforms of different γ ranges in the theoretical continuous GF -1 class mode to obtain the γ range of the designed power amplifier and determine that this range includes the γ range obtained in S3; otherwise, return to S6 to redesign the stability circuit and input matching circuit to ensure that the gain, fundamental output power, and drain efficiency of the power amplifier meet the target requirements and the condition of γ ≤ 0 is satisfied within the operating frequency band.

[0095] S9. Select multiple frequency points within the operating frequency band, perform electromagnetic layout simulation on the designed power amplifier, and determine that the drain voltage and drain current waveforms on the drain current surface of the transistor are basically the same as those in the GF -1 class mode and continuous GF -1 class mode, and the peak value of the drain current is near the maximum limit current of the transistor; otherwise, return to S5, redesign the output matching circuit, stability circuit, and input matching circuit to ensure that the design specifications of the power amplifier meet the target requirements within the operating frequency band and operate in the extended continuous GF -1 class mode.

[0096] The specific implementation of the design method of this high-efficiency power amplifier is as follows:

[0097] The design goals of the broadband high-efficiency power amplifier are: operating frequency band 0.6 - 3.2 GHz, gain greater than 9.5 dB, output power greater than 39.5 dBm, and drain efficiency greater than 60% (theoretically designed according to 70%, but there are various additional losses in the actual circuit).

[0098] Select the CGH40010F HEMT transistor of Cree's GaN, and the drain DC supply voltage V dc is 28V, the conduction angle α in Equation (2) is taken as 180°, and the gate bias voltage is set to -2.9V.

[0099] According to the maximum drain current given in the CGH40010F HEMT transistor manual, set I m to 1.5A, the knee voltage V knee is 0V, and the quantitative relationships between the theoretically calculated fundamental output power and drain efficiency in -0.5 ≤ γ ≤ 0.5 and -0.7 ≤ ξ ≤ 0 by Equations (9) and (10) are as Figure 2 shown. Figure 2 In (a) is the relationship between the fundamental output power and γ and ξ, Figure 2 in (b) is the relationship between the drain efficiency and γ and ξ. According to the requirements of drain efficiency ≥ 70% and limiting the peak value of the drain current, determine -0.5 ≤ γ ≤ 0 and -0.7 ≤ ξ ≤ 0.

[0100] Set γ = -0.5, and calculate the load admittance space on the transistor current surface in the extended continuous GF -1 class mode within the range of -0.7 ≤ ξ ≤ 0 and -1 ≤ δ ≤ 1 according to Equations (11), (12), and (13) as Figure 3 shown. From Figure 3 it can be observed that when -0.7 ≤ ξ < -0.5, the fundamental load admittance and the second harmonic load admittance overlap. Under the condition of γ ≤ 0, Figure 3 the load admittance design space of

[0101] The output matching circuit of this power amplifier is designed by using a traditional low-pass Chebyshev impedance transformation network. Since the low-pass Chebyshev network itself has good second-harmonic suppression characteristics, it can naturally suppress the second-harmonic load to the edge of the Smith chart step by step. The F4BM-220 high-frequency circuit substrate produced by Wangling Company in Taizhou City is selected, with a dielectric constant ε r = 2.2 and a loss tangent tanδ = 0.001 for microstrip circuit simulation and manufacturing. The equivalent circuit of the drain parasitic parameters of the CGH40010F HEMT transistor and the output matching circuit are co-designed and simulated for optimization. Through electromagnetic layout simulation and parameter optimization, the load admittance locus on the transistor current plane at 0.6 - 3.2 GHz is obtained as Figure 4 shown. As Figure 4 can be seen, the admittances within the operating frequency band of 0.6 - 3.2 GHz are all distributed within the fundamental-wave load admittance design space, and most of them are distributed in the overlapping region of the fundamental-wave load admittance and the second-harmonic load admittance. The second-harmonic load admittances within 3.2 - 6.4 GHz are all distributed within the second-harmonic load admittance space, and the third-harmonic admittances within 6.4 - 9.6 GHz are close to the short-circuit point of the Smith chart.

[0102] The stability circuit and input matching circuit at the input end of the power amplifier are designed, and the schematic diagram and physical object of the final obtained embodiment are as Figure 5 shown. At 0.6 GHz and 3.2 GHz respectively, the gate voltage waveform inside the transistor in the electromagnetic simulation Figure 5 circuit and the internal gate-source impedance locus at 0.6 - 6.4 GHz are as Figure 6 shown. As Figure 6 can be seen, deep valleys and concavities are generated in the negative half-axis region of the gate voltage waveform inside the transistor at the two frequency points of 0.6 GHz and 3.2 GHz, verifying that the condition of γ ≤ 0 is satisfied.

[0103] The electromagnetic layout of the embodiment is simulated and the physical object of the embodiment is tested. The simulation and test results are as Figure 7 shown. Figure 7 The results show that the designed power amplifier has an output power P out of 39.8 - 42.2 dBm, a gain Gain of 9.8 - 12.2 dB, a drain efficiency DE of 61% - 78.6%, and a relative bandwidth RBW of 136.8% within 0.6 - 3.2 GHz.

[0104] The waveforms of the drain voltage and current on the current plane of the power amplifier at the two frequency points of 0.6 GHz and 3.2 GHz are simulated and designed as Figure 8 shown, Figure 8Among them, (a) shows the drain voltage and current waveforms of the 0.6 GHz simulation. Figure 8 Among them, (b) shows the drain voltage and current waveforms of the 3.2 GHz simulation. It can be seen that the peak values of the drain current at the two frequency points are around 1.5 A, which confirms that the transistor can maintain stable operation for a long time, and the drain voltage waveform is basically a half-sine rectified waveform. The drain current waveform is basically consistent with the GF -1 class mode and continuous GF -1 mode, which also confirms that the power amplifier operates in the extended continuous GF -1 class mode.

[0105] Figure 9 Among them, (a) shows the relationships of the simulated output power, gain, and drain efficiency with respect to the input power. Figure 9 Among them, (b) shows the variations of the measured output power, gain, and drain efficiency with respect to the input power. Figure 9 The relationships of the output power, gain, and drain efficiency of the designed power amplifier at 0.6 GHz, 1.9 GHz, and 3.2 GHz with respect to the input power are given. The results show that the simulation and measurement results are in good agreement.

[0106] The designed extended continuous GF -1 class mode power amplifier is compared with the state-of-the-art continuous class mode power amplifiers reported in recent years as shown in Table 1:

[0107]

[0108] The relative bandwidth of this embodiment is 138.6%. Compared with Comparative Examples 1 to 4, the operating bandwidth of this embodiment is the largest. Especially compared with the continuous GF -1 class mode power amplifier in Comparative Example 4, the operating bandwidth of this example exceeds two octaves. Compared with Comparative Examples 1 to 3, the output power of this embodiment is greater. Compared with Comparative Examples 1 and 2, the drain efficiency of this embodiment is greater. The gain, output power, and drain efficiency of this embodiment have comparable performance levels compared with other comparative examples.

[0109] Although the embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention.

Claims

1. A design method for a high-efficiency power amplifier, characterized in that: include: S1. According to GF -1 Class mode, continuous GF -1 Class pattern construction extends continuous GF -1 Normalized drain voltage and drain current of a class-mode power amplifier; S2. According to the drain current obtained in S1, the variation law of the normalized drain current waveform with ξ and γ is analyzed. In order to limit the peak value of the drain current, the value range of ξ and γ is preliminarily determined; wherein ξ is a parameter factor in the resistance term of the drain current expression, and γ is the ratio of the second harmonic voltage of the transistor gate to the fundamental voltage; S3. Get extended continuous GF -1 The fundamental output power and drain efficiency of the quasi-mode power amplifier, selecting a GaN transistor suitable for the fundamental output power of the power amplifier, setting a target drain efficiency, and further determining the range of ξ and γ; S4. Get extended continuous GF -1 The fundamental load admittance, second harmonic load admittance and third harmonic load admittance of the quasi-mode power amplifier are determined according to the range of ξ and γ to determine the load admittance design space in the Smith chart; S5. According to the target operating frequency band, design the output matching circuit of the power amplifier, and then convert it into a microstrip circuit. Through electromagnetic layout simulation, ensure that the circuit composed of the transistor drain parasitic parameter equivalent circuit and the microstrip circuit meets the fundamental load admittance, second harmonic load admittance and third harmonic load admittance distribution in the operating frequency band within the load admittance design space; if not, redesign the output matching circuit; S6. Design a stabilization circuit at the input of the power amplifier according to the target operating frequency band and convert it into a microstrip circuit; S7. Select multiple frequency points according to the target operating frequency band, obtain the best source impedance for each frequency point, design the input matching circuit using broadband matching technology, and convert it into a microstrip circuit; S8. Select multiple frequency points within the working frequency band, perform electromagnetic layout simulation on the designed power amplifier, simulate the gate voltage waveform inside the transistor, and compare it with the theoretical continuous GF -1 The gate voltage waveforms of different γ ranges of the similar mode are compared to obtain the γ range of the designed power amplifier, and it is determined that the range includes the γ range obtained in S3; otherwise, return to S6 to redesign the stabilization circuit and the input matching circuit; S9. Select multiple frequency points covering the working frequency band, perform electromagnetic layout simulation on the designed power amplifier, and determine the drain voltage and drain current waveform on the transistor drain current surface and GF -1 Class patterns and continuous GF -1 The corresponding waveforms in the class mode are basically the same, and the peak value of the drain current is near the maximum limiting current of the transistor; Otherwise, return to S5 to redesign the output matching circuit, the stabilization circuit and the input matching circuit.

2. The method for designing a high efficiency power amplifier according to claim 1, characterized in that: The extended continuous GF in S1 -1 The normalized drain voltage of the quasi-mode power amplifier follows GF -1 Class mode, continuous GF -1 The normalized drain voltage of the class mode is: Extended continuous GF -1 The drain current of a class-mode PA is an additional resistor term placed in the continuous GF -1 The resistance term is 1+ξcosθ, and the continuous GF is extended. -1 The drain current of the class-mode power amplifier is specifically: Where θ is the angular frequency, α is the conduction angle, β is the zero-crossing cutoff angle, γ is the ratio of the second harmonic voltage to the fundamental voltage at the transistor gate, and I m is the drain peak current, i r2 is the real part of the second harmonic drain current; δ takes values ​​between -1 and 1, and ξ takes values ​​between -1 and 1.

3. The design method of a high efficiency power amplifier according to claim 2, characterized in that: The S2 also includes determining the initial value range of γ and ξ, which specifically includes: Extending GF by analysis -1 The normalized drain current waveform of the quasi-mode varies with γ and ξ. Considering the peak value of the drain current, the range of γ and ξ is preliminarily determined, that is, γ≤0 and ξ≤0.

4. The design method of a high efficiency power amplifier according to claim 3, characterized in that: The S3 is specifically: Using GF -1 The quasi-mode drain current is expanded into the approximate form of the third harmonic Fourier series, which is equivalent to the extended continuous GF -1 The drain current of the class-mode power amplifier is calculated as: In the formula, It's GF -1 The DC component of the quasi-mode drain current, is the fundamental component of the drain current, is the second harmonic component of the drain current, is the third harmonic component of the drain current; The calculated drain current is expanded by Fourier series and the similar terms are combined to obtain the extended continuous GF -1 The DC component of the quasi-mode drain current, the real and imaginary parts of the fundamental component, and the real and imaginary parts of the second harmonic component are: In the formula, is an extended continuous GF -1 The DC component of the quasi-mode drain current, is the real part of the fundamental component of the drain current, is the imaginary part of the fundamental component of the drain current, is the real part of the second harmonic component of the drain current, is the imaginary part of the second harmonic component of the drain current; Using extended continuous GF -1 Drain voltage and extended continuous GF of class-mode power amplifier -1 The DC component and the real part of the fundamental component in the class-mode drain current are derived, and the continuous GF is extended in S3 -1 The fundamental output power and drain efficiency of the class-mode power amplifier are: Where V dc and V knee are the transistor drain supply voltage and knee voltage, P out,ECCGF-1 is an extended continuous GF -1 Fundamental output power of the quasi-mode power amplifier, η ECCGF-1 is the drain efficiency of the power amplifier in this mode; Select a GaN transistor suitable for the fundamental output power of the power amplifier. According to the supply voltage, maximum drain current peak and knee voltage of the transistor, establish a three-dimensional surface diagram of the fundamental output power and drain efficiency as a function of γ and ξ. According to the set conditional range of drain efficiency, further determine the value range of γ and ξ.

5. The design method of a high efficiency power amplifier according to claim 4, characterized in that: The load admittance design space in the Smith chart is determined in S4, specifically: Using extended continuous GF -1 Drain voltage and extended continuous GF of class-mode power amplifier -1 The DC component of the quasi-mode drain current, the real and imaginary parts of the fundamental component, and the real and imaginary parts of the second harmonic component are derived to obtain the extended continuous GF -1 Fundamental load admittance and second harmonic load admittance of the similar mode: Where V dc and V knee are the transistor drain supply voltage and knee voltage, respectively, is the fundamental load admittance, is the second harmonic load admittance, is the third harmonic load admittance, expanding the continuous GF -1 The third harmonic load admittance of the quasi-mode can be established because the drain-source capacitance inside the transistor is short-circuited at the frequency of the third harmonic; By setting ξ = 0, we can determine the extended continuous GF -1 Theoretical results of fundamental load admittance, second harmonic load admittance and third harmonic load admittance of similar mode and typical continuous GF -1 The expressions of the fundamental load admittance, second harmonic load admittance and third harmonic load admittance of the quasi-mode are consistent, which confirms the derived extended continuous GF -1 The accuracy of the fundamental component real and imaginary parts, second harmonic component real and imaginary parts, fundamental load admittance, second harmonic load admittance and third harmonic load admittance of the quasi-mode drain current; According to the extended continuous GF -1 The second harmonic load admittance of the quasi-mode, if ξ>0, the second harmonic admittance The real part of is a negative number, which is impossible in actual power amplifier design. It is determined that the value of ξ must be less than or equal to 0. According to the range of ξ and γ obtained in step S3, and -1≤δ≤1, the extended continuous GF -1 The fundamental load admittance, second harmonic load admittance and third harmonic load admittance of the quasi-mode jointly determine the load admittance design space in the Smith chart, including the fundamental load admittance space, the second harmonic load admittance space and the third harmonic load admittance space.

6. The design method of a high efficiency power amplifier according to claim 5, characterized in that: The S5 is specifically: According to the target operating frequency band, select appropriate broadband matching technology and high-frequency circuit substrate to design the output matching microstrip circuit of the power amplifier. At the same time, combine the transistor drain parasitic parameter equivalent circuit and the output matching microstrip circuit to perform electromagnetic simulation to ensure that the fundamental load admittance and second harmonic load admittance obtained on the transistor current plane are distributed in the load admittance design space, and the third harmonic load admittance is located in the load admittance space. The range set near the short-circuit point determined by the third harmonic load admittance space; if it is not satisfied, redesign the output matching circuit.

7. The design method of a high efficiency power amplifier according to claim 6, characterized in that: The S6 is specifically: According to the target operating frequency band, a stabilization circuit is designed at the input end of the power amplifier and converted into a microstrip circuit. The high-frequency circuit substrate selected is the same as that in S5. Electromagnetic layout simulation is used to ensure that the stability factor of the stabilization circuit, transistors, and output matching circuit within the operating frequency band is greater than 1.

8. The design method of a high efficiency power amplifier according to claim 7, characterized in that: The S7 is specifically: According to the working frequency band, multiple frequency points are reasonably selected, and the input end of the power amplifier including the stabilization circuit, transistor, and output matching circuit is source pulled. After obtaining the optimal source impedance of each frequency point, the input matching circuit is designed using broadband matching technology and converted into a microstrip circuit with the same high-frequency circuit substrate as S5; through electromagnetic layout simulation and adjustment of input matching circuit parameters, it is ensured that the gain, fundamental output power and drain efficiency of the designed power amplifier within the working frequency band meet the target requirements.

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