Layout generation method and device, electronic equipment and storage medium

Abstract

The invention relates to a layout generation method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring first information, second information, third information and fourth information; generating a target layout based on the first information, the second information, the third information and the fourth information; the target layout comprises device layouts of the plurality of to-be-tested devices, a device layout of the at least one test device and a connection relationship between the plurality of to-be-tested devices and the at least one test device. According to the method provided by the embodiment of the invention, the layout for testing the to-be-tested equipment can be generated based on the configuration information of the equipment, the wiring configuration information and the through hole configuration information, so that the consumption of time and energy of a user is reduced, and the layout generation efficiency and the use experience of the user are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic devices, and particularly to a layout generation method, apparatus, electronic device, and storage medium. Background Art

[0002] Currently, the performance test process of a device can be implemented through a Testkey layout. The Testkey layout can connect multiple variant forms of a device to be tested to a test device to obtain a test circuit, and determine the performance of each variant form of a device to be tested by reading the readings of the test device.

[0003] However, in the process of generating the Testkey layout, it is necessary for the user to manually implement processes such as the placement of devices and the wiring between devices. Thus, it takes a lot of time and effort of the user, bringing a bad user experience. Summary of the Invention

[0004] To overcome the problems existing in the related art, the present disclosure provides a layout generation method, apparatus, electronic device, and storage medium.

[0005] According to the first aspect of the embodiments of the present disclosure, a layout generation method is provided, including:

[0006] Obtain first information, second information, third information, and fourth information; the first information includes configuration information of multiple devices to be tested, the second information includes configuration information of at least one test device, the third information includes wiring configuration information between the multiple devices to be tested and the at least one test device, and the fourth information includes via configuration information of multiple vias, where the vias are used to connect devices to be tested and test devices on different layers, and the test device is used to test the performance of the device to be tested connected to the test device;

[0007] Generate a target layout based on the first information, the second information, the third information, and the fourth information; the target layout includes the device layout of the multiple devices to be tested, the device layout of the at least one test device, and the connection relationship between the multiple devices to be tested and the at least one test device.

[0008] In some embodiments, the generating a target layout based on the first information, the second information, the third information, and the fourth information includes:

[0009] Generate the multiple devices to be tested based on the first information;

[0010] Determine the at least one test device based on the second information;

[0011] Based on the first information, the second information, the third information, and the fourth information, connect the multiple devices to be tested and the at least one test device to obtain the target layout.

[0012] In some embodiments, the first information includes the device type, connection port, and layer where each device to be tested among the multiple devices to be tested is located. The connection port is the port through which the device to be tested is connected to the test device. The second information includes the configuration information of at least one test device divided according to the device type of the device to be tested. The third information includes multiple wiring configuration information divided according to the device type of the device to be tested and the connection port of the device to be tested. The fourth information includes multiple via configuration information divided according to the device type of the device to be tested and the layer where the device to be tested is located. Based on the first information, the second information, the third information, and the fourth information, connecting the multiple devices to be tested and the at least one test device to obtain the target layout includes:

[0013] For each device to be tested, obtain the target device type, target connection port, and target layer of the device to be tested from the first information;

[0014] Based on the target device type, determine the target test device corresponding to the device to be tested in the second information; the target test device is any device among the at least one test device;

[0015] Based on the target device type and the target connection port, determine the target wiring configuration information corresponding to the target device type and the target connection port in the third information;

[0016] Based on the target device type and the target layer, determine the target via configuration information corresponding to the target device type and the target layer in the fourth information;

[0017] Based on the target wiring configuration information and the target via configuration information, connect the device to be tested and the target test device to obtain the target layout.

[0018] In some embodiments, the method further includes:

[0019] When the third information does not include the wiring configuration information corresponding to the target device type and the target connection port, stop connecting the device to be tested and the target test device.

[0020] In some embodiments, the method further includes:

[0021] When the fourth information does not include the through-hole configuration information corresponding to the target device type and the target layer, determine the preset through-hole configuration information as the target through-hole configuration information.

[0022] In some embodiments, the second information further includes a target identifier of the target layout, and the method further includes:

[0023] Display the target identifier on the target layout; the identifier is used to distinguish different layouts.

[0024] In some embodiments, generating the target layout based on the first information, the second information, the third information, and the fourth information includes:

[0025] Input the first information, the second information, the third information, and the fourth information into an automated program to obtain the target layout.

[0026] According to a second aspect of the embodiments of the present disclosure, there is provided a layout generation device, including:

[0027] An acquisition module, configured to acquire first information, second information, third information, and fourth information; the first information includes configuration information of a plurality of devices to be tested, the second information includes configuration information of at least one test device, the third information includes wiring configuration information between the plurality of devices to be tested and the at least one test device, the fourth information includes through-hole configuration information of a plurality of through-holes for connecting devices to be tested and test devices on different layers, and the test device is used to test the performance of the devices to be tested connected to the test device;

[0028] A generation module, configured to generate a target layout based on the first information, the second information, the third information, and the fourth information; the target layout includes the device layout of the plurality of devices to be tested, the device layout of the at least one test device, and the connection relationship between the plurality of devices to be tested and the at least one test device.

[0029] According to a third aspect of the embodiments of the present disclosure, there is provided an electronic device, including a memory and a processor, where the memory stores a computer program, and when the processor executes the computer program, the steps of the method described in the first aspect are implemented.

[0030] According to a fourth aspect of the embodiments of the present disclosure, there is provided a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method described in the first aspect are implemented.

[0031] The technical solutions provided by the embodiments of the present disclosure may include the following beneficial effects:

[0032] The method provided by the embodiments of the present disclosure can generate a layout for testing a device to be tested based on the configuration information of the device, the wiring configuration information, and the via configuration information, thereby reducing the consumption of the user's time and energy and improving the layout generation efficiency and the user experience.

[0033] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. Description of the Drawings

[0034] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present invention and used together with the specification to explain the principles of the present invention.

[0035] Figure 1 is a flowchart of a layout generation method shown according to an exemplary embodiment.

[0036] Figure 2 is a schematic diagram of fixed parameters of a first piece of information shown according to an exemplary embodiment.

[0037] Figure 3 is a schematic diagram of custom parameters of a first piece of information shown according to an exemplary embodiment.

[0038] Figure 4 is a schematic diagram of a second piece of information shown according to an exemplary embodiment.

[0039] Figure 5 is a schematic diagram of a third piece of information shown according to an exemplary embodiment.

[0040] Figure 6 is a schematic diagram of a fourth piece of information shown according to an exemplary embodiment.

[0041] Figure 7 is a flowchart of a layout generation method shown according to an exemplary embodiment.

[0042] Figure 8 is a schematic diagram of a layout generation method shown according to an exemplary embodiment.

[0043] Figure 9 is a flowchart of a layout generation method shown according to an exemplary embodiment.

[0044] Figure 10 is a schematic diagram of a layout shown according to an exemplary embodiment.

[0045] Figure 11 is a block diagram of a layout generation device shown according to an exemplary embodiment.

[0046] Figure 12 It is a block diagram of an electronic device shown according to an exemplary embodiment. Detailed implementation manners

[0047] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present invention. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0048] In the design process of a semiconductor, the performance of a test device can be analyzed through experiments, so as to help designers determine the influence of the configuration parameters of the device on the manufacturing results. For example, the performance of devices under different process parameters is different. By testing the performance of each device with different process parameters, the process parameters with the best performance can be determined, thereby helping designers design the device.

[0049] Currently, the performance test process of a device can be implemented through a Testkey layout. The Testkey layout can connect multiple variant forms of a device to be tested to a test device to obtain a test circuit, and determine the performance of each variant form of a device to be tested by reading the readings of the test device.

[0050] However, in the process of generating the Testkey layout, the user needs to manually implement processes such as the placement of devices and the wiring between devices. Thus, it takes a lot of time and energy of the user, bringing a bad user experience.

[0051] To solve the above problems, the present disclosure provides a method for obtaining first information, second information, third information, and fourth information; the first information includes configuration information of multiple devices to be tested, the second information includes configuration information of at least one test device, the third information includes wiring configuration information between multiple devices to be tested and at least one test device, and the fourth information includes via configuration information of multiple vias, where the vias are used to connect devices to be tested and test devices on different layers, and the test device is used to test the performance of the device to be tested connected to the test device; based on the first information, second information, third information, and fourth information, a target layout is generated; the target layout includes the device layout of multiple devices to be tested, the device layout of at least one test device, and the connection relationship between multiple devices to be tested and at least one test device. The method provided by the embodiments of the present disclosure can generate a layout for testing a device to be tested based on the configuration information, wiring configuration information, and via configuration information of the device, thereby reducing the consumption of the user's time and energy and improving the layout generation efficiency and the user experience.

[0052] Exemplary embodiments of the present disclosure provide a layout generation method, which can be applied to an electronic device. The electronic device can specifically be an intelligent device such as a mobile phone, a tablet computer, a notebook, an intelligent robot, or an intelligent wearable device. In addition, various hardware resources are provided on the electronic device, as well as an energy storage device that provides electrical energy for the operation of various hardware resources.

[0053] Figure 1 is a flowchart of a layout generation method shown according to an exemplary embodiment, which is executed by an electronic device. Refer to Figure 1 and the method includes the following steps.

[0054] Step S101, obtain first information, second information, third information, and fourth information; the first information includes configuration information of multiple devices to be tested, the second information includes configuration information of at least one test device, the third information includes wiring configuration information between the multiple devices to be tested and the at least one test device, and the fourth information includes via configuration information of multiple vias. The vias are used to connect the devices to be tested and the test device on different layers, and the test device is used to test the performance of the device to be tested connected to the test device.

[0055] Among them, the device to be tested can include any device. For example, the device to be tested can be a chip, a printed circuit board, or electronic components such as resistors, capacitors, inductors, and transistors. The multiple devices to be tested refer to different variant forms of a device to be tested, that is, the devices corresponding to the same device to be tested under different configurations, different sizes, and / or different versions. For example, when the device to be tested is a chip, chips with different sizes and different configuration parameters can be determined. In some embodiments, the multiple devices to be tested can be displayed in an array in the layout.

[0056] The test device can refer to a PAD (pad or solder joint), and the PAD can be used to test the performance of a device. For example, the PAD can test a specific point in a circuit or the electrical performance of a circuit.

[0057] In some embodiments, the PAD can be connected to the device to be tested to form a test line. Then, a probe can be used to contact the PAD to read the reading of the PAD, so as to determine whether the function and performance of the device to be tested meet the design requirements based on the reading of the PAD. Or, the variant form corresponding to the best performance of the device to be tested can also be determined based on the reading of the PAD, so as to provide a design idea for designers. For example, designers can design the device to be tested based on the variant form corresponding to the best performance of the device to be tested.

[0058] In some embodiments, different variant forms of the device under test can be obtained through a parameterized cell (pcell, Parameterized Cell). The pcell allows users to create and modify the layout of a device by defining parameters. In this way, different device instances can be generated by adjusting the parameters, thereby improving the flexibility and efficiency of the design, reducing repetitive work, and improving the design efficiency. Correspondingly, a pcell of the device under test can be designed, and by adjusting the parameters of the device under test, multiple instances of the device under test can be obtained, that is, multiple variant forms of a device under test.

[0059] In some embodiments, the first information, the second information, the third information, and the fourth information can be preset in the electronic device. When any one or more of the first information, the second information, the third information, and the fourth information are needed, the corresponding information can be called from the cache of the electronic device.

[0060] It should be noted that the embodiments of the present disclosure do not limit the specific information included in the first information, the second information, the third information, and the fourth information. The specific information included in the first information, the second information, the third information, and the fourth information can be added, deleted, or modified based on actual needs. Several specific types of information included in the first information, the second information, the third information, and the fourth information are exemplarily given below.

[0061] As Figure 2 a schematic diagram of the fixed parameters of a certain first information and Figure 3Schematic diagram of custom parameters of the first information shown. The first information may include configuration information of the device under test. Taking the device under test as a transistor as an example, the first information may include: Module (device type of the device under test), TLLOGO (test circuit name), InstName (instance name), LibName (device library name of the device under test), CellName (cell name), DUTType (type of the device under test), DUTlocation (location of the device under test), DUTOnent (component of the device under test), DUTOffset (offset of the device under test), BottomLayer (bottom layer), TopLayer (top layer), PinNum (pin number, used to indicate the connection port of the device under test), D, G, S, B (ports corresponding to four different pins), pcellLib (parameterized cell library), pcellName (parameterized cell name), ModelName (model name), Priority (priority), Sanity (check), HLT (halt), Golden (best standard), Noise (noise), NPType (data type or attribute), VtType (type information of the VARIANT data type), Comments (comment information), Length (length), Finger ("finger" structure of the transistor), Stack (stack structure of the transistor), Multi (transistors connected in parallel), sa / sb (distance from the source and drain of the transistor to the boundary of the transistor active region), sxact (actual size of the transistor in the X direction), syact (actual size of the transistor in the Y direction), nfin (number of Fingers of the transistor), I (current), polyPitch (distance between polysilicon gates), CTwidth (contact hole width of the transistor), nf_stack_sw (combination of the number of Fingers and the number of Stacks of the transistor), fingers (number of Fingers of the transistor), SDB (distance between the source and drain of the transistor), multi_x (number of parallel transistors in the X direction), multi_y (number of parallel transistors in the Y direction), total_x (total size of the transistor in the X direction), total_y (total size of the transistor in the Y direction), start_x (starting coordinate position of the transistor on the X axis), start_y (starting coordinate position of the transistor on the Y axis), routing (function for selecting the best path), addDio (used to add digital input / output devices or interfaces), isDNW (used to determine whether a certain condition or state is "DNW").

[0062] It should be noted that when the device under test is other devices, the configuration parameters included in the first information can refer to the configuration parameters on the transistor as the device under test, which will not be elaborated here.

[0063] As Figure 4 shown in the schematic diagram of a second piece of information, the second piece of information may include the configuration information of the test device. For example, Module (device type of the device under test), PadLib (test device library), PadCell (test device unit), PadType (type of the test device), ROW (row where the test device is located), Column (column where the test device is located), PitchX (pitch or spacing of the test device in the X direction), PitchY (pitch or spacing of the test device in the Y direction), BndryLayer (boundary layer), BndryEncL (expansion or surrounding distance of the boundary layer in the left direction), BndryEnc B (expansion or surrounding distance of the boundary layer in the lower direction), BndryEncR (expansion or surrounding distance of the boundary layer in the right direction), BndryEncT (expansion or surrounding distance of the boundary layer in the upper direction), BottomLayer (bottom layer), TopLayer (top layer), LOGOLib (logo library), LOGOCell (logo unit), LOGOOrient (angle of the logo), LOGOOffset (offset of the logo), LOGOPitchX (pitch or spacing of the logo in the X direction), LOGOPitchY (pitch or spacing of the logo in the Y direction), LOGOROW (maximum number of characters allowed in one row of the logo), CreateLabel (flag indicating whether to create a label), LabelLayer (a type of layer for displaying text and symbol annotations), LabelPrefix (prefix part of the label for identifying the category or type of the label). Optionally, the type of the test device can be a single unit or a unit array).

[0064] The wiring configuration information is used to characterize the information about the arrangement and setting of wires between multiple devices under test and at least one test device. As Figure 5 shown in the schematic diagram of a third piece of information, the third piece of information may include Module (device type of the device under test), Port (connection port of the device under test), BottomLayer (bottom layer), TopLayer (top layer), TestLayer (test layer), RouteType (wiring type), width (line width), Space (line spacing), SingleLayer (single-layer wiring mode), ANT (avoiding antenna effect), Taper (process or shape of gradually tapering or narrowing).

[0065] It should be noted that the device under test and the test device may be in different layers. In one example, when connecting the device under test and the test device in different layers, the devices can be connected through vias. Among them, the vias can be used to connect signals or power supplies between different layers to achieve the connection between devices in different physical layers. In some embodiments, the via configuration information of the vias on different layers can be different or the same, and the via configuration information can be determined and selected based on the layer. As Figure 6 A schematic diagram of a fourth piece of information. The fourth piece of information may include Module (the device type of the device under test), Layer (the layer where the device under test is located), Width (the width of the via), Height (the height of the via), SpaceX (the minimum distance of the via in the X direction), SpaceY (the minimum distance of the via in the Y direction), EncX (the surrounding or extended distance of the via in the X direction), and EncY (the surrounding or extended distance of the via in the Y direction).

[0066] Step S102, generate a target layout based on the first piece of information, the second piece of information, the third piece of information, and the fourth piece of information; the target layout includes the device layouts of multiple devices under test, the device layouts of at least one test device, and the connection relationships between multiple devices under test and at least one test device.

[0067] In some embodiments, the first piece of information, the second piece of information, the third piece of information, and the fourth piece of information can be input into an automated program, and then the target layout can be automatically generated through the automated program. Among them, the automated program can be a computer program preset in the electronic device.

[0068] The method provided by the embodiments of the present disclosure can generate a layout for testing the device under test based on the device configuration information, the wiring configuration information, and the via configuration information, thereby reducing the consumption of the user's time and energy and improving the layout generation efficiency and the user's experience.

[0069] In some embodiments, referring to the content included in the first piece of information, the second piece of information, the third piece of information, and the fourth piece of information in the above embodiments, the following Figure 7 illustrates the process of generating the target layout through the shown embodiments.

[0070] Figure 7 is a flowchart of a layout generation method shown according to an exemplary embodiment, which is executed by an electronic device. Refer to Figure 7 , and the method includes the following steps.

[0071] Step S701, generate multiple devices under test based on the first piece of information.

[0072] It should be noted that the first information includes the configuration information of multiple devices to be tested, and multiple test devices need to be determined in the target layout. Therefore, in some embodiments, multiple devices to be tested can be determined based on the configuration information of the multiple devices to be tested included in the first information. For example, according to Figure 2 and Figure 3 the relevant parameters of the transistors in the information shown (such as the "finger" structure of the transistors, the stacked structure of the transistors, the actual size of the transistors in the X direction, the actual size of the transistors in the Y direction, the number of fingers of the transistors, etc.), multiple test devices in the layout can be determined.

[0073] Step S702, based on the second information, determine at least one test device.

[0074] In some embodiments, at least one test device can be generated based on the configuration information of the multiple test devices in the second information. The generation process of the at least one test device can refer to the generation process of the above-mentioned multiple devices to be tested, and will not be elaborated here.

[0075] In some embodiments, at least one test device can be pre-stored in the electronic device, and there is an association relationship between the second information and the at least one test device. Correspondingly, in some embodiments, at least one test device can be determined based on the association relationship between the second information and the at least one test device.

[0076] Step S703, based on the first information, the second information, the third information, and the fourth information, connect the multiple devices to be tested and the at least one test device to obtain the target layout.

[0077] In some embodiments, based on the configuration information in the first information and the second information, the multiple devices to be tested and the at least one test device can be displayed at the specified positions specified in the configuration information. For example, based on Figure 2 and Figure 3 parameters such as the coordinate positions of the devices to be tested in the X direction and the Y direction in the information shown, the devices to be tested can be displayed at the specified positions; similarly, based on Figure 4 parameters such as the row where the test device is located, the column where the test device is located, and the spacing of the test device in the X direction or the Y direction in the information, the test device can be displayed at the specified positions. Then, based on the third information and the fourth information, the multiple devices to be tested and the at least one test device are connected to obtain the target layout. For example, based on parameters such as the line pitch, line width, wiring type, length and height of the via included in the third information and the fourth information, the connection of the multiple devices to be tested and the at least one test device is realized.

[0078] In some embodiments, the first information includes the device type, connection port, and layer where each device under test is located among a plurality of devices under test. The connection port is the port through which the device under test is connected to the test device. The second information includes the configuration information of at least one test device divided according to the device type of the device under test. The third information includes the device type of the device under test, the connection port of the device under test, and a plurality of wiring configuration information divided according to the device type and connection port of the device under test. The fourth information includes the device type of the device under test, the layer where the device under test is located, and a plurality of via configuration information divided according to the device type and layer where the device under test is located.

[0079] In one example, the test device corresponding to the device under test can be determined based on the device type of the device under test, so that during the subsequent connection process between the device under test and the test device, the connection between the device under test and the corresponding test device can be achieved. Additionally, the same test device can be connected to multiple devices under test.

[0080] It should be noted that for the second information, the configuration information of at least one test device can be divided in advance according to the device type of the device under test; for the third information, a plurality of wiring configuration information can be divided in advance according to the device type and connection port of the device under test; for the fourth information, a plurality of via configuration information can be divided in advance according to the device type and layer where the device under test is located. In this way, the configured information of at least one test device, a plurality of wiring configuration information, and a plurality of via configuration information that have been classified can be called during the layout generation process.

[0081] In some embodiments, for each device under test, the target device type, target connection port, and target layer of the device under test can be obtained from the first information; based on the target device type, the target test device corresponding to the device under test can be determined from the second information; the target test device is any one of at least one test device; based on the target device type and target connection port, the target wiring configuration information corresponding to the target device type and target connection port can be determined from the third information; based on the target device type and target layer, the target via configuration information corresponding to the target device type and target layer can be determined from the fourth information; based on the target wiring configuration information and target via configuration information, the device under test and the target test device can be connected to obtain the target layout. Among them, the target test device is any one of at least one test device.

[0082] That is, for the second information, based on the target device type, the configuration information of the target test device corresponding to the target device type can be determined in the second information, and then the target test device and the configuration information of the target test device can be determined; for the third information, based on the target device type and the target connection port, the wiring configuration information corresponding to the target device type and the target connection port can be determined in the third information; for the fourth information, based on the target device type and the target layer, the via configuration information corresponding to the target device type and the target layer can be determined in the fourth information. In this way, the target test device, the target wiring configuration information, and the target via information corresponding to the current device under test can be determined.

[0083] In addition, it should be noted that the wiring process between the device under test and the target test device can be implemented based on the shortest distance principle. The shortest distance principle means that the length of the line is made as short as possible during wiring. In this way, short circuits between multiple devices under test and at least one test device can be avoided, and the resistance and inductance during signal transmission can be reduced, thereby reducing signal attenuation and delay, and improving signal integrity and timing accuracy.

[0084] In some embodiments, the connection port can be determined based on the header and value of Pinum in the first information, and the specific determination process will not be described in detail here. Optionally, the connection port can be any one of the G port, D port, S port, and B port. Among them, the G port represents the gate, the D port represents the drain, the S port represents the source, and the B port represents the substrate or body, which is usually connected to the source.

[0085] In some embodiments, when the third information does not include the wiring configuration information corresponding to the target device type and the target connection port, the connection between the device under test and the target test device is stopped. That is, when the third information does not include the wiring configuration information corresponding to the target device type and the target connection port, the wiring of this device under test is skipped.

[0086] In some embodiments, when the fourth information does not include the via configuration information corresponding to the target device type and the target layer, the preset via configuration information is determined as the target via configuration information. The preset via configuration information can be the general via configuration information preset in the electronic device, and the preset via configuration information can be set and selected based on actual needs. For example, the preset via configuration information can be determined based on the layer, and the preset via configuration information corresponding to different layers can be different.

[0087] During the design process, an electronic device may generate multiple layout diagrams, and different layout diagrams can be used to test different devices. Therefore, in some embodiments, the second information further includes identification information of the target layout diagram. In some embodiments, the identification information includes a target identifier. Correspondingly, after the target layout diagram is generated, the target identifier can be drawn on the target layout diagram, so that the target identifier can be displayed on the target layout diagram to facilitate designers to distinguish the layout diagrams.

[0088] In addition, it should be noted that the identifiers of different layout diagrams are different, that is, each layout diagram corresponds to one identifier. In this way, it can help users quickly distinguish different layout diagrams and avoid the problem of confusion between different layout diagrams.

[0089] The method provided by the embodiments of the present disclosure can connect multiple devices to be tested and at least one test device based on the specific information in the first information, the second information, the third information, and the fourth information, so as to obtain a target layout diagram. Moreover, the target layout diagram can be distinguished by using the target identifier, so as to realize the distinction between different layout diagrams. In this way, the connection relationship between multiple devices to be tested and at least one test device can be automatically obtained, so as to quickly generate the target layout diagram, save the user's time, and improve the efficiency of layout diagram generation.

[0090] In some embodiments, after the target layout diagram is generated, multiple devices to be tested can be tested based on the target layout diagram, and a probe can be used to read the readings of the test devices, so as to determine the performance of each device to be tested among the multiple devices to be tested, and further determine whether each device to be tested is normal. Optionally, the variant form corresponding to the best performance of the device to be tested can also be determined based on the readings corresponding to each device to be tested, and designers can refer to the configuration parameters of the variant form corresponding to the best performance to design the device to be tested in the actual process. In this way, the accuracy and usage effect of the device to be tested can be improved in actual applications.

[0091] In some embodiments, for the convenience of understanding, a specific embodiment is given below:

[0092] Obtain four csv files required for generating the layout diagram. The four csv files are dut csv (the first information), pad csv (the second information), route csv (the third information), and via csv (the fourth information). A brief description of the four csv files is given below:

[0093] In the DUT CSV, based on the pcellLib (parameterized cell library) and pcellName (parameterized cell name), the pcell (parameterized cell) used to generate the DUT (device under test) can be determined. Additionally, DUTLocation (location of the device under test) is used to characterize the position where the DUT is placed in the target layout, and Pinnum (pin number) is used to indicate that the port of the DUT is connected to the specified pad (test device).

[0094] In the pad CSV, the cellview of the pad is determined by PadLib (test device library) and PadCell (test device cell). Additionally, Padtype (type of the test device) can indicate whether the pad is a single cell or a cell array, and the logo-related parameters represent the cell used to place the logo.

[0095] In the route CSV, the routing is first classified by Module (device type of the device under test) and port (connection port). Different Modules and ports use different routing configurations. When the route for a specific Module and port is not included in the third information, the routing for this Module / port is skipped.

[0096] In the via CSV, the via (through-hole) is classified by Module (device type of the device under test) and the layer where the device under test is located. Different Modules and the layers where the device under test is located use different via configurations. When the via for a specific Module and the layer where the device under test is located is not included in the fourth information, the default via configuration information obtained from the tech file (preset file) is used.

[0097] Then, a pcell device library (including multiple devices under test in the pcell library) is generated based on the DUT CSV, and a pad device library (including at least one test device in the pad device library) and a logo device library (including the target logo in the logo device library) are obtained. Then, based on the pcell device library, pad device library, logo device library, DUT CSV, pad CSV, route CSV, and via CSV, the target layout is generated.

[0098] Figure 8 It is a flowchart of a layout generation method shown according to an exemplary embodiment and is executed by an electronic device. Refer to Figure 8, the method includes generating a plurality of devices to be tested based on first information, and obtaining at least one test device and a target identifier. Then, the first information, second information, third information, fourth information, the plurality of devices to be tested, the at least one test device, and the target identifier are input into an automation program to obtain a target layout showing the target identifier.

[0099] Figure 9 is a flowchart of a layout generation method shown according to an exemplary embodiment, which is executed by an electronic device. Refer to Figure 9 , the method includes the following steps.

[0100] Step S901, obtain first information, second information, third information, and fourth information.

[0101] Step S902, generate a plurality of devices to be tested based on the first information.

[0102] Step S903, determine at least one test device based on the second information.

[0103] Step S904, for each device to be tested, obtain the target device type, target connection port, and target layer of the device to be tested from the first information.

[0104] Step S905, based on the target device type, determine the target test device corresponding to the device to be tested in the second information.

[0105] Step S906, based on the target device type and the target connection port, determine the target wiring configuration information corresponding to the target device type and the target connection port in the third information.

[0106] Step S907, based on the target device type and the target layer, determine the target via configuration information corresponding to the target device type and the target layer in the fourth information.

[0107] Step S908, based on the target wiring configuration information and the target via configuration information, connect the device to be tested and the target test device to obtain a target layout.

[0108] Step S909, display the target identifier on the target layout.

[0109] Figure 10 is a schematic diagram of a layout method shown according to an exemplary embodiment. The layout includes a plurality of test devices 1001, a plurality of devices to be tested (not shown in the figure), and the connection relationships between the plurality of test devices and the plurality of devices to be tested.

[0110] The exemplary embodiment of the present disclosure provides a layout generation device, as Figure 11 shown, is a block diagram of a layout generation device shown in the present disclosure. The block diagram includes:

[0111] An acquisition module 1101, configured to acquire first information, second information, third information, and fourth information; the first information includes configuration information of a plurality of devices to be tested, the second information includes configuration information of at least one test device, the third information includes wiring configuration information between the plurality of devices to be tested and the at least one test device, and the fourth information includes via configuration information of a plurality of vias for connecting devices to be tested and test devices on different layers, and the test device is used to test the performance of the devices to be tested connected to the test device;

[0112] A generation module 1102, configured to generate a target layout based on the first information, the second information, the third information, and the fourth information; the target layout includes device layouts of a plurality of devices to be tested, device layouts of at least one test device, and connection relationships between the plurality of devices to be tested and the at least one test device.

[0113] In some embodiments, the generation module 1102 is configured to:

[0114] Generate a plurality of devices to be tested based on the first information;

[0115] Determine at least one test device based on the second information;

[0116] Connect the plurality of devices to be tested and the at least one test device based on the first information, the second information, the third information, and the fourth information to obtain a target layout.

[0117] In some embodiments, the first information includes the device type, connection port, and layer where each device to be tested is located among the plurality of devices to be tested, the connection port is a port for connecting the device to be tested and the test device, the second information includes configuration information of at least one test device divided according to the device type of the device to be tested, the third information includes a plurality of wiring configuration information divided according to the device type of the device to be tested and the connection port of the device to be tested, and the fourth information includes a plurality of via configuration information divided according to the device type of the device to be tested and the layer where the device to be tested is located. The generation module 1102 is configured to:

[0118] For each device to be tested, obtain the target device type, target connection port, and target layer of the device to be tested from the first information;

[0119] Based on the target device type, determine the target test device corresponding to the device to be tested in the second information; the target test device is any one of the at least one test device;

[0120] Based on the target device type and the target connection port, determine the target wiring configuration information corresponding to the target device type and the target connection port in the third information;

[0121] Determine the target via configuration information corresponding to the target device type and the target layer in the fourth information based on the target device type and the target layer;

[0122] Connect the device under test and the target test device based on the target wiring configuration information and the target via configuration information to obtain a target layout.

[0123] In some embodiments, the generating module 1102 is further configured to:

[0124] When the third information does not include the wiring configuration information corresponding to the target device type and the target connection port, stop connecting the device under test and the target test device.

[0125] In some embodiments, the generating module 1102 is further configured to:

[0126] When the fourth information does not include the via configuration information corresponding to the target device type and the target layer, determine the preset via configuration information as the target via configuration information.

[0127] In some embodiments, the second information further includes the target identifier of the target layout, and the generating module 1102 is further configured to:

[0128] Display the target identifier on the target layout; the identifier is used to distinguish different layouts.

[0129] In some embodiments, the generating module 1102 is configured to:

[0130] Input the first information, the second information, the third information, and the fourth information into an automation program to obtain a target layout.

[0131] Each module in the above layout generating device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in or independent of the processor in the electronic device in the form of hardware, or stored in the memory of the electronic device in the form of software, so that the processor can call and execute the operations corresponding to the above respective modules.

[0132] In an exemplary embodiment, an electronic device is provided, including a processor and a memory, where the memory stores a computer program, and when the processor executes the computer program, the steps of any of the above layout generating methods are implemented.

[0133] In an exemplary embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above layout generating methods are implemented. The computer-readable storage medium can be ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0134] Reference Figure 12 A block diagram of an electronic device that can be the subject of the present disclosure will now be described. The electronic device 120 includes a computing unit 121 that can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 122 or a computer program loaded from a storage unit 128 into a random access memory (RAM) 123. In the RAM 123, various programs and data required for the operation of the electronic device 120 can also be stored. The computing unit 121, the ROM 122, and the RAM 123 are connected to each other via a bus 124. An input / output (I / O) interface 125 is also connected to the bus 124.

[0135] A plurality of components in the electronic device 120 are connected to the I / O interface 125, including: an input unit 126, an output unit 127, a storage unit 128, and a communication unit 129. The input unit 126 can be any type of device that can input information into the electronic device 120. The input unit 126 can receive input numerical or character information, and generate key signal inputs related to user settings and / or function controls of the electronic device 120, and can include, but is not limited to, a mouse, a keyboard, a touch screen, a trackpad, a trackball, a joystick, a microphone, and / or a remote control. The output unit 127 can be any type of device that can present information, and can include, but is not limited to, a display, a speaker, a video / audio output terminal, a vibrator, and / or a printer. The storage unit 128 can include, but is not limited to, magnetic disks and optical discs. The communication unit 129 allows the electronic device 120 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks, and can include, but is not limited to, a modem, a network card, an infrared communication device, a wireless communication transceiver, and / or a chipset, such as a BluetoothTM device, a WiFi device, a WiMax device, a cellular communication device, and / or the like.

[0136] The computing unit 121 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 121 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 121 executes the various methods and processes described above, such as the layout generation method. For example, in some embodiments, the layout generation method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as the storage unit 128. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 120 via the ROM 122 and / or the communication unit 129. When the computer program is loaded into the RAM 123 and executed by the computing unit 121, one or more steps of the layout generation method described above can be executed. Alternatively, in other embodiments, the computing unit 121 can be configured to execute the layout generation method by any other suitable means (e.g., by means of firmware).

[0137] The electronic device 120 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for executing the above-described layout generation method.

[0138] Those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include known common knowledge or conventional technical means in the technical field not disclosed in this disclosure. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present invention are pointed out by the following claims.

[0139] It should be understood that the present invention is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.

Claims

1. A layout generation method, characterized in that: include: Acquire first information, second information, third information and fourth information; the first information includes configuration information of a plurality of devices to be tested, the second information includes configuration information of at least one test device, the third information includes wiring configuration information between the plurality of devices to be tested and the at least one test device, the fourth information includes through-hole configuration information of a plurality of through-holes, the through-holes are used to connect devices to be tested and test devices of different layers, the test devices are used to test the performance of the devices to be tested connected to the test devices; Based on the first information, the second information, the third information and the fourth information, a target layout is generated; the target layout includes the device layout of the multiple devices to be tested, the device layout of the at least one test device and the connection relationship between the multiple devices to be tested and the at least one test device.

2. The layout generation method according to claim 1, characterized in that: The generating a target layout based on the first information, the second information, the third information and the fourth information includes: Based on the first information, generating the plurality of devices to be tested; determining the at least one test device based on the second information; Based on the first information, the second information, the third information and the fourth information, the plurality of devices to be tested and the at least one testing device are connected to obtain the target layout.

3. The layout generation method according to claim 2, characterized in that: The first information includes the device type, connection port and layer of each device under test in a plurality of devices under test, the connection port is a port for connecting the device under test to the test device, the second information includes configuration information of at least one test device divided according to the device type of the device under test, the third information includes a plurality of wiring configuration information divided according to the device type of the device under test and the connection port of the device under test, the fourth information includes a plurality of through-hole configuration information divided according to the device type of the device under test and the layer where the device under test is located, and the plurality of devices under test and the at least one test device are connected based on the first information, the second information, the third information and the fourth information to obtain the target layout, including: For each device to be tested, obtaining a target device type, a target connection port, and a target layer of the device to be tested from the first information; Based on the target device type, determining a target test device corresponding to the device to be tested in the second information; the target test device is any one of the at least one test device; Based on the target device type and the target connection port, determine the target wiring configuration information corresponding to the target device type and the target connection port in the third information; Based on the target device type and the target layer, determining target through-hole configuration information corresponding to the target device type and the target layer in the fourth information; Based on the target wiring configuration information and the target through-hole configuration information, the device to be tested and the target test device are connected to obtain the target layout.

4. The layout generation method according to claim 3, characterized in that: The method further comprises: When the third information does not include the target device type and the wiring configuration information corresponding to the target connection port, the connection between the device to be tested and the target test device is stopped.

5. The layout generation method according to claim 3, characterized in that: The method further comprises: When the fourth information does not include the target device type and the through-hole configuration information corresponding to the target layer, the preset through-hole configuration information is determined as the target through-hole configuration information.

6. The layout generation method according to claim 2, characterized in that: The second information also includes a target identifier of the target layout, and the method further includes: The target logo is displayed on the target layout; the logo is used to distinguish different layouts.

7. The layout generation method according to claim 1, characterized in that: The generating a target layout based on the first information, the second information, the third information and the fourth information includes: The first information, the second information, the third information and the fourth information are input into an automated program to obtain the target layout.

8. A layout generation device, characterized in that: include: an acquisition module, configured to acquire first information, second information, third information and fourth information; The first information includes configuration information of a plurality of devices to be tested, the second information includes configuration information of at least one test device, the third information includes wiring configuration information between the plurality of devices to be tested and the at least one test device, the fourth information includes through-hole configuration information of a plurality of through-holes, the through-holes are used to connect devices to be tested and test devices of different layers, and the test devices are used to test the performance of the devices to be tested connected to the test devices; A generating module, configured to generate a target layout based on the first information, the second information, the third information and the fourth information; The target layout includes the device layout of the plurality of devices to be tested, the device layout of the at least one testing device, and the connection relationship between the plurality of devices to be tested and the at least one testing device.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the layout generation method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the layout generation method according to any one of claims 1 to 7 are implemented.

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