Memory device having buffer chip including input / output macro

Abstract

The present disclosure relates to a memory device having a buffer chip including input / output macros. The memory device includes: a memory chip; a controller controlling the memory chip; and a buffer chip transferring the plurality of signals between the controller and the memory chip. The buffer chip includes a plurality of input / output macros. Each of the plurality of input / output macros includes an external input / output unit that receives a signal from the controller and an internal input / output unit that transmits a signal to the memory chip. Each of the external input / output cells and the internal input / output cells is electrically connected to a bump that overlaps a region of each of the plurality of input / output macros.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0165008, filed on November 24, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the disclosed technology generally relate to a buffer chip, a memory package, and a storage device. Background Art

[0004] A storage device may include at least one memory chip, and the at least one memory chip may include a plurality of memory cells that store data. The storage device may include a controller that controls the memory chip.

[0005] For example, the controller may control operations of writing data to the memory chip or reading or erasing data written to the memory chip.

[0006] The controller may send signals such as commands or data for controlling the memory chip to the memory chip. The controller may receive data read from the memory chip.

[0007] Capacitance may be formed in a path for sending and receiving signals between the controller and the memory chip. Due to this capacitance, there may be a problem that the signal transmission and reception performance between the controller and the memory chip may deteriorate. Summary of the Invention

[0008] Various embodiments of the disclosed technology are directed to providing a measure capable of improving signal transmission and reception performance between at least one memory chip included in a storage device implementing a bump setting structure and a controller.

[0009] In an embodiment, a storage device may include: at least one memory chip; a controller configured to control the at least one memory chip; and a buffer chip configured to transfer a plurality of signals between the controller and the at least one memory chip, wherein the buffer chip includes a plurality of input / output macros, each of the plurality of input / output macros includes an external input / output unit that receives signals from the controller and an internal input / output unit that sends signals to the at least one memory chip, and each of the external input / output unit and the internal input / output unit is electrically connected to a bump that overlaps a region of each of the plurality of input / output macros.

[0010] In an embodiment, a memory package may include: a package substrate; at least one memory chip located on the package substrate; and a buffer chip located on the package substrate and including a plurality of input / output macros that send signals to and receive signals from the at least one memory chip, wherein each of the plurality of input / output macros includes an external input / output unit that receives signals from outside the buffer chip and an internal input / output unit that is electrically connected to the external input / output unit within the area of each of the plurality of input / output macros and sends signals to the at least one memory chip.

[0011] In an embodiment, a storage device trained to reduce signal delay deviation may include: at least one memory package having a signal interface trained to reduce input and output signal delays; and a controller configured to control the at least one memory package, wherein the at least one memory package further includes at least one memory chip and a buffer chip for implementing the signal interface between the at least one memory chip and the controller.

[0012] According to an embodiment of the disclosed technology, by improving the signal transmission and reception performance between the controller and the memory chip, the operation speed of the storage device can be increased and the power consumption can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram showing an example of a schematic configuration of a storage device according to an embodiment of the present disclosure.

[0014] Figure 2 is a diagram showing an example of a schematic configuration of a memory chip included in a storage device according to an embodiment of the present disclosure.

[0015] Figure 3 is a diagram showing an example of a schematic configuration of a buffer chip included in a storage device according to an embodiment of the present disclosure.

[0016] Figure 4 is a diagram showing an example of a method of training a buffer chip that transmits signals to be sent and received between a controller and a memory chip in a storage device.

[0017] Figure 5 is a diagram showing an example of a structure in which input / output macros are arranged in a buffer chip according to an embodiment of the present disclosure.

[0018] Figure 6 and Figure 7 is a diagram showing an example of an input / output macro included in a buffer chip according to an embodiment of the present disclosure.

[0019] Figure 8 It is a diagram showing an example of a control block included in a buffer chip according to an embodiment of the present disclosure.

[0020] Figure 9 It is a diagram showing another example of the structure in which input / output macros are arranged in a buffer chip according to an embodiment of the present disclosure.

[0021] Figure 10 It is a diagram showing an example of the structure for connecting a buffer chip and a memory chip in a memory package according to an embodiment of the present disclosure. Detailed Description

[0022] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown in an illustrative manner, and the same reference numerals and symbols can be used in the drawings to designate the same or similar components, even if these components are shown in different drawings from each other. Further, in the following description of examples or embodiments of the present disclosure, when it is determined that the description of well-known functions and components incorporated herein may obscure the subject matter in some embodiments of the present disclosure, the detailed description thereof will be omitted. Terms such as "including", "having", "containing", "constituting", "consisting of", and "formed of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "merely". Unless the context clearly indicates otherwise, as used herein, the singular form is also intended to include the plural form.

[0023] Terms such as "first", "second", "A", "B", "(A)", or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms does not limit the nature, order, sequence, or number, etc. of the element, but is only used to distinguish the corresponding element from other elements.

[0024] When it is mentioned that a first element "is connected or coupled", "is in contact or overlaps" with a second element, etc., it should be interpreted to include not only the case where the first element can be "directly connected or coupled" or "directly in contact or overlaps" with the second element, but also the case where a third element can be "inserted" between the first element and the second element, or the first element and the second element can be "connected or coupled" or "in contact or overlap" with each other via a fourth element, etc. Here, the second element may be included in at least one of two or more elements that are "connected or coupled", "in contact or overlap", etc.

[0025] When using time - related terms such as "after", "subsequently", "next", "before", etc. to describe the process or operation of an element or configuration, or the flow or steps in an operation, process, or manufacturing method, these terms can be used to describe non - continuous or non - sequential processes or operations, unless used together with the terms "directly" or "immediately".

[0026] In addition, when referring to any dimension, relative size, etc., even if no relevant description is specified, the numerical value or corresponding information of the element or feature (e.g., horizontal, range, etc.) should be considered to include the tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all meanings of the term "can".

[0027] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0028] Figure 1 is a diagram showing an example of a schematic configuration of a storage device 100 according to an embodiment of the present disclosure.

[0029] Referring to Figure 1 , a storage device 100 according to an embodiment of the present disclosure may include at least one memory package 200. The storage device 100 may include a controller 300 that controls the memory package 200.

[0030] The memory package 200 may include at least one memory chip 220. For example, the memory chip 220 may be disposed on a package substrate 210. The memory chip 220 may be electrically connected to the package substrate 210 through package bumps (not shown).

[0031] The memory package 200 may include a buffer chip 230 that transmits signals received from the outside (e.g., the controller 300) to the memory chip 220.

[0032] The buffer chip 230 may be disposed on the package substrate 210. The buffer chip 230 may be electrically connected to the package substrate 210 through package bumps. The buffer chip 230 may be electrically connected to the memory chip 220 through a connection line 240.

[0033] The buffer chip 230 may be electrically connected to the controller 300, etc. through printed circuit bumps 400 located under the package substrate 210. Although Figure 1Although not shown, the controller 300 and the memory package 200 included in the storage device 100 may be disposed on a printed circuit board (not shown). The memory package 200 on the printed circuit board may be electrically connected to the printed circuit board through printed circuit bumps 400. The controller 300 on the printed circuit board may be electrically connected to the printed circuit board through printed circuit bumps 400 and may be electrically connected to the memory package 200.

[0034] For example, the buffer chip 230 may reduce the delay of signals received from the controller 300 or reduce the delay deviation between different signals, and may transmit one or more signals to the memory chip 220.

[0035] A plurality of memory chips 220 may be included in the memory package 200. For example, the plurality of memory chips 220 may be arranged in a stacked structure.

[0036] For example, the memory chip 220 may be implemented in various types, such as NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), and spin transfer torque random access memory (STT-RAM). The memory chip 220 may be implemented in a three-dimensional array structure. Embodiments of the disclosed technology may be applied not only to flash memories in which a charge storage layer is configured as a floating gate, but also to charge trapping flash memories in which a charge storage layer is configured as an insulating film.

[0037] The memory chip 220 may include a plurality of memory blocks.

[0038] The memory chip 220 may operate in response to the control of the controller 300. The operations of the memory chip 220 may include, for example, a programming operation (also referred to as a "write operation"), an erase operation, and a read operation.

[0039] The controller 300 may control the programming, erasing, reading, and background operations of the memory chip 220. The background operations may include at least one of, for example, garbage collection, wear leveling, read recycling, and bad block management operations.

[0040] The controller 300 may control the operation of the memory chip 220 according to the request of a device located outside the storage device 100. In addition, the controller 300 may control the operation of the memory chip 220 regardless of external requests.

[0041] For example, the controller 300 may control the operation of the memory chip 220 according to the request of the host device.

[0042] For example, the host device may be a computer, an ultra-mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet computer, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured for a data center, one of various electronic devices configured for a home network, one of various electronic devices configured for a telematics network, an RFID (radio frequency identification) device, a mobile device capable of being driven under human control or autonomously (e.g., a vehicle, a robot, or a drone), and so on. Optionally, the host device may be a virtual / augmented reality device that provides 2D or 3D virtual reality images or augmented reality images. Additionally, the host device may be any one of various electronic devices that require the storage device 100 capable of storing data.

[0043] The host device may include at least one operating system. The operating system can generally manage and control the functions and operations of the host device and can control the interoperability between the host device and the storage device 100. Depending on the mobility of the host device, the operating system can be classified into a general operating system and a mobile operating system.

[0044] The controller 300 and the host device may be separate devices from each other. According to an embodiment of the present disclosure, the controller 300 and the host device may be implemented by being integrated into one device. Hereinafter, for ease of explanation, it will be described by taking as an example that the controller 300 and the host device are separate devices from each other.

[0045] The controller 300 may include a host interface that provides an interface for communicating with the host device. The controller 300 may include a memory interface that provides an interface for communicating with the memory chip 220.

[0046] The controller 300 may include a control circuit that controls all operations of the controller 300. The control circuit may include, for example, a processor. The control circuit may include a working memory for the operation of the processor and may optionally include an error detection and correction circuit.

[0047] The processor may communicate with the host device through the host interface and may communicate with the memory chip 220 through the memory interface.

[0048] The processor may perform the function of interpreting commands input from the host device and transmitting the commands to the memory chip 220.

[0049] For example, the processor may include a flash translation layer or may correspond to a flash translation layer. The processor may convert a logical block address provided by a host device into a physical block address. The processor may receive the logical block address and use a mapping table to convert the logical block address into a physical block address.

[0050] For example, the processor may run firmware to control the operation of the controller 300. The operation of the storage device 100 described in the embodiments of the disclosed technology may be implemented in a manner in which the processor runs firmware that defines the corresponding operation.

[0051] The firmware, which is a program to be run in the storage device 100 to drive the storage device 100, may include various functional layers corresponding to the above-described processor. For example, the firmware may include binary data that defines the code for running each functional layer.

[0052] For example, the firmware may be loaded from the memory chip 220 or a separate non-volatile memory (e.g., ROM or NOR flash) located outside the memory chip 220 into the working memory. The processor may first load all or a part of the firmware into the working memory when performing a boot operation after power-on.

[0053] The processor may perform logical operations defined in the firmware loaded into the working memory to control the overall operation of the controller 300. The processor may control the controller 300 to generate commands or signals based on the result of performing the logical operations defined in the firmware. When a part of the firmware that defines the logical operations to be performed is not loaded into the working memory, the processor may generate an event (e.g., an interrupt) for loading the corresponding part of the firmware into the working memory.

[0054] The working memory may store the firmware, program code, commands, or data required to drive the controller 300. The working memory may be located inside or outside the controller 300. The working memory, which is, for example, a volatile memory, may include at least one of SRAM (static RAM), DRAM (dynamic RAM), and SDRAM (synchronous DRAM). In some cases, the working memory may be located both inside and outside the controller 300.

[0055] Figure 2 FIG. is a diagram showing an example of a schematic configuration of the memory chip 220 included in the storage device 100 according to an embodiment of the present disclosure.

[0056] Referring to Figure 2 , the memory chip 220 may include a memory cell array 221, an address decoder 222, a read and write circuit 223, control logic 224, and a voltage generation circuit 225.

[0057] The memory cell array 221 may include a plurality of memory blocks BLK (i.e., BLK1 to BLKz, where z is a natural number of 2 or greater).

[0058] In the plurality of memory blocks BLK, a plurality of word lines WL and a plurality of bit lines BL may be provided, and a plurality of memory cells may be arranged.

[0059] The plurality of memory blocks BLK may be coupled to the address decoder 222 via a plurality of word lines WL. The plurality of memory blocks BLK may be coupled to the read and write circuit 223 via a plurality of bit lines BL.

[0060] Each of the plurality of memory blocks BLK may include a plurality of memory cells. The plurality of memory cells may be non-volatile memory cells, and may be configured using non-volatile memory cells each having a vertical channel structure.

[0061] The memory cell array 221 may be configured using a two-dimensional memory cell array, or may be configured using a three-dimensional memory cell array.

[0062] Each of the plurality of memory cells included in the memory cell array 221 may store at least 1 bit of data. For example, each of the plurality of memory cells included in the memory cell array 221 may be a single-level cell (SLC) that stores 1 bit of data. In another example, each of the plurality of memory cells included in the memory cell array 221 may be a multi-level cell (MLC) that stores 2 bits of data, a three-level cell (TLC) that stores 3 bits of data, a four-level cell (QLC) that stores 4 bits of data, or a memory cell that stores 5 or more bits of data.

[0063] The number of bits of data stored in each of the plurality of memory cells may be determined dynamically. For example, a single-level cell that stores 1 bit of data may be changed to a three-level cell that stores 3 bits of data.

[0064] The address decoder 222, the read and write circuit 223, the control logic 224, and the voltage generation circuit 225 may operate as peripheral circuits for driving the memory cell array 221.

[0065] The address decoder 222 may be coupled to the memory cell array 221 via a plurality of word lines WL. The address decoder 222 may be configured to operate in response to the control of the control logic 224.

[0066] The address decoder 222 may receive an address through the input / output buffer in the memory chip 220. The address decoder 222 may be configured to decode the block address in the received address. The address decoder 222 may select at least one memory block BLK according to the decoded block address.

[0067] The address decoder 222 can receive a read voltage Vread and a pass voltage Vpass from the voltage generation circuit 225.

[0068] During a read operation, in an operation of applying a read voltage, the address decoder 222 can apply the read voltage Vread to a selected word line WL in a selected memory block BLK, and can apply the pass voltage Vpass to the remaining unselected word lines WL.

[0069] In a program verification operation, the address decoder 222 can apply a verification voltage generated in the voltage generation circuit 225 to a selected word line WL in a selected memory block BLK, and can apply the pass voltage Vpass to the remaining unselected word lines WL.

[0070] The address decoder 222 can be configured to decode a column address in the received address. The address decoder 222 can transmit the decoded column address to the read and write circuit 223.

[0071] The read operation and the program operation of the memory chip 220 can be performed in units of pages. The address received when requesting each of the read operation and the program operation can include at least one of a block address, a row address, and a column address.

[0072] The address decoder 222 can select one memory block BLK and one word line WL according to the block address and the row address. The column address can be decoded by the address decoder 222 and provided to the read and write circuit 223.

[0073] The address decoder 222 can include at least one of a block decoder, a row decoder, a column decoder, and an address buffer.

[0074] The read and write circuit 223 can include a plurality of page buffers PB. The read and write circuit 223 can operate as a read circuit in a read operation of the memory cell array 221, and can operate as a write circuit in a write operation of the memory cell array 221.

[0075] The read and write circuit 223 including a plurality of page buffers PB can also be referred to as a page buffer circuit or a data register circuit. The read and write circuit 223 can include a data buffer responsible for data processing functions, and can further include a cache buffer responsible for cache functions.

[0076] Multiple page buffers PB can be connected to the memory cell array 221 through multiple bit lines BL. In a read operation and a program verification operation, the multiple page buffers PB can continuously supply a sense current to the bit lines BL connected to the memory cells to sense the threshold voltage (Vth) of the memory cells, and can latch the sensed data by sensing a change in the amount of current flowing according to the programmed state of the corresponding memory cells through a sense node.

[0077] The read and write circuit 223 can operate in response to a page buffer control signal output from the control logic 224.

[0078] In a read operation, the read and write circuit 223 can temporarily store the read data by sensing the data of the memory cells, and then, can output the data DATA to the input / output buffer of the memory chip 220. As an exemplary embodiment, in addition to the page buffer PB or the page register, the read and write circuit 223 can further include a column selection circuit.

[0079] The control logic 224 can be connected to the address decoder 222, the read and write circuit 223, and the voltage generation circuit 225. The control logic 224 can receive a command CMD and a control signal CTRL through the input / output buffer of the memory chip 220.

[0080] The control logic 224 can be configured to control all operations of the memory chip 220 in response to the control signal CTRL. The control logic 224 can output a control signal for adjusting the precharge potential level of the sense nodes of the multiple page buffers PB.

[0081] The control logic 224 can control the read and write circuit 223 to perform a read operation on the memory cell array 221. The voltage generation circuit 225 can generate a read voltage Vread and a pass voltage Vpass used in the read operation in response to a voltage generation circuit control signal output from the control logic 224.

[0082] Each of the storage blocks BLK of the memory chip 220 described above can be configured using multiple pages corresponding to multiple word lines WL and multiple strings corresponding to multiple bit lines BL.

[0083] In the storage block BLK, the multiple word lines WL and the multiple bit lines BL can be arranged to intersect each other. A memory cell connected to one of the multiple word lines WL and one of the multiple bit lines BL can be defined. A transistor can be provided in each memory cell.

[0084] A transistor provided in a memory cell may include a drain, a source, and a gate. The drain (or source) of the transistor may be connected to a corresponding bit line BL directly or via another transistor. The source (or drain) of the transistor may be connected to a source line (which may be ground) directly or via another transistor. The gate of the transistor may include a floating gate surrounded by a dielectric and a control gate to which a gate voltage is applied from a word line WL.

[0085] In each memory block BLK, a first selection line (also referred to as a source selection line or a drain selection line) may be additionally provided outside the first outermost word line WL among the two outermost word lines WL that is closer to the read and write circuit 223, and a second selection line (also referred to as a drain selection line or a source selection line) may be additionally provided outside the second outermost word line WL among the two outermost word lines WL.

[0086] At least one dummy word line may be additionally provided between the first outermost word line and the first selection line. At least one dummy word line may also be additionally provided between the second outermost word line and the second selection line.

[0087] The read operation and the programming operation (write operation) of the above memory block BLK may be performed in units of pages, and the erase operation may be performed in units of memory blocks.

[0088] Figure 3 FIG. is a diagram showing an example of a schematic configuration of a buffer chip 230 included in a storage device 100 according to an embodiment of the present disclosure.

[0089] Referring to Figure 3 , the buffer chip 230 may receive a signal from a Figure 1 controller 300 and send the signal to the memory chip 220. The buffer chip 230 may send the signal received from the memory chip 220 to the controller 300.

[0090] The buffer chip 230 may include a plurality of input / output macros 500 that send and receive signals between the controller 300 and the memory chip 220.

[0091] For example, multiple input / output macros 500 can be respectively disposed in different (non-overlapping) regions of the buffer chip 230. For example, a first region where one of the multiple input / output macros 500 is set is different from a second region where another of the multiple input / output macros 500 is set. The first region is distinguishable from the second region, and the first region does not overlap with the second region. Each of the multiple input / output macros 500 can include an external input / output unit 510 and an internal input / output unit 520. In an embodiment, each of the multiple input / output macros 500 can include a multiplexer 530 that connects the external input / output unit 510 and the internal input / output unit 520.

[0092] The external input / output unit 510 can receive a signal sent from the controller 300. The internal input / output unit 520 can send the signal received through the external input / output unit 510 to the memory chip 220.

[0093] The external input / output unit 510 and the internal input / output unit 520 can be configured with, for example, inverters and can be located in the region of each of the multiple input / output macros 500. The external input / output unit 510 and the internal input / output unit 520 can be electrically connected to each other in the region of each of the multiple input / output macros 500.

[0094] Multiple memory chips 220 can be included in the memory package 200, and in order to send a signal to the multiple memory chips 220, multiple internal input / output units 520 can be set in the input / output macro 500.

[0095] In the case where the input / output macro 500 includes multiple internal input / output units 520, the multiplexer 530 for selecting the internal input / output unit 520 can be set in the input / output macro 500, and the signal received by the external input / output unit 510 is transmitted through this internal input / output unit 520. For example, the multiplexer 530 can select the internal input / output unit 520 corresponding to the memory chip 220 to which the signal received from the controller 300 is to be sent based on the chip enable signal.

[0096] The structure of the buffer chip 230 can be implemented by the input / output macro 500 having the following structure, in which the signal received through the external input / output unit 510 is sent to the memory chip 220 through the internal input / output unit 520.

[0097] Since the external input / output unit 510 and the internal input / output unit 520 are electrically connected to each other within the region of each input / output macro 500, the distance between the external input / output unit 510 and the internal input / output unit 520 can be reduced, and it can be beneficial to implement a routing structure for the electrical connection between the external input / output unit 510 and the internal input / output unit 520.

[0098] The buffer chip 230 can use multiple input / output macros 500 to reduce signal delay caused by capacitance formed in the path of transmitting and receiving signals between the controller 300 and the memory chip 220.

[0099] By setting each of the multiple input / output macros 500, delay deviation between the signals transmitted and received between the controller 300 and the memory chip 220 can be prevented or reduced. The external input / output unit 510 included in each of the multiple input / output macros 500 transmits signals through the internal input / output unit 520 via training for setting each of the multiple input / output macros 500.

[0100] Figure 4 is a diagram showing an example of a method of training the buffer chip 230 according to an embodiment of the present disclosure. The buffer chip 230 transmits signals to be transmitted and received between the controller 300 and the memory chip 220 in the storage device 100.

[0101] Referring to Figure 4 , signals can be transmitted and received between the controller 300 included in the storage device 100 and the memory chip 220. The controller 300 can send signals to the buffer chip 230 included in the memory package 200 through the physical layer.

[0102] The buffer chip 230 can include multiple input / output macros 500, and each input / output macro 500 includes an external input / output unit 510 and an internal input / output unit 520. Each input / output macro 500 can receive signals from the controller 300 and send signals to the memory chip 220.

[0103] The paths through which the multiple input / output macros 500 transmit signals respectively may be different from each other, and the capacitance of each path may deviate. In order to eliminate or reduce the deviation of signal delay between the multiple input / output macros 500, training for setting each of the multiple input / output macros 500 can be performed.

[0104] Since the input / output macro 500 included in the buffer chip 230 has a re-driver structure in which signals are received from the controller 300 and sent to the memory chip 220 without separate processing, the setting of the input / output macro 500 can be performed through the transmission and reception of signals between the controller 300 and the memory chip 220.

[0105] Without separately performing training between the controller 300 and the buffer chip 230 and between the buffer chip 230 and the memory chip 220, each of the plurality of input / output macros 500 provided for signal transmission and reception can be performed by training the signals transmitted and received between the controller 300 and the memory chip 220. Through the training method, the delay deviation of signals transmitted and received by each of the plurality of input / output macros 500 can be eliminated or reduced.

[0106] In this way, training for eliminating or reducing signal delay deviation can be performed through the buffer chip 230 including a plurality of input / output macros 500 each configured with an external input / output unit 510 and an internal input / output unit 520, and the signal transmission and reception performance between the controller 300 and the memory chip 220 can be improved.

[0107] Since the external input / output unit 510 and the internal input / output unit 520 are provided in each of the plurality of input / output macros 500, the routing structure between the external input / output unit 510 and the internal input / output unit 520 can also be implemented.

[0108] In addition, since the plurality of input / output macros 500 each configured with an external input / output unit 510 and an internal input / output unit 520 are respectively provided in separate regions of the buffer chip 230, it is advantageous for the setting of the package bumps connected to the external input / output unit 510 and the internal input / output unit 520.

[0109] Figure 5 It is a diagram showing an example of the structure in which the input / output macro 500 according to an embodiment of the present disclosure is arranged in the buffer chip 230.

[0110] Refer to Figure 5 , in the buffer chip 230, the plurality of input / output macros 500 can be arranged in the form of tiles, for example. The structure in which the plurality of input / output macros 500 are arranged in the form of tiles is a representative example, and the plurality of input / output macros 500 can be set in various ways, and each input / output macro 500 has a structure in which the external input / output unit 510 and the internal input / output unit 520 are set to be located within the region of the corresponding input / output macro 500.

[0111] Each of the plurality of input / output macros 500 may be configured to include an external input / output unit 510 and an internal input / output unit 520.

[0112] According to an embodiment of the present disclosure, each input / output macro 500 may be configured to include an internal input / output unit 520. The internal input / output unit 520 included in the input / output macro 500 may have a structure connected to an external input / output unit 510 located outside the input / output macro 500. The internal input / output units 520 that transmit the same type of signal may be arranged adjacent to each other, and the external input / output unit 510 may be located in a separate area.

[0113] Through the internal input / output unit 520 included in the input / output macro 500, the same type of signal may be sent to different memory chips 220 in the memory package 200. Through the internal input / output units 520 included in different input / output macros 500, different types of signals may be sent to the same memory chip 220.

[0114] The internal input / output unit 520 included in each input / output macro 500 may vary according to the type of signal transmitted by the input / output macro 500 or the number of memory chips 220 included in the memory package 200.

[0115] For example, one external input / output unit 510 and four internal input / output units 521, 522, 523, and 524 may be provided in the input / output macro 500. The external input / output unit 510 may receive a signal from the controller 300 through an external input / output pad 610. The internal input / output unit 520 may send the signal to the memory chip 220 through an internal input / output pad 620. Four internal input / output pads 621, 622, 623, and 624 may be electrically connected to the four internal input / output units 521, 522, 523, and 524, respectively.

[0116] The external input / output pad 610 may be located inside the external input / output unit 510 or may be located outside the external input / output unit 510. The internal input / output pad 620 may be located inside the internal input / output unit 520 or may be located outside the internal input / output unit 520.

[0117] Since the external input / output unit 510 and the four internal input / output units 521, 522, 523, and 524 are located within the area of the input / output macro 500, it is beneficial for the connection between the external input / output unit 510 and the internal input / output unit 520. Since the external input / output pads 610 and the internal input / output pads 620 are located within the area of the input / output macro 500, the input / output macro 500 can be implemented with a simple structure. For example, if multiple external input / output pads 610 are set in a certain area and are aggregated among the multiple external input / output pads 610, and multiple internal input / output pads 620 are set in different areas and are aggregated among the multiple internal input / output pads 620, it may be difficult to connect between the external input / output pads 610 and the internal input / output pads 620, and the connection may be complex. However, according to the simple structure of the present disclosure, the connection between the external input / output pads 610 and the internal input / output pads 620 can be simply implemented.

[0118] The external input / output unit 510 included in the input / output macro 500 can be electrically connected to Bump_e, that is, the external package bump 710, and the external package bump 710 overlaps with the area of the corresponding input / output macro 500. The internal input / output unit 520 included in the input / output macro 500 can be electrically connected to Bump_i, that is, the internal package bump 720, and the internal package bump 720 overlaps with the area of the corresponding input / output macro 500.

[0119] Since the external package bump 710 and the internal package bump 720 are respectively positioned to overlap with the area of the corresponding input / output macro 500 and are electrically connected to the external input / output unit 510 and the internal input / output unit 520, it is beneficial for the setting of the package bumps in the buffer chip 230. The electrical connection between the package bumps and the input / output macro 500 can be implemented with a simple structure. The external package bump 710 can be electrically connected to the external input / output unit 510, and the external input / output unit 510 is set in the area overlapping with the external package bump 710. The internal package bump 720 can be electrically connected to the internal input / output unit 520, and the internal input / output unit 520 is set in the area overlapping with the internal package bump 720. The connection structure can be simply implemented.

[0120] Therefore, according to the embodiments of the present disclosure, through the structure of the input / output macro 500 including the external input / output unit 510 and the internal input / output unit 520, it is beneficial for the training of the buffer chip 230, and a signal transmission path or a package bump setting structure can be implemented.

[0121] The structures of the external input / output unit 510 and the internal input / output unit 520 included in the input / output macro 500 may vary according to the type of signal transmitted by the input / output macro 500.

[0122] For example, data strobe signals DQS, data signals DQ, chip enable signals CE, command latch enable signals CLE, address latch enable signals ALE, write enable signals WE, read enable signals RE, etc. may be transmitted by the buffer chip 230.

[0123] The chip enable signal CE may be a signal indicating that the memory chip 220 is operable. The command latch enable signal CLE may be a signal for receiving commands, and the address latch enable signal ALE may be a signal for receiving addresses. The write enable signal WE may be a signal that is triggered when data including commands and addresses is loaded into the memory chip 220. The read enable signal RE may be a signal that is triggered when data is loaded into the controller 300.

[0124] The signals to be transmitted by the input / output macro 500 may be transmitted unidirectionally or bidirectionally between the controller 300 and the memory chip 220.

[0125] Figure 6 and Figure 7 is a diagram showing an example of the input / output macro 500 included in the buffer chip 230 according to an embodiment of the present disclosure. Figure 6 Shows an example of the structure of the input / output macro 500 when the signal transmitted by the input / output macro 500 is a unidirectionally transmitted signal. Figure 7 Shows an example of the structure of the input / output macro 500 when the signal transmitted by the input / output macro 500 is a bidirectionally transmitted signal.

[0126] Referring to Figure 6 shown in <EX 1>, shows an example of the input / output macro 500 that transmits the chip enable signal CE.

[0127] The input / output macro 500 may include an external input / output unit 510 and an internal input / output unit 520. The external input / output unit 510 and the external input / output pads 610 may be electrically connected, and the internal input / output unit 520 and the internal input / output pads 620 may be electrically connected.

[0128] The external input / output unit 510 and the internal input / output unit 520 may have a structure for unidirectionally transmitting signals, and may output a signal ICE_active indicating the activation of the internal chip enable signal iCE according to the chip enable signal CE. For example, the decoded internal chip enable signals ICE_Decoded[3:0] may be input to the input / output macro 500 and may be used to indicate that the memory chip 220 is to be activated.

[0129] Refer to Figure 6 As shown in <EX 2>, an example of the input / output macro 500 for transmitting the address latch enable signal ALE, the command latch enable signal CLE, and the write enable signal WE is shown.

[0130] In the case where four memory chips 220 are included in the memory package 200, the input / output macro 500 for transmitting the above signals may include an external input / output unit 510, a first internal input / output unit 521, a second internal input / output unit 522, a third internal input / output unit 523, and a fourth internal input / output unit 524.

[0131] The external input / output unit 510 may be electrically connected to the external input / output pad 610. The first internal input / output unit 521 may be electrically connected to the first internal input / output pad 621. The second internal input / output unit 522, the third internal input / output unit 523, and the fourth internal input / output unit 524 may be electrically connected to the second internal input / output pad 622, the third internal input / output pad 623, and the fourth internal input / output pad 624, respectively.

[0132] The external input / output unit 510 and the four internal input / output units 521, 522, 523, and 524 may have a structure for unidirectionally transmitting signals.

[0133] The input / output macro 500 may output an internal address latch enable signal iALE, an internal command latch enable signal iCLE, and an internal write enable signal iWE according to the address latch enable signal ALE, the command latch enable signal CLE, and the write enable signal WE.

[0134] In an embodiment of the present disclosure, a data signal DQ or a data strobe signal DQS may be transmitted bidirectionally between the controller 300 and the memory chip 220, and the input / output macro 500 may be configured for such signal transmission.

[0135] Refer to Figure 7As shown in <EX 3>, an example of an input / output macro 500 for transmitting data signal DQ is shown. The input / output macro 500 may include an external input / output unit 510 capable of transmitting and receiving signals bidirectionally and an internal input / output unit 520 capable of transmitting and receiving signals bidirectionally. The input / output macro 500 may include an internal input / output unit 520 corresponding to the memory chip 220. For example, when the memory package 200 includes four memory chips 220, the internal input / output unit 520 may include four internal input / output units 521, 522, 523, and 524. The number of internal input / output units 520 may change according to the number of memory chips 200 included in the memory package 200.

[0136] The input / output macro 500 may receive a direction control signal indicating the signal transmission / reception direction from the outside. The input / output macro 500 may transmit the data signal DQ while adjusting the direction for transmitting and receiving signals according to the direction control signal.

[0137] Referring to Figure 7 As shown in <EX 4>, an example of an input / output macro 500 for transmitting data strobe signal DQS is shown. The input / output macro 500 may have a structure for transmitting and receiving differential signals. For example, each of the data strobe signal DQS c and the data strobe signal DQS t may be input to or output from each of the two external input / output pads 610. Each of the data strobe signal DQS c and the data strobe signal DQS t may be input to or output from each of the two internal input / output pads 620. When the input / output macro 500 transmits and receives one or more differential signals, a plurality of input / output pads may be electrically connected to each of the external input / output unit 510 and the internal input / output unit 520. The external input / output unit 510 may be electrically connected to the two external input / output pads 610, and each of the internal input / output units 520 may be electrically connected to the two internal input / output pads 620. And for example, when the memory package 200 includes four memory chips 220, the internal input / output pads 620 may include four pairs of internal input / output pads 621, 622, 623, and 624. The number of internal input / output pads 620 may change according to the number of memory chips 200 included in the memory package 200.

[0138] The input / output macro 500 can provide a simple structure for transmitting signals unidirectionally or bidirectionally. The signal transmission path can be simply implemented. Through the input / output macro 500, a structure capable of transmitting and receiving differential signals can be provided, and the noise of the signals transmitted by the buffer chip 230 can be reduced.

[0139] In an embodiment of the present disclosure, the buffer chip 230 may include a control block for providing some signals related to the control of the input / output macro 500.

[0140] Figure 8 is a diagram showing an example of the control block included in the buffer chip 230 according to an embodiment of the present disclosure.

[0141] Referring to Figure 8 , for example, the buffer chip 230 may include a direction control block for outputting a direction control signal.

[0142] The direction control block IO Direction Control Block may receive, for example, an internal chip enable signal iCE, an internal address latch enable signal iALE, an internal command latch enable signal iCLE, an internal write enable signal iWE, an internal read enable signal iRE, and an internal data strobe signal iDQS, and may output a direction control signal indicating the transmission direction of the internal data signal iDQ. The direction control block may receive a reset signal PON_RESET for the operation of the corresponding block.

[0143] The direction control signal may be input to the input / output macro 500. The input / output macro 500 may control the direction of transmitting and receiving signals between the controller 300 and the memory chip 220 according to the direction control signal.

[0144] For another example, the buffer chip 230 may include a Special Function Register (SFR) block.

[0145] For example, the SFR block may receive a reset signal PON_RESET for operation, and may receive an internal chip enable signal iCE, etc. The SFR (Special Function Register) block may receive internal data and store information required for the operation of the buffer chip 230, or may output external data by performing operations based on the internal data. The SFR block may adjust the interface between the controller 300 and the memory chip 220. For example, the SFR block may store parameter values representing the connection characteristics with the controller 300 or the memory chip 220. The SFR block may perform interface adjustment by controlling the parameter values.

[0146] The above-described direction control block and SFR block may be located in a region of the buffer chip 230 other than the region where the input / output macro 500 is provided. Optionally, the direction control block and SFR block may be located in a region overlapping with the input / output macro 500.

[0147] In an embodiment of the present disclosure, the signal transmission and reception performance between the controller 300 and the memory chip 220 can be improved through the training of the buffer chip 230 including the input / output macro 500 having a re-driver structure, and the operation of the input / output macro 500 can be supported by setting some functional blocks, etc. in the buffer chip 230.

[0148] The input / output macro 500 of the buffer chip 230 may be provided in the form of the above-described tile or in various other forms, and may be provided in a form based on the type of signal transmitted by the input / output macro 500.

[0149] Figure 9 is a diagram showing another example of the structure in which the input / output macro 500 according to an embodiment of the present disclosure is arranged in the buffer chip 230.

[0150] Referring to Figure 9 , the plurality of input / output macros 500 included in the buffer chip 230 may be arranged in the form of tiles. For example, the plurality of input / output macros 500 may be provided in the form of a 4X5 tile as in <Case A>, or may be provided in the form of a 2X10 tile as in <Case B>.

[0151] In the region of each input / output macro 500, an external package bump Bump_e electrically connected to the external input / output unit 510, an internal package bump Bump_i electrically connected to the internal input / output unit 520, etc. may be provided, and a power supply bump Bump_p for power supply, a ground bump Bump_g for grounding, etc. may be provided. Figure 9 Examples of the positions of the power supply bump Bump_p and the ground bump Bump_g are shown, but the positions of the power supply bump Bump_p and the ground bump Bump_g are not limited thereto.

[0152] The input / output macro 500 arranged in the buffer chip 230 may be provided by distinguishing according to the type of signal transmitted by the input / output macro 500.

[0153] For example, in <Case A>, when the area indicated by 901 is an area closer to the memory chip 220, high-speed signals can be transmitted through the input / output macro 500 provided in the area indicated by 901. For example, data signals DQ or read enable signals RE can be transmitted and received through the input / output macro 500 provided in the area indicated by 901. Signals for low-speed operations such as chip enable signals CE, write enable signals WE, address latch enable signals ALE, and command latch enable signals CLE can be transmitted and received through the input / output macro 500 provided in an area other than the area indicated by 901.

[0154] In the case of <Case B>, high-speed signals such as data signals DQ and read enable signals RE can be transmitted and received through the input / output macro 500 provided in the area indicated by 902. Low-speed signals such as chip enable signals CE, write enable signals WE, address latch enable signals ALE, and command latch enable signals CLE can be transmitted and received through the input / output macro 500 provided in an area other than the area indicated by 902.

[0155] According to the setting of the input / output macro 500, the signal transmission / reception path between the buffer chip 230 and the memory chip 220 can be reduced to improve the high-speed signal transmission / reception performance.

[0156] In addition, according to an embodiment of the present disclosure, since the external input / output unit 510 and the internal input / output unit 520 that transmit the same type of signal are located in the area of the corresponding input / output macro 500, a structure capable of reducing the delay of the signal transmission and reception path between the buffer chip 230 and the memory chip 220 can be provided.

[0157] Figure 10 is a diagram showing an example of a structure connecting the buffer chip 230 and the memory chip 220 in the memory package 200 according to an embodiment of the present disclosure.

[0158] Referring to Figure 10 , as an example, a structure in which the buffer chip 230 and four memory chips 220 are provided in the memory package 200 is shown. This structure may be a structure in which the second memory chip 220B, the third memory chip 220C, and the fourth memory chip 220D are sequentially stacked on the first memory chip 220A.

[0159] The internal package bumps Bump_i of the input / output macro 500 included in the buffer chip 230 can be electrically connected to the memory pads Pad_m of the memory chip 220. As an example, Figure 10The input / output macro 500 of the buffer chip 230 is shown electrically connected to the portion where the memory pad Pad_m to which the data signal DQ is applied is located. The input / output macro 500 electrically connected to the memory pad Pad_m to which the data signal DQ is applied may be located in a region of the buffer chip 230 adjacent to the memory chip 220.

[0160] The internal package bump Bump_i of the input / output macro 500 may be connected to the interconnection of the package substrate 210 in the region indicated by 1001. The internal package bump Bump_i of the input / output macro 500 may be electrically connected to the memory pad Pad_m of the memory chip 220 through the interconnection of the package substrate 210.

[0161] The internal package bump Bump_i included in the input / output macro 500 may be electrically connected to the memory pad Pad_m that inputs the same type of signal. For example, the internal package bump Bump_i included in the input / output macro 500 may be electrically connected to the memory pad Pad_m that inputs the data signal DQ in different memory chips 220.

[0162] Since signals of the same type are sent to different memory chips 220 through the internal package bumps Bump_i included in each input / output macro 500, the signal transmission / reception paths between the input / output macro 500 of the buffer chip 230 and the memory pads Pad_m of the memory chips 220 may be formed without crossing each other, as in the portion indicated by 1002.

[0163] In the case of preventing, minimizing, or reducing signal interference caused by the crossing of the paths for transmitting and receiving signals between the buffer chip 230 and the memory chip 220, the signal transmission and reception performance of the buffer chip 230 can be improved.

[0164] Although various embodiments of the disclosed technology have been described for illustrative purposes with specific details and variations, those skilled in the art will understand that various modifications, additions, and substitutions can be made based on what is disclosed or shown in the disclosed technology without departing from the spirit and scope of the disclosed technology as defined by the following claims.

Claims

1. A storage device, comprising: at least one memory chip; A controller, controlling the at least one memory chip; as well as a buffer chip for transmitting a plurality of signals between the controller and the at least one memory chip, The buffer chip includes a plurality of input / output macros, each of the plurality of input / output macros includes an external input / output unit that receives a signal from the controller and an internal input / output unit that sends the signal to the at least one memory chip, and each of the external input / output unit and the internal input / output unit is electrically connected to a bump that overlaps an area of ​​each of the plurality of input / output macros.

2. The storage device according to claim 1, wherein: Each of the plurality of input / output macros is arranged in the buffer chip in the form of a tile.

3. The storage device according to claim 1, wherein: The external input / output unit and the internal input / output unit are electrically connected to each other in a region overlapping each of the plurality of input / output macros.

4. The storage device according to claim 1, wherein: A power bump and a ground bump are located in a region of each of the plurality of input / output macros.

5. The storage device according to claim 1, wherein: At least one of the plurality of input / output macros includes a plurality of internal input / output cells therein, and the plurality of internal input / output cells transmit the signals to different memory chips, respectively.

6. The storage device according to claim 5, wherein: A plurality of signals of the same type are transmitted through the plurality of internal input / output units.

7. The storage device according to claim 5, wherein: The buffer chip further includes a multiplexer electrically connecting the external input / output unit to the plurality of internal input / output units.

8. The storage device according to claim 1, wherein: A type of a signal transmitted to the at least one memory chip through a first input / output macro among the plurality of input / output macros is different from a type of a signal transmitted to the at least one memory chip through a second input / output macro.

9. The storage device according to claim 1, wherein: In at least one of the plurality of input / output macros, the signal is transmitted in a single direction from the external input / output unit to the internal input / output unit.

10. The storage device according to claim 1, wherein: In at least one of the plurality of input / output macros, the signal is transmitted in a bidirectional direction between the external input / output unit and the internal input / output unit.

11. The storage device according to claim 1, wherein: At least one of the plurality of input / output macros receives a direction control signal that controls a direction in which the signal is transmitted.

12. The storage device according to claim 1, wherein: At least one of the plurality of input / output macros receives a differential signal through the external input / output unit and transmits the differential signal through the internal input / output unit.

13. A memory package, comprising: Package substrate; at least one memory chip, located on the packaging substrate; as well as A buffer chip is located on the package substrate and includes a plurality of input / output macros, the plurality of input / output macros transmit signals to the at least one memory chip and receive signals from the at least one memory chip, wherein each of the plurality of input / output macros includes an external input / output unit and an internal input / output unit, the external input / output unit receives a signal from the outside of the buffer chip, and the internal input / output unit is electrically connected to the external input / output unit in a region of each of the plurality of input / output macros and transmits the signal to the at least one memory chip.

14. The memory package of claim 13, wherein: Each of the external input / output cell and the internal input / output cell is electrically connected to a bump that overlaps a region of each of the plurality of input / output macros.

15. The memory package of claim 13, wherein: A plurality of bumps overlapping an area of ​​each of the plurality of input / output macros are electrically connected to different memory chips, respectively.

16. The memory package of claim 13, wherein: The buffer chip includes a direction control block that controls a direction in which the signal is transmitted in at least one of the plurality of input / output macros.

17. A storage device, the storage device being trained to reduce signal delay variation, the storage device comprising: at least one memory package having a signal interface trained to reduce input and output signal delays; as well as a controller to control the at least one memory package, The at least one memory package further includes at least one memory chip and a buffer chip implementing a signal interface between the at least one memory chip and the controller.

18. The storage device according to claim 17, wherein: The buffer chip further includes a plurality of input / output macros having at least one setting to minimize delay skew between a plurality of signals transmitted and received between the controller and the at least one memory chip.

19. The storage device according to claim 18, wherein: At least one setting of the plurality of input / output macros is trained to minimize delay skew between a plurality of signals transmitted and received between the controller and the at least one memory chip.

20. The storage device according to claim 19, wherein: The plurality of input / output macros further include a plurality of package bump interconnects to a package substrate for a signal transmission / reception path indicated by a first region disposed between the plurality of input / output macros of the buffer chip and the plurality of memory pads of the memory chip, and wherein a plurality of signal transmission / reception paths between a plurality of input / output macros of the buffer chip and a plurality of memory pads of the memory chip are connected in a portion indicated by a second region, and the signal transmission / reception paths in the second region do not cross each other.

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