Method, device and equipment for detecting refresh cycle of DRAM (Dynamic Random Access Memory) and computer readable medium

Abstract

The invention provides a refresh cycle detection method, device and equipment of a DRAM (Dynamic Random Access Memory), a computer readable medium and a program product. The method comprises the following steps: distributing a buffer area with a preset capacity for refresh cycle detection; traversing the test data to the buffer area, and continuously reading the data in the initial refresh cycle; recording each refresh cycle and checking whether the read data is complete or not; and shortening the initial refresh cycle in response to the condition that the difference value between the refresh cycle and the initial refresh cycle is within a preset threshold range and the read data is complete. According to the embodiment, the actual refresh cycle can be detected by making the difference between the refresh cycle and the initial refresh and judging whether the difference value is within the preset range or not, and the reliability of the detection method is improved. And if the read data is judged to be complete, the initial refresh cycle can be adjusted to continue detection, so that a basis is provided for setting a matched refresh cycle.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and more particularly to a method, apparatus, device, and computer-readable medium for detecting the refresh cycle of a DRAM. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a computer memory technology used for temporarily storing and accessing data. DRAM has the advantages of high-density storage and low cost, and has become the main type of memory commonly used in computer systems.

[0003] A DRAM cell consists of a capacitor, and the charge gradually leaks over time and needs to be refreshed regularly to maintain data integrity. Therefore, when designing a DRAM, it is necessary to continuously detect the refresh cycle. Summary of the Invention

[0004] This section of the present invention is used to briefly introduce concepts that will be described in detail in the following detailed implementation section. This section of the present invention is not intended to identify the key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0005] Some embodiments of the present invention propose a method, apparatus, device, computer-readable medium, and program product for detecting the refresh cycle of a DRAM to solve the technical problems mentioned in the above background art section.

[0006] In a first aspect, some embodiments of the present invention provide a method for detecting the refresh cycle of a DRAM, the method including: allocating a buffer with a preset capacity for refresh cycle detection; after traversing test data into the buffer, continuously reading the data within an initial refresh cycle; recording each refresh cycle and checking whether the read data is complete; and shortening the initial refresh cycle in response to the difference between the refresh cycle and the initial refresh cycle being within a preset threshold and the read data being complete.

[0007] In a second aspect, some embodiments of the present invention provide a device for detecting the refresh cycle of a DRAM, the device including: an allocation unit configured to allocate a buffer with a preset capacity for refresh cycle detection; a reading unit configured to continuously read the data within an initial refresh cycle after traversing test data into the buffer; a recording unit configured to record each refresh cycle and check whether the read data is complete; and an adjustment unit configured to shorten the initial refresh cycle in response to the difference between the refresh cycle and the initial refresh cycle being within a preset threshold and the read data being complete.

[0008] In a third aspect, an embodiment of the present application provides an electronic device, which includes: one or more processors; a storage device for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any implementation manner of the first aspect.

[0009] In a fourth aspect, an embodiment of the present application provides a computer-readable medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the method described in any implementation manner of the first aspect.

[0010] In a fifth aspect, some embodiments of the present invention provide a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the method described in any implementation manner of the above-mentioned first aspect.

[0011] The above embodiments of the present invention have the following beneficial effects: Through the refresh cycle detection method of the DRAM of the present invention, by setting an initial refresh cycle in a buffer with a preset capacity and continuously reading data, it is possible to record each refresh cycle and determine whether the read data is complete. By subtracting the above refresh cycle from the initial refresh, and judging whether the difference is within a preset range, the actual refresh cycle can be detected, improving the reliability of the detection method. And judging that the read data is complete enables adjusting the initial refresh cycle to continue the detection, thus providing a basis for setting a matching refresh cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0013] Figure 1 is a flowchart of some embodiments of the refresh cycle detection method of the DRAM according to the present invention;

[0014] Figure 2 is a schematic structural diagram of some embodiments of the refresh cycle detection device of the DRAM according to the present invention;

[0015] Figure 3 is a schematic structural diagram of an electronic device suitable for implementing some embodiments of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] The technical solution of the present invention will be clearly and completely described below in conjunction with embodiments. Obviously, the described embodiments are some, but not all, embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0017] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0018] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined. In addition, the terms "mounted", "connected" and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0019] The present invention will be described in detail below with reference to the drawings and in conjunction with embodiments.

[0020] First, please refer to Figure 1 , which shows a flow 100 of some embodiments of the refresh cycle detection method of a DRAM according to the present invention. The refresh cycle detection method of the DRAM includes the following steps:

[0021] Step 101, allocate a buffer with a preset capacity for refresh cycle detection.

[0022] In some embodiments, the execution subject of the method may be an electronic device. The electronic device may be hardware or software. When the electronic device is hardware, it may be implemented as a distributed cluster composed of multiple servers or terminal devices, or as a single server or a single terminal device. When the electronic device is embodied as software, it may be installed in the above-listed hardware devices. It may be implemented as multiple software or software modules for providing distributed services, or as a single software or software module. No specific limitation is made here.

[0023] The electronic device can allocate a buffer with a preset capacity in various ways for refresh cycle detection.

[0024] It should be noted that the above preset capacity can be adjusted according to the actual situation or detection requirements. For example, 1M or 10M.

[0025] Step 102, after traversing the test data into the buffer, continuously read the data within the initial refresh cycle.

[0026] In some embodiments, after traversing the test data into the buffer, the staff can set the detection duration, and within this detection duration, continuously read the data in the buffer at the initial refresh cycle. The above initial refresh cycle can be set by the electronic device or input by those skilled in the art.

[0027] Step 103, record each refresh cycle and check whether the read data is complete.

[0028] In some embodiments, the refresh cycle can be collected and recorded by connecting a logic analyzer or an oscilloscope, etc. Compare the read data with the test data to determine whether the data is exactly the same.

[0029] Step 104, in response to the difference between the refresh cycle and the initial refresh cycle being within the preset threshold and the read data being complete, shorten the initial refresh cycle

[0030] In some embodiments, in order to determine whether the actual refresh cycle is carried out according to the initial refresh cycle, the difference between the refresh cycle and the initial refresh cycle can be compared with the preset threshold. If the difference is within the preset threshold, it indicates that the refresh cycle is relatively close to the initial refresh cycle. When the above difference exceeds the preset threshold, it indicates that an error occurs in the refresh cycle. At this time, the internal timer can be checked.

[0031] The above preset threshold can be determined by those skilled in the art according to the design requirements or the actual situation.

[0032] The above preset threshold can also be obtained by analyzing the difference between the refresh period and the preset refresh period through an artificial intelligence chip. Among them, the machine learning model carried by the above artificial intelligence chip is obtained by training with a training sample set.

[0033] As an example, the machine learning model can be obtained by performing the following training steps based on the training sample set: inputting the differences between the sample refresh periods and the sample preset periods of at least one training sample in the training sample set into the initial machine learning model respectively to obtain the corresponding preset thresholds; comparing the preset thresholds corresponding to each sample difference in the above at least one training sample with the corresponding sample preset thresholds; determining the prediction accuracy of the above initial machine learning model according to the comparison results; determining whether the above prediction accuracy is greater than a preset accuracy threshold; in response to determining that the above accuracy is greater than the above preset accuracy threshold, using the above initial machine learning model as the trained machine learning model; in response to determining that the above accuracy is not greater than the above preset accuracy threshold, adjusting the parameters of the above initial machine learning model, and using the unused training samples to form a training sample set, using the adjusted initial machine learning model as the initial machine learning model, and performing the above training steps again. It can be understood that after the above training, the machine learning model can be used to represent the corresponding relationship between the difference and the preset threshold. The above-mentioned machine learning model can be a convolutional neural network model.

[0034] As an example, the above machine learning model can include a difference and corresponding relationship table. Among them, the corresponding relationship table can be a corresponding relationship table of the corresponding relationships between a large number of differences and preset thresholds by those skilled in the art. In this way, the difference is compared with multiple differences in the corresponding relationship table in sequence. If a certain difference in the corresponding relationship table is the same as or close to the difference, the preset threshold corresponding to the difference in the corresponding relationship table is used as the preset threshold indicated by the difference. Thus, the preset threshold can be determined for the difference.

[0035] As another example, the above initial machine learning model can be an untrained deep learning model or an incompletely trained deep learning model. Each layer of the initial deep learning model can be set with initial parameters, and the parameters can be continuously adjusted during the training process of the deep learning model. The initial deep learning model can be various types of untrained or incompletely trained artificial neural networks or a model obtained by combining multiple untrained or incompletely trained artificial neural networks. For example, the initial deep learning model can be an untrained convolutional neural network, or an untrained recurrent neural network, or a model obtained by combining an untrained convolutional neural network, an untrained recurrent neural network, and an untrained fully connected layer.

[0036] In some embodiments, when the difference between the above refresh period and the initial refresh period is within a preset threshold, it is determined whether the read data is complete. If the data is incomplete, it indicates that the refresh is not frequent enough and the storage unit fails to retain the data. Therefore, it is necessary to extend the above initial refresh period. If the read data is complete, it indicates that the current refresh frequency can enable the storage unit to retain the data. At this time, the initial refresh period can be shortened and the detection can be performed again. In this way, a more suitable refresh period can be set.

[0037] Further referring to Figure 2 , as an implementation of the method shown in Figure 1 , some embodiments of the present invention provide a device for detecting the refresh period of a DRAM. These device embodiments correspond to those method embodiments shown in Figure 1 , and the device can be specifically applied to various electronic devices.

[0038] As shown in Figure 2 , a device 200 for detecting the refresh period of a DRAM in some embodiments includes: an allocation unit 201, a reading unit 202, a recording unit 203, and an adjustment unit 204. Among them, the allocation unit 201 is configured to allocate a buffer with a preset capacity for refresh period detection. The reading unit 202 is configured to continuously read data within the initial refresh period after traversing the test data into the buffer. The recording unit 203 is configured to record each refresh period and check whether the read data is complete. The adjustment unit 204 is configured to shorten the initial refresh period in response to the difference between the refresh period and the initial refresh period being within a preset threshold range and the read data being complete.

[0039] It can be understood that the various units described in the device 200 correspond to the respective steps in the method described with reference to Figure 1 . Therefore, the operations, features, and beneficial effects described above for the method also apply to the device 200 and the units included therein, and will not be repeated here.

[0040] Next, referring to Figure 3 , which shows a schematic structural diagram of an electronic device 300 suitable for implementing some embodiments of the present invention. Figure 3 The electronic device shown is only an example and should not impose any limitations on the functions and usage scopes of the embodiments of the present invention.

[0041] As shown in Figure 3As shown, the electronic device 300 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 301, which may perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 302 or the program loaded from the storage device 308 into the random access memory (RAM) 303. In the RAM 303, various programs and data required for the operation of the electronic device 300 are also stored. The processing device 301, the ROM 302, and the RAM 303 are connected to each other through a bus 304. The input / output (I / O) interface 305 is also connected to the bus 304.

[0042] Generally, the following devices may be connected to the I / O interface 305: an input device 306 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 307 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 308 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 309. The communication device 309 may allow the electronic device 300 to communicate with other devices wirelessly or wiredly to exchange data. Although Figure 3 the electronic device 300 with various devices is shown, it should be understood that it is not required to implement or have all the shown devices. Instead, more or fewer devices may be implemented or had. Figure 3 Each block shown in may represent one device or, as needed, multiple devices.

[0043] In particular, according to some embodiments of the present invention, the process described above with reference to the flowchart may be implemented as a computer software program. For example, some embodiments of the present invention include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program codes for executing the method shown in the flowchart. In such some embodiments, the computer program may be downloaded and installed from the network through the communication device 309, or installed from the storage device 308, or installed from the ROM 302. When the computer program is executed by the processing device 301, the above functions defined in the method of some embodiments of the present invention are executed.

[0044] It should be noted that the computer-readable medium described in some embodiments of the present invention may be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0045] In some embodiments of the present invention, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In some embodiments of the present invention, the computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above.

[0046] The computer-readable signal medium may also be any computer-readable medium other than the computer-readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0047] In some embodiments, the client and the server can communicate using any currently known or future-developed network protocol such as HTTP (HyperText Transfer Protocol), and can be interconnected with digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include local area networks ("LANs"), wide area networks ("WANs"), the Internet (e.g., the Internet), and end-to-end networks (e.g., ad hoc end-to-end networks), as well as any currently known or future-developed networks.

[0048] The above computer-readable medium may be included in the above electronic device; or it may exist separately and not be assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the one or more programs are executed by the electronic device, the electronic device is caused to: allocate a buffer with a preset capacity for refresh cycle detection; after traversing test data into the buffer, continuously read data within an initial refresh cycle; record each refresh cycle and check whether the read data is complete; and in response to the difference between the refresh cycle and the initial refresh cycle being within a preset threshold range and the read data being complete, shorten the initial refresh cycle.

[0049] Computer program code for performing the operations of some embodiments of the present invention may be written in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., by using an Internet service provider to connect through the Internet).

[0050] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0051] The units described in some embodiments of the present invention can be implemented in software or in hardware. The described units can also be provided in a processor. For example, it can be described as: a processor includes an allocation unit, a reading unit, a recording unit, and an adjustment unit. Among them, the names of these units do not constitute a limitation on the units themselves in some cases. For example, the allocation unit can also be described as "a unit that allocates a buffer with a preset capacity for refresh cycle detection".

[0052] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that can be used include: Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), Application Specific Standard Product (ASSP), System on Chip (SOC), Complex Programmable Logic Device (CPLD), and so on.

[0053] Some embodiments of the present invention also provide a computer program product, including a computer program which, when executed by a processor, implements any one of the above-mentioned DRAM refresh cycle detection methods.

[0054] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A DRAM refresh cycle detection method, characterized in that: The method comprises: Allocate a buffer of preset capacity for refresh cycle detection; After traversing the test data into the buffer, continue to read the data during the initial refresh cycle; Record each refresh cycle and check whether the read data is complete; In response to the difference between the refresh cycle and the initial refresh cycle being within a preset threshold and the read data being complete, the initial refresh cycle is shortened.

2. The DRAM refresh cycle detection method according to claim 1, characterized in that: The refresh cycle is recorded by connecting to a logic analyzer.

3. The DRAM refresh cycle detection method according to claim 2, characterized in that: The method further comprises: In response to a difference between the refresh period and the initial refresh period exceeding a preset threshold, the timer is checked.

4. The DRAM refresh cycle detection method according to claim 3, characterized in that: The preset threshold is obtained by analyzing the refresh cycle and the preset refresh cycle through the artificial intelligence chip, wherein the machine learning model carried by the artificial intelligence chip is obtained by training through a training sample set.

5. The refresh cycle detection method of DRAM according to claim 4, characterized in that: The training sample set includes a sample refresh period, a difference between sample preset periods, and a sample preset threshold. The machine learning model is trained using the sample difference as input and the sample preset threshold as the expected output.

6. The DRAM refresh cycle detection method according to claim 1, characterized in that: The method further comprises: In response to the difference between the refresh cycle and the initial refresh cycle being within a preset threshold, the read value is incomplete, the initial refresh cycle is extended, and re-detection is performed.

7. A DRAM refresh cycle detection device, characterized in that: include: an allocation unit configured to allocate a buffer of a preset capacity for refresh cycle detection; a reading unit, configured to continuously read the data within an initial refresh cycle after traversing the test data into the buffer; a recording unit configured to record each refresh cycle and check whether the read data is complete; The adjustment unit is configured to shorten the initial refresh cycle in response to the difference between the refresh cycle and the initial refresh cycle being within a preset threshold and the read data being complete.

8. An electronic device, comprising: one or more processors; a storage device having one or more programs stored thereon, When the one or more programs are executed by the one or more processors, the one or more processors are enabled to implement the refresh cycle detection method for the DRAM as described in any one of claims 1-6.

9. A computer readable medium having a computer program stored thereon, wherein: When the program is executed by a processor, the refresh cycle detection method of the DRAM as described in any one of claims 1 to 6 can be implemented.

10. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program can implement the refresh cycle detection method of a DRAM according to any one of claims 1 to 6.

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