Programmable input buffer circuit, data processing method and chip

Abstract

The invention relates to a programmable input buffer circuit, a data processing method and a chip, and the circuit comprises a data input module which is used for receiving data inputted by a peripheral, and storing the data inputted by the peripheral to a buffer module; the instruction decoding module is used for receiving an instruction sent by the instruction assembly line and analyzing the instruction according to a preset decoding table to obtain decoding information; the relative read address module is used for obtaining a relative read address according to the decoding information; the absolute read address module is used for generating an absolute read address according to the relative read address; the buffer module is used for storing the data received by the data input module and outputting the data stored in the buffer module according to the absolute read address; and the data output module is used for processing the data output by the buffer module and then sending the data to an instruction assembly line. The circuit provided by the invention has flexible programmable capability and can adapt to continuous change of a network protocol.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a programmable input buffer circuit, a data processing method, and a chip. Background Art

[0002] In network data transmission, a storage device used to bridge the speed gap of different data processing rates is called a buffer. Buffers are divided into two types: input buffers (In Buffer) and output buffers (Out Buffer). The function of an input buffer is to temporarily store the data sent by a peripheral device so that the processor can fetch it. The function of an output buffer is to temporarily store the data sent by the processor to a peripheral device. A buffer can coordinate and buffer a high-speed processor and a slow-speed peripheral device to achieve data transfer synchronization.

[0003] Currently used input buffers are usually in a non-programmable fixed form. Different input buffers with different functions are selected according to different requirements, and their functions cannot be changed. It is a fixed-function circuit. The fixed-form input buffer has the following problems: When a new function is added to the network protocol, the fixed-form input buffer cannot handle the new protocol features. Especially in the current situation of the rapid development of the Internet / cloud, network protocols are constantly changing, so it cannot meet the operation needs of Internet / cloud manufacturers. Summary of the Invention

[0004] The purpose of this application is to provide a programmable input buffer circuit, a data processing method, and a chip, which have flexible programmable capabilities and can adapt to the continuous changes of network protocols.

[0005] To achieve the above purpose, an embodiment of this application provides a programmable input buffer circuit, including: A data input module, configured to receive data input by a peripheral device and store the data input by the peripheral device into a buffer module; An instruction decoding module, configured to receive an instruction issued by an instruction pipeline and parse the instruction according to a preset decoding table to obtain decoding information; A relative read address module, configured to obtain a relative read address according to the decoding information; An absolute read address module, configured to generate an absolute read address according to the relative read address; A buffer module, configured to store the data received by the data input module and output the data stored in the buffer module according to the absolute read address; A data output module, connected to the buffer module, configured to process the data output by the buffer module and send it to the instruction pipeline.

[0006] The embodiment of the present application further provides a data processing method, which is implemented based on the above programmable input buffer circuit. The method includes: The data input module receives the data input by the peripheral device and stores the data input by the peripheral device into the buffer module; The instruction decoding module receives the instructions issued by the instruction pipeline and parses the instructions according to a preset decoding table to obtain decoding information; The relative read address module obtains a relative read address according to the decoding information; The absolute read address module generates an absolute read address according to the relative read address; The buffer module stores the data received by the data input module and outputs the data stored in the buffer module according to the absolute read address; The data output module processes the data output by the buffer module and sends it to the instruction pipeline.

[0007] The embodiment of the present application further provides a chip, including the above programmable input buffer circuit.

[0008] The embodiment of the present application provides a programmable input buffer circuit, a data processing method, and a chip. Only a preset instruction set needs to be provided. The instruction set includes multiple basic instructions, such as the RISC-V instruction set or a set of the RISC-V instruction set and other custom instructions. Therefore, when applying the embodiment of the present application, a preset decoding table can be written according to the Buffer function requirements and the preset instruction set to endow the instruction decoding module with corresponding decoding capabilities, so as to decode the instructions of the instruction pipeline of the processor to obtain corresponding decoding information. Modules such as the relative read address module, the absolute read address module, the buffer module, and the data output module can read the cached data from the buffer module according to the decoding information and then return it to the instruction pipeline of the processor. As described in the background art, the currently used input buffer is usually in a non-programmable fixed form, which is a fixed-function circuit. Compared with the fixed-form input buffer, the programmable input buffer circuit of the embodiment of the present application has flexible programmable capabilities, enabling it to adapt to the continuous changes of network protocols, maximizing the service life of the device, and saving the device replacement cost.

[0009] More features and advantages of the embodiment of the present application are reflected hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0011] Figure 1 It is a structural diagram of a programmable input buffer circuit in an embodiment of the present application.

[0012] Figure 2 It is a structural diagram of a programmable input buffer circuit in another embodiment of the present application.

[0013] Figure 3 It is a flowchart of a data processing method in an embodiment of the present application.

[0014] Markings in the figure: 1 - data input module; 2 - instruction decoding module; 3 - relative read address module; 4 - absolute read address module; 5 - buffer module, 51 - read address generation module, 52 - Buffer module; 6 - data output module. Detailed Description of the Embodiment

[0015] The detailed description of the accompanying drawings is intended to be an illustration of the current preferred embodiment of the present application, rather than representing the only form in which the present application can be implemented. It should be understood that the same or equivalent functions can be completed by different embodiments intended to be included within the spirit and scope of the present application.

[0016] Refer to Figure 1 , an embodiment of the present application provides a programmable input buffer circuit, including a data input module 1, an instruction decoding module 2, a relative read address module 3, an absolute read address module 4, a buffer module 5, and a data output module 6.

[0017] The data input module 1 is used to receive the data input by the peripheral device and store the data input by the peripheral device into the buffer module 5. Specifically, the function of the input buffer is to temporarily store the data sent by the peripheral device so that the processor can fetch it; in the circuit of this embodiment, the data input by the peripheral device is temporarily stored in the buffer module 5.

[0018] The instruction decoding module 2 is configured to receive the instructions issued by the instruction pipeline and parse the instructions according to a preset decoding table to obtain decoding information. Specifically, when the processor needs to fetch the data stored in the Buffer module 52, the instruction pipeline of the processor inputs an instruction to the circuit of this embodiment. The instruction decoding module 22 receives the instruction and decodes the instruction according to the preset decoding table. The preset decoding table records the definition information of various instructions. According to the decoding table, the meaning of the instruction can be known, and the corresponding decoding information can be decoded. If the instruction is not in the decoding table, the instruction is decoded as illegal and fed back to the instruction pipeline for an exception handling process.

[0019] The relative read address module 3 is connected to the instruction decoding module 2 and is configured to obtain a relative read address according to the decoding information. Specifically, the relative read address can be a read address value with a granularity of 1 bit, 2 bits, 4 bits, or 8 bits. The relative read address may come from the immediate value of the instruction or a certain field segment of the source operand of the instruction.

[0020] The absolute read address module 4 is connected to the relative read address module 3 and is configured to generate an absolute read address according to the relative read address. Specifically, after obtaining the relative read address, the relative read address needs to be converted into an absolute read address for accessing the storage unit (Memory) of the buffer module 5.

[0021] The buffer module 5 is respectively connected to the data input module 1 and the absolute read address module 4, and is configured to store the data received by the data input module 1 and output the data stored in the buffer module 5 according to the output of the absolute read address module 4; The data output module 6 is connected to the buffer module 5 and is configured to process the data output by the buffer module 5 and send it to the instruction pipeline.

[0022] It should be noted that the embodiment of the present application provides a programmable input buffer circuit. Only a preset instruction set needs to be provided. The instruction set includes multiple basic instructions, such as the RISC-V instruction set or a combination of the RISC-V instruction set and other custom instructions. Compared with most instruction sets, the RISC-V instruction set can be freely used for any purpose, allowing anyone to design, manufacture, and sell RISC-V chips and software. Therefore, when applying the embodiment of the present application, a preset decoding table can be written according to the Buffer function requirements and the preset instruction set, endowing the instruction decoding module 2 with corresponding decoding capabilities, capable of decoding the instructions in the instruction pipeline of the processor to obtain corresponding decoding information. Relative to modules such as the read address module 3, the absolute read address module 4, the read address generation module 51, the Buffer module 52, and the data output module 6, cache data can be read from the Buffer module 52 according to the decoding information and then returned to the instruction pipeline of the processor. The flexible programmable ability enables the input buffer circuit of the embodiment of the present application to adapt to the continuous changes of network protocols, maximally extending the service life of the device and saving the device replacement cost.

[0023] In some embodiments, referring to Figure 2 , the buffer module 5 specifically includes: The read address generation module 51, connected to the absolute read address module 4, is used to generate a depth read address according to the absolute read address. Specifically, the Buffer module 52 of the circuit in this embodiment adopts a multi-bank storage structure. Therefore, it is necessary to further obtain the depth read address. For example, the multi-bank storage structure is designed with 4 banks, and the 4 banks are sequentially numbered as Bank0, Bank1, Bank2, and Bank3. The bit width of each bank is 64 bit. Assuming that 256-bit data starting from Byte9 of the absolute read address needs to be read, and Byte9 is located in the 0th row of Bank1, then the Memory depth read addresses of Bank0, Bank1, Bank2, and Bank3 need to be generated as 1, 0, 0, and 0 respectively, indicating that 64-bit data of the 1st row of Bank0, 64-bit data of the 0th row of Bank1, 64-bit data of the 0th row of Bank2, and 64-bit data of the 0th row of Bank3 need to be read, and then the data output from the 4 banks is spliced into a large-bit-width data of 256 bit.

[0024] The Buffer module 52 is respectively connected to the data input module 1, the read address generation module 51, and the data output module 6, and is used to store the data input by the peripheral device, and output the data stored in the Buffer module 52 according to the deep read address; wherein, the Buffer module 52 includes a multi-bank storage structure. Specifically, the design of the multi-bank storage structure can be determined according to the design function indexes of the processor. For example, if it is required to "support 256-bit bus writing and read any 1 to 256 consecutive bits at the same time", then it can be designed as n 256-bit wide Bank Memories, where n is a positive integer greater than or equal to 2.

[0025] It should be noted that the circuit of this embodiment, as the source data Buffer for processing network packets, can perform read access after the instruction decoding in the instruction pipeline, and can read the protocol fields or Payload data in the packet in any Bit (minimum 1 bit, maximum up to the maximum width of the pipeline, including but not limited to 256 bits, 512 bits, 1024 bits, 2048 bits, etc.) unit, so as to achieve efficient data comparison and data transfer, and meet the characteristic requirements of network processing data.

[0026] In some embodiments, the instruction decoding module 2 is specifically configured to receive the first instruction issued by the instruction pipeline, and parse the first instruction according to a preset decoding table to obtain the first decoding information; The relative read address module 3 is specifically configured to obtain a first relative read address according to the first decoding information; The absolute read address module 4 includes a first absolute read address unit connected to the relative read address module 3, and the first absolute read address unit is configured to obtain a first absolute read address according to the first decoding information; The read address generation module 51 includes a first read address generation unit connected to the first absolute read address unit, and the first read address generation unit is configured to obtain a first deep read address according to the first absolute read address; The Buffer module 52 includes a Meta Buffer connected to the first read address generation unit, and the Meta Buffer is configured to output the data stored in the Meta Buffer according to the first deep read address.

[0027] Specifically, in this embodiment, a Meta Buffer is designed. The Meta Bufffer is mainly used to store the metadata of network packets, such as packet types, the offset addresses of each packet header, various Qos information that the packet needs to process, and other information that needs to be transmitted together with the packet.

[0028] Specifically, the first instruction is an instruction to read data from the Meta Buffer. The instruction decoding module 2 obtains first decoding information through parsing. The relative read address module 3 determines that the processor is to fetch corresponding data from the Meta Buffer according to the first decoding information. After the relative read address module 3 obtains a first relative read address according to the first decoding information, it sends the first relative read address to a first absolute read address unit corresponding to the Meta Buffer.

[0029] It should be noted that the specific use of the Meta Buffer is well-known to those skilled in the art. The inventive point of this embodiment does not lie in the functional design of the Meta Buffer, but lies in enabling the input buffer circuit to have flexible programmable capabilities. Moreover, the Meta Buffer is designed as a multi-Bank storage structure to achieve output of any bit of data. Therefore, the data storage use of the Meta Buffer will not be described in more detail here.

[0030] In some embodiments, the absolute read address module 4 further includes a first register, and the first register is used to record the absolute read address offset of the Meta Buffer. Among them, the first absolute read address unit is specifically used to add the first relative read address and the absolute read address offset of the Meta Buffer to obtain the first absolute read address when the first instruction indicates obtaining the first absolute read address in the first manner; and use the first relative read address as the first absolute read address when the first instruction indicates obtaining the first absolute read address in the second manner.

[0031] Specifically, the first instruction contains indication information on what manner to use to obtain the first absolute read address, which is obtained according to pre-programming. Further, when obtaining the first absolute read address, the value of the first register is updated to "current value + relative read address + access data size".

[0032] In some embodiments, the instruction decoding module 2 is specifically used to receive a second instruction sent by an instruction pipeline and parse the second instruction according to a preset decoding table to obtain second decoding information. The relative read address module 3 is specifically used to obtain a second relative read address according to the second decoding information. The absolute read address module 4 includes a second absolute read address unit connected to the relative read address module 3, and the second absolute read address unit is used to obtain a second absolute read address according to the second decoding information. The read address generation module 51 includes a second read address generation unit connected to the second absolute read address unit, and the second read address generation unit is configured to obtain a second depth read address according to the second absolute read address; The Buffer module 52 includes a packet Buffer connected to the second read address generation unit, and the packet Buffer is configured to output data stored in the packet Buffer according to the second depth read address.

[0033] Specifically, in this embodiment, a packet Buffer is designed, and the packet Buffer is mainly used to store externally input packets or partial packet information, such as: packet headers, packet headers + packet tails, or packet preambles + packet headers, etc.

[0034] Specifically, the second instruction is an instruction to read data from the packet Buffer. The instruction decoding module 2 obtains second decoding information through parsing. The relative read address module 3 determines that the processor is to fetch corresponding data from the packet Buffer according to the second decoding information. After the relative read address module 3 obtains a second relative read address according to the second decoding information, it sends the second relative read address to a second absolute read address unit corresponding to the packet Buffer.

[0035] It should be noted that the specific use of the packet Buffer is well-known to those skilled in the art. The inventive point of this embodiment does not lie in the functional design of the packet Buffer, but lies in enabling the input buffer circuit to have flexible programmable capabilities. Moreover, the packet Buffer is designed as a multi-Bank storage structure to achieve the output of any bit of data. Therefore, the data storage use of the packet Buffer will not be described in more detail here.

[0036] In some embodiments, the absolute read address module 4 further includes a second register, and the second register is configured to record the absolute read address offset of the packet Buffer; Among them, the second absolute read address unit is specifically configured to add the second relative read address and the absolute read address offset of the packet Buffer to obtain the second absolute read address when the second instruction indicates using the first method to obtain the second absolute read address; when the second instruction indicates using the second method to obtain the second absolute read address, use the second relative read address as the second absolute read address.

[0037] Specifically, the second instruction includes indication information on which method to use to obtain the second absolute read address, which is obtained according to pre-programming. Further, when obtaining the second absolute read address, update the value of the second register to "current value + relative read address + access data size".

[0038] In some embodiments, the instruction decoding module 2 is specifically configured to receive a third instruction issued by an instruction pipeline, and parse the third instruction according to a preset decoding table to obtain third decoding information; The relative read address module 3 is specifically configured to obtain a third relative read address according to the third decoding information; The absolute read address module 4 includes a third absolute read address unit connected to the relative read address module 3, and the third absolute read address unit is configured to obtain a third absolute read address according to the third decoding information; The read address generation module 51 includes a third read address generation unit connected to the third absolute read address unit, and the third read address generation unit is configured to obtain a third depth read address according to the third absolute read address; The Buffer module 52 includes a Key Buffer connected to the third read address generation unit, and the KeyBuffer is configured to output data stored in the Key Buffer according to the third depth read address.

[0039] Specifically, in this embodiment, a Key Buffer is designed. The Key Buffer is mainly used to store keywords required for table lookup. The keyword may be a set of data spliced by multiple instructions, for example: the five-tuple information of a packet.

[0040] Specifically, the third instruction is an instruction to read data from the Key Buffer. The instruction decoding module 2 obtains third decoding information through parsing. The relative read address module 3 determines that the processor is to fetch corresponding data from the Key Buffer according to the third decoding information. After the relative read address module 3 obtains a third relative read address according to the third decoding information, it sends the third relative read address to the third absolute read address unit corresponding to the Key Buffer.

[0041] It should be noted that the specific use of the Key Buffer is well known to those skilled in the art. The inventive point of this embodiment does not lie in the functional design of the Key Buffer, but in enabling the input buffer circuit to have flexible programmable capabilities. Moreover, the Key Buffer is designed as a multi-Bank storage structure to achieve the output of any bit of data. Therefore, the data storage use of the KeyBuffer will not be described in more detail here.

[0042] In some embodiments, the absolute read address module 4 further includes a third register, and the third register is configured to record the absolute read address offset of the Key Buffer; Among them, the third absolute read address unit is specifically configured to, when the third instruction indicates obtaining the third absolute read address in the first manner, add the third relative read address and the absolute read address offset of the Key Buffer to obtain the third absolute read address; when the third instruction indicates obtaining the third absolute read address in the second manner, use the third relative read address as the third absolute read address.

[0043] Specifically, the third instruction includes indication information on which manner to use to obtain the third absolute read address, which is obtained through pre-programming. Further, when obtaining the third absolute read address, update the value of the third register to "current value + relative read address + access data size".

[0044] In some embodiments, the data output module 6 is specifically configured to splice, shift, mask, or perform format conversion on the data output by the Buffer module 52.

[0045] Specifically, for example, the multi-bank storage structure adopts a 4-Bank design. The 4 Banks are sequentially numbered as Bank0, Bank1, Bank2, and Bank3. The bit width of each Bank is 64 bits. Assume the absolute read address is Byte9, and Byte9 is located in the 0th row of Bank1. Then, the Memory depth access read addresses of Bank0, Bank1, Bank2, and Bank3 need to be generated as 1, 0, 0, 0 respectively, indicating that it is necessary to read 64-bit data from the 1st row of Bank0, 64-bit data from the 0th row of Bank1, 64-bit data from the 0th row of Bank2, and 64-bit data from the 0th row of Bank3. Then, splice the 4 64-bit data output by the 4 Banks into a large-bit-width data of 256 bits in sequence according to the Bank number. After splicing, although a large-bit-width data of 256 bits is obtained, the sorting of the 4 64-bit data is incorrect because actually the 64-bit data output by Bank1 should be in the front. At this time, it is necessary to determine the shift information according to the absolute read address, shift the 4 64-bit data and then splice them, and mask some bits of data that are not needed. The format conversion swap refers to the big-endian and little-endian format conversion, and whether to perform the conversion depends on the data format requirements of the instruction pipeline and the data output of the circuit design.

[0046] Refer to Figure 3 , this embodiment of the present application further provides a data processing method, which is implemented based on the programmable input buffer circuit described in the above embodiment. The method includes the following steps: Step S1: The data input module receives the data input by the peripheral device and stores the data input by the peripheral device into the buffer module; Step S2: The instruction decoding module receives the instruction sent by the instruction pipeline and parses the instruction according to a preset decoding table to obtain decoding information; Step S3: The relative read address module obtains a relative read address according to the decoding information; Step S4: The absolute read address module generates an absolute read address according to the relative read address; Step S5: The buffer module stores the data input by the peripheral device and outputs the data stored in the buffer module according to the absolute read address; Step S6: The data output module processes the data output by the buffer module and sends it to the instruction pipeline.

[0047] In some embodiments, Step S5 specifically includes: Step S51: The read address generation module generates a depth read address according to the absolute read address; Step S52: The Buffer module outputs the data stored in the Buffer module according to the depth read address; wherein, the Buffer module includes a multi-bank storage structure.

[0048] In some embodiments, Step S2 specifically includes: The instruction decoding module receives the first instruction sent by the instruction pipeline and parses the first instruction according to a preset decoding table to obtain first decoding information; Step S3 specifically includes: The relative read address module obtains a first relative read address according to the first decoding information; Step S4 specifically includes: The first absolute read address unit obtains a first absolute read address according to the first decoding information; Step S51 specifically includes: The first read address generation unit obtains a first depth read address according to the first absolute read address; Step S52 specifically includes: Meta Buffer outputs the data stored in MetaBuffer according to the first depth read address.

[0049] In some embodiments, Step S4 specifically includes: The relative read address module determines to obtain a second absolute read address using a first method or a second method according to the first decoding information; When obtaining the first absolute read address using the first method, the first absolute read address unit obtains the absolute read address offset of Meta Buffer recorded in the first register, and adds the first relative read address and the absolute read address offset of Meta Buffer to obtain the first absolute read address; When obtaining the first absolute read address using the second method, the first absolute read address unit uses the first relative read address as the first absolute read address.

[0050] In some embodiments, step S2 specifically includes: The instruction decoding module receives the second instruction sent by the instruction pipeline and parses the second instruction according to a preset decoding table to obtain second decoding information. Step S3 specifically includes: The relative read address module obtains a second relative read address according to the second decoding information. Step S4 specifically includes: The second absolute read address unit obtains a second absolute read address according to the second decoding information. Step S51 specifically includes: The second read address generation unit obtains a second depth read address according to the second absolute read address. Step S52 specifically includes: The packet Buffer outputs the data stored in the packet Buffer according to the second depth read address.

[0051] In some embodiments, step S4 specifically includes: The relative read address module determines whether to use the first method or the second method to obtain the second absolute read address according to the second decoding information. When obtaining the second absolute read address using the first method, the second absolute read address unit obtains the absolute read address offset of the packet Buffer recorded in the second register, and adds the second relative read address and the absolute read address offset of the packet Buffer to obtain the second absolute read address. When obtaining the second absolute read address using the second method, the second absolute read address unit uses the second relative read address as the second absolute read address.

[0052] In some embodiments, step S2 specifically includes: The instruction decoding module receives the third instruction sent by the instruction pipeline and parses the third instruction according to a preset decoding table to obtain third decoding information. Step S3 specifically includes: The relative read address module obtains a third relative read address according to the third decoding information. Step S4 specifically includes: The third absolute read address unit obtains a third absolute read address according to the third decoding information. Step S51 specifically includes: The third read address generation unit obtains a third depth read address according to the third absolute read address. Step S52 specifically includes: The Key Buffer outputs the data stored in the Key Buffer according to the third depth read address.

[0053] In some embodiments, step S51 specifically includes: The relative read address module determines to obtain the third absolute read address using the first method or the second method according to the third decoding information; When obtaining the third absolute read address using the first method, the third absolute read address unit obtains the absolute read address offset of the Key Buffer recorded in the third register, and adds the third relative read address and the absolute read address offset of the Key Buffer to obtain the third absolute read address; When obtaining the third absolute read address using the method, the third absolute read address unit uses the third relative read address as the third absolute read address.

[0054] In some embodiments, the data output module processes the data output by the Buffer module and then sends it to the instruction pipeline, including: The data output module splices, shifts, masks, or performs format conversion on the data output by the Buffer module, and then sends it to the instruction pipeline.

[0055] The data processing method of the embodiments of the present application is implemented based on the programmable input buffer circuit of the above embodiments. The circuit principle of the programmable input buffer circuit of the above embodiments has been described in detail. Therefore, the content not described in detail in the data processing method of this embodiment can be obtained by referring to the programmable input buffer circuit of the above embodiments, so it will not be elaborated in this embodiment.

[0056] Another embodiment of the present application provides a chip, including the programmable input buffer circuit described in the above embodiments.

[0057] The various embodiments of the present application have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to technologies in the market, or to enable other ordinary skill in the art in the technical field to understand the embodiments disclosed herein.

Claims

1. A programmable input buffer circuit, characterized in that, it includes: A data input module, configured to receive data input by a peripheral device and store the data input by the peripheral device into a buffer module; An instruction decoding module, configured to receive an instruction issued by an instruction pipeline and parse the instruction according to a preset decoding table to obtain decoding information; A relative read address module, configured to obtain a relative read address according to the decoding information; An absolute read address module, configured to generate an absolute read address according to the relative read address; A buffer module, configured to store the data received by the data input module and output the data stored in the buffer module according to the absolute read address; A data output module, configured to process the data output by the buffer module and send it to the instruction pipeline.

2. The programmable input buffer circuit according to claim 1, characterized in that, the buffer module includes: A read address generation module, configured to generate a depth read address according to the absolute read address; A Buffer module, configured to store the data received by the data input module and output the data stored in the Buffer module according to the depth read address; wherein, the Buffer module includes a multi-bank storage structure.

3. The programmable input buffer circuit according to claim 2, characterized in that, the instruction decoding module is specifically configured to receive a first instruction issued by an instruction pipeline and parse the first instruction according to a preset decoding table to obtain first decoding information; the relative read address module is specifically configured to obtain a first relative read address according to the first decoding information; the absolute read address module includes a first absolute read address unit of the relative read address module, and the first absolute read address unit is configured to obtain a first absolute read address according to the first decoding information; the read address generation module includes a first read address generation unit, and the first read address generation unit is configured to obtain a first depth read address according to the first absolute read address; the Buffer module includes a Meta Buffer, and the Meta Buffer is configured to output the data stored in the Meta Buffer according to the first depth read address, and the Meta Buffer is a multi-bank storage structure.

4. The programmable input buffer circuit according to claim 3, characterized in that, the absolute read address module further includes a first register, and the first register is configured to record the absolute read address offset of the Meta Buffer; wherein, the first absolute read address unit is specifically configured to add the first relative read address and the absolute read address offset of the Meta Buffer to obtain the first absolute read address when the first instruction indicates to obtain the first absolute read address in a first manner; when the first instruction indicates to obtain the first absolute read address in a second manner, use the first relative read address as the first absolute read address.

5. The programmable input buffer circuit according to claim 2, characterized in that, The instruction decoding module is specifically configured to receive a second instruction issued by an instruction pipeline, and parse the second instruction according to a preset decoding table to obtain second decoding information; The relative read address module is specifically configured to obtain a second relative read address according to the second decoding information; The absolute read address module includes a second absolute read address unit of the relative read address module, and the second absolute read address unit is configured to obtain a second absolute read address according to the second decoding information; The read address generation module includes a second read address generation unit, and the second read address generation unit is configured to obtain a second depth read address according to the second absolute read address; The Buffer module includes a message Buffer, and the message Buffer is configured to output data stored in the message Buffer according to the second depth read address, and the message Buffer is a multi-bank storage structure.

6. The programmable input buffer circuit according to claim 5, wherein, the absolute read address module further includes a second register, and the second register is configured to record an absolute read address offset of the message Buffer; wherein, the second absolute read address unit is specifically configured to add the second relative read address and the absolute read address offset of the message Buffer to obtain the second absolute read address when the second instruction indicates to obtain the second absolute read address in a first manner; and use the second relative read address as the second absolute read address when the second instruction indicates to obtain the second absolute read address in a second manner.

7. The programmable input buffer circuit according to claim 2, wherein, the instruction decoding module is specifically configured to receive a third instruction issued by an instruction pipeline, and parse the third instruction according to a preset decoding table to obtain third decoding information; the relative read address module is specifically configured to obtain a third relative read address according to the third decoding information; the absolute read address module includes a third absolute read address unit of the relative read address module, and the third absolute read address unit is configured to obtain a third absolute read address according to the third decoding information; the read address generation module includes a third read address generation unit, and the third read address generation unit is configured to obtain a third depth read address according to the third absolute read address; the Buffer module includes a Key Buffer, and the Key Buffer is configured to output data stored in the Key Buffer according to the third depth read address, and the Key Buffer is a multi-bank storage structure.

8. The programmable input buffer circuit according to claim 7, wherein, the absolute read address module further includes a third register, and the third register is configured to record an absolute read address offset of the Key Buffer; Wherein, the third absolute read address unit is specifically configured to, when the third instruction indicates obtaining the third absolute read address by using the first method, add the third relative read address and the absolute read address offset of the Key Buffer to obtain the third absolute read address; when the third instruction indicates obtaining the third absolute read address by using the second method, use the third relative read address as the third absolute read address.

9. The programmable input buffer circuit according to any one of claims 1 to 8, wherein, the data output module is specifically configured to splice, shift, mask, or perform format conversion on the data output by the Buffer module.

10. A data processing method implemented based on the programmable input buffer circuit according to any one of claims 1 to 9, the method comprises: The data input module receives the data input by the peripheral device and stores the data input by the peripheral device into the buffer module; The instruction decoding module receives the instruction issued by the instruction pipeline and parses the instruction according to a preset decoding table to obtain decoding information; The relative read address module obtains a relative read address according to the decoding information; The absolute read address module generates an absolute read address according to the relative read address; The buffer module stores the data received by the data input module and outputs the data stored in the buffer module according to the absolute read address; The data output module processes the data output by the buffer module and sends it to the instruction pipeline.

11. The data processing method according to claim 10, wherein, the method specifically comprises: The read address generation module generates a depth read address according to the absolute read address; The Buffer module outputs the data stored in the Buffer module according to the depth read address; wherein, the Buffer module includes a multi-bank storage structure.

12. The data processing method according to claim 11, wherein, the method specifically comprises: The instruction decoding module receives a first instruction issued by the instruction pipeline and parses the first instruction according to a preset decoding table to obtain first decoding information; The relative read address module obtains a first relative read address according to the first decoding information; The first absolute read address unit obtains a first absolute read address according to the first decoding information; The first read address generation unit obtains a first depth read address according to the first absolute read address; The Meta Buffer outputs the data stored in the Meta Buffer according to the first depth read address.

13. The data processing method according to claim 12, wherein, the first absolute read address unit obtaining a first absolute read address according to the first decoding information comprises: The relative read address module determines to obtain a second absolute read address by using the first method or the second method according to the first decoding information; When obtaining the first absolute read address using the first method, the first absolute read address unit obtains the absolute read address offset of the Meta Buffer recorded in the first register, and adds the first relative read address and the absolute read address offset of the Meta Buffer to obtain the first absolute read address; When obtaining the first absolute read address using the second method, the first absolute read address unit uses the first relative read address as the first absolute read address.

14. The data processing method according to claim 10, characterized in that, the method specifically includes: The instruction decoding module receives a second instruction sent by the instruction pipeline, and parses the second instruction according to a preset decoding table to obtain second decoding information; The relative read address module obtains a second relative read address according to the second decoding information; The second absolute read address unit obtains a second absolute read address according to the second decoding information; The second read address generation unit obtains a second depth read address according to the second absolute read address; The packet Buffer outputs the data stored in the packet Buffer according to the second depth read address.

15. The data processing method according to claim 14, characterized in that, the second absolute read address unit obtaining a second absolute read address according to the second decoding information includes: The relative read address module determines to use the first method or the second method to obtain the second absolute read address according to the second decoding information; When obtaining the second absolute read address using the first method, the second absolute read address unit obtains the absolute read address offset of the packet Buffer recorded in the second register, and adds the second relative read address and the absolute read address offset of the packet Buffer to obtain the second absolute read address; When obtaining the second absolute read address using the second method, the second absolute read address unit uses the second relative read address as the second absolute read address.

16. The data processing method according to claim 10, characterized in that, the method includes: The instruction decoding module receives a third instruction sent by the instruction pipeline, and parses the third instruction according to a preset decoding table to obtain third decoding information; The relative read address module obtains a third relative read address according to the third decoding information; The third absolute read address unit obtains a third absolute read address according to the third decoding information; The third read address generation unit obtains a third depth read address according to the third absolute read address; The Key Buffer outputs the data stored in the Key Buffer according to the third depth read address.

17. The data processing method according to claim 16, characterized in that, the third absolute read address unit obtaining a third absolute read address according to the third decoding information includes: The relative read address module determines to use the first method or the second method to obtain the third absolute read address according to the third decoding information; When obtaining the third absolute read address using the first method, the third absolute read address unit obtains the absolute read address offset of the Key Buffer recorded in the third register, and adds the third relative read address and the absolute read address offset of the Key Buffer to obtain the third absolute read address; When obtaining the third absolute read address using a method, the third absolute read address unit uses the third relative read address as the third absolute read address.

18. The data processing method according to any one of claims 10 to 17, characterized in that, the data output module processes the data output by the Buffer module and then sends it to the instruction pipeline, including: The data output module splices, shifts, masks, or performs format conversion on the data output by the Buffer module, and then sends it to the instruction pipeline.

19. A chip, characterized in that, it includes the programmable input buffer circuit according to any one of claims 1 to 10.

Images