Programmable output buffer circuit, data processing method and chip

Abstract

The invention relates to a programmable output buffer circuit, a data processing method and a chip, and the circuit comprises an instruction decoding module which is used for receiving a data writing instruction sent by an instruction pipeline, and decoding the data writing instruction according to a preset decoding table, so as to obtain a relative writing address and to-be-written data; the absolute write address acquisition module is used for generating an absolute write address according to the relative write address; the writing control module is used for generating a writing control instruction according to the absolute writing address and data to be written; the Buffer module is used for storing the to-be-written data to a storage position corresponding to the absolute write address according to the write control instruction; and the sending data processing module is used for processing the data output by the Buffer module to obtain bus interface data and sending the bus interface data to external equipment. The circuit provided by the invention has flexible programmable capability and can adapt to continuous change of a network protocol.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and particularly relates to a programmable output buffer circuit, a data processing method, and a chip. Background Art

[0002] In network data transmission, a storage device used to bridge the speed gap between different data processing rates is called a buffer. Buffers are divided into two types: input buffers (In Buffer) and output buffers (Out Buffer). The function of an input buffer is to temporarily store data sent by external devices so that the processor can fetch it; the function of an output buffer is to temporarily store data sent by the processor to external devices. Buffers can coordinate and buffer between a network processor operating at high speed and external devices operating at low speed, achieving data transfer synchronization.

[0003] Currently used output buffers are usually in a non-programmable fixed form. Different input buffers with different functions are selected according to different requirements, and their functions cannot be changed. It is a fixed-function circuit. The fixed-form input buffer has the following problems: When new functions are added to the network protocol, the fixed-form output buffer cannot support the new protocol features. Especially in the current situation of the rapid development of the Internet / cloud, network protocols are constantly changing, so it cannot meet the operation needs of Internet / cloud manufacturers. Summary of the Invention

[0004] The purpose of the present application is to provide a programmable output buffer circuit, a data processing method, and a chip, which have flexible programmable capabilities and can adapt to the continuous changes of network protocols.

[0005] To achieve the above purpose, an embodiment of the present application provides a programmable output buffer circuit, including: An instruction decoding module, configured to receive a write data instruction sent by an instruction pipeline, and decode the write data instruction according to a preset decoding table to obtain a relative write address and data to be written; An absolute write address obtaining module, configured to generate an absolute write address according to the relative write address; A write control module, configured to generate a write control instruction according to the absolute write address and the data to be written; A Buffer module, configured to store the data to be written to a storage location corresponding to the absolute write address according to the write control instruction; A transmitted data processing module, configured to process the data output by the Buffer module to obtain bus interface data, and send the bus interface data to an external device.

[0006] The embodiment of the present application further provides a data processing method, which is implemented based on the above programmable output buffer circuit. The method includes: The instruction decoding module receives the write data instruction sent by the instruction pipeline, and decodes the write data instruction according to a preset decoding table to obtain a relative write address and data to be written. The absolute write address acquisition module generates an absolute write address according to the relative write address. The write control module generates a write control instruction according to the absolute write address and the data to be written. The Buffer module stores the data to be written into the storage location corresponding to the absolute write address according to the write control instruction. The data sending and processing module processes the data output by the Buffer module and sends it to an external device.

[0007] The embodiment of the present application further provides a chip, which includes the above programmable output buffer circuit.

[0008] The embodiment of the present application provides a programmable output buffer circuit, a data processing method, and a chip. Only a preset instruction set needs to be provided. The instruction set includes multiple basic instructions, such as the RISC-V instruction set or a set of the RISC-V instruction set and other custom instructions. Therefore, when applying the embodiment of the present application, a preset decoding table can be written according to the Buffer function requirements and the preset instruction set, endowing the instruction decoding module with corresponding decoding capabilities, capable of decoding the instructions in the instruction pipeline of the processor to obtain corresponding data to be written and address data. Modules such as the absolute write address module and the Buffer module can write the data to be written into the Buffer module for temporary storage according to the data to be written and the address data. Finally, the data temporarily stored in the Buffer module is sent to an external device by the data sending and processing module. As described in the background art, the currently used output buffer is usually in a non-programmable fixed form, which is a fixed-function circuit. Compared with the fixed-form output buffer, the output buffer circuit of the embodiment of the present application has flexible programmable capabilities, enabling it to adapt to the continuous changes of network protocols, maximizing the service life of the device, and saving the device replacement cost.

[0009] More features and advantages of the embodiment of the present application are reflected in the specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0011] Figure 1 It is a structural diagram of a programmable output buffer circuit in an embodiment of the present application.

[0012] Figure 2 It is a structural diagram of a multi-bank memory in an embodiment of the present application.

[0013] Figure 3 It is a structural diagram of a programmable output buffer circuit in another embodiment of the present application.

[0014] Figure 4 It is a flowchart of a data processing method in an embodiment of the present application. Detailed implementation manners

[0015] Refer to Figure 1 In an embodiment of the present application, a programmable output buffer (Out-Buffer) circuit is provided, which includes an instruction decoding module, an absolute write address acquisition module, a write control module, a Buffer module, and a transmitted data processing module.

[0016] The instruction decoding module 1 is configured to receive the write data instruction sent by the instruction pipeline, decode the write data instruction according to a preset decoding table to obtain a relative write address and data to be written, send the relative write address to the absolute write address acquisition module 2, and send the data to be written to the write control module 3.

[0017] Specifically, the relative write address can be a write address value with a granularity of 1 bit, 2 bits, 4 bits, or 8 bits. The instruction pipeline of the network processor sends a write control instruction to the programmable output buffer circuit of this embodiment to write the data to be sent to an external device into the Buffer module 4 for temporary storage and then send it to the external device later. In this embodiment, only a preset instruction set needs to be provided. The instruction set includes multiple basic instructions, such as the RISC-V instruction set or a set of the RISC-V instruction set and other custom instructions. Therefore, when applying the embodiment of the present application, a preset decoding table can be written according to the Buffer function requirements and the preset instruction set to endow the instruction decoding module 1 with corresponding decoding capabilities, and the instructions of the processor's instruction pipeline can be decoded to obtain corresponding data to be written and relative write addresses, etc.

[0018] The absolute write address acquisition module 2, connected to the instruction decoding module 1, is configured to generate an absolute write address based on the relative write address and send the absolute write address to the write control module 3.

[0019] Specifically, the relative write address is the base address for accessing the memory in the Buffer module 4. The correct position of the memory cannot be directly accessed based on the relative write address, and an absolute write address needs to be obtained by adding a corresponding offset address to the relative write address.

[0020] The write control module 3, connected to the instruction decoding module 1, is configured to generate a write control instruction based on the absolute write address and the data to be written, and send the write control instruction to the Buffer module 4.

[0021] Specifically, the write control instruction includes the absolute write address and the data to be written.

[0022] The Buffer module 4, connected to the write control module 3, is configured to store the data to be written to the storage location corresponding to the absolute write address according to the write control instruction.

[0023] Specifically, the data temporarily stored in the Buffer module 4 is sent to the external device in sequence. After the data is written and temporarily stored in the Buffer module 4, the network processor can continue with other tasks. Compared with directly sending the data to the external device, the high-speed network processor does not need to wait for the response of the slow-speed external device, thereby improving the working efficiency of the network processor. It should be noted that the Buffer module 4 with special functions can be designed according to the usage function and service characteristic requirements of the Out Buffer. In this embodiment, it is not limited to a specific Buffer module 4 with special functions. The Buffer module 4 is, for example, one or more of a Meta Buffer, a message, and a Key Buffer.

[0024] The data sending processing module 5, connected to the Buffer module 4, is configured to process the data output by the Buffer module 4 to obtain bus interface data and send the bus interface data to the external device.

[0025] Specifically, the data output by the Buffer module 4 does not meet the bus interface requirements. Therefore, the data needs to be processed into bus interface data that meets the requirements before it can be sent to the external device through the bus interface.

[0026] It should be noted that when the output buffer of this embodiment is applied, only a preset instruction set needs to be provided. The instruction set includes multiple basic instructions, such as the RISC-V instruction set or a combination of the RISC-V instruction set and other custom instructions. Thus, when applying the embodiment of the present application, a preset decoding table can be written according to the Buffer function requirements and the preset instruction set, endowing the instruction decoding module with corresponding decoding capabilities, being able to decode the instructions in the instruction pipeline of the processor to obtain corresponding data to be written and address data. Modules such as the absolute write address module and the Buffer module can write the data to be written into the Buffer module for temporary storage according to the data to be written and the address data, and finally send the data temporarily stored in the Buffer module to an external device through the data sending and processing module. As described in the background art, the currently used output buffer is usually in an unprogrammable fixed form, which is a kind of fixed function circuit. Compared with the fixed-form output buffer, the output buffer circuit of the embodiment of the present application has flexible programmable capabilities, enabling it to adapt to the continuous changes of network protocols, maximizing the service life of the device, and saving the device replacement cost.

[0027] In some embodiments, the Buffer module 4 includes at least one multi-Bank memory; the multi-Bank memory is formed by splicing multiple physical storage banks with the same structure, and each physical storage bank is a Bank; the design of the multi-Bank memory can be determined according to the design function indicators of the processor. For example, if it is required to "support 256-bit bus writing and simultaneously read any 1 to 256 consecutive bits", then it can be designed as n 256-bit wide Banks, where n is a positive integer greater than or equal to 2. As Figure 2 shown in a 4-Bank memory, that is, it includes 4 identical physical storage banks, numbered Bank0, Bank1, Bank2, and Bank3 respectively.

[0028] The write control module 3 is used to determine to write the data to be written into at least one physical storage bank according to the absolute write address and the length of the data to be written, generate the depth write address, write enable signal of the at least one physical storage bank, and the data written into the at least one physical storage bank, and generate corresponding write control instructions according to the depth write address, write enable signal of the at least one physical storage bank, and the data written into the at least one physical storage bank; The multi-Bank memory is used to store the data to be written into the corresponding at least one physical storage bank according to the write control instructions.

[0029] Specifically, when writing data to be written into a multi - Bank memory, it is necessary to determine which Bank of the multi - Bank memory the data to be written will be written into. Therefore, it is necessary to determine which address spaces of the multi - Bank memory the data to be written will occupy according to the absolute write address and the length of the data to be written. For example, Figure 2 as shown, the bit - width of each Bank is 64 bit, and the overall bit - width of the multi - Bank memory is 256 bit. The write - enable signal includes four bits [a, b, c, d], corresponding to Bank0, Bank1, Bank2, and Bank3 respectively.

[0030] For example, if the absolute write address is Byte9, Byte0~Byte7 is the 0th row of Bank0, Byte8~Byte15 is the 0th row of Bank1, Byte16~Byte23 is the 0th row of Bank2, and Byte24~Byte31 is the 0th row of Bank3, then Byte9 is located in the 0th row of Bank1. If the length of the data to be written is 64 bit (1Byte = 8bit), then the data to be written needs to occupy the storage space of the 0th row of Bank1 and Bank2, and does not need to occupy the storage space of Bank0 and Bank3. It is determined to write the data to be written into Bank1 and Bank2, and generate the depth write addresses, write - enable signals, and data written into Bank1 and Bank2. The generated depth write addresses of Bank1 and Bank2 are 0 and 0 respectively, the write - enable signals of Bank1 and Bank2 are valid. The valid write - enable signal can be represented by 1, and the invalid write - enable signal can be represented by 0. It is determined to write the first 56 - bit data of the data to be written into Bank1 (the address space of Byte9~Byte15 in the 0th row), and write the last 8 - bit data of the data to be written into Bank2 (the address space of Byte16 in the 0th row). Finally, corresponding write control instructions are generated according to the depth write addresses, write - enable signals, and data written into Bank1 and Bank2.

[0031] For another example, the absolute write address is Byte25. Byte0 to Byte7 are the 0th row of Bank0, Byte8 to Byte15 are the 0th row of Bank1, Byte16 to Byte23 are the 0th row of Bank2, and Byte24 to Byte31 are the 0th row of Bank3. Then Byte25 is located in the 0th row of Bank3. If the length of the data to be written is 64 bits (1 Byte = 8 bits), the data to be written needs to occupy the storage spaces of the 0th row of Bank3 and the 1st row of Bank0, and does not need to occupy the storage spaces of Bank1 and Bank2. It is determined to write the data to be written into Bank0 and Bank3, and the deep write addresses, write enable signals, and data written into Bank0 and Bank3 are generated. The generated deep write addresses of Bank0 and Bank3 are 1 and 0 respectively, and the write enable signals of Bank0 and Bank3 are valid. The valid write enable signal can be represented by 1, and the invalid write enable signal can be represented by 0. It is determined to write the first 56-bit data of the data to be written into Bank3 (the address space of Byte25 to Byte31 in the 0th row), and write the last 8-bit data of the data to be written into Bank0 (the address space of Byte32 in the 1st row). Finally, corresponding write control instructions are generated according to the deep write addresses, write enable signals, and data written into Bank0 and Bank3.

[0032] The multi-Bank memory is used to store the data to be written into at least one physical memory bank corresponding to the deep write address and the write enable signal according to the write control instruction.

[0033] Specifically, for example, the absolute write address is Byte9, the length of the data to be written is 64 bits, the deep write addresses of Bank1 and Bank2 are 0 and 0 respectively, the write enable signals of Bank1 and Bank2 are valid, and the first 56-bit data of the data to be written is written into Bank1 (the address space of Byte9 to Byte15 in the 0th row), and the multi-Bank memory writes the last 8-bit data of the data to be written into Bank2 (the address space of Byte16 in the 1st row); For another example, the absolute write address is Byte25, the length of the data to be written is 64 bits, the deep write addresses of Bank0 and Bank3 are 1 and 0 respectively, the write enable signals of Bank0 and Bank3 are valid, and the multi-Bank memory writes the first 56-bit data of the data to be written into Bank3 (the address space of Byte25 to Byte31 in the 0th row), and writes the last 8-bit data of the data to be written into the address space of Byte32 in the 1st row of Bank0.

[0034] In some embodiments, the instruction decoding module 1 is specifically configured to receive a first write data instruction issued by an instruction pipeline, decode the first write data instruction according to the decoding table to obtain a first relative write address and a first data to be written, and determine that the functional Buffer to be accessed is a Meta Buffer, and then send the first relative write address and the first data to be written to a first write control unit corresponding to the Meta Buffer.

[0035] Specifically, different functional Buffers are designed according to different data types. In this embodiment, the Buffer module 4 includes a Meta Buffer, and the first write control instruction is used to indicate writing the data to be written into the Meta Buffer. The MetaBuffer is mainly used to store metadata of network packets, such as packet types, offset addresses of each packet header, various Qos information that the packet needs to process, and other information that needs to be transmitted with the packet. It should be noted that the specific use of the MetaBuffer is well-known to those skilled in the art. The inventive point of this embodiment does not lie in the functional design of the Meta Buffer, but in enabling the input buffer circuit to have flexible programmable capabilities. Moreover, the Meta Buffer is designed as a multi-Bank memory to achieve output of any bit of data. Therefore, the data storage use of the Meta Buffer will not be described in more detail here.

[0036] The absolute write address acquisition module 2 includes a first absolute write address acquisition unit. The first absolute write address acquisition unit is connected to the instruction decoding module 1, and the first absolute write address acquisition unit is used to generate a first absolute write address according to the first relative write address; The write control module 3 includes a first write control unit. The first write control unit is connected to the first absolute write address. The first write control unit is used to determine at least one physical storage bank of the Meta Buffer to which the first data to be written is to be written according to the first absolute write address and the length of the first data to be written, and generate a depth write address, a write enable signal, and data to be written into at least one physical storage bank of the Meta Buffer, and generate a corresponding first write control instruction according to the depth write address, the write enable signal, and the data to be written into at least one physical storage bank of the Meta Buffer; The Buffer module 4 includes a Meta Buffer, and the Meta Buffer includes a multi - Bank memory of multiple physical storage banks. The Meta Buffer is used to store the first data to be written into at least one physical storage bank of the Meta Buffer according to the first write control instruction.

[0037] In some embodiments, the absolute write address acquisition module 2 further includes a first register, and the first register is used to record the offset address of the Meta Buffer; When the first write data instruction is of the automatic mode instruction type, the first write control instruction carries a relative write address and does not carry an offset address. The instruction decoding module 1 is specifically configured to decode the first write data instruction to obtain a first relative write address. The first absolute write address acquisition unit is specifically configured to add the first relative write address and the offset address of the Meta Buffer to obtain the first absolute write address, and update the offset address of the Meta Buffer according to the first absolute write address and the length of the first data to be written; specifically, the updated offset address of the Meta Buffer is "the first absolute write address + the length of the first data to be written", that is, write "the first absolute write address + the length of the first data to be written" into the first register; When the first write data instruction is of the non - automatic mode instruction type, the first write control instruction carries a relative write address and an offset address. The instruction decoding module 1 is specifically configured to decode the first write data instruction to obtain a first relative write address and a first offset address. The first absolute write address acquisition unit is specifically configured to add the first relative write address and the first offset address to obtain the first absolute write address. At this time, it is not necessary to update the offset address of the Meta Buffer in the first register.

[0038] In some embodiments, the instruction decoding module 1 is specifically configured to receive a second write data instruction issued by an instruction pipeline, decode the second write data instruction according to the decoding table to obtain a second relative write address and a second data to be written, and determine that the functional Buffer to be accessed is a message Buffer, then send the second relative write address and the second data to be written to a second write control unit corresponding to the message Buffer.

[0039] Specifically, different functional Buffers are designed according to different data types. In this embodiment, the Buffer module 4 includes a message Buffer, and the second write control instruction is used to indicate writing the data to be written into the message Buffer. The message Buffer is mainly used to store externally input messages or partial message information, such as: message headers, message headers + message tails, or message leaders + message headers, etc. It should be noted that the specific use of the message Buffer is well-known to those skilled in the art. The inventive point of this embodiment does not lie in the functional design of the message Buffer, but in enabling the input buffer circuit to have flexible programmable capabilities. Moreover, the message Buffer is designed as a multi-Bank memory to achieve output of any bit of data. Therefore, the data storage use of the message Buffer will not be described in more detail here.

[0040] The absolute write address acquisition module 2 includes a second absolute write address acquisition unit, and the second absolute write address acquisition unit is connected to the instruction decoding module 1. The second absolute write address acquisition unit is used to generate a second absolute write address according to the second relative write address; The write control module 3 includes a second write control unit, and the second write control unit is connected to the second absolute write address. The second write control unit is used to determine at least one physical storage bank of the message Buffer to which the second data to be written is to be written according to the second absolute write address and the length of the second data to be written, and generate a depth write address, a write enable signal of at least one physical storage bank of the message Buffer, and data written into at least one physical storage bank of the message Buffer, and generate a corresponding second write control instruction according to the depth write address, the write enable signal of at least one physical storage bank of the message Buffer, and the data written into at least one physical storage bank of the message Buffer; The Buffer module 4 includes a message Buffer, and the message Buffer includes a multi-Bank memory with multiple physical storage banks. The message Buffer is used to store the second data to be written into at least one physical storage bank of the message Buffer according to the second write control instruction.

[0041] In some embodiments, the absolute write address acquisition module 2 further includes a second register, and the second register is used to record the offset address of the message Buffer; When the second write data instruction is of the automatic mode instruction type, the second write control instruction carries a relative write address and does not carry an offset address. The instruction decoding module 1 is specifically configured to decode the second write data instruction to obtain a second relative write address. The second absolute write address acquisition unit is specifically configured to add the second relative write address and the offset address of the message Buffer to obtain the second absolute write address, and update the offset address of the message Buffer according to the second absolute write address and the length of the second data to be written. Specifically, the updated offset address of the message Buffer is "the second absolute write address + the length of the second data to be written", that is, write "the second absolute write address + the length of the second data to be written" into the second register. When the second write data instruction is of the non-automatic mode instruction type, the second write control instruction carries a relative write address and an offset address. The instruction decoding module 1 is specifically configured to decode the second write data instruction to obtain a second relative write address and a second offset address. The second absolute write address acquisition unit is specifically configured to add the second relative write address and the second offset address to obtain the second absolute write address. At this time, it is not necessary to update the offset address of the message Buffer in the second register.

[0042] In some embodiments, the instruction decoding module 1 is specifically configured to receive a third write data instruction issued by an instruction pipeline, decode the third write data instruction according to the decoding table to obtain a third relative write address and a third data to be written, and determine that the function Buffer to be accessed is the Key Buffer, then send the third relative write address and the third data to be written to a third write control unit corresponding to the Key Buffer.

[0043] Specifically, different function Buffers are designed according to different data types. In this embodiment, the Buffer module 4 includes a Key Buffer. The third write control instruction is used to indicate writing the data to be written into the Key Buffer. The KeyBuffer is mainly used to store the keywords required for table lookup. The keyword may be a set of data spliced by multiple instructions, such as the five-tuple information of a message. It should be noted that the specific use of the Key Buffer is well known to those skilled in the art. The invention point of this embodiment does not lie in the functional design of the Key Buffer, but lies in enabling the input buffer circuit to have flexible programmable capabilities. And the Key Buffer is designed as a multi-Bank memory to achieve output of any bit data. Therefore, the data storage use of the Key Buffer is not described in more detail here.

[0044] The absolute write address acquisition module 2 includes a third absolute write address acquisition unit, which is connected to the instruction decoding module 1. The third absolute write address acquisition unit is configured to generate a third absolute write address according to the third relative write address; The write control module 3 includes a third write control unit, which is connected to the third absolute write address. The third write control unit is configured to determine at least one physical storage bank of the Key Buffer to which the third data to be written is to be written according to the third absolute write address and the length of the third data to be written, and generate a depth write address, a write enable signal, and data to be written into at least one physical storage bank of the Key Buffer, and generate a corresponding third write control instruction according to the depth write address, the write enable signal, and the data to be written into at least one physical storage bank of the Key Buffer; The Buffer module 4 includes a Key Buffer, and the Key Buffer includes a multi-Bank memory with a plurality of physical storage banks. The Key Buffer is configured to store the third data to be written into at least one physical storage bank of the Key Buffer according to the third write control instruction.

[0045] In some embodiments, the absolute write address acquisition module 2 further includes a third register, which is configured to record the offset address of the Key Buffer; When the third write data instruction is of the automatic mode instruction type, the third write control instruction carries a relative write address and does not carry an offset address. The instruction decoding module 1 is specifically configured to decode the third write data instruction to obtain a third relative write address. The third absolute write address acquisition unit is specifically configured to add the third relative write address and the offset address of the Key Buffer to obtain the third absolute write address, and update the offset address of the Key Buffer according to the third absolute write address and the length of the third data to be written; specifically, the updated offset address of the Key Buffer is "third absolute write address + length of the third data to be written", that is, write "third absolute write address + length of the third data to be written" into the third register; When the third write data instruction is of the non-automatic mode instruction type, the third write control instruction carries a relative write address and an offset address. The instruction decoding module 1 is specifically configured to decode the third write data instruction to obtain a third relative write address and a third offset address. The third absolute write address obtaining unit is specifically configured to add the third relative write address and the third offset address to obtain the third absolute write address. At this time, it is not necessary to update the offset address of the KeyBuffer in the third register.

[0046] In some embodiments, the sending data processing module 5 is specifically configured to splice, shift, mask, or perform format conversion on the multiple data output by the multiple physical storage banks to obtain bus interface data, and send the bus interface data to an external device.

[0047] Specifically, for example, a multi-Bank memory adopts a 4-Bank design. The 4 Banks are sequentially numbered as Bank0, Bank1, Bank2, and Bank3. The bit width of each Bank is 64 bits. If a target data to be output is segmented and stored in multiple Banks, then operations such as splicing and shifting need to be performed on the data output by the multiple Banks. If the bit width of the bus interface data is greater than the bit width of the output target data, then a masking operation needs to be performed on several bits. The format conversion swap refers to the big-endian and little-endian format conversion. Whether to perform the conversion depends on the data format requirements of the instruction pipeline and the data output of the circuit design.

[0048] In some embodiments, refer to Figure 3 , the circuit further includes: A sending instruction queue 6, which is used to temporarily store the instructions issued by the instruction pipeline.

[0049] Specifically, the sending instruction queue is a FIFO (First IN First Out) module. The instructions in the sending instruction queue are used to read the data in the Buffer module 4 and send it to an external device through the sending data processing module 5 and the bus interface. Because multi-cycle operations may be required, the instructions coming from the instruction pipeline of the network processor need to be temporarily stored in the sending instruction queue. The instructions in the sending instruction queue are queued and executed in the order of first come first served. When the corresponding function Buffer in the Buffer module 4 is idle, the earliest-arrived instruction in the sending instruction queue is sent to the corresponding function Buffer. After receiving the instruction, the corresponding function Buffer outputs the corresponding data to the sending data processing module 5.

[0050] Refer to Figure 4, another embodiment of the present application provides a data processing method, which is implemented based on the programmable output buffer circuit described in the above embodiment. The method includes: Step S1, the instruction decoding module receives the write data instruction issued by the instruction pipeline, decodes the write data instruction according to a preset decoding table, and obtains a relative write address and data to be written; Step S2, the absolute write address acquisition module generates an absolute write address according to the relative write address; Step S3, the write control module generates a write control instruction according to the absolute write address and the data to be written; Step S4, the Buffer module stores the data to be written to the storage location corresponding to the absolute write address according to the write control instruction; Step S5, the data sending and processing module processes the data output by the Buffer module and sends it to an external device.

[0051] In some embodiments, the Buffer module includes at least one multi-Bank memory; The method specifically includes: The write control module determines the depth write address, write enable signal, and data written to each physical storage bank according to the absolute write address and the length of the data to be written, and generates a write control instruction according to the depth write address, write enable signal, and data written to each physical storage bank; The multi-Bank memory stores the data to be written into the corresponding at least one physical storage bank according to the write control instruction.

[0052] In some embodiments, the absolute write address acquisition module includes a first absolute write address acquisition unit, the write control module includes a first write control unit, the Buffer module includes a Meta Buffer, and the Meta Buffer is a multi-Bank memory including multiple physical storage banks; The method specifically includes: The instruction decoding module receives the first write data instruction issued by the instruction pipeline, decodes the first write data instruction according to the decoding table to obtain a first relative write address and a first data to be written, and determines that the Buffer to be accessed is the Meta Buffer; The first absolute write address acquisition unit generates a first absolute write address according to the first relative write address; The first write control unit determines the depth write address, write enable signal, and data to be written into each physical storage bank of the Meta Buffer according to the first absolute write address and the length of the data to be written, and generates a first write control instruction according to the depth write address, write enable signal, and data to be written into each physical storage bank of the Meta Buffer; The Meta Buffer stores the data to be written into at least one corresponding physical storage bank according to the first write control instruction.

[0053] In some embodiments, the absolute write address acquisition module further includes a first register for recording the offset address of the Meta Buffer; The method specifically includes: When the first write data instruction is of the automatic mode instruction type, the instruction decoding module decodes the first write data instruction to obtain a first relative write address, and the first absolute write address acquisition unit adds the first relative write address and the offset address of the Meta Buffer to obtain the first absolute write address; When the first write data instruction is of the non-automatic mode instruction type, the instruction decoding module decodes the first write data instruction to obtain a first relative write address and a first offset address, and the first absolute write address acquisition unit adds the first relative write address and the first offset address to obtain the first absolute write address, and updates the offset address of the Meta Buffer according to the first absolute write address and the length of the first data to be written.

[0054] In some embodiments, the absolute write address acquisition module includes a second absolute write address acquisition unit, the write control module includes a second write control unit, the Buffer module includes a message Buffer, and the message Buffer is a multi-Bank memory including a plurality of physical storage banks; The method specifically includes: The instruction decoding module receives a second write data instruction sent by the instruction pipeline, decodes the second write data instruction according to the decoding table to obtain a second relative write address and second data to be written, and determines that the Buffer to be accessed is the message Buffer; The second absolute write address acquisition unit generates a second absolute write address according to the second relative write address; The second write control unit determines the depth write address, write enable signal, and data to be written to each physical memory bank of the packet Buffer according to the second absolute write address and the length of the data to be written, and generates a second write control instruction according to the depth write address, write enable signal, and data to be written to each physical memory bank of the packet Buffer; According to the second write control instruction, the packet Buffer stores the data to be written into at least one corresponding physical memory bank.

[0055] In some embodiments, the absolute write address acquisition module further includes a second register, and the second register records the offset address of the packet Buffer; The method specifically includes: When the second write data instruction is of the automatic mode instruction type, the instruction decoding module decodes the second write data instruction to obtain a second relative write address, and the second absolute write address acquisition unit adds the second relative write address and the offset address of the packet Buffer to obtain the second absolute write address; When the second write data instruction is of the non-automatic mode instruction type, the instruction decoding module decodes the second write data instruction to obtain a second relative write address and a second offset address, and the second absolute write address acquisition unit adds the second relative write address and the second offset address to obtain the second absolute write address, and updates the offset address of the packet Buffer according to the second absolute write address and the length of the second data to be written.

[0056] In some embodiments, the absolute write address acquisition module includes a third absolute write address acquisition unit, the write control module includes a third write control unit, the Buffer module includes a Key Buffer, and the Key Buffer is a multi-Bank memory including multiple physical memory banks, The method specifically includes: The instruction decoding module receives a third write data instruction sent by an instruction pipeline, decodes the third write data instruction according to the decoding table to obtain a third relative write address and third data to be written, and determines that the Buffer to be accessed is the Key Buffer; The third absolute write address acquisition unit generates a third absolute write address according to the third relative write address; The third write control unit determines the depth write addresses, write enable signals, and data to be written into each physical memory bank of the Key Buffer according to the third absolute write address and the length of the data to be written, and generates a third write control instruction according to the depth write addresses, write enable signals, and data to be written into each physical memory bank of the Key Buffer; The Key Buffer stores the data to be written into at least one corresponding physical memory bank according to the third write control instruction.

[0057] In some embodiments, the absolute write address acquisition module further includes a third register, and the third register records the offset address of the Key Buffer; The method specifically includes: When the third write data instruction is of the automatic mode instruction type, the instruction decoding module decodes the third write data instruction to obtain a third relative write address, and the third absolute write address acquisition unit adds the third relative write address and the offset address of the Key Buffer to obtain the third absolute write address; When the third write data instruction is of the non - automatic mode instruction type, the instruction decoding module decodes the third write data instruction to obtain a third relative write address and a third offset address, the third absolute write address acquisition unit adds the third relative write address and the third offset address to obtain the third absolute write address, and updates the offset address of the Key Buffer according to the third absolute write address and the length of the third data to be written.

[0058] The data processing method of the embodiment of the present application is implemented based on the programmable output buffer circuit of the above - mentioned embodiment. The circuit principle of the programmable output buffer circuit of the above - mentioned embodiment has been described in detail. Therefore, the content not described in detail in the data processing method of this embodiment can be obtained by referring to the programmable output buffer circuit of the above - mentioned embodiment, so it will not be elaborated in this embodiment.

[0059] Another embodiment of the present application provides a chip, including the programmable output buffer circuit described in the above - mentioned embodiment.

[0060] The embodiments of the present application have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or the improvement of the technology in the market, or to enable other ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A programmable output buffer circuit, characterized in that, it includes: An instruction decoding module, configured to receive a write data instruction sent by an instruction pipeline, and decode the write data instruction according to a preset decoding table to obtain a relative write address and data to be written; An absolute write address obtaining module, configured to generate an absolute write address according to the relative write address; A write control module, configured to generate a write control instruction according to the absolute write address and the data to be written; A Buffer module, configured to store the data to be written to a storage location corresponding to the absolute write address according to the write control instruction; A transmitted data processing module, configured to process the data output by the Buffer module to obtain bus interface data, and send the bus interface data to a bus.

2. The programmable output buffer circuit according to claim 1, characterized in that, the Buffer module includes at least one multi-Bank memory, and the multi-Bank memory includes a plurality of physical memory banks; the write control module is configured to determine to write the data to be written to at least one physical memory bank according to the absolute write address and the length of the data to be written, generate a depth write address, a write enable signal of the at least one physical memory bank, and data written to the at least one physical memory bank, and generate a corresponding write control instruction according to the depth write address, the write enable signal of the at least one physical memory bank, and the data written to the at least one physical memory bank; the multi-Bank memory is configured to store the data to be written to the corresponding at least one physical memory bank according to the write control instruction.

3. The programmable output buffer circuit according to claim 2, characterized in that, the instruction decoding module is specifically configured to receive a first write data instruction sent by an instruction pipeline, decode the first write data instruction according to the decoding table to obtain a first relative write address and a first data to be written, and determine that the Buffer to be accessed is a Meta Buffer; the absolute write address obtaining module includes a first absolute write address obtaining unit, and the first absolute write address obtaining unit is configured to generate a first absolute write address according to the first relative write address; the write control module includes a first write control unit, and the first write control unit is configured to determine to write the first data to be written to at least one physical memory bank of the Meta Buffer according to the first absolute write address and the length of the first data to be written, and generate a depth write address, a write enable signal of the at least one physical memory bank of the Meta Buffer, and data written to the at least one physical memory bank of the Meta Buffer, and generate a corresponding first write control instruction according to the depth write address, the write enable signal of the at least one physical memory bank of the Meta Buffer, and the data written to the at least one physical memory bank of the Meta Buffer; The Buffer module includes a Meta Buffer, and the Meta Buffer includes a multi - Bank memory of multiple physical storage banks. The Meta Buffer is used to store the first data to be written into at least one physical storage bank of the Meta Buffer according to the first write control instruction.

4. The programmable output buffer circuit according to claim 3, wherein, the absolute write address acquisition module further includes a first register, and the first register is used to record the offset address of the Meta Buffer; when the first write data instruction is a preset automatic mode instruction type, the instruction decoding module is specifically configured to decode the first write data instruction to obtain a first relative write address, and the first absolute write address acquisition unit is specifically configured to add the first relative write address and the offset address of the Meta Buffer to obtain the first absolute write address; when the first write data instruction is a preset non - automatic mode instruction type, the instruction decoding module is specifically configured to decode the first write data instruction to obtain a first relative write address and a first offset address, and the first absolute write address acquisition unit is specifically configured to add the first relative write address and the first offset address to obtain the first absolute write address, and update the offset address of the Meta Buffer according to the first absolute write address and the length of the first data to be written.

5. The programmable output buffer circuit according to claim 2, wherein, the instruction decoding module is specifically configured to receive a second write data instruction sent by an instruction pipeline, decode the second write data instruction according to the decoding table to obtain a second relative write address and a second data to be written, and determine that the Buffer to be accessed is a packet Buffer; the absolute write address acquisition module includes a second absolute write address acquisition unit, and the second absolute write address acquisition unit is used to generate a second absolute write address according to the second relative write address; the write control module includes a second write control unit, and the second write control unit is used to determine to write the second data to be written into at least one physical storage bank of the packet Buffer according to the second absolute write address and the length of the second data to be written, and generate a depth write address, a write enable signal of at least one physical storage bank of the packet Buffer, and data written into at least one physical storage bank of the packet Buffer, and generate a corresponding second write control instruction according to the depth write address, the write enable signal of at least one physical storage bank of the packet Buffer, and the data written into at least one physical storage bank of the packet Buffer; the Buffer module includes a packet Buffer, and the packet Buffer includes a multi - Bank memory of multiple physical storage banks. The packet Buffer is used to store the second data to be written into at least one physical storage bank of the packet Buffer according to the second write control instruction.

6. The programmable output buffer circuit according to claim 5, wherein, the absolute write address acquisition module further includes a second register, and the second register is used to record the offset address of the message Buffer; when the second write data instruction is of the automatic mode instruction type, the instruction decoding module is specifically configured to decode the second write data instruction to obtain a second relative write address, and the second absolute write address acquisition unit is specifically configured to add the second relative write address and the offset address of the message Buffer to obtain the second absolute write address; when the second write data instruction is of the non-automatic mode instruction type, the instruction decoding module is specifically configured to decode the second write data instruction to obtain a second relative write address and a second offset address, and the second absolute write address acquisition unit is specifically configured to add the second relative write address and the second offset address to obtain the second absolute write address, and update the offset address of the message Buffer according to the second absolute write address and the length of the second data to be written.

7. The programmable output buffer circuit according to claim 2, wherein, the instruction decoding module is specifically configured to receive a third write data instruction sent by an instruction pipeline, decode the third write data instruction according to the decoding table to obtain a third relative write address and a third data to be written, and determine that the Buffer to be accessed is the Key Buffer; the absolute write address acquisition module includes a third absolute write address acquisition unit, and the third absolute write address acquisition unit is used to generate a third absolute write address according to the third relative write address; the write control module includes a third write control unit, and the third write control unit is used to determine, according to the third absolute write address and the length of the third data to be written, at least one physical storage bank of the Key Buffer to which the third data to be written is to be written, and generate a depth write address, a write enable signal of at least one physical storage bank of the Key Buffer, and data written to at least one physical storage bank of the Key Buffer, and generate a corresponding third write control instruction according to the depth write address, the write enable signal of at least one physical storage bank of the Key Buffer, and the data written to at least one physical storage bank of the Key Buffer; the Buffer module includes a Key Buffer, and the Key Buffer includes a multi-Bank memory of a plurality of physical storage banks, and the Key Buffer is used to store the third data to be written into at least one physical storage bank of the Key Buffer according to the third write control instruction.

8. The programmable output buffer circuit according to claim 7, wherein, the absolute write address acquisition module further includes a third register, and the third register is used to record the offset address of the Key Buffer; When the third write data instruction is of the automatic mode instruction type, the instruction decoding module is specifically configured to decode the third write data instruction to obtain a third relative write address, and the third absolute write address obtaining unit is specifically configured to add the third relative write address and the offset address of the Key Buffer to obtain the third absolute write address; When the third write data instruction is of the non - automatic mode instruction type, the instruction decoding module is specifically configured to decode the third write data instruction to obtain a third relative write address and a third offset address, and the third absolute write address obtaining unit is specifically configured to add the third relative write address and the third offset address to obtain the third absolute write address, and update the offset address of the Key Buffer according to the third absolute write address and the length of the third data to be written.

9. The programmable output buffer circuit according to any one of claims 1 to 8, characterized in that, The data sending processing module is specifically configured to splice, shift, mask or perform format conversion on the multiple data output by the multiple physical storage banks to obtain bus interface data, and send the bus interface data to an external device.

10. The programmable output buffer circuit according to any one of claims 1 to 8, characterized in that, further comprising: A send instruction queue for temporarily storing instructions issued by an instruction pipeline.

11. A data processing method, characterized in that, implemented based on the programmable output buffer circuit according to claim 1, the method comprising: The instruction decoding module receives a write data instruction issued by an instruction pipeline, and decodes the write data instruction according to a preset decoding table to obtain a relative write address and data to be written; The absolute write address obtaining module generates an absolute write address according to the relative write address; The write control module generates a write control instruction according to the absolute write address and the data to be written; The Buffer module stores the data to be written to a storage location corresponding to the absolute write address according to the write control instruction; The data sending processing module processes the data output by the Buffer module and sends it to an external device.

12. The data processing method according to claim 11, characterized in that, The Buffer module includes at least one multi - Bank memory; The method specifically includes: The write control module determines to write the data to be written into at least one physical storage bank according to the absolute write address and the length of the data to be written, generates depth write addresses, write enable signals and data to be written into the at least one physical storage bank, and generates corresponding write control instructions according to the depth write addresses, write enable signals and data to be written into the at least one physical storage bank; The multi - Bank memory stores the data to be written into the corresponding at least one physical storage bank according to the write control instruction.

13. The data processing method according to claim 12, characterized in that, The absolute write address acquisition module includes a first absolute write address acquisition unit, the write control module includes a first write control unit, the Buffer module includes a Meta Buffer, and the Meta Buffer is a multi-Bank memory including a plurality of physical memory banks; The method specifically includes: The instruction decoding module receives a first write data instruction sent by an instruction pipeline, decodes the first write data instruction according to the decoding table to obtain a first relative write address and a first data to be written, and determines that the Buffer to be accessed is the Meta Buffer; The first absolute write address acquisition unit generates a first absolute write address according to the first relative write address; The first write control unit is configured to determine at least one physical memory bank of the Meta Buffer to which the first data to be written is to be written according to the first absolute write address and the length of the first data to be written, and generate a depth write address, a write enable signal of at least one physical memory bank of the Meta Buffer, and data written to at least one physical memory bank of the Meta Buffer, and generate a corresponding first write control instruction according to the depth write address, the write enable signal of at least one physical memory bank of the Meta Buffer, and the data written to at least one physical memory bank of the Meta Buffer; The Meta Buffer is configured to store the first data to be written into at least one physical memory bank of the Meta Buffer according to the first write control instruction.

14. The data processing method according to claim 13, wherein, the absolute write address acquisition module further includes a first register, and the first register is configured to record an offset address of the Meta Buffer; The method specifically includes: When the first write data instruction is of an automatic mode instruction type, the instruction decoding module decodes the first write data instruction to obtain a first relative write address, and the first absolute write address acquisition unit adds the first relative write address and the offset address of the Meta Buffer to obtain the first absolute write address; When the first write data instruction is of a non-automatic mode instruction type, the instruction decoding module decodes the first write data instruction to obtain a first relative write address and a first offset address, the first absolute write address acquisition unit adds the first relative write address and the first offset address to obtain the first absolute write address, and updates the offset address of the Meta Buffer according to the first absolute write address and the length of the first data to be written.

15. The data processing method according to claim 12, wherein, the absolute write address acquisition module includes a second absolute write address acquisition unit, the write control module includes a second write control unit, the Buffer module includes a message Buffer, and the message Buffer is a multi-Bank memory including a plurality of physical memory banks; The method specifically includes: The instruction decoding module receives the second write data instruction issued by the instruction pipeline, decodes the second write data instruction according to the decoding table to obtain a second relative write address and second data to be written, and determines that the Buffer to be accessed is the message Buffer; The second absolute write address obtaining unit generates a second absolute write address according to the second relative write address; The second write control unit determines at least one physical storage bank of the message Buffer to which the second data to be written is to be written according to the second absolute write address and the length of the second data to be written, generates a depth write address, a write enable signal of at least one physical storage bank of the message Buffer, and data written to at least one physical storage bank of the message Buffer, and generates a corresponding second write control instruction according to the depth write address, the write enable signal of at least one physical storage bank of the message Buffer, and the data written to at least one physical storage bank of the message Buffer; The message Buffer stores the second data to be written into at least one physical storage bank of the message Buffer according to the second write control instruction.

16. The data processing method according to claim 15, wherein, the absolute write address obtaining module further includes a second register, and the second register records the offset address of the message Buffer; the method specifically includes: when the second write data instruction is of the automatic mode instruction type, the instruction decoding module decodes the second write data instruction to obtain a second relative write address, and the second absolute write address obtaining unit adds the second relative write address and the offset address of the message Buffer to obtain the second absolute write address; when the second write data instruction is of the non-automatic mode instruction type, the instruction decoding module decodes the second write data instruction to obtain a second relative write address and a second offset address, the second absolute write address obtaining unit adds the second relative write address and the second offset address to obtain the second absolute write address, and updates the offset address of the message Buffer according to the second absolute write address and the length of the second data to be written.

17. The data processing method according to claim 12, wherein, the absolute write address obtaining module includes a third absolute write address obtaining unit, the write control module includes a third write control unit, the Buffer module includes a KeyBuffer, and the Key Buffer is a multi-Bank memory including a plurality of physical storage banks, the method specifically includes: the instruction decoding module receives a third write data instruction issued by the instruction pipeline, decodes the third write data instruction according to the decoding table to obtain a third relative write address and third data to be written, and determines that the Buffer to be accessed is the Key Buffer; the third absolute write address obtaining unit generates a third absolute write address according to the third relative write address; The third write control unit determines at least one physical storage bank in the Key Buffer to which the third data to be written is to be written according to the third absolute write address and the length of the third data to be written, and generates a depth write address, a write enable signal, and data to be written to at least one physical storage bank of the Key Buffer, and generates a corresponding third write control instruction according to the depth write address, the write enable signal, and the data to be written to at least one physical storage bank of the Key Buffer; The Key Buffer stores the third data to be written into at least one physical storage bank of the Key Buffer according to the third write control instruction.

18. The data processing method according to claim 17, wherein, the absolute write address acquisition module further includes a third register, and the third register records the offset address of the Key Buffer; the method specifically includes: when the third write data instruction is of the automatic mode instruction type, the instruction decoding module decodes the third write data instruction to obtain a third relative write address, and the third absolute write address acquisition unit adds the third relative write address and the offset address of the Key Buffer to obtain the third absolute write address; when the third write data instruction is of the non-automatic mode instruction type, the instruction decoding module decodes the third write data instruction to obtain a third relative write address and a third offset address, the third absolute write address acquisition unit adds the third relative write address and the third offset address to obtain the third absolute write address, and updates the offset address of the Key Buffer according to the third absolute write address and the length of the third data to be written.

19. A chip, wherein, it includes the programmable output buffer circuit according to any one of claims 1 to 10.

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