A logic chip, a memory chip, a chip stack structure and a memory

Abstract

The present disclosure provides a logic chip, a memory chip, a chip stack structure and a memory, the logic chip has a plurality of channel signal areas, the conductive vias in which are divided into a plurality of repair unit groups, each repair unit group includes 4 repair units, the first repair unit and the second repair unit are symmetrical along a first axis, the third repair unit and the fourth repair unit are symmetrical along the first axis, and the first repair unit and the fourth repair unit are symmetrical along a second axis.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and particularly relates to a logic chip, a storage chip, a chip stacking structure and a memory. BACKGROUND

[0002] With the development of integrated circuit technology, the production process of semiconductor devices has made significant progress. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits, etc. In this context, in order to solve the difficulties encountered by two-dimensional semiconductor devices and pursue lower production costs per unit storage unit, multiple chips can be stacked to form a three-dimensional semiconductor device by using a bonding process (for example: hybrid bonding, bumping, wire bonding). However, for three-dimensional semiconductor devices, the connection structure between different chips still has problems such as large parasitic capacitance and large parasitic resistance, which affect the quality of signal transmission. SUMMARY

[0003] The embodiments of the present disclosure provide a logic chip, a storage chip, a chip stacking structure and a memory.

[0004] In a first aspect, the embodiments of the present disclosure provide a logic chip, the logic chip comprising m channel signal regions arranged in a first direction in sequence, the logic chip having a chip axis extending in a second direction and passing through the center of the logic chip, the m channel signal regions being symmetrical about the chip axis; m is a positive integer; each of the channel signal regions has a first axis and a second axis, the first axis extending in the first direction or the second direction, the second axis being perpendicular to the first axis and intersecting at the center of the channel signal region; each of the channel signal regions is penetrated by a plurality of conductive vias in a third direction, the first direction, the second direction and the third direction being perpendicular to each other, the first direction and the second direction being parallel to the top surface of the logic chip, the third direction being perpendicular to the top surface of the logic chip; for each of the channel signal regions, the plurality of conductive vias therein are divided into a plurality of repair unit groups; each of the repair unit groups comprises a first repair unit, a second repair unit, a third repair unit and a fourth repair unit; the first repair unit and the second repair unit are symmetrical along the first axis of the channel signal region, the third repair unit and the fourth repair unit are symmetrical along the first axis of the channel signal region, and the first repair unit and the fourth repair unit are symmetrical along the second axis of the channel signal region; each of the repair units comprises at least one redundant conductive via and at least one normal conductive via, when any of the normal conductive vias is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit in a preset signal switching direction; any of the conductive vias in any of the repair units is electrically connected to the internal circuit of the logic chip when used to transmit an effective signal; the normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit correspond to each other and are symmetrical along the first axis of the channel signal region, the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit correspond to each other and are symmetrical along the first axis of the channel signal region, and the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit correspond to each other and are symmetrical along the second axis of the channel signal region.

[0005] In some embodiments, for each of the repair unit groups, the preset switching direction of the conductive via in the first repair unit and the preset switching direction of the conductive via in the second repair unit are symmetrical along a first axis of the channel signal region; the preset switching direction of the conductive via in the third repair unit and the preset switching direction of the conductive via in the fourth repair unit are symmetrical along the first axis of the channel signal region; the preset switching direction of the conductive via in the first repair unit and the preset switching direction of the conductive via in the fourth repair unit are symmetrical along a second axis of the channel signal region; the preset switching direction of the conductive via in the second repair unit and the preset switching direction of the conductive via in the third repair unit are symmetrical along the second axis of the channel signal region.

[0006] In some embodiments, each of the channel signal regions is divided into 2x2 signal areas, the conductive vias in each of the signal areas are divided into n groups of conductive vias with the same distribution, n being a positive integer; in the same channel signal region, the groups of conductive vias in the first signal area and the groups of conductive vias in the second signal area correspond to each other and are symmetrical along a first axis of the channel signal region, the groups of conductive vias in the third signal area and the groups of conductive vias in the fourth signal area correspond to each other and are symmetrical along the first axis of the channel signal region, and the groups of conductive vias in the first signal area and the groups of conductive vias in the fourth signal area correspond to each other and are symmetrical along a second axis of the channel signal region; each of the groups of conductive vias includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via; in the same channel signal region, the first conductive via in one of the groups of conductive vias in the first signal area, the second conductive via in the corresponding group of conductive vias in the second signal area, the third conductive via in the corresponding group of conductive vias in the third signal area, and the fourth conductive via in the corresponding group of conductive vias in the fourth signal area are symmetrical along the first axis and symmetrical along the second axis; in the same channel signal region, the second conductive via in one of the groups of conductive vias in the first signal area, the first conductive via in the corresponding group of conductive vias in the second signal area, the fourth conductive via in the corresponding group of conductive vias in the third signal area, and the third conductive via in the corresponding group of conductive vias in the fourth signal area are symmetrical along the first axis and symmetrical along the second axis; in the same channel signal region, the third conductive via in one of the groups of conductive vias in the first signal area, the fourth conductive via in the corresponding group of conductive vias in the second signal area, the first conductive via in the corresponding group of conductive vias in the third signal area, and the second conductive via in the corresponding group of conductive vias in the fourth signal area are symmetrical along the first axis and symmetrical along the second axis; and in the same channel signal region, the fourth conductive via in one of the groups of conductive vias in the first signal area, the third conductive via in the corresponding group of conductive vias in the second signal area, the second conductive via in the corresponding group of conductive vias in the third signal area, and the first conductive via in the corresponding group of conductive vias in the fourth signal area are symmetrical along the first axis and symmetrical along the second axis.

[0007] In some embodiments, the B conductive via groups in each of the signal regions are referred to as a conductive via combination, and the conductive via groups b in the corresponding conductive via combinations in all the signal regions are collectively symmetrical along the first axis and symmetrical along the second axis, B is a positive integer less than or equal to n, and b is a natural number less than B; the corresponding conductive via combination in each of the signal regions in the same channel signal region collectively forms four groups of repair units: for the first group of repair units, the first repair unit thereof includes the first conductive via of each of the conductive via groups in the conductive via combination in the first signal region; the second repair unit thereof includes the second conductive via of each of the conductive via groups in the conductive via combination in the second signal region; the third repair unit thereof includes the third conductive via of each of the conductive via groups in the conductive via combination in the third signal region; and the fourth repair unit thereof includes the fourth conductive via of each of the conductive via groups in the conductive via combination in the fourth signal region; for the second group of repair units, the first repair unit thereof includes the first conductive via of each of the conductive via groups in the conductive via combination in the second signal region; the second repair unit thereof includes the second conductive via of each of the conductive via groups in the conductive via combination in the first signal region; the third repair unit thereof includes the third conductive via of each of the conductive via groups in the conductive via combination in the fourth signal region; and the fourth repair unit thereof includes the fourth conductive via of each of the conductive via groups in the conductive via combination in the third signal region; for the third group of repair units, the first repair unit thereof includes the first conductive via of each of the conductive via groups in the conductive via combination in the third signal region; the second repair unit thereof includes the second conductive via of each of the conductive via groups in the conductive via combination in the fourth signal region; the third repair unit thereof includes the third conductive via of each of the conductive via groups in the conductive via combination in the first signal region; and the fourth repair unit thereof includes the fourth conductive via of each of the conductive via groups in the conductive via combination in the second signal region; and for the fourth group of repair units, the first repair unit thereof includes the first conductive via of each of the conductive via groups in the conductive via combination in the fourth signal region; the second repair unit thereof includes the second conductive via of each of the conductive via groups in the conductive via combination in the third signal region; the third repair unit thereof includes the third conductive via of each of the conductive via groups in the conductive via combination in the second signal region; and the fourth repair unit thereof includes the fourth conductive via of each of the conductive via groups in the conductive via combination in the first signal region.The fourth repair unit includes all fourth conductive vias in the conductive via combination in the first signal area.

[0008] In some embodiments, when B=3, b is 0, 1 or 2; all conductive vias in conductive via group 0 are normal conductive vias; the preset switching direction of conductive vias in the Xth repair unit is that the Xth conductive via in conductive via group 0 is allowed to switch to the Xth conductive via in conductive via group 1 in the same signal area, the Xth conductive via in conductive via group 1 is allowed to switch to the Xth conductive via in conductive via group 2 in the same signal area; X is one, two, three or four.

[0009] In some embodiments, when B=6, b is 0, 1, 2, 3, 4 or 5; all conductive vias in conductive via group 2 are normal conductive vias; the preset switching direction of conductive vias in the Xth repair unit is that the Xth conductive via in conductive via group 2 is allowed to switch to the Xth conductive via in conductive via group 3 in the same signal area, the Xth conductive via in conductive via group 3 is allowed to switch to the Xth conductive via in conductive via group 4 in the same signal area, the Xth conductive via in conductive via group 4 is allowed to switch to the Xth conductive via in conductive via group 1 in the same signal area; the Xth conductive via in conductive via group 1 is allowed to switch to the Xth conductive via in conductive via group 0 in the same signal area; the Xth conductive via in conductive via group 0 is allowed to switch to the Xth conductive via in conductive via group 5 in the same signal area.

[0010] In some embodiments, in each signal area, the conductive via group 0, the conductive via group 1 and the conductive via group 2 are aligned in a first direction; the conductive via group 3, the conductive via group 4 and the conductive via group 5 are aligned in the first direction; the conductive via group 0 and the conductive via group 5 are aligned in a second direction, the conductive via group 1 and the conductive via group 4 are aligned in the second direction, and the conductive via group 2 and the conductive via group 3 are aligned in the second direction.

[0011] In some embodiments, the conductive vias are prepared by any one of via-first, via-middle, via-last, back side via-last process or a plurality of processes; different conductive vias in the same logic chip are electrically isolated.

[0012] In a second aspect, the embodiments of the present disclosure provide a memory chip, which comprises m channels, the m channels are arranged in sequence along a first direction, the memory chip has a chip axis extending along a second direction and passing through the center of the memory chip, and the m channels are symmetrical about the chip axis; each of the channels comprises a first memory array region, a channel signal region and a second memory array region arranged in sequence along the second direction, and the center of each of the channel signal regions coincides with the center of the channel; m is a positive integer; each of the channel signal regions has a first axis and a second axis, the first axis extends along the first direction or the second direction, the second axis is perpendicular to the first axis and intersects at the center of the channel signal region; each of the channel signal regions is penetrated by a plurality of conductive vias along a third direction, the first direction, the second direction and the third direction are perpendicular to each other, the first direction and the second direction are parallel to the top surface of the memory chip, and the third direction is perpendicular to the top surface of the memory chip; for each of the channel signal regions, the plurality of conductive vias are divided into a plurality of repair unit groups; each of the repair unit groups comprises a first repair unit, a second repair unit, a third repair unit and a fourth repair unit; the first repair unit and the second repair unit are symmetrical along the first axis of the channel signal region, the third repair unit and the fourth repair unit are symmetrical along the first axis of the channel signal region, and the first repair unit and the fourth repair unit are symmetrical along the second axis of the channel signal region; each of the repair units comprises at least one redundant conductive via and at least one normal conductive via, when any of the normal conductive vias is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset signal switching direction; any of the conductive vias in the first repair unit is electrically connected to the internal circuit of the memory chip when used to transmit an effective signal; the normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit correspond to each other and are symmetrical along the first axis of the channel signal region, the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit correspond to each other and are symmetrical along the first axis of the channel signal region, and the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit correspond to each other and are symmetrical along the second axis of the channel signal region.

[0013] In some embodiments, for each of the repair unit groups, the preset switching direction of the conductive via in the first repair unit and the preset switching direction of the conductive via in the second repair unit are symmetrical along a first axis of the channel signal region; the preset switching direction of the conductive via in the third repair unit and the preset switching direction of the conductive via in the fourth repair unit are symmetrical along the first axis of the channel signal region; the preset switching direction of the conductive via in the first repair unit and the preset switching direction of the conductive via in the fourth repair unit are symmetrical along a second axis of the channel signal region; the preset switching direction of the conductive via in the second repair unit and the preset switching direction of the conductive via in the third repair unit are symmetrical along the second axis of the channel signal region.

[0014] In some embodiments, each of the channel signal regions is divided into 2x2 signal regions, the conductive vias in each of the signal regions are divided into n groups of conductive vias with the same distribution, n being a positive integer; in the same channel signal region, the groups of conductive vias in the first signal region and the groups of conductive vias in the second signal region correspond to each other and are symmetrical along a first axis, the groups of conductive vias in the third signal region and the groups of conductive vias in the fourth signal region correspond to each other and are symmetrical along the first axis, the groups of conductive vias in the first signal region and the groups of conductive vias in the fourth signal region correspond to each other and are symmetrical along a second axis; each of the groups of conductive vias includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via; for the same channel signal region, the first conductive via in one group of conductive vias in the first signal region, the second conductive via in the corresponding group of conductive vias in the second signal region, the third conductive via in the corresponding group of conductive vias in the third signal region, and the fourth conductive via in the corresponding group of conductive vias in the fourth signal region are symmetrical along the first axis and symmetrical along the second axis; in the same channel signal region, the second conductive via in one group of conductive vias in the first signal region, the first conductive via in the corresponding group of conductive vias in the second signal region, the fourth conductive via in the corresponding group of conductive vias in the third signal region, and the third conductive via in the corresponding group of conductive vias in the fourth signal region are symmetrical along the first axis and symmetrical along the second axis; in the same channel signal region, the third conductive via in one group of conductive vias in the first signal region, the fourth conductive via in the corresponding group of conductive vias in the second signal region, the first conductive via in the corresponding group of conductive vias in the third signal region, and the second conductive via in the corresponding group of conductive vias in the fourth signal region are symmetrical along the first axis and symmetrical along the second axis; in the same channel signal region, the fourth conductive via in one group of conductive vias in the first signal region, the third conductive via in the corresponding group of conductive vias in the second signal region, the second conductive via in the corresponding group of conductive vias in the third signal region, and the first conductive via in the corresponding group of conductive vias in the fourth signal region are symmetrical along the first axis and symmetrical along the second axis.

[0015] In some embodiments, the B conductive via groups in each of the signal regions are referred to as a conductive via combination, and the conductive via groups b in the corresponding conductive via combinations in all the signal regions are collectively symmetrical along the first axis and symmetrical along the second axis, B is a positive integer less than or equal to n, and b is a natural number less than B; the corresponding conductive via combination in each of the signal regions in the same channel signal region collectively forms four groups of repair units: for the first group of repair units, the first repair unit thereof includes the first conductive via of each of the conductive via groups in the conductive via combination in the first signal region; the second repair unit thereof includes the second conductive via of each of the conductive via groups in the conductive via combination in the second signal region; the third repair unit thereof includes the third conductive via of each of the conductive via groups in the conductive via combination in the third signal region; and the fourth repair unit thereof includes the fourth conductive via of each of the conductive via groups in the conductive via combination in the fourth signal region; for the second group of repair units, the first repair unit thereof includes the first conductive via of each of the conductive via groups in the conductive via combination in the second signal region; the second repair unit thereof includes the second conductive via of each of the conductive via groups in the conductive via combination in the first signal region; the third repair unit thereof includes the third conductive via of each of the conductive via groups in the conductive via combination in the fourth signal region; and the fourth repair unit thereof includes the fourth conductive via of each of the conductive via groups in the conductive via combination in the third signal region; for the third group of repair units, the first repair unit thereof includes the first conductive via of each of the conductive via groups in the conductive via combination in the third signal region; the second repair unit thereof includes the second conductive via of each of the conductive via groups in the conductive via combination in the fourth signal region; the third repair unit thereof includes the third conductive via of each of the conductive via groups in the conductive via combination in the first signal region; and the fourth repair unit thereof includes the fourth conductive via of each of the conductive via groups in the conductive via combination in the second signal region; and for the fourth group of repair units, the first repair unit thereof includes the first conductive via of each of the conductive via groups in the conductive via combination in the fourth signal region; the second repair unit thereof includes the second conductive via of each of the conductive via groups in the conductive via combination in the third signal region; the third repair unit thereof includes the third conductive via of each of the conductive via groups in the conductive via combination in the second signal region; and the fourth repair unit thereof includes the fourth conductive via of each of the conductive via groups in the conductive via combination in the first signal region.The fourth repair unit includes all fourth conductive vias in the conductive via combination in the first signal area.

[0016] In some embodiments, when B=3, b is 0, 1 or 2; all conductive vias in the conductive via group 0 are normal conductive vias; and the preset switching direction of the conductive vias in the first repair unit is that the first conductive via in the conductive via group 0 is allowed to switch to the first conductive via in the conductive via group 1 in the same signal area, and the first conductive via in the conductive via group 1 is allowed to switch to the first conductive via in the conductive via group 2 in the same signal area.

[0017] In some embodiments, when B=6, b is 0, 1, 2, 3, 4 or 5; all conductive vias in the conductive via group 0 in all signal areas are normal conductive vias; the preset switching direction of the conductive vias in the first repair unit is that the first conductive via in the conductive via group 2 is allowed to switch to the first conductive via in the conductive via group 3 in the same signal area, the first conductive via in the conductive via group 3 is allowed to switch to the first conductive via in the conductive via group 4 in the same signal area, the first conductive via in the conductive via group 4 is allowed to switch to the first conductive via in the conductive via group 1 in the same signal area; the first conductive via in the conductive via group 1 is allowed to switch to the first conductive via in the conductive via group 0 in the same signal area; and the first conductive via in the conductive via group 0 is allowed to switch to the first conductive via in the conductive via group 5 in the same signal area.

[0018] In a third aspect, the embodiments of the present disclosure provide a chip stacking structure, which comprises the logic chip in the first aspect and at least one stacking unit, and the logic chip and the at least one stacking unit are stacked in sequence along a third direction; each stacking unit comprises a first memory chip, a second memory chip, a third memory chip and a fourth memory chip stacked in sequence along the third direction, and the third direction is perpendicular to the top surface of each chip; the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are the memory chips in the second aspect; the first memory chip and the second memory chip are stacked in a face-to-face manner, the second memory chip and the third memory chip are stacked in a back-to-back manner, and the third memory chip and the fourth memory chip are stacked in a face-to-face manner; the logic chip and the first memory chip are stacked in a back-to-back manner; or, the logic chip and the first memory chip are stacked in a face-to-back manner.

[0019] In some embodiments, the logic chip comprises m channel signal regions arranged along a first direction, each of the memory chips has m channels arranged along the first direction, and each of the channels comprises a first memory array region, a channel signal region and a second memory array region sequentially distributed along a second direction; the first direction, the second direction and the third direction are perpendicular to each other, the first direction and the second direction are parallel to a top surface of each chip; in a case where the logic chip and the first memory chip are stacked in a back-to-back manner, and the first axis of the logic chip and each of the memory chips respectively extends along the first direction, an m-i th channel signal region in the logic chip is aligned with the channel signal region in an i+1 th channel in the first memory chip, the channel signal region in an i+1 th channel in the second memory chip, the channel signal region in an m-i th channel in the third memory chip and the channel signal region in an m-i th channel in the fourth memory chip along a third direction; wherein i is a natural number less than m.

[0020] In some embodiments, the logic chip comprises m channel signal regions arranged along a first direction, each of the memory chips has m channels arranged along the first direction, and each of the channels comprises a first memory array region, a channel signal region and a second memory array region sequentially distributed along a second direction; in a case where the logic chip and the first memory chip are stacked in a back-to-back manner, and the second axis of the logic chip and each of the memory chips respectively extends along the first direction, an i+1 th channel signal region in the logic chip is aligned with the channel signal region in an i+1 th channel in the first memory chip, the channel signal region in an m-i th channel in the second memory chip, the channel signal region in an m-i th channel in the third memory chip and the channel signal region in an i+1 th channel in the fourth memory chip along a third direction; wherein i is a natural number less than m.

[0021] In some embodiments, each of the channel signal regions in each of the channels is divided into 2x2 signal regions arranged in an array; only for the channel signal regions aligned along the third direction: a fourth signal region belonging to the logic chip, a first signal region belonging to the first memory chip, a second signal region belonging to the second memory chip, a third signal region belonging to the third memory chip, and a fourth signal region belonging to the fourth memory chip are aligned along the third direction; the third signal region belonging to the logic chip, the second signal region belonging to the first memory chip, the first signal region belonging to the second memory chip, the fourth signal region belonging to the third memory chip, and the third signal region belonging to the fourth memory chip are aligned along the third direction; the second signal region belonging to the logic chip, the third signal region belonging to the first memory chip, the fourth signal region belonging to the second memory chip, the first signal region belonging to the third memory chip, and the second signal region belonging to the fourth memory chip are aligned along the third direction; and the first signal region belonging to the logic chip, the fourth signal region belonging to the first memory chip, the third signal region belonging to the second memory chip, the second signal region belonging to the third memory chip, and the first signal region belonging to the fourth memory chip are aligned along the third direction.

[0022] In some embodiments, each of the signal regions comprises n groups of conductive vias with same distribution position, each of the groups of conductive vias comprises a first conductive via, a second conductive via, a third conductive via and a fourth conductive via; only for the multiple signal regions aligned along the third direction: the fourth conductive vias belonging to the logic chip, the first conductive vias belonging to the first memory chip, the second conductive vias belonging to the second memory chip, the third conductive vias belonging to the third memory chip, the fourth conductive vias belonging to the fourth memory chip are aligned along the third direction; the third conductive vias belonging to the logic chip, the second conductive vias belonging to the first memory chip, the first conductive vias belonging to the second memory chip, the fourth conductive vias belonging to the third memory chip, the third conductive vias belonging to the fourth memory chip are aligned along the third direction; the second conductive vias belonging to the logic chip, the third conductive vias belonging to the first memory chip, the fourth conductive vias belonging to the second memory chip, the first conductive vias belonging to the third memory chip, the second conductive vias belonging to the fourth memory chip are aligned along the third direction; the first conductive vias belonging to the logic chip, the fourth conductive vias belonging to the first memory chip, the third conductive vias belonging to the second memory chip, the second conductive vias belonging to the third memory chip, the first conductive vias belonging to the fourth memory chip are aligned along the third direction; wherein the multiple conductive vias aligned along the third direction are coupled to form a signal transmission channel.

[0023] In some embodiments, one of the fourth repair units in the logic chip, one of the first repair units in the first memory chip, one of the second repair units in the second memory chip, one of the third repair units in the third memory chip, and one of the fourth repair units in the fourth memory chip are aligned along a third direction and synchronously perform a conductive via switching operation; one of the third repair units in the logic chip, one of the second repair units in the first memory chip, one of the first repair units in the second memory chip, one of the fourth repair units in the third memory chip, and one of the third repair units in the fourth memory chip are aligned along the third direction and synchronously perform the conductive via switching operation; one of the second repair units in the logic chip, one of the third repair units in the first memory chip, one of the fourth repair units in the second memory chip, one of the first repair units in the third memory chip, and one of the second repair units in the fourth memory chip are aligned along the third direction and synchronously perform the conductive via switching operation; and one of the first repair units in the logic chip, one of the fourth repair units in the first memory chip, one of the third repair units in the second memory chip, one of the second repair units in the third memory chip, and one of the first repair units in the fourth memory chip are aligned along the third direction and synchronously perform the conductive via switching operation.

[0024] In some embodiments, the logic chip comprises m channel signal regions arranged along a first direction, each of the memory chips has m channels arranged along the first direction, and each of the channels comprises a first memory array region, a channel signal region, and a second memory array region sequentially arranged along a second direction; in the case that the logic chip and the first memory chip are stacked in a back-to-back manner, and the first axis of the logic chip and each of the memory chips respectively extends along the first direction, an i+1th channel signal region in the logic chip is aligned with the channel signal region in an i+1th channel in the first memory chip, the channel signal region in an i+1th channel in the second memory chip, the channel signal region in an m-i channel in the third memory chip, and the channel signal region in an m-i channel in the fourth memory chip along a third direction; wherein i is a natural number less than m.

[0025] In some embodiments, the logic chip comprises m channel signal regions arranged along a first direction, each of the memory chips has m channels arranged along the first direction, and each of the channels comprises a first memory array region, a channel signal region and a second memory array region sequentially arranged along a second direction; in the case that the logic chip and the first memory chip are stacked in a back-to-back manner, and the second axis of the logic chip and each of the memory chips respectively extends along the first direction, the m-i th channel signal region in the logic chip is aligned with the channel signal region in the i+1 th channel in the first memory chip, the channel signal region in the m-i th channel in the second memory chip, the channel signal region in the m-i th channel in the third memory chip and the channel signal region in the i+1 th channel in the fourth memory chip along a third direction; wherein i is a natural number less than m.

[0026] In some embodiments, the channel signal region in each of the channels is divided into 2x2 signal regions arranged in an array; only for the plurality of channel signal regions aligned along the third direction: the second signal region belonging to the logic chip, the first signal region belonging to the first memory chip, the second signal region belonging to the second memory chip, the third signal region belonging to the third memory chip, and the fourth signal region belonging to the fourth memory chip are aligned along the third direction; the first signal region belonging to the logic chip, the second signal region belonging to the first memory chip, the first signal region belonging to the second memory chip, the fourth signal region belonging to the third memory chip, and the third signal region belonging to the fourth memory chip are aligned along the third direction; the fourth signal region belonging to the logic chip, the third signal region belonging to the first memory chip, the fourth signal region belonging to the second memory chip, the first signal region belonging to the third memory chip, and the second signal region belonging to the fourth memory chip are aligned along the third direction; the third signal region belonging to the logic chip, the fourth signal region belonging to the first memory chip, the third signal region belonging to the second memory chip, the second signal region belonging to the third memory chip, and the first signal region belonging to the fourth memory chip are aligned along the third direction.

[0027] In some embodiments, each of the signal regions comprises n groups of conductive vias with same distribution, each of the groups of conductive vias comprises a first conductive via, a second conductive via, a third conductive via and a fourth conductive via; for a plurality of the signal regions aligned along the third direction: the second conductive vias belonging to the logic chip, the first conductive vias belonging to the first memory chip, the second conductive vias belonging to the second memory chip, the third conductive vias belonging to the third memory chip, the fourth conductive vias belonging to the fourth memory chip are aligned along the third direction; the first conductive vias belonging to the logic chip, the second conductive vias belonging to the first memory chip, the first conductive vias belonging to the second memory chip, the fourth conductive vias belonging to the third memory chip, the third conductive vias belonging to the fourth memory chip are aligned along the third direction; the fourth conductive vias belonging to the logic chip, the third conductive vias belonging to the first memory chip, the fourth conductive vias belonging to the second memory chip, the first conductive vias belonging to the third memory chip, the second conductive vias belonging to the fourth memory chip are aligned along the third direction; the third conductive vias belonging to the logic chip, the fourth conductive vias belonging to the first memory chip, the third conductive vias belonging to the second memory chip, the second conductive vias belonging to the third memory chip, the first conductive vias belonging to the fourth memory chip are aligned along the third direction; wherein the plurality of conductive vias aligned along the third direction are coupled to form a signal transmission channel.

[0028] In some embodiments, one of the second repair units in the logic chip, one of the first repair units in the first memory chip, one of the second repair units in the second memory chip, one of the third repair units in the third memory chip, and one of the fourth repair units in the fourth memory chip are aligned in the third direction and perform a conductive via switching operation synchronously; one of the first repair units in the logic chip, one of the second repair units in the first memory chip, one of the first repair units in the second memory chip, one of the fourth repair units in the third memory chip, and one of the third repair units in the fourth memory chip are aligned in the third direction and perform a conductive via switching operation synchronously; one of the fourth repair units in the logic chip, one of the third repair units in the first memory chip, one of the fourth repair units in the second memory chip, one of the first repair units in the third memory chip, and one of the second repair units in the fourth memory chip are aligned in the third direction and perform a conductive via switching operation synchronously; and one of the third repair units in the logic chip, one of the fourth repair units in the first memory chip, one of the third repair units in the second memory chip, one of the second repair units in the third memory chip, and one of the first repair units in the fourth memory chip are aligned in the third direction and perform a conductive via switching operation synchronously.

[0029] In some embodiments, for two chips connected face-to-face, the positions where the conductive vias in the two chips are aligned in the third direction are electrically connected by a hybrid bonding process; for two chips connected back-to-back or for two chips connected back-to-face, the positions where the conductive vias in the two chips are aligned in the third direction are electrically connected by a conductive bump bonding process; or, for two chips connected face-to-face or for two chips connected back-to-back or for two chips connected back-to-face, the positions where the conductive vias in the two chips are aligned in the third direction are electrically connected by a hybrid bonding process; or, for two chips connected face-to-face or for two chips connected back-to-back or for two chips connected back-to-face, the positions where the conductive vias in the two chips are aligned in the third direction are electrically connected by a conductive bump bonding process.

[0030] In a fourth aspect, the embodiments of the present disclosure provide a memory, including the chip stack structure according to any one of the third aspect.

[0031] The embodiment of the present disclosure provides a logic chip, a storage chip, a chip stacking structure and a memory, a plurality of channel signal regions exist in each chip, a conductive via is symmetrically arranged in each channel signal region, so that the chip stacking structure formed by the storage chip realizes signal rotation transmission effect through the direct connection configuration of the conductive via, and the parasitic resistance and the parasitic capacitance are relatively small; meanwhile, a repair unit is also symmetrically divided in each channel signal region, so that the redundancy repair function of the above chip stacking structure can be realized, and the stability of the storage chip is improved. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 It is a structural schematic diagram of a chip;

[0033] Figure 2A It is a structural schematic diagram of a chip stacking structure Figure 1 ;

[0034] Figure 2B It is a structural schematic diagram of a chip stacking structure Figure 1 ;

[0035] Figure 3 It is a schematic diagram of a logic chip provided by the embodiment of the present disclosure;

[0036] Figure 4A / Figure 4B It is a schematic diagram of a logic chip provided by the embodiment of the present disclosure;

[0037] Figures 5-6D It is a schematic diagram of a repair unit in a logic chip provided by the embodiment of the present disclosure;

[0038] Figures 7-8D It is a schematic diagram of a repair unit in another logic chip provided by the embodiment of the present disclosure;

[0039] Figure 9 It is a schematic diagram of a storage chip provided by the embodiment of the present disclosure;

[0040] Figure 10A / Figure 10B It is a schematic diagram of a storage chip provided by the embodiment of the present disclosure;

[0041] Figures 11-12D It is a schematic diagram of a repair unit in a storage chip provided by the embodiment of the present disclosure;

[0042] Figures 13-14D It is a schematic diagram of a repair unit in another storage chip provided by the embodiment of the present disclosure;

[0043] Figure 15 It is a structural schematic diagram of a chip stacking structure provided by the embodiment of the present disclosure;

[0044] Figure 16A Figure 16B A position diagram of a repair unit in a chip stacking structure provided by an embodiment of the present disclosure is shown in FIG. 2A.

[0045] Figure 17A Figure 17B Figure 17C A specific diagram of a first chip stacking structure provided by an embodiment of the present disclosure is shown in FIG. 3A.

[0046] Figure 18A Figure 18B A specific diagram of a second chip stacking structure provided by an embodiment of the present disclosure is shown in FIG. 4A.

[0047] Figure 19A Figure 19B A specific diagram of a third chip stacking structure provided by an embodiment of the present disclosure is shown in FIG. 5A.

[0048] Figure 20A Figure 20B A specific diagram of a fourth chip stacking structure provided by an embodiment of the present disclosure is shown in FIG. 6A.

[0049] Figure 21 A signal transmission diagram of a chip stacking structure provided by an embodiment of the present disclosure is shown in FIG. 7A.

[0050] Figure 22A A repair process diagram of a chip stacking structure provided by an embodiment of the present disclosure is shown in FIG. 22B.

[0051] Figure 23 A signal transmission diagram of another chip stacking structure provided by an embodiment of the present disclosure is shown in FIG. 23A.

[0052] Figure 24A A repair process diagram of another chip stacking structure provided by an embodiment of the present disclosure is shown in FIG. 24B.

[0053] Figure 25 A component structure diagram of a memory provided by an embodiment of the present disclosure is shown in FIG. 25A. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only for the purpose of explaining the related application, and are not intended to limit the present disclosure. In addition, it should be noted that only the parts related to the application are shown in the drawings for the purpose of description.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. The terminology used in the description herein is for describing the embodiments of the present disclosure only and is not intended to limit the present disclosure.​​​​​​

[0056] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or a different subset of all possible embodiments, and can be combined with each other as long as there is no conflict.

[0057] It should be noted that the terms "first", "second", "third" involved in the embodiments of the present disclosure are only to distinguish similar objects, and do not represent a specific order of the objects. Understandably, "first", "second", "third" can be interchanged in a specific order or sequence as long as it is allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0058] Before introducing the embodiments of the present disclosure, the three directions for describing the three-dimensional structure that the plane may use are defined. Taking the Cartesian coordinate system as an example, the three directions can include a first direction, a second direction, and a third direction.

[0059] Please refer to Figure 1 , the semiconductor chip (which can be a memory chip or a logic chip) can include a top surface on the front surface and a bottom surface on the back surface opposite the front surface; in the case of ignoring the flatness of the top surface and the bottom surface, the direction intersecting (e.g. perpendicular) with the top surface and the bottom surface of the semiconductor chip is defined as the third direction. On the top surface of the semiconductor chip, two directions perpendicular to each other are defined, i.e. the first direction and the second direction, and the first direction is perpendicular to one edge of the semiconductor chip, and the second direction is perpendicular to the other edge of the semiconductor chip.

[0060] Please refer to Figure 1 , the semiconductor chip includes a substrate, one surface of the substrate forms an active surface for making devices (such as transistors, capacitors, etc.), and a plurality of metal layers (such as M1, M2, M3, …) are distributed between the substrate and the top surface. Figure 1 Two types of conductive vias (e.g. through-silicon vias TSV) are also shown in

[0061] As shown in Figure 1 , for the conductive via of type 1, it penetrates the bottom surface and the top surface along the third direction, and the conductive via is connected to the internal circuit of the chip through the metal layer.

[0062] As shown in Figure 1 , for the conductive via of type 2, it only penetrates the substrate along the third direction, and needs to cooperate with a contact structure penetrating the top surface along the third direction to achieve signal transmission together; the contact structure and the conductive via are not directly electrically connected, but are indirectly electrically connected through the metal layer. For example: Figure 1The contact structures in the memory chip are connected to M4, M4 is connected to M1 via M3 and M2 in turn, and M1 is connected to the conductive via. Of course, the contact structures and the conductive via can also be designed to be directly electrically connected in other embodiments.

[0063] Meanwhile, the types of the conductive via are not limited to the above two, which are only examples. In particular, the drawings presented in the present disclosure are not meant to be actual views of any particular microelectronic device or component thereof, but are merely idealized representations used for describing the illustrative embodiments. Therefore, the drawings are not necessarily to scale.

[0064] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0065] In an embodiment, a memory chip and a logic chip are provided, and each of the memory chip and the logic chip includes a plurality of conductive vias penetrating through the chip along a third direction, the conductive vias are used to realize signal transmission between different chips, and all the conductive vias can be located at any position. In particular, every four conductive vias can be regarded as a conductive via group in function, but the positions of the four conductive vias are not limited.

[0066] In a specific embodiment, eight memory chips and one logic chip described above are stacked to form a 3D memory device, meanwhile, the conductive vias of the eight memory chips are aligned along the third direction, and the nine conductive vias in the aligned state along the third direction are connected to form an electrical path. Please refer to Figure 2A which shows a signal transmission schematic diagram of a chip stack structure. As Figure 2A shown, the chip stack structure includes memory chips 0-7 and a logic chip, Figure 2A Only four conductive vias D0-D3 are shown for each memory chip, and the four conductive vias D0-D3 belong to the same conductive via group, at this time, the conductive vias D0 in the eight memory chips and the logic chip are aligned to form an electrical path, the conductive vias D1 in the eight memory chips and the logic chip are aligned to form an electrical path, and so on. The remaining conductive vias are similar.

[0067] Meanwhile, each memory chip and the logic chip are also provided with a plurality of driving circuits Figure 2A only one of which is shown in a dashed box in the figure, and the remaining driving circuits are not boxed), and each conductive via is connected to a driving circuit; each memory chip is also provided with a plurality of data selectors (for example Figure 2AIn the above embodiment, each of the conductive vias is connected to a driving circuit and a data selector. In other words, the data selector can select which signal transmitted by the conductive via is output to the internal of the memory chip or which signal output by the memory chip is output to the conductive via.

[0068] For the whole memory device, different regions in different memory chips will be divided into different channels (for example, CH0, CH1, CH4, CH5) for management. The signal Signal_CH0 of the channel CH0 is transmitted through an electrical path composed of "the conductive via D0 in the logic chip, the conductive via D0 in the memory chip 0, the conductive via D0 in the memory chip 1, the conductive via D0 in the memory chip 2, the conductive via D0 in the memory chip 3, the conductive via D0 in the memory chip 4, the conductive via D0 in the memory chip 5, the conductive via D0 in the memory chip 6, and the conductive via D0 in the memory chip 7". The selection signals of the data selector mux0 in the memory chip 0 and the data selector mux4 in the memory chip 4 are both SEL_C0, that is, the signal Signal_CH0 can enter the memory chip 0 and the memory chip 4 through the above-mentioned electrical path. The output process of the signal can be understood similarly.

[0069] As can be seen from the above, the memory chip 0 only needs to obtain signals from the conductive via D0, the memory chip 1 only needs to obtain signals from the conductive via D1, and so on. That is, each memory chip only needs to obtain signals from one conductive via in one conductive via group. It is worth noting that different memory chips may need to obtain signals from different conductive vias. However, since all memory chips need to be designed to have the same structure during the process of manufacturing (so as to maximize the cost and manpower), all conductive vias in the memory chips need to be designed with corresponding driving structures and data selectors in order to achieve structural consistency. Further, when the chip stacking structure shown in Figure 2A is used, each conductive via corresponds to a driving circuit; during the working process of the chip stacking structure, all driving circuits in all memory chips in the same channel need to be driven, which has a large load and a large parasitic capacitance, seriously affecting the performance of the chips, restricting the transmission efficiency and increasing the power consumption, and also restricting the number of chip stacking in the three-dimensional device.

[0070] In another embodiment, please refer to Figure 2B which shows the signal transmission of another chip stacking structure. In particular, Figure 2B only part of the conductive vias are identified (D0-D3), and the others are omitted, but for Figure 4AFor example, the markings for conductive vias aligned along a third direction are the same. Figure 2B As shown, the chip stack structure also includes eight memory chips and one logic chip aligned along a third direction. However, the conductive vias in each memory chip are rotatably connected to another conductive via at a different position in another memory chip, achieving a spiral upward connection as a whole. That is, the signal Signal_CH0 of channel CH0 is transmitted through “conductive via D0 in logic chip 0 – conductive via D1 in memory chip 0 – conductive via D2 in memory chip 1 – conductive via D3 in memory chip 2 – conductive via D0 in memory chip 3 – conductive via D1 in memory chip 4 – conductive via D2 in memory chip 5 – conductive via D3 in memory chip 6 – conductive via D0 in memory chip 7”, and the other signals are similar.

[0071] In this way, memory chip 0 can obtain the signal Signal_CH0 through the output terminal of the conductive via D0 in the logic chip, memory chip 1 can obtain the signal Signal_CH1 through the input terminal of the conductive via D0 in memory chip 0, memory chip 2 can obtain the signal Signal_CH4 through the input terminal of the conductive via D0 in memory chip 1, memory chip 3 can obtain the signal Signal_CH5 through the input terminal of the conductive via D0 in memory chip 2, and so on. For each memory chip, only one conductive via is needed to connect to the driving circuit in each group of conductive vias, and no data selector is required, which reduces the number of devices and thus reduces parasitic capacitance. However, compared to Figure 2A The conductive via direct connection configuration. Figure 2B The process of rotary connection of through-holes in medium-voltage systems is more complex, specifically... Figure 2B A horizontal interconnect structure needs to be set between adjacent conductive vias in each memory chip. Figure 2B (Only one is marked with a pentagram in the image). The signal interconnect structure can be a metal interconnect, a conductive via, etc. To achieve the rotating connection of the conductive via, the input signal signal_CH0 must first be transmitted upwards from the conductive via D0 of the logic chip to the interconnect structure below the conductive via D0 of the memory chip 0 (not directly connected to the conductive via D0 of the memory chip 0), and then horizontally transmitted from the interconnect structure below the conductive via D0 of the memory chip 0 to the conductive via D1 of the memory chip 0. That is: Figure 2B The structure shown requires the signal to pass through the interconnect structure in each memory chip during the signal transmission process, and the output signal is similar. This inevitably leads to an increase in parasitic resistance and also increases the complexity of the manufacturing process.

[0072] In particular, Figure 2A and Figure 2BIn the chip stacking structure, all chips are active-facing, meaning that different memory chips are stacked back-to-back, and memory chips and logic chips are also stacked back-to-back, that is, the bottom surface of the upper chip is in contact with the top surface of the lower chip.

[0073] In summary, on the one hand, Figure 2A The chip stacking structure requires numerous conductive vias to transmit the corresponding signals. Combined with the associated driver circuitry and data selectors, this results in a large load and parasitic capacitance. Figure 2B The chip stacking structure has a large parasitic resistance due to its rotational configuration; on the other hand... Figure 2A and Figure 2B All existing stacking structures have certain problems and cannot be directly applied to face-to-face stacking structures. Specifically, if we want to further realize face-to-face chip stacking structures, one approach is to use two sets of masks to create two different chips, one as the active-facing chip and the other as the active-facing chip. This approach has high process complexity and uncontrollable costs. Another approach is to create an additional set of conductive vias and connect both sets of conductive vias to the same driving circuit within the memory chip. However, this leads to complex internal wiring of the memory chip, increasing both process complexity and power consumption.

[0074] In one embodiment of this disclosure, see Figure 3 This shows a schematic diagram of the active surface in logic chip 10. For example... Figure 3 As shown, the logic chip 10 includes m channel signal regions arranged sequentially along a first direction. Figure 3 (Taking m=4 as an example) The logic chip 10 has a chip axis YY' that extends along the second direction and passes through the center of the logic chip 10, and the m channel signal regions are symmetrical about the chip axis YY'.

[0075] like Figure 3 As shown, the center of the active surface of the logic chip 10 and its adjacent area are also defined as the global signal region. At this time, the first channel signal region 11, the second channel signal region 12, the global signal region, the third channel signal region 13, and the fourth channel signal region 14 are distributed sequentially along the first direction, and the upper and lower sides of the channel signal region of the logic chip 10 are used to distribute some logic control circuits of the stacked memory.

[0076] Figure 3For example, m = 4 is taken as an example, and m = 4 is also taken as an example in the following description, but m can be any positive integer. Specifically, if m is even, m / 2 channel signal regions are located on one side of the global signal region along the first direction, and the remaining m / 2 channel signal regions are located on the other side of the global signal region along the first direction; if m is odd, the (m+1) / 2 channel signal region needs to be divided into two parts located on both sides of the global signal region along the first direction, while the other (m-1) / 2 channel signal regions are located on one side of the global signal region along the first direction, and the remaining (m-1) / 2 channel signal regions are located on the other side of the global signal region along the first direction.

[0077] It should be noted that, in the chip manufacturing process, in order to distinguish different channel signal regions of the chip, a positioning structure can be made in the reference channel signal region (for example: the first channel signal region) of the logic chip 10, so that the position of the reference channel can be identified through the positioning structure during subsequent packaging, and other channels can be identified by combining the active surface orientation of the chip.

[0078] It should be noted that the global signal region and the channel signal region are both penetrated by a plurality of conductive vias along the third direction, and the third direction is perpendicular to the active surface, that is, the first direction, the second direction and the third direction are perpendicular to each other. Here, the conductive via can be a through silicon via (TSV), which is a kind of vertical interconnection structure penetrating the silicon wafer / chip, or in other embodiments, it can also be other conductive vias with conductive function, which is not limited specifically. In addition, the conductive via can adopt the form of the aforementioned type 1, or adopt the form of the aforementioned type 2.

[0079] For the global signal region, each conductive via is used to transmit a global signal, and the global signal is shared by all regions of the corresponding memory chip. The global signal includes but is not limited to: reset signal, power-on signal, stack identification signal SID / CID, power-related signal Voltage Monitor, timing-related signal Timing Aligner. In some cases, the global signal region can also refer to the pad region. The global signal can be a test signal for design for test (DFT), and through the global signal, the working condition of the internal circuit of the chip and the transmission condition of the related signal can be known. In addition, because the DFT pin pad (PAD) in the logic chip is generally located in the middle position of the chip, the conductive via of the DFT global signal is preferably located in the narrower region in the middle of the chip, that is, the position of the global signal region as shown in Figure 3 .

[0080] That is, the global signals transmitted by the global signal region are commonly used by the m channels in all the memory chips in the subsequent stacked structure; and the channel control signals transmitted by each channel signal region are only used by the specific channel in all the memory chips in the subsequent stacked structure.

[0081] Please refer to Figure 4A Each channel signal region includes a first axis AA' and a second axis BB', the first axis AA' extends along the first direction or the second direction, and the second axis BB' is perpendicular to the first axis AA' and intersects at the center of the channel signal region. For example, in Figure 3 , the first axis AA' extends along the first direction, and the second axis BB' extends along the second direction; in other embodiments, the first axis AA' can extend along the second direction, and the second axis BB' extends along the first direction. Figure 4A The global signal region is temporarily omitted. As shown in Figure 4A , each channel signal region is penetrated by a plurality of conductive vias (D0, D1, D2, D3) along a third direction, each conductive via is used to transmit the channel control signal. The first direction, the second direction and the third direction are perpendicular to each other, the first direction and the second direction are parallel to the top surface of the logic chip 10, and the third direction is perpendicular to the top surface of the logic chip 10.

[0082] In the embodiments of the present disclosure, please refer to Figure 4B For each channel signal region, the (all or part) conductive vias therein are divided into a plurality of repair unit groups. Each repair unit group includes a first repair unit, a second repair unit, a third repair unit and a fourth repair unit; the first repair unit and the second repair unit are symmetrical along the first axis AA' of the channel signal region, the third repair unit and the fourth repair unit are symmetrical along the first axis AA' of the channel signal region, and the first repair unit and the fourth repair unit are symmetrical along the second axis BB' of the channel signal region. The above symmetry features can be called four-quadrant symmetry. In particular, Figure 4B Each repair unit group in Figure 4B is only illustrative, and the shape of the actual repair unit group can be various forms.

[0083] Each repair unit (when not specified, the repair unit can refer to any one of the first repair unit, the second repair unit, the third repair unit and the fourth repair unit) includes at least one redundant conductive via and at least one normal conductive via, where the normal conductive via refers to a conductive via originally designed for transmitting an effective signal, and the redundant conductive via refers to a conductive via originally designed not to transmit any signal. However, when any normal conductive via is damaged, the redundant conductive via can be changed to a normal conductive via for transmitting an effective signal, so that the memory can still work normally. That is, for the same repair unit, when any normal conductive via is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit in a preset signal switching direction. Specifically, (1) if the switched next conductive via is a redundant conductive via, the repair ends, and the redundant conductive via becomes a new normal conductive via; (2) if the switched next conductive via is another normal conductive via, the signal originally transmitted by the switched normal conductive via continues to be switched to the next conductive via in the preset switching direction until it is switched to a redundant conductive via.

[0084] In particular, the logic chip 10 further includes a plurality of signal selection circuits (which can specifically include data selectors Mux and driving units). Taking a signal output as an example, the to-be-transmitted signal generated inside the logic chip 10 is sent to the input end of the signal selection circuit, and the output end of the signal selection circuit is connected to a plurality of conductive vias. At this time, the signal selection circuit only sends the to-be-transmitted signal to one of the conductive vias. When the conductive via is damaged, the signal selection circuit can send the to-be-transmitted signal to another conductive via, thereby realizing the switching of the conductive vias (i.e., the switching of the signal transmission channel). The corresponding structure of the signal input is adaptively understood.

[0085] In this way, via the signal selection circuit, any conductive via in any repair unit is electrically connected to the internal circuit of the logic chip 10 when used to transmit an effective signal, and any conductive via in any repair unit is electrically isolated from the internal circuit of the logic chip 10 when not transmitting an effective signal. Or it can be understood that any conductive via in any repair unit is electrically connected to the internal circuit of the logic chip 10 when it is a normal conductive via, and any conductive via in any repair unit is electrically isolated from the internal circuit of the logic chip 10 when it is not a normal conductive via.

[0086] The number of normal conductive vias and the number of redundant conductive vias in each repair unit can be flexibly determined. For example, if each repair unit includes 4 different conductive vias, the number of normal conductive vias: the number of redundant conductive vias = 2:2, or the number of normal conductive vias: the number of redundant conductive vias = 1:3, or the number of normal conductive vias: the number of redundant conductive vias = 3:1, etc. For example, if each repair unit includes 6 different conductive vias, the number of normal conductive vias: the number of redundant conductive vias = 4:2, or the number of normal conductive vias: the number of redundant conductive vias = 3:3, etc. The actual application scenario can be selected.

[0087] In the embodiments of the present disclosure, the normal conductive vias in the repair units have the following symmetry relationship: the normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit correspond one-to-one and are symmetric along the first axis AA' of the channel signal region, the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit correspond one-to-one and are symmetric along the first axis AA' of the channel signal region, and the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit correspond one-to-one and are symmetric along the second axis BB' of the channel signal region, that is, the positions of the normal conductive vias also have the characteristics of four-quadrant symmetry.

[0088] In this way, the repair units in the logic chip 10 have a four-quadrant symmetry relationship, and the normal conductive vias therein also have a four-quadrant symmetry relationship, so that the chip stacking structure formed by the logic chip and the memory chip (also having this feature) can realize signal rotation transmission effect through the direct connection configuration of the conductive vias, and the parasitic resistance and parasitic capacitance are relatively small, which can be specifically referred to subsequent description; at the same time, through the four-quadrant symmetrically arranged repair units, the redundancy repair function of the above structure can also be realized, and the stability of the chip is improved; at the same time, the distribution of the conductive via groups and the repair units in different channel signal regions is the same, and the same mask plate can be used.

[0089] In the embodiments of the present disclosure, for each repair unit group, the preset switching direction of the conductive vias in the first repair unit and the preset switching direction of the conductive vias in the second repair unit are symmetric along the first axis AA' of the channel signal region; the preset switching direction of the conductive vias in the third repair unit and the preset switching direction of the conductive vias in the fourth repair unit are symmetric along the first axis AA' of the channel signal region; the preset switching direction of the conductive vias in the first repair unit and the preset switching direction of the conductive vias in the fourth repair unit are symmetric along the second axis BB' of the channel signal region; and the preset switching direction of the conductive vias in the second repair unit and the preset switching direction of the conductive vias in the third repair unit are symmetric along the second axis BB' of the channel signal region.

[0090] Please refer toFigure 4A Each channel signal region 20 is divided into 2x2 signal areas, i.e., a first signal area 21, a second signal area 22, a third signal area 23, and a fourth signal area 24; and (all or part of) the conductive vias in each signal area are divided into n conductive via groups with the same distribution, where n is a positive integer, Figure 4A Each dotted box in the middle is a conductive via group. As shown in Figure 4A The conductive via groups in the first signal area 21 and the conductive via groups in the second signal area 22 correspond one-to-one and are symmetrical along the first axis AA' of the channel signal region, the conductive via groups in the third signal area 23 and the conductive via groups in the fourth signal area 24 correspond one-to-one and are symmetrical along the first axis AA' of the channel signal region, and the conductive via groups in the first signal area 21 and the conductive via groups in the fourth signal area 24 correspond one-to-one and are symmetrical along the second axis BB' of the channel signal region, i.e., the conductive via groups are also four-quadrant symmetrical. Here, Figure 4A Only one conductive via group is shown for each signal area, but in fact there are many conductive via groups for each signal area.

[0091] As shown in Figure 4A Each conductive via group includes a first conductive via D0, a second conductive via D1, a third conductive via D2, and a fourth conductive via D3; and has the following symmetry relationships:

[0092] (1) In the same channel signal region, the entire group consisting of the first conductive via D0 in one conductive via group in the first signal area 21, the second conductive via D1 in the corresponding conductive via group in the second signal area 22, the third conductive via D2 in the corresponding conductive via group in the third signal area 23, and the fourth conductive via D3 in the corresponding conductive via group in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0093] (2) In the same channel signal region, the entire group consisting of the second conductive via D1 in one conductive via group in the first signal area 21, the first conductive via D0 in the corresponding conductive via group in the second signal area 22, the fourth conductive via D3 in the corresponding conductive via group in the third signal area 23, and the third conductive via D2 in the corresponding conductive via group in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0094] (3) In the same channel signal area, the whole composed of the third conductive via D2 in one conductive via group in the first signal area 21, the fourth conductive via D3 in the corresponding conductive via group in the second signal area 22, the first conductive via D0 in the corresponding conductive via group in the third signal area 23, and the second conductive via D1 in the corresponding conductive via group in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0095] (4) In the same channel signal area, the whole composed of the fourth conductive via D3 in one conductive via group in the first signal area 21, the third conductive via D2 in the corresponding conductive via group in the second signal area 22, the second conductive via D1 in the corresponding conductive via group in the third signal area 23, and the first conductive via D0 in the corresponding conductive via group in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB'.

[0096] It should be understood that, in the above embodiment, Figure 4A each of the 4 conductive vias in each conductive via group is arranged in a 2x2 array, but in other embodiments, the 4 conductive vias in each conductive via group can be arranged in any manner, as long as the above symmetry principle is followed.

[0097] Due to the limited length, only one channel signal area is taken as an example to illustrate the composition and principle of the repair unit group in the subsequent drawings, but in fact, the structures of all channel signal areas are the same, that is, any one of the channel signal areas in the drawings can be understood as any one of the channel signal area 11, the channel signal area 12, the channel signal area 13, and the channel signal area 14.

[0098] In some embodiments, the B conductive via groups in each signal area are referred to as one conductive via combination, and the whole composed of the conductive via groups b in the corresponding conductive via combinations in all signal areas is symmetrical along the first axis AA' and symmetrical along the second axis BB', B is a positive integer less than or equal to n, and b is a natural number less than B.

[0099] The corresponding one conductive via combination in each signal area in the same channel signal area collectively constitutes 4 repair unit groups:

[0100] (1) For the first repair unit group, the first repair unit includes: all the first conductive vias D0 of each conductive via group in the conductive via combination in the first signal area 21; the second repair unit includes: all the second conductive vias D1 of each conductive via group in the conductive via combination in the second signal area 22; the third repair unit includes: all the third conductive vias D2 of each conductive via group in the conductive via combination in the third signal area 23; and the fourth repair unit includes: all the fourth conductive vias D3 of each conductive via group in the conductive via combination in the fourth signal area 24.

[0101] (2) For the second repair unit group, the first repair unit includes: all the first conductive vias D0 of each conductive via group in the conductive via combination in the second signal area 22; the second repair unit includes: all the second conductive vias D1 of each conductive via group in the conductive via combination in the first signal area 21; the third repair unit includes: all the third conductive vias D2 of each conductive via group in the conductive via combination in the fourth signal area 24; and the fourth repair unit includes: all the fourth conductive vias D3 of each conductive via group in the conductive via combination in the third signal area 23.

[0102] (3) For the third repair unit group, the first repair unit includes: all the first conductive vias D0 of each conductive via group in the conductive via combination in the third signal area 23; the second repair unit includes: all the second conductive vias D1 of each conductive via group in the conductive via combination in the fourth signal area 24; the third repair unit includes: all the third conductive vias D2 of each conductive via group in the conductive via combination in the first signal area 21; and the fourth repair unit includes: all the fourth conductive vias D3 of each conductive via group in the conductive via combination in the second signal area 22.

[0103] (4) For the fourth repair unit group, the first repair unit includes: all the first conductive vias D0 of each conductive via group in the conductive via combination in the fourth signal area 24; the second repair unit includes: all the second conductive vias D1 of each conductive via group in the conductive via combination in the third signal area 23; the third repair unit includes: all the third conductive vias D2 of each conductive via group in the conductive via combination in the second signal area 22; and the fourth repair unit includes: all the fourth conductive vias D3 of each conductive via group in the conductive via combination in the first signal area 21.

[0104] It should be noted that for the same logic chip 10, B can have multiple values, for example, in the same logic chip 10, there are both 4-conductive via groups and 6-conductive via groups, or more forms. However, no matter how many conductive via groups are included, each conductive via group combination must form 4 repair unit groups.

[0105] In a first specific embodiment, please refer to Figure 5 , B = 3, b takes 0, 1 or 2. That is, the whole of the conductive via group 0 in the first signal area 21, the conductive via group 0 in the second signal area 22, the conductive via group 0 in the third signal area 23, and the conductive via group 0 in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB'; the whole of the conductive via group 1 in the first signal area 21, the conductive via group 1 in the second signal area 22, the conductive via group 1 in the third signal area 23, and the conductive via group 1 in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB'; and so on.

[0106] The conductive via group 0 to the conductive via group 2 in each signal area in the same channel signal area together form 4 repair unit groups:

[0107] Please refer to Figure 6A , for the first repair unit group_1: (1) the first repair unit_1 therein includes: the first conductive via of the conductive via group 0, the conductive via group 1, and the conductive via group 2 in the first signal area 21, i.e. D0 / 0, D0 / 1, D0 / 2 in the first signal area 21; (2) the second repair unit_1 therein includes: the second conductive via of the conductive via group 0, the conductive via group 1, and the conductive via group 2 in the second signal area 22, i.e. D1 / 0, D1 / 1, D1 / 2 in the second signal area 22; (3) the third repair unit_1 therein includes: the third conductive via of the conductive via group 0, the conductive via group 1, and the conductive via group 2 in the third signal area 23, i.e. D2 / 0, D2 / 1, D2 / 2 in the third signal area 23; (4) the fourth repair unit_1 therein includes: the fourth conductive via of the conductive via group 0, the conductive via group 1, and the conductive via group 2 in the fourth signal area 24, i.e. D3 / 0, D3 / 1, D3 / 2 in the fourth signal area 24.

[0108] Please refer to Figure 6BFor the 2nd repair unit group_2, (1) the first repair unit_2 therein comprises: the first conductive via of each of the conductive via group 0, the conductive via group 1, the conductive via group 2 in the second signal area 22, i.e. D0 / 0, D0 / 1, D0 / 2 in the second signal area 22; (2) the second repair unit_2 therein comprises: the second conductive via of each of the conductive via group 0, the conductive via group 1, the conductive via group 2 in the first signal area 21, i.e. D1 / 0, D1 / 1, D1 / 2 in the first signal area 21; (3) the third repair unit_2 therein comprises: the third conductive via of each of the conductive via group 0, the conductive via group 1, the conductive via group 2 in the fourth signal area 24, i.e. D2 / 0, D2 / 1, D2 / 2 in the fourth signal area 24; (4) the fourth repair unit_2 therein comprises: the fourth conductive via of each of the conductive via group 0, the conductive via group 1, the conductive via group 2 in the third signal area 23, i.e. D3 / 0, D3 / 1, D3 / 2 in the third signal area 23.

[0109] Please refer to Figure 6C For the 3rd repair unit group_3, (1) the first repair unit_3 therein comprises: the first conductive via of each of the conductive via group 0, the conductive via group 1, the conductive via group 2 in the third signal area 23, i.e. D0 / 0, D0 / 1, D0 / 2 in the third signal area 23; (2) the second repair unit_3 therein comprises: the second conductive via of each of the conductive via group 0, the conductive via group 1, the conductive via group 2 in the fourth signal area 24, i.e. D1 / 0, D1 / 1, D1 / 2 in the fourth signal area 24; (3) the third repair unit_3 therein comprises: the third conductive via of each of the conductive via group 0, the conductive via group 1, the conductive via group 2 in the first signal area 21, i.e. D2 / 0, D2 / 1, D2 / 2 in the first signal area 21; (4) the fourth repair unit_3 therein comprises: the fourth conductive via of each of the conductive via group 0, the conductive via group 1, the conductive via group 2 in the second signal area 22, i.e. D3 / 0, D3 / 1, D3 / 2 in the second signal area 22.

[0110] Please refer to Figure 6DFor the fourth repair unit group_4, (1) the first repair unit_4 therein comprises: the first conductive via of each of the conductive via group 0, the conductive via group 1 and the conductive via group 2 in the fourth signal area 24, i.e. D0 / 0, D0 / 1, D0 / 2 in the fourth signal area 24; (2) the second repair unit_4 therein comprises: the second conductive via of each of the conductive via group 0, the conductive via group 1 and the conductive via group 2 in the third signal area 23, i.e. D2 / 0, D2 / 1, D2 / 2 in the third signal area 23; (3) the third repair unit_4 therein comprises: the third conductive via of each of the conductive via group 0, the conductive via group 1 and the conductive via group 2 in the second signal area 22, i.e. D2 / 0, D2 / 1, D2 / 2 in the second signal area 22; (4) the fourth repair unit_4 therein comprises: the fourth conductive via of each of the conductive via group 0, the conductive via group 1 and the conductive via group 2 in the first signal area 21, i.e. D3 / 0, D3 / 1, D3 / 2 in the first signal area 21.

[0111] It should be noted that, as shown in Figure 6A For the first repair unit group, the first repair unit_1 (D0 / 0, D0 / 1, D0 / 2 of the first signal area 21) is symmetrical to the second repair unit_1 (D1 / 0, D1 / 1, D1 / 2 of the first signal area 22) along the first axis AA’, the third repair unit_1 (D2 / 0, D2 / 1, D2 / 2 of the third signal area 23) is symmetrical to the fourth repair unit_1 (D3 / 0, D3 / 1, D3 / 2 of the fourth signal area 24) along the first axis AA’, the first repair unit_1 (D0 / 0, D0 / 1, D0 / 2 of the first signal area 21) is symmetrical to the fourth repair unit_1 (D3 / 0, D3 / 1, D3 / 2 of the fourth signal area 24) along the second axis BB’, and the second repair unit_1 (D1 / 0, D1 / 1, D1 / 2 of the first signal area 22) is symmetrical to the third repair unit_1 (D2 / 0, D2 / 1, D2 / 2 of the third signal area 23) along the second axis BB’. Meanwhile, the second to fourth repair unit groups also have similar features.

[0112] The following provides an example of preset switching direction for better understanding of the foregoing description, but the following example is not the only solution.

[0113] Assuming that all the conductive vias in the conductive via group 0 are normal conductive vias, and the preset switching direction of the conductive via in the Xth repair unit is that the Xth conductive via in the conductive via group 0 is allowed to switch to the Xth conductive via in the conductive via group 1 in the same signal area, and the Xth conductive via in the conductive via group 1 is allowed to switch to the Xth conductive via in the conductive via group 2 in the same signal area; X is one, two, three or four.

[0114] That is, please refer toFigure 6A For the first repair unit group, the preset switching direction of the conductive via in the first repair unit_1 is: D0 / 0—D0 / 1—D0 / 2 in the first signal area 21; the preset switching direction of the conductive via in the second repair unit_1 is: D1 / 0—D1 / 1—D1 / 2 in the second signal area 22; the preset switching direction of the conductive via in the third repair unit_1 is: D2 / 0—D2 / 1—D2 / 2 in the third signal area 23; and the preset switching direction of the conductive via in the fourth repair unit_1 is: D3 / 0—D3 / 1—D3 / 2 in the fourth signal area 24.

[0115] Please refer to Figure 6B For the second repair unit group, the preset switching direction of the conductive via in the first repair unit_2 is: D0 / 0—D0 / 1—D0 / 2 in the second signal area 22; the preset switching direction of the conductive via in the second repair unit_2 is: D1 / 0—D1 / 1—D1 / 2 in the first signal area 21; the preset switching direction of the conductive via in the third repair unit_2 is: D2 / 0—D2 / 1—D2 / 2 in the fourth signal area 24; and the preset switching direction of the conductive via in the fourth repair unit_2 is: D3 / 0—D3 / 1—D3 / 2 in the third signal area 23.

[0116] Please refer to Figure 6C For the third repair unit group, the preset switching direction of the conductive via in the first repair unit_3 is: D0 / 0—D0 / 1—D0 / 2 in the third signal area 23; the preset switching direction of the conductive via in the second repair unit_3 is: D1 / 0—D1 / 1—D1 / 2 in the fourth signal area 22; the preset switching direction of the conductive via in the third repair unit_3 is: D2 / 0—D2 / 1—D2 / 2 in the first signal area 21; and the preset switching direction of the conductive via in the fourth repair unit_3 is: D3 / 0—D3 / 1—D3 / 2 in the second signal area 22.

[0117] Please refer to Figure 6D For the fourth repair unit group, the preset switching direction of the conductive via in the first repair unit_4 is: D0 / 0—D0 / 1—D0 / 2 in the fourth signal area 24; the preset switching direction of the conductive via in the second repair unit_4 is: D1 / 0—D1 / 1—D1 / 2 in the third signal area 22; the preset switching direction of the conductive via in the third repair unit_4 is: D2 / 0—D2 / 1—D2 / 2 in the second signal area 23; and the preset switching direction of the conductive via in the fourth repair unit_4 is: D3 / 0—D3 / 1—D3 / 2 in the first signal area 21.

[0118] It should be noted that for each of the above repair units, the ratio of the number of normal conductive vias and redundant conductive vias can be set arbitrarily, for example, 1:2, 2:1, etc.

[0119] For the convenience of understanding, the following is an example of a normal conductive via: redundant conductive via number = 2:1 repair ratio to provide a specific description of a signal switching related circuit. In order to realize the above switching process, please refer to Figure 6A 、 Figure 6B 、 Figure 6C and Figure 6D The logic chip 10 also includes a plurality of signal selection circuits 100 for realizing the switching of the conductive vias described above. Specifically, each signal selection circuit 100 is composed of a data selector and a plurality of drive units, the data selector in the signal selection circuit 100 is connected with a plurality of conductive vias, and the drive circuit in the signal selection circuit 100 is connected with the internal circuit of the logic chip 10, so that via the signal selection circuit 100, a specified conductive via can be selected to be in an electrically connected state with the internal circuit of the logic chip 10, and thus the switching of the conductive vias can be performed.

[0120] Take the first repair unit_1 (D0 / 0, D0 / 1, D0 / 2 in the first signal area 21) of the first repair unit group as an example, please refer to Figure 6A D0 / 0, D0 / 1 is connected to the first signal selection circuit 100, and the first signal selection circuit 100 connects D0 / 0 with the internal circuit of the logic circuit 10; D0 / 1, D0 / 2 is connected to the second signal selection circuit 100, and the second signal selection circuit 100 connects D0 / 1 with the internal circuit of the logic circuit 10; then, if D0 / 0 is damaged, the first signal selection circuit 100 connects D0 / 1 with the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 0 will be transmitted by D0 / 1; at the same time, the second signal selection circuit 100 connects D0 / 2 with the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 1 will be transmitted by D0 / 2. The rest of the repair units please refer to the understanding.

[0121] It should be noted that Figures 6A-6D is only an example of a preset switching direction; the preset switching direction actually has very flexible choices. Taking the first repair unit_1 as an example, it can be switched in turn along D0 / 0, D0 / 1, D0 / 2, or it can be switched in D0 / 2, D0 / 1, D0 / 0, or it can be switched starting from D0 / 1, etc. Of course, the four repair units must follow the symmetry feature described above, that is, if the first repair unit_1 adopts other switching forms and definitions of normal conductive vias, then the second repair unit_1, the third repair unit_1 and the fourth repair unit_1 must also adopt the corresponding switching forms and definitions of normal vias.

[0122] Thus, the conductive via positions of different repair units and the preset switching directions maintain the above-mentioned symmetrical relationship, so that the subsequently formed chip stacking structure can realize signal rotation transmission through the direct connection configuration. Details are described below.

[0123] In a second specific embodiment, please refer to Figure 7 , B = 6, and b takes 0, 1, 2, 3, 4, or 5. At this time, the conductive via groups 0-5 in each signal area in the same channel signal area constitute 4 repair unit groups:

[0124] The 6 conductive via groups in each signal area are referred to as conductive via group 0-conductive via group 5, respectively, and the whole conductive via groups b in all signal areas are symmetrical along the first axis AA' and symmetrical along the second axis BB'; b≤5; that is, the whole conductive via group 0 in the first signal area 21, the conductive via group 0 in the second signal area 22, the conductive via group 0 in the third signal area 23, and the conductive via group 0 in the fourth signal area 24 are symmetrical along the first axis AA' and symmetrical along the second axis BB'; the whole conductive via group 1 in the first signal area 21, the conductive via group 1 in the second signal area 22, the conductive via group 1 in the third signal area 23, and the conductive via group 1 in the fourth signal area 24 are symmetrical along the first axis AA' and symmetrical along the second axis BB'; and so on.

[0125] The conductive via groups 0-5 in each signal area in the same channel signal area constitute 4 repair unit groups:

[0126] Please refer to Figure 8A , for the first repair unit group_A: (1) the first repair unit_A therein includes: the first conductive via of each of the conductive via groups 0-5 in the first signal area 21, that is, D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, and D0 / 5 in the first signal area 21; (2) the second repair unit_A therein includes: the second conductive via of each of the conductive via groups 0-5 in the second signal area 22, that is, D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, and D1 / 5 in the second signal area 22; (3) the third repair unit_A therein includes: the third conductive via of each of the conductive via groups 0-5 in the third signal area 23, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, and D2 / 5 in the third signal area 23; and (4) the fourth repair unit_A therein includes: the fourth conductive via of each of the conductive via groups 0-5 in the fourth signal area 24, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, and D3 / 5 in the fourth signal area 24.

[0127] Referring to Figure 8B For the second repair unit group B, (1) the first repair unit B therein comprises: the first conductive via of each of the conductive via group 0 to the conductive via group 5 in the second signal area 22, i.e. D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the second signal area 22; (2) the second repair unit B therein comprises: the second conductive via of each of the conductive via group 0 to the conductive via group 5 in the first signal area 21, i.e. D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the first signal area 21; (3) the third repair unit B therein comprises: the third conductive via of each of the conductive via group 0 to the conductive via group 5 in the fourth signal area 24, i.e. D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the fourth signal area 24; (4) the fourth repair unit B therein comprises: the fourth conductive via of each of the conductive via group 0 to the conductive via group 5 in the third signal area 23, i.e. D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the third signal area 23.

[0128] Referring to Figure 8C For the third repair unit group C, (1) the first repair unit C therein comprises: the first conductive via of each of the conductive via group 0 to the conductive via group 5 in the third signal area 23, i.e. D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the third signal area 23; (2) the second repair unit C therein comprises: the second conductive via of each of the conductive via group 0 to the conductive via group 5 in the fourth signal area 24, i.e. D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the fourth signal area 24; (3) the third repair unit C therein comprises: the third conductive via of each of the conductive via group 0 to the conductive via group 5 in the first signal area 21, i.e. D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the first signal area 21; (4) the fourth repair unit C therein comprises: the fourth conductive via of each of the conductive via group 0 to the conductive via group 5 in the second signal area 22, i.e. D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the second signal area 22.

[0129] Referring to Figure 8DFor the fourth repair unit group D, the first repair unit therein includes: the first conductive via of each of the conductive via group 0 to the conductive via group 5 in the fourth signal region 24, i.e. D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the fourth signal region 24; (2) the second repair unit D therein includes: the second conductive via of each of the conductive via group 0 to the conductive via group 5 in the third signal region 23, i.e. D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the third signal region 23; (3) the fourth repair unit D therein includes: the third conductive via of each of the conductive via group 0 to the conductive via group 5 in the second signal region 22, i.e. D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the second signal region 22; and the fourth repair unit D therein includes: the fourth conductive via of each of the conductive via group 0 to the conductive via group 5 in the first signal region 21, i.e. D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the first signal region 21.

[0130] It should be noted that, as shown in Figure 8A the first repair unit A (D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the first signal region 21) and the second repair unit A (D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the second signal region 22) are symmetrical along the first axis AA', the fourth repair unit A (D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the fourth signal region 24) and the third repair unit A (D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the third signal region 23) are symmetrical along the first axis AA', the first repair unit A (D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the first signal region 21) and the fourth repair unit A (D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the fourth signal region 24) are symmetrical along the second axis BB', and the second repair unit A (D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the second signal region 22) and the third repair unit A (D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the third signal region 23) are symmetrical along the second axis BB'. Meanwhile, the second to fourth repair unit groups also have similar features.

[0131] The following provides an example of preset switching direction for better understanding of the foregoing description, but the following example is not the only solution.

[0132] Assuming that all the conductive vias in the conductive via group 2 of all the signal regions are normal conductive vias; the preset switching direction of the conductive vias in the Xth repair unit is that the Xth conductive via in the conductive via group 2 is allowed to switch to the Xth conductive via in the conductive via group 3 in the same signal region, the Xth conductive via in the conductive via group 3 is allowed to switch to the Xth conductive via in the conductive via group 4 in the same signal region, the Xth conductive via in the conductive via group 4 is allowed to switch to the Xth conductive via in the conductive via group 1 in the same signal region; the Xth conductive via in the conductive via group 1 is allowed to switch to the Xth conductive via in the conductive via group 0 in the same signal region; the Xth conductive via in the conductive via group 0 is allowed to switch to the Xth conductive via in the conductive via group 5 in the same signal region.

[0133] Please refer to Figure 8A The preset switching direction of the first repair unit group A is as follows:

[0134] (a) The preset switching direction of the conductive vias in the first repair unit A is D0 / 2—D0 / 3—D0 / 4—D0 / 1—D0 / 0—D0 / 5 in the first signal region 21; (b) The preset switching direction of the conductive vias in the second repair unit A is D1 / 2—D1 / 3—D1 / 4—D1 / 1—D1 / 0—D1 / 5 in the second signal region 22; (c) The preset switching direction of the conductive vias in the third repair unit A is D2 / 2—D2 / 3—D2 / 4—D2 / 1—D2 / 0—D2 / 5 in the third signal region 23; (d) The preset switching direction of the conductive vias in the fourth repair unit A is D3 / 2—D3 / 3—D3 / 4—D3 / 1—D3 / 0—D3 / 5 in the fourth signal region 24.

[0135] Please refer to Figure 8B The preset switching direction of the second repair unit group B is as follows:

[0136] (a) The preset switching direction of the conductive vias in the first repair unit B is D0 / 2—D0 / 3—D0 / 4—D0 / 1—D0 / 0—D0 / 5 in the second signal region 22; (b) The preset switching direction of the conductive vias in the second repair unit B is D1 / 2—D1 / 3—D1 / 4—D1 / 1—D1 / 0—D1 / 5 in the first signal region 21; (c) The preset switching direction of the conductive vias in the third repair unit B is D2 / 2—D2 / 3—D2 / 4—D2 / 1—D2 / 0—D2 / 5 in the fourth signal region 24; (d) The preset switching direction of the conductive vias in the fourth repair unit B is D3 / 2—D3 / 3—D3 / 4—D3 / 1—D3 / 0—D3 / 5 in the third signal region 23.

[0137] Please refer to Figure 8C The preset switching direction of the 3rd repair unit group C is described as follows:

[0138] (a) The preset switching direction of the conductive via in the first repair unit C is: D0 / 2—D0 / 3—D0 / 4—D0 / 1—D0 / 0—D0 / 5 in the third signal area 23; (b) The preset switching direction of the conductive via in the second repair unit C is: D1 / 2—D1 / 3—D1 / 4—D1 / 1—D1 / 0—D1 / 5 in the fourth signal area 24; (c) The preset switching direction of the conductive via in the second repair unit C is: D2 / 2—D2 / 3—D2 / 4—D2 / 1—D2 / 0—D2 / 5 in the first signal area 21; (d) The preset switching direction of the conductive via in the fourth repair unit C is: D3 / 2—D3 / 3—D3 / 4—D3 / 1—D3 / 0—D3 / 5 in the second signal area 22;

[0139] Please refer to Figure 8D The preset switching direction of the 4th repair unit group C is described as follows:

[0140] (a) The preset switching direction of the conductive via in the first repair unit D is: D0 / 2—D0 / 3—D0 / 4—D0 / 1—D0 / 0—D0 / 5 in the fourth signal area 24; (b) The preset switching direction of the conductive via in the second repair unit D is: D1 / 2—D1 / 3—D1 / 4—D1 / 1—D1 / 0—D1 / 5 in the third signal area 23; (c) The preset switching direction of the conductive via in the second repair unit D is: D2 / 2—D2 / 3—D2 / 4—D2 / 1—D2 / 0—D2 / 5 in the second signal area 22; (d) The preset switching direction of the conductive via in the fourth repair unit D is: D3 / 2—D3 / 3—D3 / 4—D3 / 1—D3 / 0—D3 / 5 in the first signal area 21;

[0141] The following provides a specific description of a signal switching related circuit with a repair ratio of normal conductive via: redundant conductive via number = 4:2. Take the first repair unit A of the 1st repair unit group (D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 of the first signal area 21) as an example. Please refer to Figure 8AD0 / 2, D0 / 3, D0 / 4 are connected to the first signal selection circuit 100, and the first signal selection circuit 100 connects D0 / 2 with the internal circuit of the logic circuit 10; D0 / 3, D0 / 4, D0 / 1 are connected to the second signal selection circuit 100, and the second signal selection circuit 100 connects D0 / 3 with the internal circuit of the logic circuit 10; D0 / 4, D0 / 1, D0 / 0 are connected to the third signal selection circuit 100, and the third signal selection circuit 100 connects D0 / 3 with the internal circuit of the logic circuit 10, D0 / 1, D0 / 0, D0 / 5 are connected to the fourth signal selection circuit 100, and the fourth signal selection circuit 100 connects D0 / 1 with the internal circuit of the logic circuit 10; then, if D0 / 2 is damaged, the first signal selection circuit 100 connects D0 / 3 with the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 2 will be transmitted by D0 / 3; at the same time, the second signal selection circuit 100 connects D0 / 4 with the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 3 will be transmitted by D0 / 4, the third signal selection circuit 100 connects D0 / 1 with the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 4 will be transmitted by D0 / 1, at the same time, the fourth signal selection circuit 100 connects D0 / 0 with the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 4 will be transmitted by D0 / 0. The remaining repair units are understood with reference.

[0142] Similarly, Figures 8A-8D It is only an example of the preset switching direction; the preset switching direction also has very flexible selection.

[0143] It should be noted that in the foregoing examples, in each signal area, the conductive via group 0, the conductive via group 1, and the conductive via group 2 are aligned along the first direction; the conductive via group 3, the conductive via group 4, and the conductive via group 5 are aligned along the first direction, the conductive via group 2 and the conductive via group 3 are aligned along the second direction, the conductive via group 1 and the conductive via group 4 are aligned along the second direction, and the conductive via group 0 and the conductive via group 5 are aligned along the second direction, but this is only an example, and the via groups 1-5 can be at any position in the same signal area.

[0144] In this way, the conductive via positions of different repair units and the preset switching direction maintain the above-mentioned symmetrical relationship, so that the subsequently formed chip stacking structure can realize the signal rotation transmission relationship through the direct connection configuration, which will be described in detail below.

[0145] It should be noted that for the same logic chip, it can adopt the repair unit as shown in Figure 5 , or adopt the repair unit as shown in Figure 7 , or simultaneously adopt the repair unit as shown in Figure 5 and the repair unit as shown inFigure 7 It may include two types of repair units, or more types of repair units.

[0146] It should also be noted that the conductive vias mentioned above can at least be categorized as through-silicon vias (TSVs), specifically a vertical interconnect structure that penetrates a silicon wafer / memory chip, for example... Figure 1 Type 1 in the above; of course, conductive vias can also be used. Figure 1 Type 2 in the diagram, together with the contact structure, enables signal transmission. In other embodiments, other electrical connection structures can also be selected as conductive vias.

[0147] Conductive vias can be fabricated using one or more of the following processes: pre-via, mid-via, post-via, and back-via. Pre-via refers to a via fabrication process where the via structure is created before the device, such as a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), is manufactured. Mid-via fabrication involves creating the via structure during the manufacturing process, often after device formation but before the stack-up. Post-via fabrication involves forming the via from the front side of the wafer after the back-end of line (BEOL) process. Back-via fabrication involves creating the via structure from the back side of the wafer after the BEOL process. In other words, pre-via fabrication can mean creating the via first, then the circuitry; mid-via fabrication can mean creating the circuitry and part of the metal layer first, then the via, and finally the remaining via; post-via and back-via fabrication can mean creating the circuitry and metal layer first, then the via.

[0148] In summary, the embodiments of this disclosure provide a logic chip in which the repair unit group, normal conductive via, and preset switching direction in each channel signal region have special symmetry, which can be directly applied to face-to-face stacked structures without the need for two sets of masks or two sets of vias; the chip stacked structure formed by this logic chip and (also having this feature) memory chip can achieve signal rotation transmission effect through the direct connection configuration of conductive vias, with relatively small parasitic resistance and parasitic capacitance; at the same time, through the symmetrically arranged repair units, the redundancy repair function of the above structure can be realized, improving the stability of the memory chip.

[0149] In another embodiment of this disclosure, see Figure 9 This illustration shows a structural schematic diagram of a memory chip 30 provided in an embodiment of this disclosure, which can be specifically understood as a cross-sectional schematic diagram of the active surface. For example... Figure 9As shown, the memory chip 30 includes m channels (m = 4 is taken as an example for illustration) Figure 3 The m channels are arranged in sequence along a first direction, the memory chip 9 has a chip axis YY' extending along a second direction and passing through the center of the memory chip, and the m channels are symmetrical about the chip axis YY'; each channel includes a first memory array region, a channel signal region and a second memory array region distributed in sequence along the second direction, and the center of each channel signal region coincides with the center of the channel. Here, the area of the channel signal region in the logic chip 10 is the same size as the area of the channel signal region in the memory chip 30. In particular, the area of the active surface of the logic chip 10 and the area of the active surface of the memory chip 30 can be the same, or the area of the active surface of the logic chip 10 can be larger than the area of the active surface of the memory chip 30.

[0150] It should be noted that, in the chip manufacturing process, in order to distinguish different channels of the chip, a positioning structure can be made on the reference channel (for example: the first channel) of the memory chip 30, so that the position of the reference channel can be identified through the positioning structure during subsequent packaging, and other channels can be identified by combining the active surface orientation of the chip.

[0151] Figure 9 Take m = 4 as an example for illustration, and m = 4 is also taken as an example for illustration in the following, but m can be any positive integer. Specifically, if m is even, then m / 2 channels are located on one side of the global signal region along the first direction, and the remaining m / 2 channels are located on the other side of the global signal region along the first direction; if m is odd, then the (m+1) / 2 channel needs to be divided into two parts and located on both sides of the global signal region along the first direction, and the other (m-1) / 2 channels are located on one side of the global signal region along the first direction, and the remaining (m-1) / 2 channels are located on the other side of the global signal region along the first direction.

[0152] Figure 9 It can be regarded as a sectional view of the active surface of the memory chip 30. As shown, Figure 9 The center of the active surface of the memory chip 30 and its adjacent region are defined as a global signal region, and the first channel, the second channel, the global signal region, the third channel and the fourth channel are arranged in sequence along the first direction. The signals transmitted by the global signal region are commonly used by the m channels of the memory chip; and the signals transmitted by each channel signal region are only used by the channel.

[0153] See Figure 10A which specifically shows a schematic diagram of the channel signal region 11 of the first channel, the channel signal region 12 of the second channel, the channel signal region 13 of the third channel, and the channel signal region 14 of the fourth channel. Figure 10A The global signal region is omitted.

[0154] As shown in Figure 10A each channel signal region has a first axis AA' and a second axis BB', the first axis AA' extends along a first direction or along a second direction, and the second axis BB' is perpendicular to the first axis AA' and intersects at the center of the channel signal region. Figure 4A For example, the first axis AA' extends along the first direction, and the other cases are understood adaptively.

[0155] Due to the limited space, the subsequent drawings only take one channel signal region as an example to explain the composition and principle of the repair unit group, but in fact, the structure of all channel signal regions is the same, that is, the channel signal region in the drawing can be understood as any one of the channel signal region 11, the channel signal region 12, the channel signal region 13, and the channel signal region 14.

[0156] Please refer to Figure 10A each channel signal region includes a first axis AA' and a second axis BB', the first axis AA' is parallel to the first side of the storage chip, and the first axis AA' and the second axis BB' are perpendicular to each other at the center point of the channel signal region. In Figure 11 , the first axis AA' extends along the first direction, and the second axis BB' extends along the second direction, but this is only an example and does not constitute a specific limitation. As shown in Figure 10A each channel signal region is penetrated by a plurality of conductive vias along a third direction, the first direction and the second direction are parallel to the top surface of the storage chip 30, and the third direction is perpendicular to the top surface of the storage chip 30.

[0157] The storage chip 30 also has a structure similar to the repair unit in the logical chip 10 described above, which is described as follows.

[0158] Please refer to Figure 10B For each channel signal region, the plurality of conductive vias therein are divided into a plurality of repair unit groups; each repair unit group includes a first repair unit, a second repair unit, a third repair unit, and a fourth repair unit; the first repair unit and the second repair unit are symmetrical along the first axis AA' of the channel signal region, the third repair unit and the fourth repair unit are symmetrical along the first axis AA' of the channel signal region, and the first repair unit and the fourth repair unit are symmetrical along the second axis BB' of the channel signal region.

[0159] Each repair unit includes at least one redundant conductive via and at least one normal conductive via, and when any normal conductive via is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset switching direction; the normal conductive via in the first repair unit and the normal conductive via in the second repair unit correspond to each other and are symmetrical along the first axis AA' of the channel signal area, the normal conductive via in the third repair unit and the normal conductive via in the fourth repair unit correspond to each other and are symmetrical along the first axis AA' of the channel signal area, and the normal conductive via in the first repair unit and the normal conductive via in the fourth repair unit correspond to each other and are symmetrical along the second axis BB' of the channel signal area.

[0160] In particular, for the logic chip 10, the normal conductive via in each repair unit is electrically connected to the internal circuit of the logic chip 10. In other words, referring to Figures 6A-6D , Figures 8A-8D , each repair unit is connected with the corresponding signal selection circuit 100, and any conductive via in the repair unit is electrically connected to the internal circuit of the logic chip when selected as a normal conductive via.

[0161] However, for the storage chip 30, only the conductive via in the first repair unit is electrically connected to the internal circuit of the storage chip 30 when used to transmit an effective signal, i.e., only the normal conductive via in the first repair unit is electrically connected to the internal circuit of the storage chip 30. For example, referring to the subsequent Figures 12A-12D , or 14A ~ Figure 14D , only the first repair unit is connected with the corresponding signal selection circuit 100, so that the conductive via in the first repair unit is electrically connected to the internal circuit of the logic chip when selected as a normal conductive via; all conductive vias in the second repair unit to the fourth repair unit are completely independent of the internal circuit of the storage chip 30, i.e., even if selected as a normal conductive via, they will not be electrically connected to the internal circuit of the storage chip 30.

[0162] In the embodiments of the present disclosure, for each repair unit group, the preset switching direction of the conductive via in the first repair unit and the preset switching direction of the conductive via in the second repair unit are symmetrical along the first axis AA' of the channel signal area; the preset switching direction of the conductive via in the third repair unit and the preset switching direction of the conductive via in the fourth repair unit are symmetrical along the first axis AA' of the channel signal area; the preset switching direction of the conductive via in the first repair unit and the preset switching direction of the conductive via in the fourth repair unit are symmetrical along the second axis BB' of the channel signal area; and the preset switching direction of the conductive via in the second repair unit and the preset switching direction of the conductive via in the third repair unit are symmetrical along the second axis BB' of the channel signal area.

[0163] In some embodiments, referring toFigure 10A Each channel signal region is divided into 2x2 signal areas, the conductive vias in each signal area are divided into n conductive via groups with the same distribution position, n is a positive integer, the conductive via groups in the first signal area 21 and the conductive via groups in the second signal area 22 correspond to each other and are symmetrical along the first axis AA', the conductive via groups in the third signal area 23 and the conductive via groups in the fourth signal area 24 correspond to each other and are symmetrical along the first axis AA', the conductive via groups in the first signal area 21 and the conductive via groups in the fourth signal area 24 correspond to each other and are symmetrical along the second axis BB'; each conductive via group includes a first conductive via, a second conductive via D1, a third conductive via D2 and a fourth conductive via D3 arranged in a 2x2 array.

[0164] The conductive vias in each signal area have the following characteristics:

[0165] (1) In the same channel signal region, the whole composed of the first conductive via in one conductive via group in the first signal area 21, the second conductive via D1 in the corresponding conductive via group in the second signal area 22, the third conductive via D2 in the corresponding conductive via group in the third signal area 23 and the fourth conductive via D3 in the corresponding conductive via group in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0166] (2) In the same channel signal region, the whole composed of the second conductive via D1 in one conductive via group in the first signal area 21, the first conductive via in the corresponding conductive via group in the second signal area 22, the fourth conductive via D3 in the corresponding conductive via group in the third signal area 23 and the third conductive via D2 in the corresponding conductive via group in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0167] (3) In the same channel signal region, the whole composed of the third conductive via D2 in one conductive via group in the first signal area 21, the fourth conductive via D3 in the corresponding conductive via group in the second signal area 22, the first conductive via in the corresponding conductive via group in the third signal area 23 and the second conductive via D1 in the corresponding conductive via group in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0168] (4) In the same channel signal region, the whole composed of the fourth conductive via D3 in one conductive via group in the first signal area 21, the third conductive via D2 in the corresponding conductive via group in the second signal area 22, the second conductive via D1 in the corresponding conductive via group in the third signal area 23 and the first conductive via in the corresponding conductive via group in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB'.

[0169] It should be understood that in Figure 10A each of the 4 conductive vias in each conductive via group presents a 2x2 array distribution, but in other embodiments, the 4 conductive vias in each conductive via group can be distributed arbitrarily, as long as the above symmetry principle is followed.

[0170] For better understanding, the subsequent drawings only take one channel signal area as an example to illustrate the composition and principle of the repair unit group, in particular, all channel signal areas adopt the same structure, that is, the channel signal area in the drawings can be understood as any one of the channel signal area 11, the channel signal area 12, the channel signal area 13, and the channel signal area 14.

[0171] In some embodiments, each of the B conductive via groups in each signal area is referred to as one conductive via combination, and the whole formed by the conductive via groups b in the corresponding conductive via combination in all signal areas is symmetrical along the first axis AA' and symmetrical along the second axis BB', B is a positive integer less than or equal to n, and b is a natural number less than B.

[0172] The corresponding one conductive via combination in each signal area in the same channel signal area constitutes 4 repair unit groups:

[0173] (1) For the first repair unit group, the first repair unit thereof includes the first conductive via D0 of each of the conductive via groups in the conductive via combination in the first signal area 21; the second repair unit thereof includes the second conductive via D1 of each of the conductive via groups in the conductive via combination in the second signal area 22; the third repair unit thereof includes the third conductive via D2 of each of the conductive via groups in the conductive via combination in the third signal area 23; and the fourth repair unit thereof includes the fourth conductive via D3 of each of the conductive via groups in the conductive via combination in the fourth signal area 24;

[0174] (2) For the second repair unit group, the first repair unit thereof includes the first conductive via D0 of each of the conductive via groups in the conductive via combination in the second signal area 22; the second repair unit thereof includes the second conductive via D1 of each of the conductive via groups in the conductive via combination in the first signal area 21; the third repair unit thereof includes the third conductive via D2 of each of the conductive via groups in the conductive via combination in the fourth signal area 24; and the fourth repair unit thereof includes the fourth conductive via D3 of each of the conductive via groups in the conductive via combination in the third signal area 23;

[0175] (3) For the third repair unit group, the first repair unit comprises: the first conductive via D0 of each conductive via group in the third signal area 23; the second repair unit comprises: the second conductive via D1 of each conductive via group in the fourth signal area 24; the third repair unit comprises: the third conductive via D2 of each conductive via group in the first signal area 21; and the fourth repair unit comprises: the fourth conductive via D3 of each conductive via group in the second signal area 22.

[0176] (4) For the fourth repair unit group, the first repair unit comprises: the first conductive via D0 of each conductive via group in the fourth signal area 24; the second repair unit comprises: the second conductive via D1 of each conductive via group in the third signal area 23; the third repair unit comprises: the third conductive via D2 of each conductive via group in the second signal area 22; and the fourth repair unit comprises: the fourth conductive via D3 of each conductive via group in the first signal area 21.

[0177] It should be noted that for the same logic chip 10, B can have multiple values, for example, in the same logic chip 10, there are both conductive via combinations composed of 4 conductive via groups and conductive via combinations composed of 6 conductive via groups, or more forms. However, no matter how many conductive via groups are contained, each conductive via combination must form 4 repair unit groups.

[0178] In the first specific embodiment, please refer to Figure 11 B = 3, and b takes 0, 1 or 2. At this time, the conductive via group 0 to the conductive via group 2 in each signal area in the same channel signal area together form 4 repair unit groups:

[0179] Please refer to Figure 12AFor the first repair unit group_1, (1) the first repair unit_1 therein includes: the first conductive via group 0, the first conductive via group 1, the first conductive via group 2 in the first signal area 21, i.e. D0 / 0, D0 / 1, D0 / 2 in the first signal area 21; (2) the second repair unit_1 therein includes: the second conductive via group 0, the second conductive via group 1, the second conductive via group 2 in the second signal area 22, i.e. D1 / 0, D1 / 1, D1 / 2 in the second signal area 22; (3) the third repair unit_1 therein includes: the third conductive via group 0, the third conductive via group 1, the third conductive via group 2 in the third signal area 23, i.e. D2 / 0, D2 / 1, D2 / 2 in the third signal area 23; (4) the fourth repair unit_1 therein includes: the fourth conductive via group 0, the fourth conductive via group 1, the fourth conductive via group 2 in the fourth signal area 24, i.e. D3 / 0, D3 / 1, D3 / 2 in the fourth signal area 24.

[0180] Please refer to Figure 12B For the second repair unit group_2, (1) the first repair unit_2 therein includes: the first conductive via group 0, the first conductive via group 1, the first conductive via group 2 in the second signal area 22, i.e. D0 / 0, D0 / 1, D0 / 2 in the second signal area 22; (2) the second repair unit_2 therein includes: the second conductive via group 0, the second conductive via group 1, the second conductive via group 2 in the first signal area 21, i.e. D1 / 0, D1 / 1, D1 / 2 in the first signal area 21; (3) the third repair unit_2 therein includes: the third conductive via group 0, the third conductive via group 1, the third conductive via group 2 in the fourth signal area 24, i.e. D2 / 0, D2 / 1, D2 / 2 in the fourth signal area 24; (4) the fourth repair unit_2 therein includes: the fourth conductive via group 0, the fourth conductive via group 1, the fourth conductive via group 2 in the third signal area 23, i.e. D3 / 0, D3 / 1, D3 / 2 in the third signal area 23.

[0181] Please refer to Figure 12CFor the 3rd repair unit group_3, (1) the first repair unit_3 therein comprises: the first conductive via of the conductive via group 0, conductive via group 1, conductive via group 2 in the third signal area 23, i.e. D0 / 0, D0 / 1, D0 / 2 in the third signal area 23; (2) the second repair unit_3 therein comprises: the second conductive via of the conductive via group 0, conductive via group 1, conductive via group 2 in the fourth signal area 24, i.e. D1 / 0, D1 / 1, D1 / 2 in the fourth signal area 24; (3) the third repair unit_3 therein comprises: the third conductive via of the conductive via group 0, conductive via group 1, conductive via group 2 in the first signal area 21, i.e. D2 / 0, D2 / 1, D2 / 2 in the first signal area 21; (4) the fourth repair unit_3 therein comprises: the fourth conductive via of the conductive via group 0, conductive via group 1, conductive via group 2 in the second signal area 22, i.e. D3 / 0, D3 / 1, D3 / 2 in the second signal area 22.

[0182] Please refer to Figure 12D For the 4th repair unit group_4, (1) the first repair unit_4 therein comprises: the first conductive via of the conductive via group 0, conductive via group 1, conductive via group 2 in the fourth signal area 24, i.e. D0 / 0, D0 / 1, D0 / 2 in the fourth signal area 24; (2) the second repair unit_4 therein comprises: the second conductive via of the conductive via group 0, conductive via group 1, conductive via group 2 in the third signal area 23, i.e. D2 / 0, D2 / 1, D2 / 2 in the third signal area 23; (3) the third repair unit_4 therein comprises: the third conductive via of the conductive via group 0, conductive via group 1, conductive via group 2 in the second signal area 22, i.e. D2 / 0, D2 / 1, D2 / 2 in the second signal area 22; (4) the fourth repair unit_4 therein comprises: the fourth conductive via of the conductive via group 0, conductive via group 1, conductive via group 2 in the first signal area 21, i.e. D3 / 0, D3 / 1, D3 / 2 in the first signal area 21.

[0183] The following provides an example of preset switching direction for better understanding of the foregoing description, but the following example is not the only solution.

[0184] In some embodiments, please refer to Figure 11 , the conductive vias in the conductive via group 0 are all normal conductive vias. As mentioned above, only the normal conductive vias in the first repair unit are connected to the internal of the memory chip, thus the preset switching direction of the conductive vias in any first repair unit is: the first conductive via in the conductive via group 0 is allowed to switch to the first conductive via in the conductive via group 1 in the same signal area, the first conductive via in the conductive via group 1 is allowed to switch to the first conductive via in the conductive via group 2 in the same signal area.

[0185] That is, please see Figure 12A For the first repair unit group, the preset switching direction of the conductive via in the first repair unit_1 is: D0 / 0—D0 / 1—D0 / 2 in the first signal area 21; please see Figure 12B For the second repair unit group, the preset switching direction of the conductive via in the first repair unit_2 is: D0 / 0—D0 / 1—D0 / 2 in the second signal area 22; please see Figure 12C For the third repair unit group, the preset switching direction of the conductive via in the first repair unit_3 is: D0 / 0—D0 / 1—D0 / 2 in the third signal area 23; please see Figure 12D For the fourth repair unit group, the preset switching direction of the conductive via in the first repair unit_4 is: D0 / 0—D0 / 1—D0 / 2 in the fourth signal area 24.

[0186] For the convenience of understanding, the following provides a specific description of a signal switching related circuit with a repair ratio of 2:1, that is, the number of normal conductive vias: the number of redundant conductive vias.

[0187] In order to realize the above switching process, please see Figures 12A-12D The storage chip 30 further comprises a plurality of signal selection circuits 100 for realizing the switching of the conductive vias. Taking the first repair unit_1 of the first repair unit group as an example, please see Figure 12A D0 / 0 and D0 / 1 are connected to the first signal selection circuit 100, and the first signal selection circuit 100 connects D0 / 0 with the internal circuit of the logic circuit 10; D0 / 1 and D0 / 2 are connected to the second signal selection circuit 100, and the second signal selection circuit 100 connects D0 / 1 with the internal circuit of the logic circuit 10; then, if D0 / 0 is damaged, the first signal selection circuit 100 connects D0 / 1 with the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 0 will be transmitted by D0 / 1; at the same time, the second signal selection circuit 100 connects D0 / 2 with the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 1 will be transmitted by D0 / 2. However, for the second repair unit to the fourth repair unit, no signal selection circuit 100 is provided, and whether the conductive via therein is a normal conductive via or a redundant conductive via, it is not connected to the storage chip 30, so the switching of the conductive via transmitting the signal in the repair unit of the storage chip is only followed by the switching of the conductive via transmitting the signal in the logic chip 10, and the storage chip 30 is actually not aware, so this embodiment only emphasizes the preset switching direction of the first repair unit.

[0188] The remaining repair units can be understood with reference to this.

[0189] It should be noted that Figures 12A-12D is only an example of the preset switching direction; the preset switching direction actually has very flexible choices. Taking the first repair unit_1 as an example, it can currently switch in the order of D0 / 0, D0 / 1, D0 / 2, or switch in the order of D0 / 2, D0 / 1, D0 / 0, or take D0 / 1 as the switching starting point, etc.

[0190] In this way, the conductive via positions of different repair units and the preset switching direction all maintain the above-mentioned symmetrical relationship, so as to ensure that the subsequently formed chip stacking structure can realize signal rotation transmission through a direct connection configuration. For details, please refer to the subsequent description.

[0191] In a second specific embodiment, please refer to Figure 13 , B = 6, and b takes 0, 1, 2, 3, 4, or 5. At this time, the conductive via group 0~conductive via group 5 in each signal area in the same channel signal area together constitute 4 repair unit groups:

[0192] Please refer to Figure 14A , for the first repair unit group_A: (1) the first repair unit_A therein includes: the first conductive via of each of the conductive via group 0~conductive via group 5 in the first signal area 21, that is, D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the first signal area 21; (2) the second repair unit_A therein includes: the second conductive via of each of the conductive via group 0~conductive via group 5 in the second signal area 22, that is, D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the second signal area 22; (3) the third repair unit_A therein includes: the third conductive via of each of the conductive via group 0~conductive via group 5 in the third signal area 23, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the third signal area 23; (4) the fourth repair unit_A therein includes: the fourth conductive via of each of the conductive via group 0~conductive via group 5 in the fourth signal area 24, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the fourth signal area 24.

[0193] Please refer to Figure 14BFor the second repair unit group_B, (1) the first repair unit_B includes: the first conductive vias of each of the conductive via groups 0 to 5 in the second signal area 22, namely D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the second signal area 22, namely D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the second signal area 22; (2) the second repair unit_B includes: the second conductive vias of each of the conductive via groups 0 to 5 in the first signal area 21, namely D1 in the first signal area 21. / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5; (3) The third repair unit_B includes: the third conductive via of each of the conductive via groups 0 to 5 in the fourth signal area, namely D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the fourth signal area 24; (4) The fourth repair unit_B includes: the fourth conductive via of each of the conductive via groups 0 to 5 in the third signal area 23, namely D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the third signal area 23.

[0194] Please see Figure 14C For the third repair unit group_C, the first repair unit_C includes: the first conductive vias of each of the conductive via groups 0 to 5 in the third signal area 23, namely D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, and D0 / 5 in the third signal area 23; (2) the second repair unit_C includes: the second conductive vias of each of the conductive via groups 0 to 5 in the fourth signal area 24, namely D1 / 0, D1 / 1, D1 / 2, D1 / 3, and D1 / 4 in the fourth signal area 24. (3) The third repair unit_C includes: the third conductive via of each of the conductive via groups 0 to 5 in the first signal area 21, namely D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, and D2 / 5 in the first signal area 21; (4) The fourth repair unit_C includes: the fourth conductive via of each of the conductive via groups 0 to 5 in the second signal area 22, namely D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, and D3 / 5 in the second signal area 22.

[0195] Please see Figure 14DFor the fourth repair unit group D, the first repair unit therein includes: the first conductive via of each of the conductive via groups 0~5 in the fourth signal area 24, i.e. D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the fourth signal area 24; (2) the second repair unit D therein includes: the second conductive via of each of the conductive via groups 0~5 in the third signal area 23, i.e. D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the third signal area 23; (3) the fourth repair unit D therein includes: the third conductive via of each of the conductive via groups 0~5 in the second signal area 22, i.e. D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the second signal area 22; and the fourth repair unit D therein includes: the fourth conductive via of each of the conductive via groups 0~5 in the first signal area 21, i.e. D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the first signal area 21.

[0196] The following provides an example of preset switching direction for better understanding of the foregoing description, but the following example is not the only solution.

[0197] Assuming that the conductive vias in the conductive via group 0 of all signal areas are normal conductive vias, please refer to Figure 14A Figure 14D , the preset switching direction of the conductive vias in the first repair unit is: the first conductive via in the conductive via group 2 is allowed to switch to the first conductive via in the conductive via group 3 in the same signal area, the first conductive via in the conductive via group 3 is allowed to switch to the first conductive via in the conductive via group 4 in the same signal area, the first conductive via in the conductive via group 4 is allowed to switch to the first conductive via in the conductive via group 1 in the same signal area, the first conductive via in the conductive via group 1 is allowed to switch to the first conductive via in the conductive via group 0 in the same signal area, and the first conductive via in the conductive via group 0 is allowed to switch to the first conductive via in the conductive via group 5 in the same signal area.

[0198] That is, please refer to Figure 14A , the preset switching direction of the conductive vias in the first repair unit A is: D0 / 2——D0 / 3——D0 / 4——D0 / 1——D0 / 0——D0 / 5 in the first signal area 21; please refer to Figure 14B , the preset switching direction of the conductive vias in the first repair unit B is: D0 / 2——D0 / 3——D0 / 4——D0 / 1——D0 / 0——D0 / 5 in the second signal area 22; please refer to Figure 14C ​, the preset switching direction of the conductive via in the first repair unit C is: D0 / 2—D0 / 3—D0 / 4—D0 / 1—D0 / 0—D0 / 5 in the third signal area 23; please refer to Figure 14D , the preset switching direction of the conductive via in the first repair unit D is: D0 / 2—D0 / 3—D0 / 4—D0 / 1—D0 / 0—D0 / 5 in the fourth signal area 24.

[0199] The following is a specific description of a signal switching related circuit with a repair ratio of 4:2 of the number of normal conductive vias: redundant conductive vias. Take the first repair unit A of the first repair unit group as an example, please refer to Figure 14A , D0 / 2, D0 / 3, D0 / 4 are connected to the first signal selection circuit 100, and the first signal selection circuit 100 connects D0 / 2 with the internal circuit of the logic circuit 10; D0 / 3, D0 / 4, D0 / 1 are connected to the second signal selection circuit 100, and the second signal selection circuit 100 connects D0 / 3 with the internal circuit of the logic circuit 10; D0 / 4, D0 / 1, D0 / 0 are connected to the third signal selection circuit 100, and the third signal selection circuit 100 connects D0 / 3 with the internal circuit of the logic circuit 10, D0 / 1, D0 / 0, D0 / 5 are connected to the fourth signal selection circuit 100, and the fourth signal selection circuit 100 connects D0 / 1 with the internal circuit of the logic circuit 10; then, if D0 / 2 is damaged, the first signal selection circuit 100 connects D0 / 3 with the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 2 will be transmitted by D0 / 3; at the same time, the second signal selection circuit 100 connects D0 / 4 with the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 3 will be transmitted by D0 / 4, the third signal selection circuit 100 connects D0 / 1 with the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 4 will be transmitted by D0 / 1, at the same time, the fourth signal selection circuit 100 connects D0 / 0 with the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 4 will be transmitted by D0 / 0. The remaining repair units please refer to the understanding.

[0200] Similarly, for the storage chip 30, only the conductive via in the first repair unit (i.e. the conductive via filled with the pure white pattern) is connected with the corresponding signal selection circuit 100; similarly, for the second repair unit to the fourth repair unit, whether the conductive via therein is a normal conductive via or a redundant conductive via is not connected to the storage chip 30, so the switching of the conductive via transmitting the signal in the repair unit of the storage chip is only followed by the switching of the conductive via transmitting the signal in the logic chip 10, and the storage chip 30 is actually unaware, so the present embodiment only emphasizes the preset switching direction of the first repair unit.

[0201] The present embodiment of the present disclosure provides a storage chip 30, wherein the conductive via in each channel signal region is symmetrical about a first axis AA' and symmetrical about a second axis BB', and the switching direction of the repair unit further composed of the conductive via also follows the symmetry principle. The above storage chip not only has smaller parasitic capacitance and parasitic resistance when forming a chip stacking structure, but also realizes a face-to-face stacking mode; at the same time, the present embodiment of the present disclosure also provides a related mechanism for redundancy repair under the structure.

[0202] In another embodiment of the present disclosure, see Figure 15 which shows a schematic diagram of the composition structure of a chip stacking structure 40 provided by the present embodiment of the present disclosure. As Figure 15 indicated, the chip stacking structure 40 includes the aforementioned logic chip 10 and at least one stacking unit, and the logic chip 10 and the at least one stacking unit are stacked in sequence along a third direction; each stacking unit includes a first storage chip 31, a second storage chip 32, a third storage chip 33 and a fourth storage chip 34 stacked along the third direction; the structure of the logic chip 10 and the first storage chip 31, the second storage chip 32, the third storage chip 33 and the fourth storage chip 34 are all the aforementioned storage chip 30. The third direction is perpendicular to the top surface of each chip.

[0203] For each stacking unit, the first storage chip 31 and the second storage chip 32 are stacked in a face-to-face manner, the second storage chip 32 and the third storage chip 33 are stacked in a back-to-back manner, and the third storage chip 33 and the fourth storage chip 34 are stacked in a face-to-face manner; the first storage chip 31 in the first stacking unit and the logic chip 10 are stacked in a back-to-face manner, or the first storage chip 31 in the first stacking unit and the logic chip 10 are stacked in a back-to-back manner.

[0204] In the embodiments of the present disclosure, face-to-face stacking refers to that the top surfaces of the two chips are approximately aligned along the third direction, and the center points, the first axis AA' and the second axis BB' of the top surfaces of the two chips are aligned along the third direction; back-to-back stacking refers to that the top surfaces of the two chips are approximately aligned along the third direction; face-to-back stacking refers to that the top surface of one chip is approximately aligned with the bottom surface of the other chip along the third direction. When the logic chip or the storage chip is not specified, the "chip" can refer to the logic chip or the storage chip.

[0205] It should be noted that, in one possibility, for the two chips connected face-to-face, the bonding surfaces (positions where the conductive vias are aligned along the third direction) of the two chips are electrically connected through a hyperbonding structure (also referred to as a bonding column); for the two chips connected back-to-back or for the two chips connected face-to-back, the bonding surfaces (positions where the conductive vias are aligned along the third direction) of the two chips are electrically connected through a conductive bump (also referred to as a micro bump).

[0206] In another possibility, for the two chips connected face-to-face, or for the two chips connected back-to-back, or for the two chips connected face-to-back, the bonding surfaces (positions where the conductive vias are aligned along the third direction) of the two chips are connected through a hyperbonding structure.

[0207] In yet another possibility, for the two chips connected face-to-face, or for the two chips connected back-to-back, or for the two chips connected face-to-back, the bonding surfaces (positions where the conductive vias are aligned along the third direction) of the two chips are connected through a conductive bump.

[0208] Here, the above chip can refer to the logic chip 10 or the storage chip 30.

[0209] It should be noted that, compared with the conductive bump process, the face-to-face connection using the hyperbonding process can make the adjacent storage chips fit more closely, with substantially no gap, thereby greatly reducing the height of the chip stacking structure, which is one of the advantages of face-to-face stacking. Of course, the two storage chips connected back-to-back can also be connected through a hyperbonding structure, but the connection performance is weaker than that of the connection through the conductive bump process. In this way, in the embodiments of the present disclosure, the chip stacking structure supports face-to-face stacking and has better performance.

[0210] As aforementioned, the logic chip 10 and each memory chip have n repair unit groups, and the n repair unit groups in the logic chip 10, the n repair unit groups in each first memory chip 31, the n repair unit groups in each second memory chip 32, the n repair unit groups in each third memory chip 33, and the n repair unit groups in each fourth memory chip 34 correspond to each other and are aligned along the third direction, so that the logic chip 10 and each memory chip will perform the signal switching operation synchronously when a certain conductive via is damaged.

[0211] In some embodiments, the logic chip 10 comprises m channel signal regions arranged along a first direction, each memory chip has m channels arranged along the first direction, and each channel comprises a first memory array region, a channel signal region, and a second memory array region arranged along a second direction in sequence; the first direction, the second direction, and the third direction are perpendicular to each other, and the first direction and the second direction are parallel to the top surface of each chip.

[0212] In particular, Figure 15 Two second directions are shown in the middle because, for the sake of clarity, the perspective angles of the adjacent two chips are different, so as to correspond to one second direction respectively.

[0213] It should be understood that the logic chip 10 or each memory chip can be divided into a high-bit transmission region and a low-bit transmission region, and the arrows in the subsequent drawings are located in the high-bit transmission region of the chip. In particular, the high-bit transmission region and the low-bit transmission region in the embodiments of the present disclosure are only to distinguish the two regions of the memory chip, and do not have additional other restrictions, and have nothing to do with the commonly said high-bit data and low-bit data in the data transmission process.

[0214] In the first specific embodiment, please refer to Figure 17A In the case that the logic chip 10 and the first memory chip 31 are stacked in a back-to-back manner, and the first axis AA' of the logic chip 10 and each of the memory chips 30 extends along the first direction (i.e., the second axis AA' divides the chip into a high-bit transmission region and a low-bit transmission region), the high-bit transmission region of the logic chip 10, the high-bit transmission region of the first memory chip 31, the low-bit transmission region of the second memory chip 32, the low-bit transmission region of the third memory chip 33, and the high-bit transmission region of the fourth memory chip 34 are aligned along the third direction; the low-bit transmission region of the logic chip 10, the low-bit transmission region of the first memory chip 31, the high-bit transmission region of the second memory chip 32, the high-bit transmission region of the third memory chip 33, and the low-bit transmission region of the fourth memory chip 34 are aligned along the third direction.

[0215] The channel signal regions of the respective chips have the following alignment relationship: the m-i th channel signal region in the logic chip 10 is aligned with the channel signal region in the i+1 th channel in the first memory chip 31, the channel signal region in the i+1 th channel in the second memory chip 32, the channel signal region in the m-i th channel in the third memory chip 33, and the channel signal region in the m-i th channel in the fourth memory chip 34 along the third direction; wherein i is a natural number less than m.

[0216] Figure 17A Taking m=4 as an example, at this time:

[0217] (1) the fourth channel signal region 14 in the logic chip 10, the channel signal region 11 in the first channel in the first memory chip 31, the channel signal region 11 in the first channel in the second memory chip 32, the channel signal region 14 in the fourth channel in the third memory chip 33, and the channel signal region 14 in the fourth channel in the fourth memory chip 34 are aligned along the third direction;

[0218] (2) the third channel signal region 13 in the logic chip 10, the channel signal region 12 in the second channel in the first memory chip 31, the channel signal region 12 in the second channel in the second memory chip 32, the channel signal region 13 in the third channel in the third memory chip 33, and the channel signal region 13 in the third channel in the fourth memory chip 34 are aligned along the third direction;

[0219] (3) the second channel signal region 12 in the logic chip 10, the channel signal region 13 in the third channel in the first memory chip 31, the channel signal region 13 in the third channel in the second memory chip 32, the channel signal region 12 in the second channel in the third memory chip 33, and the channel signal region 12 in the second channel in the fourth memory chip 34 are aligned along the third direction;

[0220] (4) the first channel signal region 11 in the logic chip 10, the channel signal region 14 in the fourth channel in the first memory chip 31, the channel signal region 14 in the fourth channel in the second memory chip 32, the channel signal region 11 in the first channel in the third memory chip 33, and the channel signal region 11 in the first channel in the fourth memory chip 34 are aligned along the third direction.

[0221] In the second specific embodiment, please refer to Figure 18A(illustrated by taking m=4 as an example), in the case where the logic chip 10 and the first memory chip 31 are stacked in a back-to-back manner, and the second axis BB' of the logic chip 10 and each memory chip respectively extends along the first direction (i.e. the second axis BB' divides the chip into a high transmission region and a low transmission region), the low transmission region of the logic chip 10, the high transmission region of the first memory chip 31, the high transmission region of the second memory chip 32, the low transmission region of the third memory chip 33, and the low transmission region of the fourth memory chip 34 are aligned along the third direction; the high transmission region of the logic chip 10, the low transmission region of the first memory chip 31, the low transmission region of the second memory chip 32, the high transmission region of the third memory chip 33, and the high transmission region of the fourth memory chip 34 are aligned along the third direction.

[0222] Specifically, the channel signal regions of each chip have the following symmetry relationship: the i+1th channel signal region in the logic chip 10 is aligned along the third direction with the channel signal region in the i+1th channel in the first memory chip 31, the channel signal region in the m-i channel in the second memory chip 32, the channel signal region in the m-i channel in the third memory chip 33, and the channel signal region in the i+1th channel in the fourth memory chip 34; wherein i is a natural number less than m.

[0223] Figure 18A Illustrated by taking m=4 as an example, at this time:

[0224] (1) the first channel signal region 11 in the logic chip 10, the channel signal region 11 in the first channel in the first memory chip 31, the channel signal region 14 in the fourth channel in the second memory chip 32, the channel signal region 14 in the fourth channel in the third memory chip 33, and the channel signal region 11 in the first channel in the fourth memory chip 34 are aligned along the third direction;

[0225] (2) the second channel signal region 12 in the logic chip 10, the channel signal region 12 in the second channel in the first memory chip 31, the channel signal region 13 in the third channel in the second memory chip 32, the channel signal region 13 in the third channel in the third memory chip 33, and the channel signal region 12 in the second channel in the fourth memory chip 34 are aligned along the third direction;

[0226] (3) the third channel signal region 13 in the logic chip 10, the channel signal region 13 in the third channel in the first memory chip 31, the channel signal region 12 in the second channel in the second memory chip 32, the channel signal region 12 in the second channel in the third memory chip 33, and the channel signal region 13 in the third channel in the fourth memory chip 34 are aligned along the third direction;

[0227] (4) The fourth channel signal area 14 in the logic chip 10, the channel signal area 14 in the fourth channel in the first memory chip 31, the channel signal area 11 in the first channel in the second memory chip 32, the channel signal area 11 in the first channel in the third memory chip 33, and the channel signal area 14 in the fourth channel in the fourth memory chip 34 are aligned along the third direction.

[0228] In brief, for Figures 17A-18B , the logic chip 10 and the fourth memory chip 34 are arranged in the same way.

[0229] It is also necessary to point out that the channel signal area in each channel of the memory chip 30 and the logic chip 31 is divided into 2x2 signal areas arranged in an array. Please refer to Figure 17B or Figure 18B , for the plurality of channel signal areas aligned along the third direction, the following features are provided:

[0230] (1) The fourth signal area 24 belonging to the logic chip 10, the first signal area 21 belonging to the first memory chip 31, the second signal area 22 belonging to the second memory chip 32, the third signal area 23 belonging to the third memory chip 33, and the fourth signal area 24 belonging to the fourth memory chip 34 are aligned along the third direction;

[0231] (2) The third signal area 23 belonging to the logic chip 10, the second signal area 22 belonging to the first memory chip 31, the first signal area 21 belonging to the second memory chip 32, the fourth signal area 24 belonging to the third memory chip 33, and the third signal area 23 belonging to the fourth memory chip 34 are aligned along the third direction;

[0232] (3) The second signal area 22 belonging to the logic chip 10, the third signal area 23 belonging to the first memory chip 31, the fourth signal area 24 belonging to the second memory chip 32, the first signal area 21 belonging to the third memory chip 33, and the second signal area 22 belonging to the fourth memory chip 34 are aligned along the third direction;

[0233] (4) The first signal area 21 belonging to the logic chip 10, the fourth signal area 24 belonging to the first memory chip 31, the third signal area 23 belonging to the second memory chip 32, the second signal area 22 belonging to the third memory chip 33, and the first signal area 21 belonging to the fourth memory chip 34 are aligned along the third direction.

[0234] In some embodiments, each signal region includes n groups of conductive vias with the same distribution position, in each channel signal region, the conductive via group of the first signal region and the conductive via group of the second signal region correspond one by one and are symmetric about the first axis, the conductive via group of the third signal region and the conductive via group of the fourth signal region correspond one by one and are symmetric about the first axis, and the conductive via group of the first signal region and the conductive via group of the fourth signal region correspond one by one and are symmetric about the second axis. Meanwhile, the conductive via groups in different channel signal regions correspond one by one and have the same distribution position (relative to the center of the signal region); each conductive via group includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via.

[0235] Please refer to Figure 17B or Figure 18B , for a plurality of signal regions aligned along the third direction:

[0236] (1) the fourth conductive via D3 belonging to the logic chip 10, the first conductive via D0 belonging to the first storage chip 31, the second conductive via D1 belonging to the second storage chip 32, the third conductive via D2 belonging to the third storage chip 33, and the fourth conductive via D3 belonging to the fourth storage chip 34 are aligned along the third direction;

[0237] (2) the third conductive via D2 belonging to the logic chip 10, the second conductive via D1 belonging to the first storage chip 31, the first conductive via D0 belonging to the second storage chip 32, the fourth conductive via D3 belonging to the third storage chip 33, and the third conductive via D2 belonging to the fourth storage chip 34 are aligned along the third direction;

[0238] (3) the second conductive via D1 belonging to the logic chip 10, the third conductive via D2 belonging to the first storage chip 31, the fourth conductive via D3 belonging to the second storage chip 32, the first conductive via D0 belonging to the third storage chip 33, and the second conductive via D1 belonging to the fourth storage chip 34 are aligned along the third direction;

[0239] (4) the first conductive via D0 belonging to the logic chip 10, the fourth conductive via D3 belonging to the first storage chip 31, the third conductive via D2 belonging to the second storage chip 32, the second conductive via D1 belonging to the third storage chip 33, and the first conductive via D0 belonging to the fourth storage chip 34 are aligned along the third direction; wherein the plurality of conductive vias aligned along the third direction are coupled to form a signal transmission channel.

[0240] Please refer to Figure 16A , when stacking according to the first and second specific embodiments, the repair units of the respective chips have the following relationship:

[0241] (a) one fourth repair unit in the logic chip 10, one first repair unit in the first memory chip 31, one second repair unit in the second memory chip 32, one third repair unit in the third memory chip 33, and one fourth repair unit in the fourth memory chip 34 are aligned along the third direction and perform the conductive via switching operation synchronously;

[0242] (b) one third repair unit in the logic chip 10, one second repair unit in the first memory chip 31, one first repair unit in the second memory chip 32, one fourth repair unit in the third memory chip 33, and one third repair unit in the fourth memory chip 34 are aligned along the third direction and perform the conductive via switching operation synchronously;

[0243] (c) one second repair unit in the logic chip 10, one third repair unit in the first memory chip 31, one fourth repair unit in the second memory chip 32, one first repair unit in the third memory chip 33, and one second repair unit in the fourth memory chip 34 are aligned along the third direction and perform the conductive via switching operation synchronously;

[0244] (d) one first repair unit in the logic chip 10, one fourth repair unit in the first memory chip 31, one third repair unit in the second memory chip 32, one second repair unit in the third memory chip 33, and one first repair unit in the fourth memory chip 34 are aligned along the third direction and perform the conductive via switching operation synchronously.

[0245] It should be noted that for the logic chip 10, each repair unit therein is coupled to the internal circuit, i.e. the normal conductive via in each repair unit is electrically connected to the internal circuit of the logic chip 10; but for the memory chip, only the first repair unit is coupled to the internal circuit, i.e. only the normal conductive via in the first repair unit is electrically connected to the internal circuit of the memory chip, and all the conductive vias in the second, third and fourth repair units are isolated from the internal circuit of the logic chip 10.

[0246] Figure 17C The division of the repair unit groups and the stacking manner of the first embodiment are taken as an example to show the schematic diagram of one repair unit group of the logic chip 10 and the symmetry and switching direction of the first repair unit in each corresponding memory chip, and the other repair units are omitted. That is, in the repair unit group of the logic chip 10 and the first memory chip 31, Figure 5 and Figure 11 The division of the repair unit groups and the stacking manner of the first embodiment are taken as an example to show the schematic diagram of one repair unit group of the logic chip 10 and the symmetry and switching direction of the first repair unit in each corresponding memory chip, and the other repair units are omitted. That is, in the repair unit group of the logic chip 10 and the first memory chip 31, Figure 17CIn the middle, the first repair unit, the second repair unit, the third repair unit and the fourth repair unit indicated by the curved arrow in the logic chip 10 are all coupled to the internal circuit; but for the storage chip, only the first repair unit indicated by the curved arrow is coupled to the internal circuit.

[0247] Figure 7 And Figure 13 The chip stack structure formed by the repair unit group of the above has the above characteristics, please understand accordingly.

[0248] In this way, the repair units of the chip stack structure 40 are aligned in the third direction, and have symmetrical switching directions, so that the same switching function can be realized.

[0249] In the third specific embodiment, please refer to Figure 19A (illustrated by taking m=4 as an example), in the case where the logic chip 10 and the first storage chip 31 are stacked in a back-to-back manner, and the first axis AA' of the logic chip 10 and each storage chip respectively extends in the first direction (i.e. the first axis AA' divides the chip into a high transmission area and a low transmission area), the low transmission area of the logic chip 10, the high transmission area of the first storage chip 31, the low transmission area of the second storage chip 32, the low transmission area of the third storage chip 33, and the high transmission area of the fourth storage chip 34 are aligned in the third direction; the high transmission area of the logic chip 10, the low transmission area of the first storage chip 31, the high transmission area of the second storage chip 32, the high transmission area of the third storage chip 33, and the low transmission area of the fourth storage chip 34 are aligned in the third direction.

[0250] Specifically, the channel signal area of each chip has the following symmetrical relationship: the i+1th channel signal area in the logic chip 10 is aligned in the third direction with the channel signal area in the i+1th channel in the first storage chip 31, the channel signal area in the i+1th channel in the second storage chip 32, the channel signal area in the m-i channel in the third storage chip 33, and the channel signal area in the m-i channel in the fourth storage chip 34; where i is a natural number less than m.

[0251] Figure 19A Taking m=4 as an example for illustration, at this time:

[0252] (1) the first channel signal area 11 in the logic chip 10, the channel signal area 11 in the first channel in the first storage chip 31, the channel signal area 11 in the first channel in the second storage chip 32, the channel signal area 14 in the fourth channel in the third storage chip 33, and the channel signal area 14 in the fourth channel in the fourth storage chip 34 are aligned in the third direction;

[0253] (2) the second channel signal area 12 in the logic chip 10, the second channel signal area 12 in the second channel in the first memory chip 31, the second channel signal area 12 in the second channel in the second memory chip 32, the third channel signal area 13 in the third channel in the third memory chip 33, and the third channel signal area 13 in the third channel in the fourth memory chip 34 are aligned along the third direction;

[0254] (3) the third channel signal area 13 in the logic chip 10, the third channel signal area 13 in the third channel in the first memory chip 31, the third channel signal area 13 in the third channel in the second memory chip 32, the second channel signal area 12 in the second channel in the third memory chip 33, and the second channel signal area 12 in the second channel in the fourth memory chip 34 are aligned along the third direction;

[0255] (4) the fourth channel signal area 14 in the logic chip 10, the fourth channel signal area 14 in the fourth channel in the first memory chip 31, the fourth channel signal area 14 in the fourth channel in the second memory chip 32, the first channel signal area 11 in the first channel in the third memory chip 33, and the first channel signal area 11 in the first channel in the fourth memory chip 34 are aligned along the third direction.

[0256] In the fourth specific embodiment, please refer to Figure 20A (in the case of m=4, for example), in the case of m=4 and the logic chip 10 and the first memory chip 31 are stacked in a back-to-back manner, and the second axis BB' of the logic chip 10 and each memory chip respectively extends along the first direction (i.e. the second axis BB' divides the chip into a high transmission area and a low transmission area), the high transmission area of the logic chip 10, the high transmission area of the first memory chip 31, the high transmission area of the second memory chip 32, the low transmission area of the third memory chip 33, and the low transmission area of the fourth memory chip 34 are aligned along the third direction; the low transmission area of the logic chip 10, the low transmission area of the first memory chip 31, the low transmission area of the second memory chip 32, the high transmission area of the third memory chip 33, and the high transmission area of the fourth memory chip 34 are aligned along the third direction.

[0257] Specifically, the channel signal areas of each chip have the following symmetry relationship: the m-i th channel signal area in the logic chip 10 is aligned along the third direction with the i+1 th channel signal area in the first memory chip 31, the m-i th channel signal area in the second memory chip 32, the m-i th channel signal area in the third memory chip 33, and the i+1 th channel signal area in the fourth memory chip 34; wherein i is a natural number less than m.

[0258] (1) The fourth channel signal area 14 in the logic chip 10, the channel signal area 11 in the first channel in the first memory chip 31, the channel signal area 14 in the fourth channel in the second memory chip 32, the channel signal area 14 in the fourth channel in the third memory chip 33, and the channel signal area 11 in the first channel in the fourth memory chip 34 are aligned in the third direction;

[0259] (2) The third channel signal area 13 in the logic chip 10, the channel signal area 12 in the second channel in the first memory chip 31, the channel signal area 13 in the third channel in the second memory chip 32, the channel signal area 13 in the third channel in the third memory chip 33, and the channel signal area 12 in the second channel in the fourth memory chip 34 are aligned in the third direction;

[0260] (3) The second channel signal area 12 in the logic chip 10, the channel signal area 13 in the third channel in the first memory chip 31, the channel signal area 12 in the second channel in the second memory chip 32, the channel signal area 12 in the second channel in the third memory chip 33, and the channel signal area 13 in the third channel in the fourth memory chip 34 are aligned in the third direction;

[0261] (4) The first channel signal area 11 in the logic chip 10, the channel signal area 14 in the fourth channel in the first memory chip 31, the channel signal area 11 in the first channel in the second memory chip 32, the channel signal area 11 in the first channel in the third memory chip 33, and the channel signal area 14 in the fourth channel in the fourth memory chip 34 are aligned in the third direction.

[0262] In short, for Figures 19A-20B , the logic chip 10 and the second memory chip 32 are arranged in the same way.

[0263] In some embodiments, please refer to Figure 19B and Figure 20B , the channel signal areas in each channel of the memory chips and the logic chip 10 are divided into 2x2 signal areas arranged in an array. Please refer to Figure 19B and Figure 19B , for the plurality of channel signal areas aligned in the third direction:

[0264] (1) The second signal area 22 belonging to the logic chip 10, the first signal area 21 belonging to the first memory chip 31, the second signal area 22 belonging to the second memory chip 32, the third signal area 23 belonging to the third memory chip 33, and the fourth signal area 24 belonging to the fourth memory chip 34 are aligned in the third direction;

[0265] (2) The first signal area 21 belonging to the logic chip 10, the second signal area 22 belonging to the first memory chip 31, the first signal area 21 belonging to the second memory chip 32, the fourth signal area 24 belonging to the third memory chip 33, and the third signal area 23 belonging to the fourth memory chip 34 are aligned along the third direction;

[0266] (3) The fourth signal area 24 belonging to the logic chip 10, the third signal area 23 belonging to the first memory chip 31, the fourth signal area 24 belonging to the second memory chip 32, the first signal area 21 belonging to the third memory chip 33, and the second signal area 22 belonging to the fourth memory chip 34 are aligned along the third direction;

[0267] (4) The third signal area 23 belonging to the logic chip 10, the fourth signal area 24 belonging to the first memory chip 31, the third signal area 23 belonging to the second memory chip 32, the second signal area 22 belonging to the third memory chip 33, and the first signal area 21 belonging to the fourth memory chip 34 are aligned along the third direction.

[0268] Please refer to Figure 19B or Figure 19B Each signal area of the memory chips and the logic chip 10 includes n groups of conductive vias with the same distribution position, and each group of conductive vias includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via.

[0269] For the plurality of signal areas aligned along the third direction:

[0270] (1) The second conductive via D1 belonging to the logic chip 10, the first conductive via D0 belonging to the first memory chip 31, the second conductive via D1 belonging to the second memory chip 32, the third conductive via D2 belonging to the third memory chip 33, and the fourth conductive via D3 belonging to the fourth memory chip 34 are aligned along the third direction;

[0271] (2) The first conductive via D0 belonging to the logic chip 10, the second conductive via D1 belonging to the first memory chip 31, the first conductive via D0 belonging to the second memory chip 32, the fourth conductive via D3 belonging to the third memory chip 33, and the third conductive via D2 belonging to the fourth memory chip 34 are aligned along the third direction;

[0272] (3) The fourth conductive via D3 belonging to the logic chip 10, the third conductive via D2 belonging to the first memory chip 31, the fourth conductive via D3 belonging to the second memory chip 32, the first conductive via D0 belonging to the third memory chip 33, and the second conductive via D1 belonging to the fourth memory chip 34 are aligned along the third direction;

[0273] (4) the third conductive via D2 belonging to the logic chip 10, the fourth conductive via D3 belonging to the first memory chip 31, the third conductive via D2 belonging to the second memory chip 32, the second conductive via D1 belonging to the third memory chip 33, and the first conductive via DO belonging to the fourth memory chip 34 are aligned along the third direction;

[0274] The plurality of conductive vias aligned along the third direction are coupled to form a signal transmission channel.

[0275] Referring to Figure 16B For the third and fourth specific embodiments, the repair units of the respective chips have the following relationships:

[0276] (a) a second repair unit in the logic chip 10, a first repair unit in the first memory chip 31, a second repair unit in the second memory chip 32, a third repair unit in the third memory chip 33, and a fourth repair unit in the fourth memory chip 34 are aligned along the third direction and perform the conductive via switching operation synchronously;

[0277] (b) a first repair unit in the logic chip 10, a second repair unit in the first memory chip 31, a first repair unit in the second memory chip 32, a fourth repair unit in the third memory chip 33, and a third repair unit in the fourth memory chip 34 are aligned along the third direction and perform the conductive via switching operation synchronously;

[0278] (c) a fourth repair unit in the logic chip 10, a third repair unit in the first memory chip 31, a fourth repair unit in the second memory chip 32, a first repair unit in the third memory chip 33, and a second repair unit in the fourth memory chip 34 are aligned along the third direction and perform the conductive via switching operation synchronously;

[0279] (d) a third repair unit in the logic chip 10, a fourth repair unit in the first memory chip 31, a third repair unit in the second memory chip 32, a second repair unit in the third memory chip 33, and a first repair unit in the fourth memory chip 34 are aligned along the third direction and perform the conductive via switching operation synchronously.

[0280] Similarly, the repair units of the chip stack structure 40 are aligned along the third direction and have symmetrical switching directions, so that the same switching function can be achieved.

[0281] To facilitate understanding of the signal switching process of the chip stack structure 40, the signal switching is described below for specific working scenarios: Figure 5 The logic chip 10 and Figure 11The storage chip 30 provided by the present application is formed by stacking the storage chips 30 through Figure 17A The chip stack structure 40 is formed by stacking the storage chips 30 through Figure 21 The chip stack structure 40 is formed by stacking the storage chips 30 through

[0282] Figures 21-22B The chip stack structure 40 is formed by stacking the storage chips 30 through

[0283] The chip stack structure 40 is formed by stacking the storage chips 30 through Figure 21 The following exemplary working scenarios are provided:

[0284] The chip stack structure 40 is formed by stacking the storage chips 30 through

[0285] The chip stack structure 40 is formed by stacking the storage chips 30 through Figure 22AAs shown, D3 / 0 in the fourth signal area in the logic chip 10, D0 / 0 in the first signal area in the first memory chip 31, D1 / 0 in the second signal area in the second memory chip 32, D2 / 0 in the third signal area in the third memory chip 33, and D3 / 0 in the fourth signal area in the fourth memory chip 34 are connected to form a signal channel (the first normal signal channel); at the same time, D3 / 1 in the fourth signal area in the logic chip 10, D0 / 1 in the first signal area in the first memory chip 31, D1 / 1 in the second signal area in the second memory chip 32, D2 / 1 in the third signal area in the third memory chip 33, and D3 / 1 in the fourth signal area in the fourth memory chip 34 are connected to form a signal channel (the second normal signal channel), and the above are all normal conductive vias; at the same time, D3 / 2 in the fourth signal area in the logic chip 10, D0 / 2 in the first signal area in the first memory chip 31, D1 / 2 in the second signal area in the second memory chip 32, D2 / 2 in the third signal area in the third memory chip 33, and D3 / 2 in the fourth signal area in the fourth memory chip 34 are connected to form a signal channel (the first redundant signal channel);

[0286] When all the conductive vias are normal, please refer to Figure 22B , the signal selection circuit 100a in the logic chip 10 connects D3 / 0 with the internal circuit, and the signal selection circuit 100c in the first memory chip 31 connects D0 / 0 with the internal circuit, so that the first normal signal channel is used to transmit an effective signal (denoted as signal1), and the logic chip 10 can send / receive the effective signal signal1 from D3 / 0 through the signal selection circuit 100a, and the first memory chip 31 can receive / send the effective signal signal1 from D0 / 0 through the signal selection circuit 100c;

[0287] Similarly, the signal selection circuit 100b in the logic chip 10 connects D3 / 1 with the internal circuit, and the second normal signal channel sends / receives another effective signal (denoted as signal2), and the signal selection circuit 100d in the first memory chip 31 connects D0 / 1 with the internal circuit, so as to receive / send the effective signal signal2;

[0288] Please refer to Figure 7, assuming that any one of the conductive vias in the first normal signal channel is damaged, i.e. the corresponding first normal signal channel cannot be used, at this time, the redundant signal channel is used for repair, then for the logic chip 10, the signal selection circuit 100a connects D0 / 1 with the internal circuit, which is used to replace the original D0 / 0 to send / receive the effective signal signal1; the signal selection circuit 100b connects D0 / 2 with the internal circuit, which is used to replace the original D0 / 1 to send / receive the effective signal signal2; at the same time, for the first storage chip 31, the signal selection circuit 100c connects D0 / 1 with the internal circuit, which is used to replace the original D0 / 0 to receive / send the effective signal signal1; the signal selection circuit 100d connects D0 / 2 with the internal circuit, which is used to replace the original D0 / 1 to receive / send the effective signal signal12; thereby completing the switching work of the first normal signal channel to the second normal signal channel and the second normal signal channel to the first redundant signal channel.

[0289] The following will be described in detail for the following specific working scenarios: using Figure 13 The logic chip 10 and Figure 17A The storage chip 30 provided by the present application are stacked in the form of Figure 23 The chip stack structure 40, assuming that each repair unit is a 4:2 repair. Please refer to Figures 23-24B , which provides a signal transmission schematic diagram of the chip stack structure 40.

[0290] Please refer to Figure 23 , the following exemplary working scenarios are provided:

[0291] Take the fourth repair unit composed of D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the fourth signal area of the logic chip 10, the first repair unit composed of D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the first signal area of the first storage chip 31, the second repair unit composed of D1 / 0, D1 / 1, D1 / 2, D1 / 3, D0 / 4, D1 / 5 in the second signal area of the second storage chip 32, the third repair unit composed of D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the third signal area of the third storage chip 33, and the fourth repair unit composed of D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the fourth signal area of the fourth storage chip 34 as examples to illustrate the specific process of signal switching.

[0292] As Figure 24AAs shown, D3 / 2 in the fourth signal area of the logic chip 10, D0 / 2 in the first signal area of the first memory chip 31, D1 / 2 in the second signal area of the second memory chip 32, D2 / 2 in the third signal area of the third memory chip 33, and D3 / 2 in the fourth signal area of the fourth memory chip 34 are connected to form a signal channel (the first normal signal channel); D3 / 3 in the fourth signal area of the logic chip 10, D0 / 3 in the first signal area of the first memory chip 31, D1 / 3 in the second signal area of the second memory chip 32, D2 / 3 in the third signal area of the third memory chip 33, and D3 / 3 in the fourth signal area of the fourth memory chip 34 are connected to form a signal channel (the second normal signal channel); D3 / 4 in the fourth signal area of the logic chip 10, D0 / 4 in the first signal area of the first memory chip 31, D1 / 4 in the second signal area of the second memory chip 32, D2 / 4 in the third signal area of the third memory chip 33, and D3 / 4 in the fourth signal area of the fourth memory chip 34 are connected to form a signal channel (the third normal signal channel); D3 / 1 in the fourth signal area of the logic chip 10, D0 / 1 in the first signal area of the first memory chip 31, D1 / 1 in the second signal area of the second memory chip 32, D2 / 1 in the third signal area of the third memory chip 33, and D3 / 0 in the fourth signal area of the fourth memory chip 34 are connected to form a signal channel (the fourth normal signal channel); and all the above are normal conductive vias;

[0293] Meanwhile, D3 / 0 in the fourth signal area of the logic chip 10, D0 / 0 in the first signal area of the first memory chip 31, D1 / 0 in the second signal area of the second memory chip 32, D2 / 0 in the third signal area of the third memory chip 33, and D3 / 0 in the fourth signal area of the fourth memory chip 34 are connected to form a signal channel (the first redundant signal channel); D3 / 5 in the fourth signal area of the logic chip 10, D0 / 5 in the first signal area of the first memory chip 31, D1 / 5 in the second signal area of the second memory chip 32, D2 / 5 in the third signal area of the third memory chip 33, and D3 / 5 in the fourth signal area of the fourth memory chip 34 are connected to form a signal channel (the second redundant signal channel);

[0294] In the case that all the conductive vias are normal, please refer to Figure 24B, the signal selection circuit 100A in the logic chip 10 connects D3 / 2 with the internal circuit, the signal selection circuit 100E in the first memory chip 31 connects D0 / 2 with the internal circuit, thus the first normal signal channel is used to transmit the valid signal (marked as signal1), specifically, the logic chip 10 can transmit / receive the valid signal signal1 from D2 / 6 through the signal selection circuit 100A, the first memory chip 31 can receive / transmit the valid signal signal1 from D1 / 1 through the signal selection circuit 100E;

[0295] Similarly, the signal selection circuit 100B in the logic chip 10 connects D3 / 3 with the internal circuit, the second normal signal channel transmits / receives another valid signal (marked as signal2), the signal selection circuit 100F in the first memory chip 31 connects D0 / 3 with the internal circuit, thus receives / transmits the valid signal signal2; the signal selection circuit 100C in the logic chip 10 connects D3 / 4 with the internal circuit, the second normal signal channel transmits / receives another valid signal (marked as signal3), the signal selection circuit 100G in the first memory chip 31 connects D0 / 4 with the internal circuit, thus receives / transmits the valid signal signal3; the signal selection circuit 100D in the logic chip 10 connects D3 / 4 with the internal circuit, the second normal signal channel transmits / receives another valid signal (marked as signal4), the signal selection circuit 100H in the first memory chip 31 connects D0 / 4 with the internal circuit, thus receives / transmits the valid signal signal4.

[0296] Please refer to Figure 17B , assuming that the first normal signal channel cannot be used, at this time, the redundant signal channel needs to be used for repair, then for the logic chip 10, the signal selection circuit 100A connects D3 / 3 with the internal circuit, which is used to replace the original D3 / 2 to transmit / receive the valid signal signal1; the signal selection circuit 100B connects D3 / 4 with the internal circuit, which is used to replace the original D3 / 3 to transmit / receive the valid signal signal2; the signal selection circuit 100C connects D3 / 1 with the internal circuit, which is used to replace the original D3 / 4 to transmit / receive the valid signal signal3; the signal selection circuit 100D connects D3 / 0 with the internal circuit, which is used to replace the original D3 / 1 to transmit / receive the valid signal signal4;

[0297] Meanwhile, for the first memory chip 31, the signal selection circuit 100E connects D0 / 3 with the internal circuit, for receiving / transmitting the effective signal signal1 instead of the original D1 / 2; the signal selection circuit 100F connects D0 / 4 with the internal circuit, for receiving / transmitting the effective signal signal12 instead of the original D0 / 3; the signal selection circuit 100G connects D0 / 1 with the internal circuit, for receiving / transmitting the effective signal signal13 instead of the original D0 / 4; the signal selection circuit 100H connects D0 / 0 with the internal circuit, for receiving / transmitting the effective signal signal15 instead of the original D0 / 1;

[0298] Thus, the switching work from the first normal signal channel to the second normal signal channel, from the second normal signal channel to the third normal signal channel, from the third normal signal channel to the fourth normal signal channel, and from the fourth normal signal channel to the first redundant signal channel is completed.

[0299] Meanwhile, from Figure 18B , Figure 19B , Figure 20B , Figures 21-24B , Figure 17B It can be seen that, for the chip stacking structure 40, the signal transmission path from bottom to top will be similar to the following form: please refer to Figure 18B , Figure 19B , the fourth conductive via D3 in the logic chip 10 (or the fourth conductive via D1 in the logic chip 10, please refer to Figure 20B , Figure 2B ) - the first conductive via D0 in the first memory chip 31 - the second conductive via D1 in the second memory chip 32 - the third conductive via D2 in the third memory chip 33 - the fourth conductive via D3 in the fourth memory chip 34 …” for transmission. That is, for the chip stacking structure 40, the conductive vias therein are still in a straight connection configuration from a physical point of view, but from the absolute position of the conductive vias on the active surface, the conductive vias therein can be regarded as a functional rotation configuration, that is, through the physical straight connection configuration, a signal transmission effect similar to Figure 2B (the rotation transmission effect of conductive via D0 - conductive via D1 - conductive via D2 - conductive via D3 …”) is achieved. Simply put, Figure 25 the chip stacking structure 40 in needs a physical spiral structure, which necessarily has a horizontal interconnection structure, while the chip stacking structure 40 in the embodiment of the present disclosure is a straight connection structure in physics, without a horizontal interconnection structure, the parasitic resistance is greatly reduced, and the transmission speed and transmission performance are greatly improved.

[0300] In still another embodiment of the present disclosure, please refer to Figure 25Fig. 1 shows a schematic diagram of a chip stack structure according to an embodiment of the present disclosure. ​ As shown, the memory 70 includes the chip stack structure 40 of the foregoing embodiment.

[0301] In some embodiments, the chip stack structure 40 can be applied to the memory 70. The memory 70 can be, for example, a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), a Synchronous Dynamic Random Access Memory (SDRAM), a Double Data Rate SDRAM (DDR SDRAM), or the like, which is not limited herein.

[0302] In the embodiments of the present disclosure, the chip area of the memory 70 can be reduced, and the chip manufacturing cost can be reduced.

[0303] The details not disclosed in the embodiments of the present disclosure can be understood with reference to the foregoing description of the embodiments.

[0304] The above merely describes the preferred embodiments of the present disclosure, but is not intended to limit the protection scope of the present disclosure.

[0305] It should be noted that, in the present disclosure, the terms "comprising", "containing" or any other variants thereof are intended to cover the non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes the elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0306] The above-mentioned sequence numbers of the embodiments of the present disclosure are only for description, and do not represent the advantages or disadvantages of the embodiments.

[0307] The methods disclosed in several method embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new method embodiments.

[0308] The features disclosed in several product embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new product embodiments.

[0309] The features disclosed in several method or device embodiments of the present disclosure can be arbitrarily combined, without conflict, to form new method embodiments or device embodiments.

[0310] The above description is merely a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A logic chip, characterized by, The logic chip comprises m channel signal regions arranged in sequence along a first direction, the logic chip has a chip axis extending along a second direction and passing through the center of the logic chip, and m channel signal regions are symmetrical about the chip axis; m is a positive integer; Each channel signal region has a first axis and a second axis, the first axis extends along the first direction or the second direction, and the second axis is perpendicular to the first axis and intersects at the center of the channel signal region; Each channel signal region is penetrated by a plurality of conductive vias along a third direction, the first direction, the second direction and the third direction are perpendicular to each other, the first direction and the second direction are parallel to the top surface of the logic chip, and the third direction is perpendicular to the top surface of the logic chip; For each channel signal region, the plurality of conductive vias therein are divided into a plurality of repair unit groups; Each repair unit group comprises a first repair unit, a second repair unit, a third repair unit and a fourth repair unit; the first repair unit and the second repair unit are symmetrical along the first axis of the channel signal region, the third repair unit and the fourth repair unit are symmetrical along the first axis of the channel signal region, and the first repair unit and the fourth repair unit are symmetrical along the second axis of the channel signal region; Each repair unit comprises at least one redundant conductive via and at least one normal conductive via, when any normal conductive via is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset signal switching direction; Any conductive via in any repair unit is electrically connected to the internal circuit of the logic chip when used to transmit an effective signal; The normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit correspond to each other and are symmetrical along the first axis of the channel signal region, the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit correspond to each other and are symmetrical along the first axis of the channel signal region, and the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit correspond to each other and are symmetrical along the second axis of the channel signal region.

2. The logic chip of claim 1, wherein, For each repair unit group, the preset switching direction of the conductive vias in the first repair unit and the preset switching direction of the conductive vias in the second repair unit are symmetrical along the first axis of the channel signal region; the preset switching direction of the conductive vias in the third repair unit and the preset switching direction of the conductive vias in the fourth repair unit are symmetrical along the first axis of the channel signal region; the preset switching direction of the conductive vias in the first repair unit and the preset switching direction of the conductive vias in the fourth repair unit are symmetrical along the second axis of the channel signal region; and the preset switching direction of the conductive vias in the second repair unit and the preset switching direction of the conductive vias in the third repair unit are symmetrical along the second axis of the channel signal region.

3. The logic chip of claim 2, wherein, Each of the channel signal areas is divided into 2x2 signal regions, and the conductive vias in each of the signal regions are divided into n groups of conductive vias with the same distribution, where n is a positive integer; in the same channel signal area, the groups of conductive vias in the first signal region and the groups of conductive vias in the second signal region correspond to each other and are symmetrical along a first axis of the channel signal area, the groups of conductive vias in the third signal region and the groups of conductive vias in the fourth signal region correspond to each other and are symmetrical along the first axis of the channel signal area, and the groups of conductive vias in the first signal region and the groups of conductive vias in the fourth signal region correspond to each other and are symmetrical along a second axis of the channel signal area; Each of the groups of conductive vias includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via; In the same channel signal area, the first conductive via in one group of conductive vias in the first signal region, the second conductive via in the corresponding group of conductive vias in the second signal region, the third conductive via in the corresponding group of conductive vias in the third signal region, and the fourth conductive via in the corresponding group of conductive vias in the fourth signal region are symmetrical along the first axis and symmetrical along the second axis; In the same channel signal area, the second conductive via in one group of conductive vias in the first signal region, the first conductive via in the corresponding group of conductive vias in the second signal region, the fourth conductive via in the corresponding group of conductive vias in the third signal region, and the third conductive via in the corresponding group of conductive vias in the fourth signal region are symmetrical along the first axis and symmetrical along the second axis; In the same channel signal area, the third conductive via in one group of conductive vias in the first signal region, the fourth conductive via in the corresponding group of conductive vias in the second signal region, the first conductive via in the corresponding group of conductive vias in the third signal region, and the second conductive via in the corresponding group of conductive vias in the fourth signal region are symmetrical along the first axis and symmetrical along the second axis; In the same channel signal area, the fourth conductive via in one group of conductive vias in the first signal region, the third conductive via in the corresponding group of conductive vias in the second signal region, the second conductive via in the corresponding group of conductive vias in the third signal region, and the first conductive via in the corresponding group of conductive vias in the fourth signal region are symmetrical along the first axis and symmetrical along the second axis.

4. The logic chip of claim 3, wherein, Each of the groups of conductive vias in each of the signal regions is referred to as a combination of conductive vias, and the groups of conductive vias b in the corresponding combination of conductive vias in all signal regions are symmetrical along the first axis and symmetrical along the second axis, where B is a positive integer less than or equal to n, and b is a natural number less than B; Each of the combinations of conductive vias in each of the signal regions in the same channel signal area constitutes four groups of repair units. For the 1st said repair unit group, the first repair unit therein comprises: all the first conductive vias of each of the conductive via groups in the conductive via combination in the first signal area; the second repair unit therein comprises: all the second conductive vias of each of the conductive via groups in the conductive via combination in the second signal area; the third repair unit therein comprises: all the third conductive vias of each of the conductive via groups in the conductive via combination in the third signal area; the fourth repair unit therein comprises: all the fourth conductive vias of each of the conductive via groups in the conductive via combination in the fourth signal area; For the 2nd said repair unit group, the first repair unit therein comprises: all the first conductive vias of each of the conductive via groups in the conductive via combination in the second signal area; the second repair unit therein comprises: all the second conductive vias of each of the conductive via groups in the conductive via combination in the first signal area; the third repair unit therein comprises: all the third conductive vias of each of the conductive via groups in the conductive via combination in the fourth signal area; the fourth repair unit therein comprises: all the fourth conductive vias of each of the conductive via groups in the conductive via combination in the third signal area; For the 3rd said repair unit group, the first repair unit therein comprises: all the first conductive vias of each of the conductive via groups in the conductive via combination in the third signal area; the second repair unit therein comprises: all the second conductive vias of each of the conductive via groups in the conductive via combination in the fourth signal area; the third repair unit therein comprises: all the third conductive vias of each of the conductive via groups in the conductive via combination in the first signal area; the fourth repair unit therein comprises: all the fourth conductive vias of each of the conductive via groups in the conductive via combination in the second signal area; For the 4th said repair unit group, the first repair unit therein comprises: all the first conductive vias of each of the conductive via groups in the conductive via combination in the fourth signal area; the second repair unit therein comprises: all the second conductive vias of each of the conductive via groups in the conductive via combination in the third signal area; the third repair unit therein comprises: all the third conductive vias of each of the conductive via groups in the conductive via combination in the second signal area; the fourth repair unit therein comprises: all the fourth conductive vias of each of the conductive via groups in the conductive via combination in the first signal area.

5. The logic chip of claim 4, wherein, When B=3, b takes the value of 0, 1 or 2; all the conductive vias in conductive via group 0 are normal conductive vias; The preset switching direction of the conductive via in the Xth repair unit is that the Xth conductive via in the conductive via group 0 is allowed to switch to the Xth conductive via in the conductive via group 1 in the same signal area, the Xth conductive via in the conductive via group 1 is allowed to switch to the Xth conductive via in the conductive via group 2 in the same signal area, and X is one, two, three or four.

6. The logic chip of claim 4, wherein, When B=6, b is 0, 1, 2, 3, 4 or 5; the conductive via in the conductive via group 2 in all signal areas is a normal conductive via; The preset switching direction of the conductive via in the Xth repair unit is that the Xth conductive via in the conductive via group 2 is allowed to switch to the Xth conductive via in the conductive via group 3 in the same signal area, the Xth conductive via in the conductive via group 3 is allowed to switch to the Xth conductive via in the conductive via group 4 in the same signal area, the Xth conductive via in the conductive via group 4 is allowed to switch to the Xth conductive via in the conductive via group 1 in the same signal area, the Xth conductive via in the conductive via group 1 is allowed to switch to the Xth conductive via in the conductive via group 0 in the same signal area, and the Xth conductive via in the conductive via group 0 is allowed to switch to the Xth conductive via in the conductive via group 5 in the same signal area.

7. The logic chip of claim 6, wherein, In each signal area, the conductive via group 0, the conductive via group 1 and the conductive via group 2 are aligned along a first direction; the conductive via group 3, the conductive via group 4 and the conductive via group 5 are aligned along the first direction; the conductive via group 0 and the conductive via group 5 are aligned along a second direction, the conductive via group 1 and the conductive via group 4 are aligned along the second direction, and the conductive via group 2 and the conductive via group 3 are aligned along the second direction.

8. The logic chip of any one of claims 1-7, wherein, The conductive via is prepared by any one of a via-first process, a via-middle process, a via-last process, a back side via-last process or a plurality of processes; different conductive vias in the same logic chip are electrically isolated.

9. A memory chip, characterized by The memory chip comprises m channels, the m channels are arranged in sequence along a first direction, the memory chip has a chip axis extending along a second direction and passing through the center of the memory chip, and the m channels are symmetrical about the chip axis; each channel comprises a first memory array region, a channel signal region and a second memory array region arranged in sequence along the second direction, and the center of each channel signal region coincides with the center of the channel; m is a positive integer; Each channel signal region has a first axis and a second axis, the first axis extends along the first direction or the second direction, and the second axis is perpendicular to the first axis and intersects the center of the channel signal region; Each of the channel signal regions is penetrated by a plurality of conductive vias along a third direction, the first direction, the second direction and the third direction being perpendicular to each other, the first direction and the second direction being parallel to the top surface of the memory chip, and the third direction being perpendicular to the top surface of the memory chip; For each of the channel signal regions, the plurality of conductive vias therein are divided into a plurality of repair unit groups; each of the repair unit groups comprises a first repair unit, a second repair unit, a third repair unit and a fourth repair unit; the first repair unit and the second repair unit are symmetrical along a first axis of the channel signal region, the third repair unit and the fourth repair unit are symmetrical along the first axis of the channel signal region, and the first repair unit and the fourth repair unit are symmetrical along a second axis of the channel signal region; Each of the repair units comprises at least one redundant conductive via and at least one normal conductive via, when any of the normal conductive vias is damaged, the effective signal transmitted by the normal conductive via is switched to a next conductive via in the same repair unit along a preset switching direction; Any of the conductive vias in the first repair unit is electrically connected to the internal circuit of the memory chip when used to transmit an effective signal; The normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit correspond to each other and are symmetrical along the first axis of the channel signal region, the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit correspond to each other and are symmetrical along the first axis of the channel signal region, and the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit correspond to each other and are symmetrical along the second axis of the channel signal region.

10. The memory chip of claim 9, wherein, For each of the repair unit groups, the preset switching direction of the conductive vias in the first repair unit and the preset switching direction of the conductive vias in the second repair unit are symmetrical along the first axis of the channel signal region; the preset switching direction of the conductive vias in the third repair unit and the preset switching direction of the conductive vias in the fourth repair unit are symmetrical along the first axis of the channel signal region; the preset switching direction of the conductive vias in the first repair unit and the preset switching direction of the conductive vias in the fourth repair unit are symmetrical along the second axis of the channel signal region; and the preset switching direction of the conductive vias in the second repair unit and the preset switching direction of the conductive vias in the third repair unit are symmetrical along the second axis of the channel signal region.

11. The memory chip of claim 10, wherein, Each of the channel signal regions is divided into 2x2 signal areas, the conductive vias in each of the signal areas are divided into n groups of conductive vias with the same distribution, n is a positive integer; in the same channel signal region, the groups of conductive vias in the first signal area and the groups of conductive vias in the second signal area correspond to each other and are symmetrical along a first axis, the groups of conductive vias in the third signal area and the groups of conductive vias in the fourth signal area correspond to each other and are symmetrical along the first axis, the groups of conductive vias in the first signal area and the groups of conductive vias in the fourth signal area correspond to each other and are symmetrical along a second axis; Each of the groups of conductive vias includes a first conductive via, a second conductive via, a third conductive via and a fourth conductive via; For the same channel signal region, the first conductive via in one group of conductive vias in the first signal area, the second conductive via in the corresponding group of conductive vias in the second signal area, the third conductive via in the corresponding group of conductive vias in the third signal area and the fourth conductive via in the corresponding group of conductive vias in the fourth signal area are symmetrical along the first axis and symmetrical along the second axis; For the same channel signal region, the second conductive via in one group of conductive vias in the first signal area, the first conductive via in the corresponding group of conductive vias in the second signal area, the fourth conductive via in the corresponding group of conductive vias in the third signal area and the third conductive via in the corresponding group of conductive vias in the fourth signal area are symmetrical along the first axis and symmetrical along the second axis; For the same channel signal region, the third conductive via in one group of conductive vias in the first signal area, the fourth conductive via in the corresponding group of conductive vias in the second signal area, the first conductive via in the corresponding group of conductive vias in the third signal area and the second conductive via in the corresponding group of conductive vias in the fourth signal area are symmetrical along the first axis and symmetrical along the second axis; For the same channel signal region, the fourth conductive via in one group of conductive vias in the first signal area, the third conductive via in the corresponding group of conductive vias in the second signal area, the second conductive via in the corresponding group of conductive vias in the third signal area and the first conductive via in the corresponding group of conductive vias in the fourth signal area are symmetrical along the first axis and symmetrical along the second axis.

12. The memory chip of claim 11, wherein, Each of the groups of conductive vias in each of the signal areas is referred to as one conductive via combination, the groups of conductive vias b in the corresponding conductive via combinations in all the signal areas are symmetrical along the first axis and symmetrical along the second axis, B is a positive integer less than or equal to n, b is a natural number less than B; Each of the signal areas in the same channel signal region includes four groups of repair units corresponding to one conductive via combination. For the first of the repair unit groups, the first repair unit comprises: all the first conductive vias of the conductive via combinations in the conductive via groups in the first signal area; the second repair unit comprises: all the second conductive vias of the conductive via combinations in the conductive via groups in the second signal area; the third repair unit comprises: all the third conductive vias of the conductive via combinations in the conductive via groups in the third signal area; and the fourth repair unit comprises: all the fourth conductive vias of the conductive via combinations in the conductive via groups in the fourth signal area. For the second of the repair unit groups, the first repair unit comprises: all the first conductive vias of the conductive via combinations in the conductive via groups in the second signal area; the second repair unit comprises: all the second conductive vias of the conductive via combinations in the conductive via groups in the first signal area; the third repair unit comprises: all the third conductive vias of the conductive via combinations in the conductive via groups in the fourth signal area; and the fourth repair unit comprises: all the fourth conductive vias of the conductive via combinations in the conductive via groups in the third signal area. For the third of the repair unit groups, the first repair unit comprises: all the first conductive vias of the conductive via combinations in the conductive via groups in the third signal area; the second repair unit comprises: all the second conductive vias of the conductive via combinations in the conductive via groups in the fourth signal area; the third repair unit comprises: all the third conductive vias of the conductive via combinations in the conductive via groups in the first signal area; and the fourth repair unit comprises: all the fourth conductive vias of the conductive via combinations in the conductive via groups in the second signal area. For the fourth of the repair unit groups, the first repair unit comprises: all the first conductive vias of the conductive via combinations in the conductive via groups in the fourth signal area; the second repair unit comprises: all the second conductive vias of the conductive via combinations in the conductive via groups in the third signal area; the third repair unit comprises: all the third conductive vias of the conductive via combinations in the conductive via groups in the second signal area; and the fourth repair unit comprises: all the fourth conductive vias of the conductive via combinations in the conductive via groups in the first signal area.

13. The memory chip of claim 12, wherein, When B=3, b is 0, 1 or 2; the conductive vias in the conductive via group 0 are all normal conductive vias; The preset switching direction of the conductive via in any of the first repair units is that the first conductive via in the conductive via group 0 is allowed to switch to the first conductive via in the conductive via group 1 in the same signal area, the first conductive via in the conductive via group 1 is allowed to switch to the first conductive via in the conductive via group 2 in the same signal area.

14. The memory chip of claim 13, wherein, When B=6, b is 0, 1, 2, 3, 4 or 5; the conductive via in the conductive via group 0 in all signal areas is a normal conductive via; The preset switching direction of the conductive via in the first repair unit is that the first conductive via in the conductive via group 2 is allowed to switch to the first conductive via in the conductive via group 3 in the same signal area, the first conductive via in the conductive via group 3 is allowed to switch to the first conductive via in the conductive via group 4 in the same signal area, the first conductive via in the conductive via group 4 is allowed to switch to the first conductive via in the conductive via group 1 in the same signal area; the first conductive via in the conductive via group 1 is allowed to switch to the first conductive via in the conductive via group 0 in the same signal area; the first conductive via in the conductive via group 0 is allowed to switch to the first conductive via in the conductive via group 5 in the same signal area.

15. A chip stack structure, characterized by The chip stacking structure comprises the logic chip and at least one stacking unit as claimed in any of claims 1-8, and the logic chip and the at least one stacking unit are stacked in sequence along a third direction; each stacking unit comprises a first storage chip, a second storage chip, a third storage chip and a fourth storage chip stacked in sequence along the third direction, and the third direction is perpendicular to the top surface of each chip; the first storage chip, the second storage chip, the third storage chip and the fourth storage chip are storage chips as claimed in any of claims 9-14; The first storage chip and the second storage chip are stacked in a face-to-face manner, the second storage chip and the third storage chip are stacked in a back-to-back manner, and the third storage chip and the fourth storage chip are stacked in a face-to-face manner; The logic chip and the first storage chip are stacked in a back-to-back manner. Alternatively, the logic chip and the first storage chip are stacked in a face-to-back manner.

16. The chip stack structure of claim 15, wherein, The logic chip comprises m channel signal areas arranged along a first direction, each storage chip has m channels arranged along the first direction, and each channel comprises a first storage array area, a channel signal area and a second storage array area arranged in sequence along a second direction; The first direction, the second direction and the third direction are perpendicular to each other, and the first direction and the second direction are parallel to the top surface of each chip; In the case where the logic chip and the first storage chip are stacked in a back-to-back manner, and the first axis of the logic chip and the first axis of each storage chip extend along the first direction, The m-i th channel signal region in the logic chip is aligned with the channel signal region in the i+1 th channel in the first memory chip, the channel signal region in the i+1 th channel in the second memory chip, the channel signal region in the m-i th channel in the third memory chip, and the channel signal region in the m-i th channel in the fourth memory chip along a third direction; wherein i is a natural number less than m.

17. The chip stack structure of claim 16, wherein, The logic chip comprises m channel signal regions arranged along a first direction, each of the memory chips has m channels arranged along the first direction, and each of the channels comprises a first memory array region, a channel signal region, and a second memory array region arranged along a second direction in sequence; In the case that the logic chip and the first memory chip are stacked in a back-to-back manner, and the second axis of the logic chip and each of the memory chips extends along the first direction, The i+1 th channel signal region in the logic chip is aligned with the channel signal region in the i+1 th channel in the first memory chip, the channel signal region in the m-i th channel in the second memory chip, the channel signal region in the m-i th channel in the third memory chip, and the channel signal region in the i+1 th channel in the fourth memory chip along a third direction; wherein i is a natural number less than m.

18. The chip stack structure according to claim 16 or 17, characterized by The channel signal region in each of the channels is divided into 2x2 signal areas arranged in an array; Only for the plurality of channel signal regions aligned along the third direction: The fourth signal area belonging to the logic chip, the first signal area belonging to the first memory chip, the second signal area belonging to the second memory chip, the third signal area belonging to the third memory chip, and the fourth signal area belonging to the fourth memory chip are aligned along the third direction; The third signal area belonging to the logic chip, the second signal area belonging to the first memory chip, the first signal area belonging to the second memory chip, the fourth signal area belonging to the third memory chip, and the third signal area belonging to the fourth memory chip are aligned along the third direction; The second signal area belonging to the logic chip, the third signal area belonging to the first memory chip, the fourth signal area belonging to the second memory chip, the first signal area belonging to the third memory chip, and the second signal area belonging to the fourth memory chip are aligned along the third direction; The first signal area belonging to the logic chip, the fourth signal area belonging to the first memory chip, the third signal area belonging to the second memory chip, the second signal area belonging to the third memory chip, and the first signal area belonging to the fourth memory chip are aligned along the third direction.

19. The chip stack structure of claim 18, wherein, Each of the signal areas comprises n groups of conductive vias with the same distribution position, each of the groups of conductive vias comprises a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via; Only for the plurality of signal areas aligned along the third direction: The fourth conductive via belonging to the logic chip, the first conductive via belonging to the first memory chip, the second conductive via belonging to the second memory chip, the third conductive via belonging to the third memory chip, and the fourth conductive via belonging to the fourth memory chip are aligned along a third direction; The third conductive via belonging to the logic chip, the second conductive via belonging to the first memory chip, the first conductive via belonging to the second memory chip, the fourth conductive via belonging to the third memory chip, and the third conductive via belonging to the fourth memory chip are aligned along a third direction; The second conductive via belonging to the logic chip, the third conductive via belonging to the first memory chip, the fourth conductive via belonging to the second memory chip, the first conductive via belonging to the third memory chip, and the second conductive via belonging to the fourth memory chip are aligned along a third direction; The first conductive via belonging to the logic chip, the fourth conductive via belonging to the first memory chip, the third conductive via belonging to the second memory chip, the second conductive via belonging to the third memory chip, and the first conductive via belonging to the fourth memory chip are aligned along a third direction; The plurality of conductive vias aligned along the third direction are coupled to form a signal transmission channel.

20. The chip stack structure of claim 19, wherein one of the fourth repair units in the logic chip, one of the first repair units in the first memory chip, one of the second repair units in the second memory chip, one of the third repair units in the third memory chip, and one of the fourth repair units in the fourth memory chip are aligned along a third direction and perform conductive via switching operations synchronously; one of the third repair units in the logic chip, one of the second repair units in the first memory chip, one of the first repair units in the second memory chip, one of the fourth repair units in the third memory chip, and one of the third repair units in the fourth memory chip are aligned along a third direction and perform conductive via switching operations synchronously; one of the second repair units in the logic chip, one of the third repair units in the first memory chip, one of the fourth repair units in the second memory chip, one of the first repair units in the third memory chip, and one of the second repair units in the fourth memory chip are aligned along a third direction and perform conductive via switching operations synchronously; one of the first repair units in the logic chip, one of the fourth repair units in the first memory chip, one of the third repair units in the second memory chip, one of the second repair units in the third memory chip, and one of the first repair units in the fourth memory chip are aligned along a third direction and perform conductive via switching operations synchronously.

21. The chip stack structure of claim 15, wherein, The logic chip comprises m channel signal regions arranged along a first direction, each of the memory chips has m channels arranged along the first direction, and each of the channels comprises a first memory array region, a channel signal region and a second memory array region distributed along a second direction in sequence; In the case that the logic chip and the first memory chip are stacked in a back-to-back manner, and the first axis of the logic chip and each of the memory chips extends along a first direction, The i+1th channel signal region in the logic chip is aligned with the channel signal region in the i+1th channel of the first memory chip, the channel signal region in the i+1th channel of the second memory chip, the channel signal region in the m-i th channel of the third memory chip and the channel signal region in the m-i th channel of the fourth memory chip along a third direction; wherein i is a natural number less than m.

22. The chip stack structure of claim 15, wherein, The logic chip comprises m channel signal regions arranged along a first direction, each of the memory chips has m channels arranged along the first direction, and each of the channels comprises a first memory array region, a channel signal region and a second memory array region distributed along a second direction in sequence; In the case that the logic chip and the first memory chip are stacked in a back-to-back manner, and the second axis of the logic chip and each of the memory chips extends along a first direction, The m-i th channel signal region in the logic chip is aligned with the channel signal region in the i+1th channel of the first memory chip, the channel signal region in the m-i th channel of the second memory chip, the channel signal region in the m-i th channel of the third memory chip and the channel signal region in the i+1th channel of the fourth memory chip along a third direction; wherein i is a natural number less than m.

23. The chip stack structure according to claim 21 or 22, characterized by The channel signal region in each of the channels is divided into 2x2 signal regions arranged in an array; Only for the plurality of channel signal regions aligned along the third direction: The second signal region belonging to the logic chip, the first signal region belonging to the first memory chip, the second signal region belonging to the second memory chip, the third signal region belonging to the third memory chip and the fourth signal region belonging to the fourth memory chip are aligned along the third direction; The first signal region belonging to the logic chip, the second signal region belonging to the first memory chip, the first signal region belonging to the second memory chip, the fourth signal region belonging to the third memory chip and the third signal region belonging to the fourth memory chip are aligned along the third direction; The fourth signal region belonging to the logic chip, the third signal region belonging to the first memory chip, the fourth signal region belonging to the second memory chip, the first signal region belonging to the third memory chip and the second signal region belonging to the fourth memory chip are aligned along the third direction; The third signal region belonging to the logic chip, the fourth signal region belonging to the first memory chip, the third signal region belonging to the second memory chip, the second signal region belonging to the third memory chip, and the first signal region belonging to the fourth memory chip are aligned along a third direction.

24. The chip stack structure of claim 23, wherein, Each of the signal regions comprises n groups of conductive vias with the same distribution position, and each of the groups of conductive vias comprises a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via. For the plurality of signal regions aligned along the third direction: The second conductive via belonging to the logic chip, the first conductive via belonging to the first memory chip, the second conductive via belonging to the second memory chip, the third conductive via belonging to the third memory chip, and the fourth conductive via belonging to the fourth memory chip are aligned along the third direction; The first conductive via belonging to the logic chip, the second conductive via belonging to the first memory chip, the first conductive via belonging to the second memory chip, the fourth conductive via belonging to the third memory chip, and the third conductive via belonging to the fourth memory chip are aligned along the third direction; The fourth conductive via belonging to the logic chip, the third conductive via belonging to the first memory chip, the fourth conductive via belonging to the second memory chip, the first conductive via belonging to the third memory chip, and the second conductive via belonging to the fourth memory chip are aligned along the third direction; The third conductive via belonging to the logic chip, the fourth conductive via belonging to the first memory chip, the third conductive via belonging to the second memory chip, the second conductive via belonging to the third memory chip, and the first conductive via belonging to the fourth memory chip are aligned along the third direction; The plurality of conductive vias aligned along the third direction are coupled to form a signal transmission channel.

25. The chip stack structure of claim 24, wherein: one of the second repair units in the logic chip, one of the first repair units in the first memory chip, one of the second repair units in the second memory chip, one of the third repair units in the third memory chip, and one of the fourth repair units in the fourth memory chip are aligned along the third direction and perform conductive via switching operations synchronously; one of the first repair units in the logic chip, one of the second repair units in the first memory chip, one of the first repair units in the second memory chip, one of the fourth repair units in the third memory chip, and one of the third repair units in the fourth memory chip are aligned along the third direction and perform conductive via switching operations synchronously; The fourth repair unit in one of the logic chips, the third repair unit in one of the first memory chips, the fourth repair unit in one of the second memory chips, the first repair unit in one of the third memory chips, and the second repair unit in one of the fourth memory chips are aligned in the third direction and perform a conductive via switching operation synchronously; The third repair unit in one of the logic chips, the fourth repair unit in one of the first memory chips, the third repair unit in one of the second memory chips, the second repair unit in one of the third memory chips, and the first repair unit in one of the fourth memory chips are aligned in the third direction and perform a conductive via switching operation synchronously.

26. The chip stack structure according to any one of claims 15-25, wherein, For two chips connected face-to-face, the positions where the conductive vias in both of the two chips are aligned in the third direction are electrically connected by a hybrid bonding process; for two chips connected back-to-back or for two chips connected back-to-face, the positions where the conductive vias in both of the two chips are aligned in the third direction are electrically connected by a conductive bump bonding process; or, For two chips connected face-to-face or for two chips connected back-to-back or for two chips connected back-to-face, the positions where the conductive vias in both of the two chips are aligned in the third direction are electrically connected by a hybrid bonding process; or, For two chips connected face-to-face or for two chips connected back-to-back or for two chips connected back-to-face, the positions where the conductive vias in both of the two chips are aligned in the third direction are electrically connected by a conductive bump bonding process.

27. A memory, comprising: A chip stack structure as claimed in any one of claims 15-26.

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