Method for forming semiconductor structure, semiconductor structure and electronic device
By forming multiple oxide hard mask layers on a metal hard mask layer and transferring the via pattern, the problem of insufficient dimensional control of non-self-aligned rectangular vias in traditional processes is solved, achieving higher dimensional accuracy and improved device performance.
Patent Information
- Application Number
- CN202311598463.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-27
- Publication Date
- 2026-01-23
- Estimated Expiration
- 2043-11-27
AI Technical Summary
In the back-end manufacturing process of semiconductor devices, the traditional dual damascene integrated process has difficulty in accurately controlling the critical dimensions of rectangular vias in non-self-aligned directions, resulting in bridging between the vias and the underlying metal, which affects device performance.
By forming a first patterned oxide hard mask layer defining a trench pattern on a metal hard mask layer, and forming a planarization layer and a second patterned oxide hard mask layer defining a via pattern on it, the via pattern is transferred to the metal hard mask layer, and trenches and vias are formed in combination with etching processes, controlling the critical dimensions of the vias in non-self-aligned directions.
It improves the accuracy of critical dimension control of rectangular vias in non-self-aligned directions, expands the process window, avoids bridging between vias and underlying metal, and enhances the performance of semiconductor devices.
Smart Images
Figure CN120048792B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, in particular to a forming method of a semiconductor structure, a semiconductor structure and an electronic device. BACKGROUND
[0002] In the back end of line (BEOL) of a semiconductor device, a dual damascene structure is usually formed by using a dual damascene process, wherein a via is a key part of the dual damascene structure, and a via with a high aspect ratio is not only conducive to the contact of interlayer metal, but also conducive to reducing the resistance capacitor (RC) of the back end interconnection. As the technology node is reduced to below 7 nm, the critical dimension (CD) of the via is further reduced, and therefore higher requirements are put forward for the control accuracy of the critical dimension of the via.
[0003] Among them, the via with different length critical dimension (CD) and width critical dimension CD, such as a rectangular via, can reduce the resistance capacitor (RC) of the back end interconnection. In the related art, when a dual damascene structure with a rectangular via is formed by using a traditional dual damascene integrated process, the control accuracy of the critical dimension of the rectangular via in the non-self-aligned direction is poor, which is easy to cause bridging between the via and the front layer metal, and thus affects the performance of the semiconductor device. SUMMARY
[0004] In order to solve the problems in the prior art, the embodiments of the present application provide a forming method of a semiconductor structure, a semiconductor structure and an electronic device. The technical solution is as follows:
[0005] In one aspect, a forming method of a semiconductor structure is provided, comprising:
[0006] A substrate is provided, the substrate comprising a bottom metal layer, an interlayer dielectric layer, a metal hard mask layer and a first patterned oxide hard mask layer which are stacked; a plurality of first openings exposing the upper surface of the metal hard mask layer are formed in the first patterned oxide hard mask layer, and the plurality of first openings indicate a pattern of trenches for forming an upper metal layer;
[0007] A planarization layer is formed on the first patterned oxide hard mask layer, the planarization layer filling the plurality of first openings and covering the upper surface of the first patterned oxide hard mask layer;
[0008] A second patterned oxide hard mask layer is formed on the planarization layer, and a pattern of vias is defined in the second patterned oxide hard mask layer;
[0009] transferring a pattern of the via defined in the second patterned oxide hard mask layer to the metal hard mask layer to form a first patterned metal hard mask layer;
[0010] forming the trench and the via in the interlayer dielectric layer based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer; the bottom of the trench is in communication with the top of the via.
[0011] In one exemplary embodiment, an etch stop layer is formed between the interlayer dielectric layer and the metal hard mask layer; and the transferring a pattern of the via defined in the second patterned oxide hard mask layer to the metal hard mask layer to form a first patterned metal hard mask layer comprises:
[0012] etching the planarization layer based on a first etching process to expose an upper surface of the metal hard mask layer with the second patterned oxide hard mask layer as a mask;
[0013] etching the exposed metal hard mask layer based on a second etching process and stopping at the etch stop layer to form a second opening through the metal hard mask layer in a defined region of the metal hard mask layer corresponding to the via, the second opening having a size smaller than a size of the first opening;
[0014] removing the second patterned oxide hard mask layer and the planarization layer.
[0015] In one exemplary embodiment, the forming the trench and the via in the interlayer dielectric layer based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer comprises:
[0016] etching the remaining metal hard mask layer exposed in the first opening with the first patterned oxide hard mask layer as a mask to obtain a second patterned metal hard mask layer formed with the trench pattern; wherein during the etching process, the etch stop layer and part of the interlayer dielectric layer exposed by the second opening in the first patterned metal hard mask layer are etched to form part of the via in the interlayer dielectric layer;
[0017] etching the interlayer dielectric layer to expose the bottom metal layer along the trench pattern and the part of the via with the first patterned oxide hard mask layer and the second patterned metal hard mask layer as masks to obtain the trench and the via formed in the interlayer dielectric layer.
[0018] In one exemplary embodiment, the method further comprises:
[0019] A semiconductor substrate is provided, in which a bottom metal layer is formed;
[0020] An interlayer dielectric layer is formed on the surface of the semiconductor substrate, covering the bottom metal layer;
[0021] A metal hard mask layer is formed on the etching stop layer;
[0022] A first oxide hard mask layer is formed on the metal hard mask layer;
[0023] A first patterned photoresist layer is formed on the first oxide hard mask layer; the first patterned photoresist layer defines a pattern of trenches for forming an upper metal layer;
[0024] The first oxide hard mask layer is etched to expose the upper surface of the metal hard mask layer, using the first patterned photoresist layer as a mask;
[0025] The remaining first patterned photoresist layer is removed, obtaining the substrate.
[0026] In an exemplary embodiment, the forming a second patterned oxide hard mask layer on the planarization layer comprises:
[0027] A second oxide hard mask layer, an anti-reflective layer and a second patterned photoresist layer are sequentially formed on the planarization layer; the second patterned photoresist layer defines a pattern of vias;
[0028] The anti-reflective layer and the second oxide hard mask layer are sequentially etched, using the second patterned photoresist layer as a mask;
[0029] The remaining second patterned photoresist layer and the remaining anti-reflective layer are removed, obtaining the second patterned oxide hard mask layer.
[0030] In an exemplary embodiment, after the trenches and the vias are formed in the interlayer dielectric layer, the method further comprises:
[0031] The first patterned oxide hard mask layer and the remaining metal hard mask layer are removed.
[0032] In an exemplary embodiment, after the first patterned oxide hard mask layer and the remaining metal hard mask layer are removed, the method further comprises:
[0033] The trenches and the vias are filled with a conductive material.
[0034] In an exemplary embodiment, the photolithography process in the forming method employs a deep ultraviolet photolithography process.
[0035] In one exemplary embodiment, the length critical dimension of the via is different from the width critical dimension.
[0036] In another aspect, a semiconductor structure formed by any of the aforementioned methods is provided, the semiconductor structure comprising:
[0037] a semiconductor substrate having a bottom metal layer formed therein;
[0038] an interlayer dielectric layer formed on the surface of the semiconductor substrate and covering the bottom metal layer;
[0039] a trench and a via formed in the interlayer dielectric layer; the bottom of the trench is in communication with the top of the via.
[0040] In one exemplary embodiment, the semiconductor structure further comprises: a conductive material filled in the trench and the via.
[0041] In one exemplary embodiment, an etching stop layer is further formed on the interlayer dielectric layer, and the trench extends through the etching stop layer and into the interlayer dielectric layer.
[0042] In one exemplary embodiment, the length critical dimension of the via is different from the width critical dimension.
[0043] In another aspect, an electronic device comprising the semiconductor structure formed by any of the aforementioned methods is provided.
[0044] The embodiments of the present application provide a substrate, a metal hard mask layer in the substrate is not etched, a first patterned oxide hard mask layer defining a trench pattern is formed on the metal hard mask layer, then a planarization layer is formed on the first patterned oxide hard mask layer, and a second patterned oxide hard mask layer defining a via pattern is formed on the planarization layer, the pattern of the via defined in the second patterned oxide hard mask layer is transferred to the metal hard mask layer to form a first patterned metal hard mask layer, and then a dual damascene structure having a trench and a via is formed in an interlayer dielectric layer of the substrate based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer, so that the etching of the metal hard mask layer is performed after the second patterned oxide hard mask layer is formed, the critical dimension of the via in a non-self-alignment direction is well controlled by using the metal hard mask layer, the control accuracy of the critical dimension of the via in the non-self-alignment direction such as a rectangular via is improved, the process window of the via is expanded, and the bridging between the via and the bottom metal layer is avoided, and the performance of the semiconductor device is improved. BRIEF DESCRIPTION OF DRAWINGS
[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained from these drawings without any creative effort.
[0046] Figures la-lb Fig. 1 is a partial cross-sectional view of the process of forming a dual damascene structure by using a conventional dual damascene integration process in the prior art;
[0047] Figure lc Fig. 2 is a plan view of a partial square via in the process of forming a square via by using a conventional dual damascene integration process in the prior art;
[0048] Figure Id Fig. 3 is a plan view of a partial rectangular via in the process of forming a rectangular via by using a conventional dual damascene integration process in the prior art;
[0049] Figure 2 Fig. 4 is a flow chart of the process of forming a semiconductor structure according to an embodiment of the present application;
[0050] Figures 3-11 Fig. 5 is a cross-sectional view of the process of forming a semiconductor structure according to an embodiment of the present application;
[0051] Figure 12 Fig. 6 is a cross-sectional view of a semiconductor structure according to an embodiment of the present application; DETAILED DESCRIPTION
[0052] The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative effort belong to the scope of protection of the present application.
[0053] It is to be understood that the terms "first", "second", "third", etc. that are used in the description and in the claims of the application are used for distinguishing between similar objects, not necessarily for describing a particular sequential or chronological order. It is to be understood that the use of data "first", "second", "third", etc. herein is to be interpreted as "first", "second", "third", etc. in the context, and not necessarily in a chronological or sequential order. Furthermore, the terms "comprise", "comprising", "has", "having", "includes", "including", "contain", "containing", or any other similar phrase are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises, has, includes, contains a list of elements or steps does not necessarily lack any other element or step not expressly listed. In other words, the use of these terms herein is to be interpreted as "including but not limited to".
[0054] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", or "includes" and / or "including" when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.
[0055] Figures la-lb A portion of the cross-sectional view of the process of forming a dual damascene structure using a conventional dual damascene integration process is shown. First, a pattern of trenches is transferred into a metal hard mask layer and an oxide hard mask layer on a semiconductor substrate, as shown in FIG. 1A. Figure la As shown, the metal hard mask layer 120 and the oxide hard mask layer 130 on the semiconductor substrate 110 are etched to form a trench pattern 140 in the metal hard mask layer 120 and the oxide hard mask layer 130. Then, a via pattern is transferred into the interlayer dielectric layer to form a partial interconnection via in the interlayer dielectric layer, as shown in FIG. 1B. Figure lbAs shown, part of the interconnection via hole 150 is formed in the interlayer dielectric layer 160, and part of the interconnection via hole 150 is communicated with the trench pattern 140 in the metal hard mask layer 120 and the oxide hard mask layer 130, then the trench and the interconnection via hole are formed in the interlayer dielectric layer 160, which exposes the bottom metal layer 170 in the semiconductor substrate 110.
[0056] The conventional dual damascene integration process is friendly to form the dual damascene structure with square via hole, because the etching deviation in the self-aligned direction and the non-self-aligned direction of the square via hole is basically the same, so when the hard mask on both sides of the trench is used to control the critical dimension of the square via hole in the self-aligned direction in the conventional process, the critical dimension in the non-self-aligned direction is also controlled.
[0057] It should be noted that the self-aligned direction (Self-Aligned Via, SAV) in the embodiments of the present application refers to the direction perpendicular to the metal layer, and the non-self-aligned direction (Non Self-Aligned Via, Non-SAV) refers to the direction parallel to the metal layer.
[0058] As Figure lc shown is a plan view of part of the square via hole in the prior art using the conventional dual damascene integration process in the process of forming the square via hole, and Figure lc in which 101 represents part of the square via hole, 102 represents the hard mask layer of the upper metal layer (such as the metal hard mask layer 120 and the oxide hard mask layer 130 in the Figure la ), and 103 represents the bottom metal layer (such as the bottom metal layer 170 in the Figure la ). As Figure lc can be seen, the critical dimensions of part of the square via hole 101 in the self-aligned direction and the non-self-aligned direction are well controlled.
[0059] However, in the metal interconnection structure realized by using the via hole with different length critical dimension and width critical dimension, such as rectangular via hole, the metal spacing of the upper metal layer is larger than that of the bottom metal layer, which leads to that the self-aligned function cannot be realized by using the hard mask on both sides of the trench when the dual damascene structure with rectangular via hole is formed by using the conventional dual damascene integration process, so that the critical dimension of the via hole in the non-self-aligned direction is out of control, and finally causes the via hole to be bridged with the bottom metal. As Figure Id shown is a plan view of the rectangular via hole in the prior art using the conventional dual damascene integration process in the process of forming the rectangular via hole, Figure Id in which the critical dimension of the rectangular via hole 104 in the non-self-aligned direction is out of control, which leads to the rectangular via hole being bridged with the bottom metal.
[0060] Based on this, the embodiment of the present application provides a semiconductor structure forming method. The method provides a substrate. A metal hard mask layer in the substrate is not etched. A first patterned oxide hard mask layer defining a trench pattern is formed on the metal hard mask layer. Then, a planarization layer is formed on the first patterned oxide hard mask layer. A second patterned oxide hard mask layer defining a via pattern is formed on the planarization layer. Then, the pattern of the via defined in the second patterned oxide hard mask layer is transferred to the metal hard mask layer to form a first patterned metal hard mask layer. Then, based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer, a dual damascene structure with a trench and a via is formed in an interlayer dielectric layer of the substrate. The etching of the metal hard mask layer is performed after the formation of the second patterned oxide hard mask layer. Therefore, the critical dimension of the via in the non-self-aligned direction is well controlled by using the metal hard mask layer. The control accuracy of the critical dimension of the via in the non-self-aligned direction is improved. The process window of the via is expanded. The bridging between the via and the bottom metal layer is avoided. The performance of the semiconductor device is improved.
[0061] It should be noted that the via formed by the forming method of the embodiment of the present application can be a via with different length critical dimension and width critical dimension. For example, the via can be a rectangular via. In order to facilitate the description of the technical scheme of the embodiment of the present application, the technical scheme of the embodiment of the present application will be described in detail below taking the rectangular via as an example. It should be emphasized that the rectangular via in the embodiment of the present application can be a regular rectangular pattern via or an irregular rectangular pattern via.
[0062] Please refer to Figure 2 which is a flowchart of a semiconductor structure forming method provided by the embodiment of the present application. The semiconductor structure forming method provided by the embodiment of the present application will be described in detail below. Figures 2-11
[0063] Please refer to Figure 2 In step S201, a substrate is provided. The substrate includes a bottom metal layer, an interlayer dielectric layer, a metal hard mask layer and a first patterned oxide hard mask layer which are stacked.
[0064] The substrate provides a process operation basis for subsequent processes. As shown in Figure 3 The substrate 300 includes the bottom metal layer 310. The interlayer dielectric layer 320 is formed on the bottom metal layer 310. The metal hard mask layer 330 is formed on the interlayer dielectric layer 320. The first patterned oxide hard mask layer 340 is formed on the metal hard mask layer 330.
[0065] The material of the bottom metal layer 310 can be copper. The material of the interlayer dielectric layer 320 can be low-k dielectric material (low-k dielectric material refers to dielectric material with relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9) or ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with relative dielectric constant less than 2.6), so as to effectively reduce the parasitic capacitance between the metal layers and further reduce the back-end RC delay. The material of the metal hard mask layer 330 can be titanium nitride, titanium or copper nitride.
[0066] The first patterned oxide hard mask layer 340 defines the pattern of the trench for forming the upper metal layer. As shown in FIG. 4, a plurality of first openings 341 are formed in the first patterned oxide hard mask layer 340 to expose the upper surface of the metal hard mask layer 330, and the plurality of first openings 341 indicate the pattern of the trench for forming the upper metal layer. Figure 3 The first patterned oxide hard mask layer 340 defines the pattern of the trench for forming the upper metal layer. As shown in FIG. 4, a plurality of first openings 341 are formed in the first patterned oxide hard mask layer 340 to expose the upper surface of the metal hard mask layer 330, and the plurality of first openings 341 indicate the pattern of the trench for forming the upper metal layer.
[0067] It should be noted that the upper metal layer herein is relative to the bottom metal layer, i.e., the metal layer on the bottom metal layer and interconnected with the bottom metal layer. Since the first metal layer M1 (also referred to as M0) involves the contact layer process, it is usually not formed by the dual damascene process, and therefore, the upper metal layer in the embodiment of the present application does not include the first metal layer M1 / M0.
[0068] It can be understood that the substrate 300 can further include a dielectric material layer (not shown in the figure), and the bottom metal layer 310 is located in the dielectric material layer and is separated by the dielectric material layer to be insulated from each other.
[0069] In a specific embodiment, the substrate 300 can further include an etching stop layer 350 formed between the interlayer dielectric layer 320 and the metal hard mask layer 330.
[0070] The material of the etching stop layer 350 is denser and harder than the material of the interlayer dielectric layer 320. Since the material of the interlayer dielectric layer 320 is low-k dielectric material or ultra-low-k dielectric material, it is soft and easy to over-etch, while the material of the etching stop layer 350 is denser and harder. Forming the etching stop layer 350 on the surface of the interlayer dielectric layer 320 can better control the etching progress in the subsequent etching process, so as to ensure that the morphology and size of the subsequently formed trench and via meet the process specifications. Exemplarily, the material of the etching stop layer 350 can include one or more of SiO2, SiN, SiON and SiOC.
[0071] Based on this, before step S201, the method can further include forming the substrate 300, Figures 4a-4f As shown in FIG. 3, the substrate 300 is in the process of forming.
[0072] Referring to Figure 4a , a semiconductor substrate 410 is provided, in which a bottom metal layer 420 is formed.
[0073] In the semiconductor substrate 410, a dielectric material layer (not shown in the figure) is also formed, and the bottom metal layer 420 is located in the dielectric material layer and is insulated from each other by the dielectric material layer.
[0074] In the semiconductor substrate 410, a functional device (not shown in the figure) is also formed, which is electrically connected to the bottom metal layer 420, and the functional device may, for example, include a transistor, a resistance structure, a capacitance structure, etc.
[0075] Referring to Figure 4b , an interlayer dielectric layer 430 and an etching stop layer 440 are sequentially formed on the surface of the semiconductor substrate 410, wherein the interlayer dielectric layer 430 covers the bottom metal layer 420.
[0076] In a specific implementation, the interlayer dielectric layer 430 and the etching stop layer 440 can be sequentially formed on the surface of the semiconductor substrate 410 by chemical vapor deposition or physical vapor deposition.
[0077] Referring to Figure 4c , a metal hard mask layer 450 is formed on the etching stop layer 430. The forming process of the metal hard mask layer 450 can be physical vapor deposition.
[0078] Referring to Figure 4d , a first oxide hard mask layer 460 is formed on the metal hard mask layer 40. The material of the first oxide hard mask layer 460 can be TEOS (tetraethyl orthosilicate), and the process of forming the first oxide hard mask layer 460 can be chemical vapor deposition.
[0079] Referring to Figure 4e , a first patterned photoresist layer 470 is formed on the first oxide hard mask layer 460, which defines a pattern of a trench for forming an upper metal layer.
[0080] Referring to Figure 4f , the first oxide hard mask layer 460 is etched to stop exposing the upper surface of the metal hard mask layer 450 with the first patterned photoresist layer 470 as a mask, so as to form a first opening 341 in the defined area corresponding to the trench pattern of the first oxide hard mask layer 460, which exposes the upper surface of the metal hard mask layer 440, thereby obtaining a first patterned oxide hard mask layer, and the metal hard mask layer 450 is not damaged in this etching.
[0081] The process of etching the first oxide hard mask layer 460 can be a plasma dry etching process.
[0082] Next, the remaining first patterned photoresist layer 470 is removed, and the aforementioned substrate 300 of the present application is obtained (see Figure 3 The remaining first patterned photoresist layer 470 can be removed by a wet etching process or a plasma dry etching process.
[0083] The above-mentioned embodiments transfer the pattern of the trench to the first oxide hard mask layer only, and the metal hard mask layer is not damaged, so that the metal hard mask layer can be used to accurately control the critical dimensions of the rectangular via in the self-alignment direction and the non-self-alignment direction in subsequent processes.
[0084] Continuing to refer to Figure 2 In step S203, a planarization layer is formed on the first patterned oxide hard mask layer, the planarization layer filling the plurality of first openings and covering the upper surface of the first patterned oxide hard mask layer.
[0085] The planarization layer is mainly used to flatten the undulations caused by etching to form the first patterned oxide hard mask layer. In the present application, the material constituting the planarization layer can include a spin on hard mask (SOH) material, such as a silicon hard mask material, a carbon hard mask material, and an organic hard mask material, etc.
[0086] As shown in Figure 5 The planarization layer 510 covers the surface of the first patterned oxide hard mask layer 340 and fills the first openings 341 in the first patterned oxide hard mask layer 340.
[0087] In a specific implementation, the process of forming the planarization layer 510 can be a chemical vapor deposition method or a physical vapor deposition method.
[0088] Continuing to refer to Figure 2 In step S205, a second patterned oxide hard mask layer is formed on the planarization layer, the second patterned oxide hard mask layer defining a pattern of vias.
[0089] Specifically, referring to Figure 6a A second oxide hard mask layer 610, an anti-reflection layer 620, and a second patterned photoresist layer 630 are sequentially formed on the planarization layer 510, the second patterned photoresist layer 630 defining a pattern of rectangular vias.
[0090] The material of the second oxide hard mask layer 610 can be silicon oxide, which can include one layer of silicon oxide or multiple layers of different silicon oxide. In the embodiment of the present application, the second oxide hard mask layer 610 can include a low temperature oxide (LTO) hard mask layer 611 and an organic dielectric coating (ODC) layer 612 formed on the low temperature oxide (LTO) hard mask layer 611, wherein the low temperature oxide (LTO) hard mask layer 611 can act as a stop layer for subsequent etching of the second oxide hard mask layer 610.
[0091] Referring to Figure 6b The second oxide hard mask layer 610 is etched to form a second patterned oxide hard mask layer 650 on the planarization layer 510.
[0092] In a specific implementation, the ODC layer 612 in the second oxide hard mask layer 610 is etched to expose the low temperature oxide (LTO) hard mask layer 611 along the rectangular via pattern, and an opening 631 is formed in the ODC layer 612 at a position corresponding to the rectangular via pattern, so that the rectangular via pattern is transferred to the second oxide hard mask layer 610.
[0093] In actual applications, in order to achieve better lithography effect and better transfer of the rectangular via pattern, referring to Figure 6b In addition, an organic planarization layer (not shown in the figure) can be formed between the second oxide hard mask layer 610 and the anti-reflective layer 620. In this case, the anti-reflective layer 620, the organic planarization layer, and the second oxide hard mask layer 610 are etched in sequence to transfer the rectangular via pattern to the second oxide hard mask layer 610.
[0094] Referring to Figure 6c The remaining second patterned photoresist layer 630 and the remaining anti-reflective layer 620 are removed, and a second patterned oxide hard mask layer 650 formed on the planarization layer 510 is obtained.
[0095] It can be understood that when the organic planarization layer is formed, the remaining organic planarization layer is also removed when the remaining second patterned photoresist layer 630 and the remaining anti-reflective layer 620 are removed.
[0096] In a specific implementation, wet etching or plasma dry etching process can be used to remove the remaining second patterned photoresist layer 630, the remaining anti-reflective layer 620, and the remaining organic planarization layer.
[0097] In the embodiment, the etching process for forming the second patterned oxide hard mask layer 650 can be a plasma dry etching process.
[0098] With reference back to Figure 2 In step S207, the pattern of the via defined in the second patterned oxide hard mask layer is transferred to the metal hard mask layer to form a first patterned metal hard mask layer.
[0099] With reference back to Figure 7a The second patterned oxide hard mask layer 650 is used as a mask, and the planarization layer 510 is etched based on the first etching process until the upper surface of the metal hard mask layer 330 is exposed.
[0100] The first etching process can be a plasma dry etching process suitable for etching oxide. In a specific implementation, the second patterned oxide hard mask layer 650 is used as a mask, and etching gas CF4, CHF3, or CH2F2 is introduced, assisted by dilution gas CO, He, or Ar, to etch each layer in turn along the pattern of the rectangular via in the second patterned oxide hard mask layer 650 until the upper surface of the metal hard mask layer 330 is exposed to stop, thereby transferring the pattern of the rectangular via to the planarization layer 510 on the top surface of the metal hard mask layer 330.
[0101] Next, with reference to Figure 7b The exposed metal hard mask layer 330 is etched based on the second etching process and stopped at the etching stop layer 350 to form a second opening 701 that penetrates the metal hard mask layer 330 in the defined region corresponding to the rectangular via of the metal hard mask layer 330, and the size of the second opening 701 is smaller than the size of the first opening 341, thereby forming a first patterned metal hard mask layer 710.
[0102] The second etching process can be a plasma dry etching process suitable for etching metal. In a specific implementation, the second patterned oxide hard mask layer 650 is used as a mask, and etching gas CF4 is introduced to etch the exposed metal hard mask layer 330 and stop at the etching stop layer 350, thereby forming a second opening 701 that penetrates the metal hard mask layer 330 in the defined region corresponding to the rectangular via of the metal hard mask layer 330, and further transferring the pattern of the rectangular via to the metal hard mask layer 330.
[0103] Next, with reference to Figure 7cThe second patterned oxide hard mask layer 650 and planarization layer 510 are removed. Specifically, wet etching or plasma dry etching processes can be used to remove the second patterned oxide hard mask layer 650 and planarization layer 510. It is understood that since the size of the first opening 341 is larger than the size of the second opening 701, after removing the planarization layer 510, the first opening 341 will expose part of the remaining metal hard mask layer.
[0104] like Figure 8 The diagram shows a planar schematic of the rectangular via pattern in the first patterned metal hard mask layer 710. Since the metal hard mask layer 330 has better critical dimension control capabilities, it effectively limits the expansion of critical dimensions in the non-self-aligned direction, thereby expanding the process window of the rectangular via.
[0105] See also Figure 2 In step S209: Based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer, trenches and vias are formed in the interlayer dielectric layer, wherein the bottom of the trenches is connected to the top of the vias.
[0106] In this structure, the trenches and vias in the interlayer dielectric layer form a dual damascene structure, and the vias can expose the underlying metal layer.
[0107] For details, see Figure 9a Using the first patterned oxide hard mask layer 340 as a mask, the remaining metal hard mask layer exposed in the first opening 341 is etched to obtain the second patterned metal hard mask layer 910 with the groove pattern 901 formed.
[0108] During the etching process of the remaining metal hard mask layer exposed in the first opening 341, the etching stop layer 350 and part of the interlayer dielectric layer 320 exposed by the second opening 701 in the first patterned metal hard mask layer 710 are etched, forming a partial rectangular via 902 in the interlayer dielectric layer 320.
[0109] like Figure 10 The figure shows a schematic diagram of a portion of the rectangular vias formed in the interlayer dielectric layer. As can be seen from the figure, the key dimensions of the portion of the rectangular vias 902 in the interlayer dielectric layer 320 are precisely controlled in both the self-aligned and non-self-aligned directions.
[0110] Next, see Figure 9b Using the first patterned oxide hard mask layer 340 and the second patterned metal hard mask layer 910 as masks, the interlayer dielectric layer 320 is etched along the trench pattern 901 and part of the rectangular via 902 until the bottom metal layer 310 is exposed, resulting in trenches 903 and rectangular vias 904 formed in the interlayer dielectric layer 320.
[0111] The process of forming the trench 903 and the rectangular via 904 can be a dry etching process.
[0112] In one embodiment, after forming the trench 903 and the rectangular via 904 in the ILD layer 320, the method can further include: Figure 11 In one embodiment, after removing the first patterned oxide hard mask layer 340 and the remaining metal hard mask layer, the method can further include filling a conductive material (not shown) into the trench 903 and the rectangular via 904.
[0113] The process of removing the first patterned oxide hard mask layer 340 and the remaining metal hard mask layer can be a dry etching process or a wet etching process.
[0114] In one embodiment, after removing the first patterned oxide hard mask layer 340 and the remaining metal hard mask layer, the method can further include filling a conductive material (not shown) into the trench 903 and the rectangular via 904.
[0115] Specifically, the conductive material can be copper, and the conductive material can be deposited by a physical vapor deposition process. In other examples, the conductive material can be deposited by an electrochemical plating process or a chemical vapor deposition process.
[0116] In one embodiment, before depositing the conductive material, a barrier layer (not shown) and a seed layer (not shown) can be sequentially formed on the inner surface of the trench 903 and the rectangular via 904, and then the conductive material is deposited on the seed layer. The barrier layer can be titanium nitride, and the barrier layer can prevent the conductive material from diffusing into the adjacent ILD layer 320. The barrier layer can be formed by a physical vapor deposition process. The seed layer can be the same material as the conductive material, and the seed layer can enhance the adhesion between the conductive material and the barrier layer. The seed layer can be formed by a sputtering process or a chemical vapor deposition process.
[0117] In one embodiment, the photolithography process in the forming method can be a deep ultraviolet (DUV) photolithography process, which can include a non-immersion ultraviolet photolithography process and an immersion ultraviolet photolithography process.
[0118] The embodiment of the present application provides a substrate, a metal hard mask layer in the substrate is not etched, a first patterned oxide hard mask layer defining a trench pattern is formed on the metal hard mask layer, then a planarization layer is formed on the first patterned oxide hard mask layer, and a second patterned oxide hard mask layer defining a via pattern is formed on the planarization layer, then the pattern of the via defined in the second patterned oxide hard mask layer is transferred to the metal hard mask layer to form a first patterned metal hard mask layer, and then based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer, a dual damascene structure with a trench and a via is formed in an interlayer dielectric layer of the substrate, so that the etching of the metal hard mask layer is performed after the second patterned oxide hard mask layer is formed, thereby well controlling the critical dimension of the via in a non-self-aligned direction by using the metal hard mask layer, improving the control accuracy of the critical dimension of the via in the non-self-aligned direction such as a rectangular via, expanding the process window of the via, and avoiding bridging between the via and the bottom metal layer, thereby improving the performance of the semiconductor device.
[0119] The embodiment of the present application also provides a semiconductor structure formed based on the foregoing forming method, as shown in the figure, the semiconductor structure 1200 comprises: Figure 12
[0120] a semiconductor substrate 1210, and a bottom metal layer 1201 formed in the semiconductor substrate 1210;
[0121] an interlayer dielectric layer 1202 formed on the surface of the semiconductor substrate 1210 and covering the bottom metal layer 1201;
[0122] a trench 1203 and a via 1204 formed in the interlayer dielectric layer 1202, the bottom of the trench 1203 is in communication with the top of the via 1204.
[0123] Specifically, the via 1204 can expose the bottom metal layer 1201.
[0124] In one specific embodiment, the semiconductor structure of the embodiment of the present application further comprises: a conductive material 1206 filled in the trench 1203 and the via 1204.
[0125] In one specific embodiment, an etching stop layer 1205 can also be formed on the interlayer dielectric layer 1202, the trench 1203 penetrates through the etching stop layer 1205 and extends into the interlayer dielectric layer 1202.
[0126] In one specific embodiment, the above-mentioned via 1204 of the semiconductor structure 1200 can be a via with different length and width critical dimensions, for example, a rectangular via.
[0127] The via in the semiconductor structure of the embodiment of the present application is well controlled in the self-alignment direction and the non-self-alignment direction, thereby improving the performance of the semiconductor structure.
[0128] Correspondingly, the embodiment of the present application further provides an electronic device, which comprises the semiconductor structure formed based on the forming method of any one of the aforementioned semiconductor structures.
[0129] Since the semiconductor structure has better working performance, the electronic device adopting the semiconductor structure has improved performance. The electronic device can be any electronic product or equipment, such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or an intermediate product having the semiconductor structure, such as a device mainboard having the semiconductor structure.
[0130] Although the present application has been disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope of the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a bottom metal layer, an interlayer dielectric layer, a metal hard mask layer and a first patterned oxide hard mask layer stacked together; The first patterned oxide hard mask layer has a plurality of first openings that expose the upper surface of the metal hard mask layer, and the plurality of first openings indicate a pattern for forming trenches of the metal hard mask layer; A planarization layer is formed on the first patterned oxide hard mask layer, the planarization layer filling a plurality of the first openings and covering the upper surface of the first patterned oxide hard mask layer; A second patterned oxide hard mask layer is formed on the planarization layer, wherein a pattern of vias is defined in the second patterned oxide hard mask layer; The pattern of the vias defined in the second patterned oxide hard mask layer is transferred to the metal hard mask layer to form the first patterned metal hard mask layer; Based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer, the trench and the via are formed in the interlayer dielectric layer; the bottom of the trench is connected to the top of the via.
2. The forming method according to claim 1, characterized in that, An etching stop layer is formed between the interlayer dielectric layer and the metal hard mask layer; the step of transferring the pattern of vias defined in the second patterned oxide hard mask layer to the metal hard mask layer to form the first patterned metal hard mask layer includes: Using the second patterned oxide hard mask layer as a mask, the planarization layer is etched using the first etching process until the upper surface of the metal hard mask layer is exposed. The exposed metal hard mask layer is etched using a second etching process, and the etching stops at the etching stop layer to form a second opening penetrating the metal hard mask layer in the defined region corresponding to the via in the metal hard mask layer. The size of the second opening is smaller than the size of the first opening. Remove the second patterned oxide hard mask layer and the planarization layer.
3. The forming method according to claim 2, characterized in that, The method of forming the trench and the via in the interlayer dielectric layer based on the first patterned oxide hard mask layer and the first patterned metal hard mask layer includes: Using the first patterned oxide hard mask layer as a mask, the remaining metal hard mask layer exposed in the first opening is etched to obtain a second patterned metal hard mask layer with the trench pattern formed thereon; wherein, during the etching process, the etching stop layer and part of the interlayer dielectric layer exposed by the second opening in the first patterned metal hard mask layer are etched to form a partial via in the interlayer dielectric layer; Using the first patterned oxide hard mask layer and the second patterned metal hard mask layer as masks, the interlayer dielectric layer is etched along the trench pattern and the partial vias until the underlying metal layer is exposed, thereby obtaining the trenches and vias formed in the interlayer dielectric layer.
4. The forming method according to claim 2, characterized in that, The method further includes: A semiconductor substrate is provided, wherein the underlying metal layer is formed in the semiconductor substrate; An interlayer dielectric layer and an etch stop layer are sequentially formed on the surface of the semiconductor substrate, wherein the interlayer dielectric layer covers the underlying metal layer; A metal hard mask layer is formed on the etching stop layer; A first oxide hard mask layer is formed on the metal hard mask layer; A first patterned photoresist layer is formed on the first oxide hard mask layer; the first patterned photoresist layer defines a pattern for forming the trenches of the metal hard mask layer; Using the first patterned photoresist layer as a mask, the first oxide hard mask layer is etched until the upper surface of the metal hard mask layer is exposed; The remaining first patterned photoresist layer is removed to obtain the substrate.
5. The forming method according to claim 1, characterized in that, The formation of a second patterned oxide hard mask layer on the planarization layer includes: A second oxide hard mask layer, an anti-reflection layer, and a second patterned photoresist layer are sequentially formed on the planarization layer; the second patterned photoresist layer defines the pattern of the vias. Using the second patterned photoresist layer as a mask, the anti-reflection layer and the second oxide hard mask layer are etched sequentially. Remove the remaining second patterned photoresist layer and the remaining anti-reflective layer to obtain the second patterned oxide hard mask layer.
6. The forming method according to claim 1, characterized in that, After forming the trench and the via in the interlayer dielectric layer, the method further includes: Remove the first patterned oxide hard mask layer and the remaining metal hard mask layer.
7. The forming method according to claim 6, characterized in that, After removing the first patterned oxide hard mask layer and the remaining metal hard mask layer, the method further includes: The trench and the through hole are filled with conductive material.
8. The forming method according to any one of claims 1-7, characterized in that, The photolithography process in the formation method is deep ultraviolet photolithography.
9. The forming method according to any one of claims 1-7, characterized in that, The critical dimension of the length of the through hole is different from the critical dimension of its width.
10. A semiconductor structure, characterized in that, Formed using any one of the forming methods as described in claims 1-9, comprising: A semiconductor substrate, wherein a bottom metal layer is formed in the semiconductor substrate; An interlayer dielectric layer formed on the surface of the semiconductor substrate and covering the underlying metal layer; Trenches and vias formed in the interlayer dielectric layer; the bottom of the trench is connected to the top of the via.
11. The semiconductor structure according to claim 10, characterized in that, Also includes: Conductive material filling the trenches and through holes.
12. The semiconductor structure according to claim 10, characterized in that, An etch stop layer is also formed on the interlayer dielectric layer, and the trench penetrates the etch stop layer and extends into the interlayer dielectric layer.
13. The semiconductor structure according to any one of claims 10-12, characterized in that, The critical dimensions of the length of the through hole are different from those of its width.
14. An electronic device, characterized in that, The electronic device includes a semiconductor structure formed using the formation method as described in any one of claims 1 to 9.
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