Power module and electronic equipment

Abstract

The embodiment of the invention provides a substrate, a packaging structure and electronic equipment. The substrate is used for being electrically connected with a chip, the chip comprises a power terminal and a signal terminal, the substrate comprises a first substrate and a second substrate installed on the first substrate, the first substrate comprises a first wire, the first wire is used for being electrically connected with the power terminal, the second substrate comprises a second wire, and the second wire is used for being electrically connected with the signal terminal. The second wires are used for being electrically connected with the signal terminals, and the distance between the lines of the second wires is smaller than the distance between the lines of the first wires. The substrate provided by the invention is small in size and high in integration level.

Description

[0001] This application is a divisional application. The application number of the original application is 202080015414.5, the original application date is September 25, 2020, and the entire content of the original application is incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic technologies, and particularly to a substrate, a packaging structure, and an electronic device. Background Art

[0003] Metal substrates are widely used in high-power module packaging, such as Direct Bond Ceramic (DBC), Active Metal Brazing (AMB), and Direct Bond Aluminum (DBA). Metal substrates have good heat dissipation and high current-carrying capacity. In a package, the metal substrate functions to connect internal and external circuits, provide mechanical support, and provide electrical insulation. However, the existing metal substrates are relatively large in size. Summary of the Invention

[0004] Embodiments of this application provide a substrate, a packaging structure including the substrate, and an electronic device including the packaging structure, aiming to obtain a substrate and a packaging structure with small size and high integration, as well as an electronic device with a relatively small size while achieving good electrical performance.

[0005] In a first aspect, an embodiment of this application provides a substrate for electrically connecting to a chip. The chip includes a power terminal and a signal terminal. The substrate includes a first substrate and a second substrate mounted on the first substrate. The first substrate includes a first wiring for electrically connecting to the power terminal, and the second substrate includes a second wiring for electrically connecting to the signal terminal. The pitch between the lines of the second wiring is smaller than the pitch between the lines of the first wiring.

[0006] The substrate of this application includes a first substrate and a second substrate. The first wiring (power line) for connecting to the power terminal of the chip is formed on the first substrate, and the second wiring (signal line) for connecting to the signal terminal of the chip is formed on the second substrate. That is to say, the power line and the signal line of this application are respectively disposed on two different boards. Compared with the scheme of integrating the power line and the signal line on one board, the pitch between the lines of the second wiring can be made smaller than the pitch between the lines of the first wiring, which is beneficial to the miniaturization of the substrate, thereby improving the integration of the packaging structure, reducing the production cost, and saving the internal space of the electronic device.

[0007] In some embodiments, the first substrate includes a first metal layer, and the first wiring is formed on the first metal layer. The second substrate includes a second metal layer, and the second wiring is formed on the second metal layer. The thickness of the second metal layer is less than that of the first metal layer, so as to ensure that the pitch between the lines of the second wiring formed on the second metal layer can be made smaller than the pitch between the lines of the first wiring, so that the lines of the second wiring are more dense, which is beneficial to reducing the volume of the second substrate, realizing the miniaturization of the substrate, and improving the integration degree of the packaging structure. Of course, in other embodiments, the thickness of the second metal layer may be equal to or greater than that of the first metal layer, as long as the pitch between the lines of the second wiring formed on the second metal layer is less than the pitch between the lines of the first wiring formed on the first metal layer.

[0008] In some embodiments, the thickness of the second metal layer is 0.035 mm to 2 mm. By limiting the thickness of the second metal layer to 0.035 mm to 2 mm, it is ensured that the thickness of the second metal layer is thin enough, so that when the second wiring is formed on the second metal layer, the pitch between the lines of the second wiring can be small enough, that is, it is ensured that the second metal layer can be etched at a high density, so that the lines of the second wiring can be made more dense, which is beneficial to reducing the volume of the second substrate, realizing the miniaturization of the substrate, and improving the integration degree of the packaging structure.

[0009] In some embodiments, the pitch between two adjacent lines in the lines of the second wiring is 0.1 mm to 0.5 mm. By limiting the pitch between two adjacent lines in the lines of the second wiring to 0.1 mm to 0.5 mm, it can be ensured that the pitch between the lines of the second wiring is small enough, so as to ensure that the lines of the second wiring are dense enough, further reducing the volume of the second substrate, realizing the miniaturization of the substrate, and improving the integration degree of the packaging structure.

[0010] In some embodiments, the first metal layer includes a relief groove, and at least a part of the second substrate is embedded in the relief groove. That is to say, at least a part of the second substrate in this embodiment is embedded in the first substrate, which not only reduces the planar size of the substrate, but also reduces the size of the substrate in the thickness direction, further improving the integration degree of the substrate.

[0011] In some embodiments, the first substrate includes a carrier plate, the first metal layer is disposed on the carrier plate, and the surface of the second wiring facing away from the carrier plate is flush with the surface of the first metal layer facing away from the carrier plate. That is to say, the surface of the second wiring layer is flush with the surface of the first wiring layer. Thus, when the chip is disposed on the substrate, the chip can be flip-chip bonded to the substrate. The part of the chip having power terminals can be disposed on the first substrate and electrically connected to the first wiring, and the part of the chip having signal terminals is disposed on the second substrate and electrically connected to the second wiring, avoiding the connection between the signal terminals and the second wiring through a wire, simplifying the manufacturing steps of the packaging structure, and improving the production efficiency of the packaging structure.

[0012] In some embodiments, the second substrate further includes an insulating plate, the second wiring is disposed on the insulating plate, and one side of the insulating plate facing away from the second wiring is connected to the surface of the first wiring. By mounting the second substrate on the first substrate, it is beneficial to reduce the planar area of the entire substrate and improve the integration degree of the substrate and the packaging structure.

[0013] In some embodiments, the second substrate includes an insulating plate, the second wiring is disposed on the insulating plate, the first substrate includes a carrier plate, the first wiring is disposed on the carrier plate, the side edge of the insulating plate is connected to the side edge of the carrier plate, and the first wiring and the second wiring are spaced apart. Compared with the second substrate being welded to the surface of the first metal layer, the area of the welding surface where the side edge of the insulating plate is connected to the side edge of the carrier plate is smaller, the corresponding process cost is reduced, and the insulating plate can be welded to any side edge of the carrier plate, making the design more flexible.

[0014] In some embodiments, the first substrate further includes a third metal layer, and the third metal layer is disposed on the surface of the carrier plate facing away from the first wiring. The material of the third metal layer is copper. Of course, the third metal layer can also be other metal materials such as aluminum and nickel or non-metal materials. The third metal layer is used to conduct the heat transferred from the chip to the first wiring out, so that the chip dissipates heat faster, ensuring the electrical performance of the chip. At the same time, the third metal layer can also enhance the strength of the entire substrate.

[0015] In some embodiments, the second substrate further includes a fourth metal layer, and the fourth metal layer is disposed on the surface of the insulating plate facing away from the second wiring. The fourth metal layer is used to conduct the heat transferred from the chip to the first wiring out, so that the chip dissipates heat faster, ensuring the electrical performance of the chip. At the same time, the fourth metal layer can also enhance the strength of the second substrate.

[0016] In some embodiments, there are multiple second substrates, and the multiple second substrates are installed on the first substrate at intervals and are respectively arranged close to the chips electrically connected thereto. This is equivalent to arranging the second wiring originally provided on one board on two boards respectively, so that the second substrate can be made smaller, and the two second substrates can be respectively arranged at different positions according to the chips electrically connected thereto, with more flexible layout and easier control of the stress of the packaging structure.

[0017] In a second aspect, an embodiment of the present application further provides a packaging structure, which includes a chip and the above-mentioned substrate. The chip includes a power terminal and a signal terminal. The chip is arranged on the first wiring, the power terminal is electrically connected to the first wiring, and the signal terminal is electrically connected to the second wiring. The integration degree, heat dissipation performance and electrical performance of the packaging structure with the substrate provided by the present application are effectively improved.

[0018] In some embodiments, the signal terminal is electrically connected to the second wiring through a wire; or the signal terminal is electrically connected to the second wiring through a pad. When the second substrate is installed on the first wiring layer of the first substrate, the signal terminal is electrically connected to the second wiring through a wire. When the second substrate is embedded in the first substrate or the second substrate is connected to the side of the first substrate, the chip can be flip-chip bonded on the first substrate and the second substrate, and the signal terminal is electrically connected to the second wiring through a pad, avoiding the connection between the signal terminal and the second wiring through a wire, simplifying the manufacturing steps of the packaging structure, and improving the production efficiency of the packaging structure.

[0019] In some embodiments, the packaging structure includes a third substrate, and the third substrate includes a third wiring. The distance between the lines of the third wiring is smaller than the distance between the lines of the first wiring, and the third wiring is connected between the signal terminal and the second wiring. That is to say, the third substrate can be understood as an adapter board between the chip and the second wiring, so that the electrical connection relationship between multiple chips and the second wiring is more concise. Of course, in other embodiments, the chip can also be directly electrically connected to the second wiring.

[0020] In some embodiments, the packaging structure includes an electronic component, and the electronic component is arranged on the third substrate and electrically connected to the third wiring. The electronic component is used to assist the third wiring in the circuit transfer between the chip and the second wiring.

[0021] In a third aspect, an embodiment of the present application further provides an electronic device, which includes a circuit board and the above-mentioned packaging structure, and the packaging structure is electrically connected to the circuit board. The integration degree, heat dissipation performance and electrical performance of the electronic device with the packaging structure provided by the present application are effectively improved.

[0022] The substrate of the present application includes a first substrate and a second substrate. A first wiring (power line) for connecting to the power terminals of the chip is formed on the first substrate, and a second wiring (signal line) for connecting to the signal terminals of the chip is formed on the second substrate. That is to say, the power line and the signal line of the present application are respectively disposed on two different boards. Compared with the solution of integrating the power line and the signal line on one board, the spacing between the lines of the second wiring can be made smaller than the spacing between the lines of the first wiring, which is beneficial to the miniaturization of the substrate, thereby improving the integration degree of the packaging structure, reducing the production cost, and saving the internal space of the electronic device. Description of the Drawings

[0023] Figure 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

[0024] Figure 2 is Figure 1 a partial structural schematic diagram of the packaging structure of the power device packaging shown;

[0025] Figure 3 is Figure 2 a schematic structural diagram of a first embodiment of the substrate of the packaging structure shown;

[0026] Figure 4 a schematic structural diagram of a substrate in the related art;

[0027] Figure 5 is Figure 3 a schematic cross-sectional structure diagram of the substrate in the A-A direction shown;

[0028] Figure 6 is Figure 2 a schematic structural diagram of the combination of the substrate and the lead frame shown;

[0029] Figure 7 is Figure 3 a structural diagram of a second embodiment of the substrate shown;

[0030] Figure 8 is Figure 3 a structural diagram of a third embodiment of the substrate shown;

[0031] Figure 9 is Figure 8 a schematic cross-sectional structure diagram of the substrate shown;

[0032] Figure 10 is Figure 8 a schematic structural diagram of the combination of the substrate and the chip shown;

[0033] Figure 11 is Figure 10 a schematic cross-sectional structure diagram of the substrate shown;

[0034] Figure 12 Is Figure 3 The structural diagram of the fourth embodiment of the substrate shown;

[0035] Figure 13 Is Figure 12 The schematic cross-sectional structure diagram of the substrate shown. Detailed implementation manners

[0036] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application.

[0037] Please refer to Figure 1 , Figure 1 Is the structural diagram of an electronic device 100 provided by an embodiment of the present application.

[0038] The electronic device 100 includes a package structure 1, a circuit board 2, and a housing 3. The package structure 1 is mounted on the circuit board 2 and is electrically connected to the circuit board 2 to control the operation of the package structure 1 through the circuit board 2. Both the package structure 1 and the circuit board 2 are housed inside the housing 3. The package structure 1 is the power module of the electronic device 100 and is used to realize the conversion of electrical signals of the electronic device 100. The electronic device 100 in this embodiment includes, but is not limited to, electronic devices 100 such as wind turbines, photovoltaic generators, electric vehicles, and white household appliances that have the package structure 1. The integration degree, heat dissipation performance, and electrical performance of the electronic device 100 with the package structure 1 provided by the present application are effectively improved.

[0039] Please refer to Figure 2 , Figure 2 Is Figure 1 The package structure of the electronic device 100 shown. Some structural diagrams of this package structure can be power switch devices, such as rectification, inversion, power factor correction, etc.

[0040] The package structure 1 includes a substrate 10 and a chip 20. The chip 20 is disposed on the substrate 10. The chip 20 includes a power terminal and a signal terminal. The power terminal is an electrode such as the collector (source) and emitter (drain) of the chip 20 that bears high-power high-voltage signals, and the signal terminal is an electrode such as the control gate (gate) switch of the chip 20 that bears low-power low-voltage signals. The power terminal of the chip 20 is electrically connected to a part of the substrate 10, and the signal terminal of the chip 20 is electrically connected to another part of the substrate 10 to be electrically connected to other devices through the substrate 10. In this embodiment, the package structure 1 includes, but is not limited to, various power converters such as DC-DC converters and DC-AC converters. The integration degree, heat dissipation performance, and electrical performance of the package structure 1 with the substrate 10 provided by the present application are effectively improved.

[0041] The encapsulation structure 1 may further include an encapsulation body (not shown in the figure) and a heat sink (not shown in the figure). The encapsulation body is encapsulated on one side of the substrate 10 where the chip 20 is provided, so as to encapsulate devices such as the chip 20 on the substrate 10. The heat sink is connected to the side of the substrate 10 facing away from the chip 20 to dissipate heat from the electronic devices such as the chip 20 encapsulated in the encapsulation body, and ensure the electrical performance of devices such as the chip 20.

[0042] In some embodiments, some structures with control functions are also integrated inside the encapsulation body. For example, a control device carrying a control circuit is electrically connected to the chip 20 and can control the operation of the chip 20. For safety and reliability, the temperature state of the encapsulation structure 1 is monitored in real time. For example, a temperature sensor can be integrated in the encapsulation structure 1. If the temperature is too high or the temperature rise is too fast, it indicates that there is a danger in the circuit, and preventive actions such as turning off the power can be taken in advance.

[0043] Please refer to Figure 2 and Figure 3 , Figure 3 is Figure 2 the schematic structural diagram of the first embodiment of the substrate 10 of the encapsulation structure 1 shown.

[0044] The substrate 10 includes a first substrate 11 and a second substrate 12. The second substrate 12 is mounted on the first substrate 11. The first substrate 11 includes a first wiring 111, and the second substrate 12 includes a second wiring 121. The spacing between the lines of the second wiring 121 is smaller than the spacing between the lines of the first wiring 111. That is to say, the lines of the second wiring 121 are arranged more densely than the lines of the first wiring 111. The chip 20 is provided on the first wiring 111. The power terminals are electrically connected to the first wiring 111, and the signal terminals are electrically connected to the second wiring 121.

[0045] It can be understood that the lines on the substrate are usually formed by etching, such as Figure 4 In the related art, the lines formed on the substrate 10a include both power lines 111a for connecting to the power terminals of the chip and signal lines 121a for connecting to the signal terminals of the chip. Since the line width of the power lines 111a needs to meet the requirements of high voltage and large current, the metal layer for forming the lines on the substrate 10a needs to be made relatively thick. However, the thick metal layer is more affected by the etching process. It is necessary to consider the width difference between the top and bottom of the lines formed by etching during the etching process of the thick metal layer. Specifically, the etching process corrodes the metal layer to form grooves separating the lines. During the corrosion process, since the acid starts to corrode from the surface of the metal layer, and the side walls of the lines are also affected by the etching solution, the top of the lines is corroded wider and the bottom is corroded narrower. The difference between the top and bottom of the formed lines is proportional to the thickness of the metal layer (etching factor). The thicker the metal layer, the greater the absolute width difference between the top and bottom of the lines.

[0046] To ensure the minimum distance at the bottom of the circuit and the effective width at the top of the circuit, when the metal layer is etched, the size of the metal layer has to be relatively enlarged to ensure the effective area and width at the top of the circuit. That is to say, the size of the substrate 10a has to be relatively enlarged to ensure the effective area and width at the top of the circuit. However, the signal circuit 121a does not have requirements for high voltage and large current. Since the signal circuit 121a is also formed on a relatively thick metal layer, the distance L1 between the circuits of the signal circuit 121a cannot be reduced either, resulting in the circuit density of the signal circuit 121a being limited, which is not conducive to the miniaturization of the volume of the substrate 10a and is also not conducive to the improvement of the heat dissipation efficiency of the substrate 10a.

[0047] The substrate 10 of the present application includes a first substrate 11 and a second substrate 12. The first wiring 111 (power circuit) for connecting to the power terminals of the chip 20 is formed on the first substrate 11, and the second wiring 121 (signal circuit) for connecting to the signal terminals of the chip 20 is formed on the second substrate 12. That is to say, the power circuit and the signal circuit of the present application are respectively arranged on two different boards. Compared with the solution of integrating the power circuit and the signal circuit on one board, the distance L2 between the circuits of the second wiring 121 can be made smaller than the distance between the circuits of the first wiring 111, which is conducive to the miniaturization of the substrate 10, thereby improving the integration degree of the packaging structure 1, reducing the production cost, and saving the internal space of the electronic device 100.

[0048] At the same time, while the first substrate 11 is used for electrically connecting to the power terminals of the chip 20, it also dissipates heat from the chip 20 and plays a supporting role for devices such as the chip 20. The second substrate 12 is used for electrically connecting to the signal terminals of the chip 20 to achieve the electrical connection between the chip 20 and the external lead frame or pins. By forming the first wiring 111 and the second wiring 121 on the first substrate 11 and the second substrate 12 respectively, the first substrate 11 and the second substrate 12 are also functionally differentiated, which is conducive to the optimization of the functional layout of the substrate 10. And the second wiring 121 is not formed on the first substrate 11, which is conducive to optimizing the distribution of the first wiring 111 on the first substrate 11. Compared with forming the first wiring 111 and the second wiring 121 on the first substrate 11 at the same time, forming only the first wiring 111 on the first substrate 11 reduces the number of grooves on the first substrate 11 to a certain extent. Relatively, it increases the metal area of the first substrate 11 and optimizes the static and dynamic heat dissipation performance of the packaging structure 1.

[0049] Such as Figure 2, in this embodiment, the number of chips 20 is eight, and the eight chips 20 are arranged in parallel and spaced apart in pairs on the first wiring 111. The chips 20 can be, for example, power chips such as insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and / or diodes, or other non-power chips. The metal oxide semiconductor field effect transistor can be a silicon-based metal oxide semiconductor field effect transistor, or a silicon carbide or gallium nitride-based metal oxide semiconductor field effect transistor. The chips 20 can be fixed on the first wiring 111 by connection methods such as welding and bonding. In other embodiments, the arrangement of the chips 20 is not limited to the above description. The chips 20 can also be one or more than eight.

[0050] Please refer to Figure 3 and Figure 5 , Figure 5 is Figure 3 a schematic cross-sectional structure diagram of the substrate 10 in the A-A direction shown in the figure.

[0051] In this embodiment, the first substrate 11 includes a first metal layer 112, a carrier plate 113, and a third metal layer 114. The first metal layer 112 is disposed on the insulating and heat-conducting carrier plate 113, and the third metal layer 114 is disposed on the surface of the carrier plate 113 facing away from the first metal layer 112. It can be understood that the first metal layer 112 and the third metal layer 114 are respectively disposed on two opposite surfaces of the carrier plate 113. The substrate 10 can be formed by electroplating, crimping, or welding the first metal layer 112 and the third metal layer 114 on two opposite surfaces of the carrier plate 113 respectively. The first wiring 111 is formed on the first metal layer 112, that is, the third metal layer 114 is disposed on the surface of the carrier plate 113 facing away from the first wiring 111, and the chips 20 ( Figure 2 ) are disposed on the first metal layer 112. The first metal layer 112 forms the first wiring 111 through an etching process. Of course, in other embodiments, the first substrate may only include the first metal layer and the carrier plate.

[0052] The material of the first metal layer 112 is copper. Of course, the first metal layer 112 can also be other metal materials such as aluminum and nickel. On the one hand, the first metal layer 112 forms an electrical connection between the first wiring 111 and the chip 20. On the other hand, it can also dissipate heat from the chip 20, so that the heat of the chip 20 is transferred out through the first wiring 111, ensuring the electrical performance of the chip 20. The material of the third metal layer 114 is copper. Of course, the third metal layer 114 can also be other metal materials or non-metal materials such as aluminum and nickel. The third metal layer 114 is used to conduct the heat transferred from the chip 20 to the first wiring 111, enabling the chip 20 to dissipate heat faster, ensuring the electrical performance of the chip 20, and at the same time, the third metal layer 114 can also enhance the strength of the entire substrate 10. The material of the carrier plate 113 is ceramic. The ceramic can be, for example, ceramic materials such as alumina, silicon nitride, aluminum nitride, or reinforced aluminum nitride. The carrier plate 113 is used to achieve electrical isolation and electromagnetic shielding between the first metal layer 112 and the third metal layer 114, and reflect external electromagnetic interference, thereby avoiding external electromagnetic radiation from interfering with the normal operation of the chip 20 and reducing the interference of electromagnetic radiation in the surrounding environment on the electronic components in the packaging structure 1.

[0053] The second substrate 12 includes a second metal layer 122, an insulating plate 123, and a fourth metal layer 124. The second metal layer 122 is disposed on the insulating plate 123, and the fourth metal layer 124 is disposed on the surface of the insulating plate 123 facing away from the second metal layer 122. It can be understood that the second metal layer 122 and the fourth metal layer 124 are respectively disposed on two opposite surfaces of the insulating plate 123. The substrate 10 can be formed by electroplating, pressing, or welding the second metal layer 122 and the fourth metal layer 124 on two opposite surfaces of the insulating plate 123 respectively. The second wiring 121 is formed on the second metal layer 122, that is, the fourth metal layer 124 is disposed on the surface of the insulating plate 123 facing away from the second wiring 121. The second metal layer 122 forms the second wiring 121 through an etching process. In this embodiment, the line of the second wiring 121 is a pad. Of course, in other embodiments, the line of the second wiring 121 can also be other structures such as traces. Alternatively, the second substrate 12 can also only include an insulating plate and a second metal layer.

[0054] In this embodiment, the thickness of the second metal layer 122 is less than that of the first metal layer 112, so as to ensure that the pitch between the lines of the second wiring 121 formed on the second metal layer 122 can be made smaller than the pitch between the lines of the first wiring 111, so that the lines of the second wiring 121 are more dense, which is beneficial to reducing the volume of the second substrate 12, realizing the miniaturization of the substrate 10, and improving the integration degree of the packaging structure 1. Of course, in other embodiments, the thickness of the second metal layer 122 may be equal to or greater than the thickness of the first metal layer 112, as long as the pitch between the lines of the second wiring 121 formed on the second metal layer 122 is less than the pitch between the lines of the first wiring 111 formed on the first metal layer 112.

[0055] Specifically, the thickness of the second metal layer 122 is 0.035 mm to 2 mm. By limiting the thickness of the second metal layer 122 to 0.035 mm to 2 mm, it is ensured that the thickness of the second metal layer 122 is thin enough, so that when the second wiring 121 is formed on the second metal layer 122, the pitch between the lines of the second wiring 121 can be small enough, that is, it is ensured that the second metal layer 122 can be etched at a high density, so that the lines of the second wiring 121 can be made more dense, which is beneficial to reducing the volume of the second substrate 12, realizing the miniaturization of the substrate 10, and improving the integration degree of the packaging structure 1. Of course, the thickness of the second metal layer 122 may also be other values outside 0.035 mm to 2 mm.

[0056] The pitch between two adjacent lines in the lines of the second wiring 121 is 0.1 mm to 0.5 mm. By limiting the pitch between two adjacent lines in the lines of the second wiring 121 to 0.1 mm to 0.5 mm, it can be ensured that the pitch between the lines of the second wiring 121 is small enough, so as to ensure that the lines of the second wiring 121 are dense enough, further reducing the volume of the second substrate 12, realizing the miniaturization of the substrate 10, and improving the integration degree of the packaging structure 1. Of course, in other embodiments, the pitch between two adjacent lines in the lines of the second wiring 121 may also be other values, as long as it can ensure that the lines of the second wiring 121 are dense enough and can further reduce the volume of the second substrate 12.

[0057] The second substrate 12 can be a Direct Plating ceramic (DPC) substrate, that is, the material of the insulating board 123 is ceramic. The ceramic material can be alumina, zirconia toughened alumina ceramic, aluminum nitride, silicon nitride or other ceramic materials. The second metal layer 122 and the fourth metal layer 124 are respectively formed on the two opposite surfaces of the insulating board 123 by copper plating. The thickness of the second metal layer 122 and the fourth metal layer 124 is 35 - 200 um. The thicknesses of the second metal layer 122 and the fourth metal layer 124 can be the same or different. Of course, the second metal layer 122 and the fourth metal layer 124 can also be formed by processes such as Electroless Nickel Immersion Gold (ENIG), electroless nickel palladium gold, bare copper surface, nickel plating, gold plating, etc.

[0058] The second substrate 12 can also be a Direct copper bonding (DCB) substrate, that is, the material of the insulating board 123 is ceramic. The ceramic material can be alumina, zirconia toughened alumina ceramic, aluminum nitride or other ceramic materials. The second metal layer 122 and the fourth metal layer 124 are respectively formed on the two opposite surfaces of the insulating board 123 by copper pressing. The thickness of the second metal layer 122 and the fourth metal layer 124 is 50 - 400 um. The thicknesses of the second metal layer 122 and the fourth metal layer 124 can be the same or different. Of course, the second metal layer 122 and the fourth metal layer 124 can also be formed by processes such as Electroless Nickel Immersion Gold (ENIG), electroless nickel palladium gold, bare copper surface, nickel plating, gold plating, copper plating, etc.

[0059] The second substrate 12 can also be a Thick film Plating ceramic (TPC) substrate, that is, the material of the insulating board 123 is ceramic. The ceramic material can be alumina, zirconia toughened alumina ceramic, aluminum nitride or other ceramic materials. The second metal layer 122 and the fourth metal layer 124 are respectively formed on the two opposite surfaces of the insulating board 123 by double-sided co-firing of metal silver paste or metal copper paste with glass. The thickness of the second metal layer 122 and the fourth metal layer 124 is 35 - 200 um. The thicknesses of the second metal layer 122 and the fourth metal layer 124 can be the same or different. Of course, the second metal layer 122 and the fourth metal layer 124 can also be formed by processes such as Electroless Nickel Immersion Gold (ENIG), electroless nickel palladium gold, bare copper surface, gold plating, etc.

[0060] The second substrate 12 can also be a Printed Circuit Board (PCB), that is, the material of the insulating board 123 is a flame-retardant resin. The second metal layer 122 and the fourth metal layer 124 are respectively formed on the two opposite surfaces of the insulating board 123 by copper plating. The thickness of the second metal layer 122 and the fourth metal layer 124 is 35 - 200 um. The thicknesses of the second metal layer 122 and the fourth metal layer 124 can be the same or different. Of course, the second metal layer 122 and the fourth metal layer 124 can also be formed by processes such as Electroless Nickel Immersion Gold (ENIG), electroless nickel palladium gold, bare copper on the surface, nickel plating, gold plating, etc.

[0061] The second metal layer 122 forms the second wiring 121 to be electrically connected to the chip 20, so as to realize the electrical connection between the chip 20 and external devices. The fourth metal layer 124 is used to conduct out the heat transferred from the chip 20 to the first wiring 111, enabling the chip 20 to dissipate heat faster, ensuring the electrical performance of the chip 20. At the same time, the fourth metal layer 124 can also achieve metallization welding with the first metal layer 112. The insulating board 123 is used to achieve electrical isolation between the second metal layer 122 and the fourth metal layer 124. At the same time, the insulating board 123 also ensures the adhesion and support of the double-sided metal on the second substrate.

[0062] In this embodiment, the second substrate 12 is mounted on the first wiring 111 of the first substrate 11, and the side of the insulating board 123 facing away from the second wiring 121 is connected to the surface of the first wiring 111. Specifically, the fourth metal layer 124 on the side of the insulating board 123 facing away from the second wiring 121 is disposed on the surface of the first wiring 111, that is, the fourth metal layer 124 is disposed on the surface of the first metal layer 112. The fourth metal layer 124 is fixed on the first metal layer 112 by soldering with molten tin, laser or ultrasonic welding, and is spaced from the chip 20. By mounting the second substrate 12 on the first substrate 11, it is beneficial to reduce the planar area of the entire substrate 10 and improve the integration of the substrate 10 and the packaging structure 1. Of course, in other embodiments, the fourth metal layer can also be fixed on the first metal layer 112 by other connection methods such as bonding and clamping. Or, the insulating board 123 can also be directly fixed on the first metal layer 112.

[0063] Please refer to Figure 2 and Figure 6 , Figure 6 is Figure 2 the schematic structural diagram between the substrate 10 and the lead frame shown in

[0064] The signal terminals of the chip 20 are electrically connected to the second wiring 121 through wires. The wires are fixed to the second wiring 121 by ultrasonic bonding or soldering. The second substrate 12 is mounted on the edge of the first metal layer 112 to facilitate the electrical connection between the signal terminals and external devices through the second wiring 121 of the second substrate 12. One end of the lead frame a is electrically connected to the second wiring 121, and the other end is electrically connected to an external device to achieve the electrical connection between the chip 20 and the external device. The lead frame a can be soldered on the second wiring 121 by tin soldering, laser or ultrasonic wave, etc. Some pins of the lead frame a can also carry a thermistor to serve as over-temperature protection for the package structure 1. The width of the second substrate 12 can be greater than, less than or equal to the width of the first substrate 11. Of course, in other embodiments, a wire bonding process, such as a copper sheet, can also be used to replace the wire to connect the signal terminal and the second wiring 121 to achieve current transfer, greatly reducing the internal resistance of the package structure 1 and the cost is not too high.

[0065] As Figure 2 , the package structure 1 further includes a third substrate 13. The third substrate 13 includes a third wiring 131, and the third wiring 131 is connected between the signal terminal and the second wiring 121. That is to say, the third substrate 13 can be understood as an adapter board between the chip 20 and the second wiring 121 to make the electrical connection relationship between multiple chips 20 and the second wiring 121 more concise. Of course, in other embodiments, the chip 20 can also be directly electrically connected to the second wiring 121.

[0066] In this embodiment, the number of the third substrates 13 is two. The two third substrates 13 are spaced on the first wiring 111 and are respectively located between adjacent columns of chips 20. The signal terminal of each chip 20 is electrically connected to the third wiring 131 of the third substrate 13 close to it, and the third wiring 131 is electrically connected to the second wiring 121 to achieve the transfer between the chip 20 and the second wiring 121. Specifically, the signal terminal of the chip 20 is electrically connected to the third wiring 131 close to it through a wire, and one end of the third wiring 131 close to the second substrate 12 is electrically connected to the second wiring 121 through a wire. The transfer between the chip 20 close to it and the second wiring 121 is realized through the third substrate 13, which is simpler and neater than the way that each chip 20 is respectively connected to the second wiring 121 through a wire, and the length of the wire is also shortened. Of course, in other embodiments, the number of the third substrates 13 can also be one or more, and the arrangement of the third substrates 13 can also be set according to actual needs.

[0067] The pitch between the lines of the third wiring 131 is smaller than the pitch between the lines of the first wiring 111. That is, the pitch between the lines of the third wiring 131 can be made smaller than the pitch between the lines of the first wiring 111, which is beneficial to the miniaturization of the third substrate 13 and thus improves the integration degree of the packaging structure 1. Of course, in other embodiments, the pitch between the lines of the third wiring 131 can also be equal to or greater than the pitch between the lines of the first wiring 111.

[0068] The packaging structure 1 includes electronic components, which are arranged on the third substrate 13 and electrically connected to the third wiring 131. Specifically, the electronic components are, for example, passive components such as resistors and capacitors, and the electronic components are used to assist the third wiring 131 in circuit transfer between the chip 20 and the second wiring 121.

[0069] Please refer to Figure 7 , Figure 7 is Figure 3 the structural diagram of the second embodiment of the substrate 10 shown in

[0070] This embodiment is substantially the same as the first embodiment. The difference is that in this embodiment, there are two second substrates 12, and the two second substrates 12 are installed on the first substrate 11 at intervals. One second substrate 12 is correspondingly connected to one third substrate. The two second substrates 12 are respectively arranged close to the chips 20 electrically connected thereto. By providing two second substrates 12 in this application, it is equivalent to arranging the second wiring 121 provided on one board on two boards respectively. Thus, the second substrate 12 can be made smaller, and the two second substrates 12 can be respectively arranged at different positions according to the chips 20 electrically connected thereto, with more flexible layout and easier control of the stress of the packaging structure 1. Of course, in other embodiments, there can also be multiple second substrates 12, and the multiple second substrates 12 are installed on the first substrate 11 at intervals.

[0071] Please refer to Figure 8 and Figure 9 , Figure 8 is Figure 3 the structural diagram of the third embodiment of the substrate 10 shown in Figure 9 is Figure 8 the schematic cross-sectional structure diagram of the substrate 10 shown in

[0072] This embodiment is substantially the same as the first embodiment. The difference is that the first metal layer 112 in this embodiment includes an avoidance groove 1121, and the second substrate 12 is completely embedded in the avoidance groove 1121. Specifically, the fourth metal layer 124 of the second substrate 12 is fixedly welded to the bottom wall of the avoidance groove 1121, and the second wiring 121 of the second substrate 12 is insulated from the first metal layer 112. That is to say, the second substrate 12 in this embodiment is embedded in the first substrate 11. On the basis of reducing the planar size of the substrate 10, the size of the substrate 10 in the thickness direction is not increased, and the integration degree of the substrate 10 is further improved. Of course, in other embodiments, the second substrate 12 may also be at least partially embedded in the avoidance groove 1121, and the fourth metal layer 124 of the second substrate 12 and the avoidance groove 1121 may also be fixedly connected by bonding, clamping and other means. Or, the third substrate may also be embedded on the first metal layer.

[0073] In this embodiment, there are two second substrates 12. Correspondingly, the number of avoidance grooves 1121 is also two. Each substrate 12 is respectively embedded in the corresponding avoidance groove 1121. The line of the second wiring 121 is a trace, and the surface of the second wiring 121 facing the notch of the avoidance groove 1121 is flush with the notch. That is to say, the surface of the second wiring 121 layer facing away from the carrier plate 113 is flush with the surface of the first wiring 111 layer, so that the chip 20 can be flip-chip bonded to the substrate 10. For example, Figures 10 - 11 , the part of the chip 20 with power terminals can be arranged on the first substrate 11 and electrically connected to the first wiring 111, and the part of the chip 20 with signal terminals is arranged on the second substrate 12 and electrically connected to the second wiring 121. Specifically, both between the power terminals and the first wiring 111 and between the signal terminals and the second wiring 121 are welded through pads, so as to avoid connecting the signal terminals and the second wiring 121 through wires, simplifying the manufacturing steps of the packaging structure 1( Figure 2 ), and improving the production efficiency of the packaging structure 1. Of course, in other embodiments, the line of the second wiring 121 may also be other structures such as pads. Or, the number of the second substrates 12 and the avoidance grooves 1121 is one or more, and each second substrate is embedded in the corresponding avoidance groove at intervals. Or, all the chips are arranged on the first wiring, and the chips and the second substrate are electrically connected through wires.

[0074] Please refer to Figure 12 and Figure 13 , Figure 12 which Figure 3 is the structural diagram of the fourth embodiment of the substrate 10 shown in Figure 13 , Figure 12 and

[0075] This embodiment is substantially the same as the first embodiment, except that the side of the insulating plate 123 is connected to the side of the carrier plate 113, and the first wiring 111 and the second wiring 121 are spaced apart. Specifically, the insulating plate 123 and the carrier plate 113 are welded together by high-energy laser or other means. Compared with the second substrate 12 being welded to the surface of the first metal layer 112 in the first embodiment, the area of the welding surface where the side of the insulating plate 123 is connected to the side of the carrier plate 113 is smaller, the corresponding process cost is reduced, and the insulating plate 123 can be welded to any side of the carrier plate 113, making the design more flexible. Of course, in other embodiments, the second substrate 12 can also be mounted on the first substrate 11 by other connection means.

[0076] In the scenario of this embodiment, the line of the second wiring 121 is a trace, and the first wiring 111 of the first substrate 11 and the second wiring 121 of the second substrate 12 face the same direction, and the chip 20 can be directly flip-chip bonded to the substrate 10. The part of the chip 20 having power terminals can be disposed on the first substrate 11 and electrically connected to the first wiring 111, and the part of the chip 20 having signal terminals is disposed on the second substrate 12 and electrically connected to the second wiring 121. Specifically, both the power terminals and the first wiring 111, and the signal terminals and the second wiring 121 are welded, thereby avoiding connecting the signal terminals and the second wiring 121 through a wire, simplifying the manufacturing steps of the packaging structure 1( Figure 2 ) and improving the production efficiency of the packaging structure 1. Of course, in other embodiments, the line of the second wiring 121 can also be other structures such as pads. Or, the number of the second substrates is multiple, and the multiple second substrates are spaced and connected to any side of the first substrate, or the multiple second substrates are respectively disposed on different sides of the first substrate. Or, all the chips are disposed on the first wiring, and the chips are electrically connected to the second substrate through wires.

[0077] The protection scope of this application is not limited to the above-mentioned Embodiment 1 to Embodiment 4, and any combination of Embodiment 1 to Embodiment 4 is also within the protection scope of this application. That is to say, the above-described multiple embodiments can also be arbitrarily combined according to actual needs.

[0078] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claimed rights.

Claims

1. A power module, comprising a substrate and a chip electrically connected to the substrate, the chip comprising a power terminal and a signal terminal, Characterized in that, The substrate comprises a first substrate and a second substrate mounted on the first substrate. The first substrate comprises a first metal layer, the first metal layer comprises a first wiring, the first wiring is electrically connected to the power terminal, the second substrate comprises a second wiring, the second wiring is electrically connected to the signal terminal, the pitch between the lines of the second wiring is smaller than the pitch between the lines of the first wiring, the chip is disposed on the first wiring, and the first substrate is used to support the chip.

2. The power module according to claim 1, Characterized in that, The second substrate comprises a second metal layer, the second wiring is formed on the second metal layer, and the thickness of the second metal layer is smaller than the thickness of the first metal layer.

3. The power module according to claim 2, Characterized in that, The thickness of the second metal layer is 0.035 mm to 2 mm.

4. The power module according to any one of claims 1-3, Characterized in that, The pitch between two adjacent lines in the lines of the second wiring is 0.1 mm to 0.5 mm.

5. The power module according to claim 2, Characterized in that, The first metal layer comprises an avoidance groove, and at least a part of the second substrate is embedded in the avoidance groove.

6. The power module according to claim 5, Characterized in that, The first substrate comprises a carrier plate, the first metal layer is disposed on the carrier plate, and the surface of the second wiring facing away from the carrier plate is flush with the surface of the first metal layer facing away from the carrier plate.

7. The power module according to any one of claims 1-3, Characterized in that, The second substrate further comprises an insulating plate, the second wiring is disposed on the insulating plate, and one side of the insulating plate facing away from the second wiring is connected to the surface of the first wiring.

8. The power module according to any one of claims 1-3, Characterized in that, The second substrate comprises an insulating plate, the second wiring is disposed on the insulating plate, the first substrate comprises a carrier plate, the first wiring is disposed on the carrier plate, the side of the insulating plate and the side of the carrier plate are connected, and the first wiring and the second wiring are spaced apart.

9. The power module according to claim 8, Characterized in that, The first substrate further comprises a third metal layer, and the third metal layer is disposed on the surface of the carrier plate facing away from the first wiring.

10. The power module according to claim 7, Characterized in that, The second substrate further comprises a fourth metal layer, and the fourth metal layer is disposed on the surface of the insulating plate facing away from the second wiring.

11. The power module according to claim 1, Characterized in that, There are a plurality of the second substrates, and the plurality of second substrates are spaced and mounted on the first substrate and are respectively disposed close to the chips electrically connected thereto.

12. The power module according to claim 1, Characterized in that, The signal terminal is electrically connected to the second wiring through a wire; or the signal terminal is electrically connected to the second wiring through a pad.

13. The power module according to claim 12, wherein, the power module includes a third substrate, the third substrate includes a third wiring, a pitch between lines of the third wiring is smaller than a pitch between lines of the first wiring, and the third wiring is connected between the signal terminal and the second wiring.

14. The power module according to claim 13, wherein, the power module includes an electronic component, and the electronic component is disposed on the third substrate and electrically connected to the third wiring.

15. An electronic device, wherein, the electronic device includes a circuit board and the power module according to any one of claims 1-14, and the power module is electrically connected to the circuit board.

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