Semiconductor device
By designing a redundant capacitor array in a semiconductor device, the problem of single capacitor failure affecting capacitor accuracy and yield is solved, and the effect of improving power supply and signal integrity is achieved.
Patent Information
- Application Number
- CN202410311116.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-26
- Filing Date
- 2024-03-19
- Publication Date
- 2025-05-27
AI Technical Summary
In 2.5D and/or 3D integrated circuit devices operating at high frequencies, failure of a single capacitor may jeopardize the accuracy of the capacitor and affect the overall yield. How to improve power supply and signal integrity has become an important topic.
A semiconductor device is designed, including a package substrate, an interposer layer, an oxide layer and a top conductive layer, which is provided with a conventional capacitor array and a redundant capacitor array, which is used to replace and repair damaged conventional capacitor arrays.
Through the design of redundant capacitor arrays, the accuracy and productivity of the capacitors are improved, signal noise and leakage between integrated circuit components are reduced, and power supply and signal integrity are enhanced.
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Figure CN120048825A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to semiconductor devices. More specifically, the present disclosure relates to semiconductor devices including a redundant capacitor array. Background Art
[0002] Silicon interposers have been widely used in the manufacture of advanced 2.5D and / or 3D integrated circuits (ICs) for artificial intelligence (AI)-related applications. With the advancement of the functions of 2.5D and / or 3D integrated circuit (IC) devices, capacitors are added to the Si interposer, especially for devices operating at higher frequencies, to improve power integrity (PI) and signal integrity (SI).
[0003] However, the failure of even a single capacitor may endanger the accuracy of the final target capacitor and affect the overall yield. Therefore, how to solve the above problems is an important issue in the development of semiconductor devices. Summary of the Invention
[0004] According to an aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a package substrate, an interposer, an oxide layer, and a top conductive layer. The interposer is disposed on the package substrate and includes a plurality of regular capacitor arrays and a plurality of redundant capacitor arrays. The regular capacitor arrays are located within the interposer, and each regular capacitor array includes a plurality of regular capacitors. Each regular capacitor includes a lower electrode, a dielectric layer, and an upper electrode, where the dielectric layer is surrounded by the lower electrode, and the upper electrode is surrounded by the dielectric layer. The redundant capacitor arrays are located within the interposer, and each redundant capacitor array includes a plurality of redundant capacitors. Each redundant capacitor includes a lower electrode, a dielectric layer, and an upper electrode, where the dielectric layer is surrounded by the lower electrode, and the upper electrode is surrounded by the dielectric layer. The oxide layer is located on the interposer, and the oxide layer isolates the upper electrodes of the regular capacitors from the upper electrodes of the redundant capacitors. The top conductive layer is located on the oxide layer, and the top conductive layer connects the upper electrodes of the regular capacitors to the upper electrodes of the redundant capacitors.
[0005] According to some embodiments of the present disclosure, a first memory die and a second memory die are further included. The first memory die is disposed on the top conductive layer, and the second memory die is disposed on the top conductive layer and adjacent to the first memory die.
[0006] According to some embodiments of the present disclosure, a first memory die and a second memory die are further included. The first memory die is disposed on the top conductive layer, and the second memory die is disposed on the first memory die and overlaps the first memory die.
[0007] According to some embodiments of the present disclosure, conventional capacitor arrays are connected in series.
[0008] According to some embodiments of the present disclosure, conventional capacitor arrays are connected in parallel.
[0009] According to some embodiments of the present disclosure, redundant capacitor arrays are connected in series.
[0010] According to some embodiments of the present disclosure, redundant capacitor arrays are connected in parallel.
[0011] According to some embodiments of the present disclosure, conventional capacitor arrays are connected in series with redundant capacitor arrays.
[0012] According to some embodiments of the present disclosure, conventional capacitor arrays are connected in parallel with redundant capacitor arrays.
[0013] According to some embodiments of the present disclosure, one of a plurality of redundant capacitor arrays is connected to one of a plurality of conventional capacitor arrays.
[0014] According to some embodiments of the present disclosure, the redundant capacitor array includes a plurality of first redundant capacitor arrays and a plurality of second redundant capacitor arrays. The plurality of first redundant capacitor arrays are connected to each other, and the plurality of second redundant capacitor arrays are connected to each other, wherein the second redundant capacitor array is separated from the first redundant capacitor array.
[0015] According to some embodiments of the present disclosure, the interposer includes an N-well region and an N+ region. The N+ region is disposed in the N-well region and surrounds the conventional capacitor array and the redundant capacitor array.
[0016] According to an aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a package substrate, an interposer, an oxide layer, a bottom conductive layer, and a top conductive layer. The interposer is disposed on the package substrate. The oxide layer is disposed on the interposer, wherein the oxide layer includes a plurality of conventional capacitor arrays and a plurality of redundant capacitor arrays. The conventional capacitor arrays are located on the interposer, and each conventional capacitor array includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes two vertical portions and a horizontal portion. The dielectric layer includes two vertical portions and a horizontal portion. The upper electrode is surrounded by the dielectric layer. The redundant capacitor arrays are located on the interposer, and each redundant capacitor array includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes two vertical portions and a horizontal portion. The dielectric layer includes two vertical portions and a horizontal portion. The upper electrode is surrounded by the dielectric layer. The bottom conductive layer is located between the interposer and the oxide layer. The top conductive layer is located on the oxide layer.
[0017] According to some embodiments of the present disclosure, each of the conventional capacitor arrays and each of the redundant capacitor arrays includes a first capacitor, a second capacitor, and a third capacitor, wherein the second capacitor is disposed between the first capacitor and the third capacitor.
[0018] According to some embodiments of the present disclosure, the first capacitor includes an upper electrode, a dielectric layer surrounding the upper electrode, and a part of a bottom conductive layer, wherein the dielectric layer is in contact with the part of the bottom conductive layer.
[0019] According to some embodiments of the present disclosure, the second capacitor includes an upper electrode, a vertical portion of the dielectric layer, and a vertical portion of a lower electrode, wherein the dielectric layer is disposed between the upper electrode and the lower electrode.
[0020] According to some embodiments of the present disclosure, the third capacitor includes an upper electrode, a lateral portion of the dielectric layer, and a lateral portion of a lower electrode, wherein the dielectric layer is disposed between the upper electrode and the lower electrode.
[0021] It should be understood that the foregoing general description and the following detailed description are both by way of example and are intended to provide further explanation of the claimed present disclosure. Brief Description of the Drawings
[0022] By reading the following detailed description of the embodiments in conjunction with the accompanying drawings, the present disclosure can be more fully understood:
[0023] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to some embodiments.
[0024] Figure 2 is a top-view schematic diagram of the relationship between a conventional capacitor array and a redundant capacitor according to some embodiments.
[0025] Figure 3 is a top-view schematic diagram of the relationship between a conventional capacitor array and a redundant capacitor according to other embodiments.
[0026] Figure 4 is a cross-sectional schematic diagram of a semiconductor device according to some embodiments.
[0027] Figure 5 is a cross-sectional schematic diagram of a semiconductor device according to other embodiments.
[0028] Figure 6A is a cross-sectional schematic diagram of a semiconductor device according to some embodiments.
[0029] Figure 6B is according to some embodiments of Figure 6A a partial enlarged cross-sectional schematic diagram of.
[0030] Figure 6CAccording to some embodiments Figure 6B is an equivalent circuit diagram.
[0031] Figure 7 is a cross-sectional schematic diagram of a semiconductor device according to some embodiments.
[0032] Figure 8 is a cross-sectional schematic diagram of a semiconductor device according to other embodiments. Detailed Description of Embodiments
[0033] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
[0034] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific embodiments or examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or symbols in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate the relationship between the various embodiments and / or configurations discussed.
[0035] In addition, for ease of description, the present disclosure may use spatial relative terms, such as "below", "beneath", "lower", "above", "upper", etc., to describe the relationship of one element or feature to one or more other elements or features, as shown in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.
[0036] It should be understood that when an element or layer is referred to as "connected to" or "coupled to" another element or layer, it can be directly connected to or coupled to the other element or layer, or there may be intervening elements or layers.
[0037] Figure 1 is a cross-sectional schematic diagram of a semiconductor device 100 according to some embodiments. The semiconductor device 100 can be applied to an integrated circuit (IC) or a part thereof, such as a logic circuit, a resistor, a capacitor, an inductor, a memory (such as a dynamic random access memory (DRAM)), etc. It should be understood that for simplicity of the drawings,Figures 1 to 8 Some components of the semiconductor device 100 are not shown, and additional components may be included in other embodiments of the semiconductor device 100.
[0038] Reference Figure 1 , the semiconductor device 100 may include a package substrate 110, an interposer 120, a conventional capacitor array 130, a redundant capacitor array 140, an oxide layer 150, and a top conductive layer 160. The interposer 120 is disposed on the package substrate 110. In some embodiments, the interposer 120 may include a silicon-based material. In some embodiments, the interposer 120 may include an N-well region 122 and an N+ region 190. In some embodiments, the interposer 120 includes through-substrate vias (TSVs) (not shown). The interposer 120 and the package substrate 110 are electrically coupled through the TSVs.
[0039] In some embodiments, the package substrate 110 may be a printed circuit board, ceramic, organic material, glass, and / or semiconductor material or structure. In some embodiments, the package substrate 110 provides a base plate with power, ground, control, monitoring, etc. The package substrate 110 may include a plurality of solder balls (not shown) formed on the package substrate 110 for routing signals to other electrical devices (such as a motherboard or other chipset).
[0040] A plurality of conventional capacitor arrays 130 and a plurality of redundant capacitor arrays 140 are disposed in the interposer 120. Each conventional capacitor array 130 may include a plurality of conventional capacitors 132, where each conventional capacitor 132 may include a lower electrode 134, a dielectric layer 136, and an upper electrode 138. The lower electrode 134 may surround the dielectric layer 136, and the dielectric layer 136 may surround the upper electrode 138. In some embodiments, both the dielectric layer 136 and the lower electrode 134 have a U-shaped cross-sectional profile. In some embodiments, the lower electrode 134 and the upper electrode 138 may include a conductive material such as metal, metal alloy, metal nitride, etc. In some embodiments, the lower electrode 134 and the upper electrode 138 may include tungsten. The dielectric layer 136 includes a dielectric material such as tetraethylorthosilicate (TEOS), a low-k dielectric material, doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), etc.), and / or other suitable dielectric materials.
[0041] Each redundant capacitor array 140 may include a plurality of redundant capacitors 142, where each redundant capacitor 142 may include a lower electrode 144, a dielectric layer 146, and an upper electrode 148. The lower electrode 144 may surround the dielectric layer 146, and the dielectric layer 146 may surround the upper electrode 148. In some embodiments, both the dielectric layer 146 and the lower electrode 144 have a U-shaped cross-sectional profile. In some embodiments, the lower electrode 144 and the upper electrode 148 may include a conductive material such as a metal, a metal alloy, a metal nitride, etc. In some embodiments, the lower electrode 144 and the upper electrode 148 may include tungsten. The dielectric layer 146 includes a dielectric material such as tetraethyl orthosilicate (TEOS), a low-k dielectric material, doped silicon oxide, and / or other suitable dielectric materials.
[0042] An oxide layer 150 is disposed on the interlayer 120. The oxide layer 150 may isolate the upper electrode 138 of each conventional capacitor 132 from the upper electrode 148 of each redundant capacitor 142. In some embodiments, the oxide layer 150 may include silicon oxide (SiO 2 ), zirconium oxide, titanium oxide, aluminum oxide (Al 2 O 3 ), hafnium oxide, or a combination thereof.
[0043] A top conductive layer 160 is disposed on the oxide layer 150. The top conductive layer 160 may connect the upper electrode 138 of each conventional capacitor 132 to the upper electrode 148 of each redundant capacitor 142. In some embodiments, the top conductive layer 160 may include a conductive material such as a metal, a metal alloy, a metal nitride, etc. In some embodiments, the top conductive layer 160, the upper electrode 138, and the upper electrode 148 may include the same material. In some embodiments, the top conductive layer 160, the upper electrode 138, and the upper electrode 148 may include different materials.
[0044] An N+ region 190 is disposed in the N-well region 122 and surrounds the conventional capacitor array 130 and the redundant capacitor array 140. The N+ region 190 is coupled to the top electrode 194 through the upper electrode 192. The upper electrode 192 may be disposed in the oxide layer 150, and the top electrode 194 may be disposed on the oxide layer 150. In some embodiments, the upper electrode 192, the upper electrode 138, and the upper electrode 148 may include the same material. In some embodiments, the top electrode 194 and the top conductive layer 160 may include the same material.
[0045] Figure 2 is a top view schematic diagram of the relationship between the conventional capacitor array 130 and the redundant capacitor array 140. Refer to Figure 2, one of the redundant capacitor arrays 140 is connected to one of the conventional capacitor arrays 130. As shown, the N+ regions 190 surround the conventional capacitor array 130 and the redundant capacitor array 140. In some embodiments, one of the redundant capacitor arrays 140 and one of the conventional capacitor arrays 130 may be connected in series. In some embodiments, one of the redundant capacitor arrays 140 and one of the conventional capacitor arrays 130 may be connected in parallel. In some embodiments, multiple conventional capacitor arrays 130 may be connected in series with each other. In some embodiments, multiple conventional capacitor arrays 130 may be connected in parallel with each other. In some embodiments, multiple redundant capacitor arrays 140 may be connected in series with each other. In some embodiments, multiple redundant capacitor arrays 140 may be connected in parallel with each other. The redundant capacitor array 140 can be used to replace and repair damaged conventional capacitor arrays 130, or to adjust the capacitor value. The conventional capacitor 132 and the redundant capacitor 142 are used to reduce signal noise and reduce leakage between IC components.
[0046] Figure 3 is a top view schematic diagram of the relationship between the conventional capacitor array 130, the first redundant capacitor array 140A and the second redundant capacitor array 140B according to other embodiments. Refer to Figure 3 , multiple redundant capacitor arrays 140 may include multiple first redundant capacitor arrays 140A and multiple second redundant capacitor arrays 140B. The multiple first redundant capacitor arrays 140A may be connected to each other. The multiple second redundant capacitor arrays 140B may be connected to each other. The multiple first redundant capacitor arrays 140A and the multiple second redundant capacitor arrays 140B are separated. One of the first redundant capacitor arrays 140A is connected to one of the conventional capacitor arrays 130. One of the second redundant capacitor arrays 140B is connected to one of the conventional capacitor arrays 130. In some embodiments, more redundant capacitor arrays 140 may also be included and are respectively connected to the conventional capacitor arrays 130.
[0047] Refer to Figure 4 and Figure 5 , the semiconductor device 100 may further include a first memory die 170 and a second memory die 180. As Figure 4 shown, the first memory die 170 is disposed on the top conductive layer 160, and the second memory die 180 may be disposed on the first memory die 170. In some embodiments, the second memory die 180 overlaps the first memory die 170. The first memory die 170 is electrically connected to the top conductive layer 160, and the second memory die 180 is electrically connected to the first memory die 170.
[0048] As Figure 5As shown, a first memory die 170 is disposed on a top conductive layer 160, and a second memory die 180 is disposed on the top conductive layer 160, wherein the first memory die 170 is adjacent to the second memory die 180. Separately, the first memory die 170 is electrically connected to the top conductive layer 160, and the second memory die 180 is electrically connected to the top conductive layer 160. In some embodiments, the first memory die 170 directly contacts the top conductive layer 160, and the second memory die 180 directly contacts the top conductive layer 160. In some embodiments, the first memory die 170 and the second memory die 180 are disposed on the same plane of the top conductive layer 160.
[0049] Figure 6A is a cross-sectional schematic diagram of a semiconductor device 200 according to some embodiments. Referring to Figure 6A , the semiconductor device 200 may include a package substrate 210, an interposer 220, a conventional capacitor array 230, a redundant capacitor array 240, an oxide layer 250, a top conductive layer 260, and a bottom conductive layer 262. The interposer 220 is disposed on the package substrate 210.
[0050] The oxide layer 250 is disposed on the interposer 220. The oxide layer 250 may include a plurality of conventional capacitor arrays 230 and a plurality of redundant capacitor arrays 240.
[0051] A plurality of conventional capacitor arrays 230 and a plurality of redundant capacitor arrays 240 are disposed on the interposer 220. Each conventional capacitor array 230 may include a plurality of conventional capacitors 232, and each conventional capacitor 232 may include a lower electrode 234, a dielectric layer 236, and an upper electrode 238. The upper electrode 238 is surrounded by the dielectric layer 236. In some embodiments, both the dielectric layer 236 and the lower electrode 234 have a U-shaped cross-sectional profile. A capping layer 252 may be disposed between the lower electrode 234 and the top conductive layer 260. In some embodiments, the capping layer 252 may include SiO 2 . The capping layer 252 may insulate the lower electrode 234 from the top conductive layer 260. In some embodiments, a portion of the dielectric layer 236 may contact the bottom conductive layer 262. In some embodiments, the lower electrode 234 may contact the top conductive layer 260 and the bottom conductive layer 262.
[0052] Each redundant capacitor array 240 may include a plurality of redundant capacitors 242, and each redundant capacitor 242 may include a lower electrode 244, a dielectric layer 246, and an upper electrode 248. The upper electrode 248 is surrounded by the dielectric layer 246. In some embodiments, both the dielectric layer 246 and the lower electrode 244 have a U-shaped cross-sectional profile. A top cover layer 252 may be disposed between the lower electrode 244 and the top conductive layer 260. In some embodiments, the top cover layer 252 may include SiO 2 . The top cover layer 252 may insulate the lower electrode 234 from the top conductive layer 260. In some embodiments, a portion of the dielectric layer 246 may contact the bottom conductive layer 262. In some embodiments, the lower electrode 244 may contact the top conductive layer 260 and the bottom conductive layer 262.
[0053] The bottom conductive layer 262 is located on the interposer 220, where the bottom conductive layer 262 connects the lower electrodes 234 of the respective conventional capacitors 232 and the lower electrodes 244 of the respective redundant capacitors 242. The top conductive layer 260 is located on the oxide layer 250, where the top conductive layer 260 connects the upper electrodes 238 of the respective conventional capacitors 232 and the upper electrodes 248 of the redundant capacitors 242.
[0054] Reference Figure 6B and Figure 6C , the conventional capacitor 232 and the redundant capacitor 242 include three types of capacitors. For example, the first capacitor includes an upper electrode 238(A), a dielectric layer 236, and a bottom conductive layer 262(0), hereinafter labeled as (A,0). As shown, the first capacitor includes (A,0), (C,4), (E,8), (G,12), (I,16).
[0055] The second capacitor includes an upper electrode 238(B), a vertical portion of the dielectric layer 236, and a lower electrode 234(1 or 3), hereinafter labeled as (B,1) or (B,3). As shown, the second capacitor includes (A,1), (B,1), (B,3), (C,3), (C,5), (D,5), (D,7), (E,7), (E,9), (F,9), (F,11), (G,11), (G,13), (H,13), (H,15), and (I,15).
[0056] The third capacitor includes an upper electrode 238(B), a lateral portion of the dielectric layer 236, and a lateral portion of the lower electrode 234(2), hereinafter labeled as (B,2). As shown, the third capacitor includes (B,2), (D,6), (F,10), and (H,14).
[0057] The lower electrodes 234(1, 2, 3) share the same upper electrode 238(B). The second capacitor is disposed between the first capacitor and the third capacitor. The conventional capacitor 232 and the lower electrode 234 may be arranged in the order of "first capacitor, second capacitor, second capacitor, third capacitor, second capacitor, second capacitor, first capacitor...".
[0058] Reference Figure 7 With Figure 8 , the semiconductor device 200 may include a first memory die 270 and a second memory die 280. As Figure 7 shown, the first memory die 270 is disposed on the top conductive layer 260, and the second memory die 280 is disposed on the first memory die 270. In some embodiments, the second memory die 280 overlaps the first memory die 270. The first memory die 270 is electrically connected to the top conductive layer 260, and the second memory die 280 is electrically connected to the first memory die 270.
[0059] As Figure 8 shown, the first memory die 270 is disposed on the top conductive layer 260, and the second memory die 280 is disposed on the top conductive layer 260, where the first memory die 270 and the second memory die 280 are adjacent. Separately, the first memory die 270 is electrically connected to the top conductive layer 260, and the second memory die 280 is electrically connected to the top conductive layer 260. In some embodiments, the first memory die 270 directly contacts the top conductive layer 260, and the second memory die 280 directly contacts the top conductive layer 260. In some embodiments, the first memory die 270 and the second memory die 280 are disposed on the same plane of the top conductive layer 260.
[0060] According to the above embodiments of the present invention, the present invention provides a semiconductor device. Using the semiconductor provided by this disclosure, a new capacitor scheme can improve accuracy and yield. The redundant capacitor array can replace and / or repair a damaged conventional capacitor array, or can adjust the capacitor value. The conventional capacitor and the redundant capacitor can reduce signal noise and reduce leakage between integrated circuit elements.
[0061] Although this disclosure has been described in considerable detail with reference to certain of its embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
[0062] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations of the present disclosure that fall within the scope of the appended claims.
[0063]
Symbol Description
[0064] 100: Semiconductor device
[0065] 110: Package substrate
[0066] 120: Interposer
[0067] 122: N-well region
[0068] 130: Conventional capacitor array
[0069] 132: Conventional capacitor
[0070] 134: Lower electrode
[0071] 136: Dielectric layer
[0072] 138: Upper electrode
[0073] 140: Redundant capacitor array
[0074] 140A: First redundant capacitor array
[0075] 140B: Second redundant capacitor array
[0076] 142: Redundant capacitor
[0077] 144: Lower electrode
[0078] 146: Dielectric layer
[0079] 148: Upper electrode
[0080] 150: Oxide layer
[0081] 160: Top conductive layer
[0082] 170: First memory die
[0083] 180: Second memory die
[0084] 190: N+ region
[0085] 192: Upper electrode
[0086] 194: Top electrode
[0087] 200: Semiconductor device
[0088] 210: Package substrate
[0089] 220: Intermediary layer
[0090] 230: Conventional capacitor array
[0091] 232: Conventional capacitor
[0092] 234: Lower electrode
[0093] 236: Dielectric layer
[0094] 238: Upper electrode
[0095] 240: Redundant capacitor array
[0096] 242: Redundant capacitor
[0097] 244: Lower electrode
[0098] 246: Dielectric layer
[0099] 248: Upper electrode
[0100] 250: Oxide layer
[0101] 260: Top conductive layer
[0102] 262: Bottom conductive layer
[0103] 270: First memory die
[0104] 280: Second memory die.
Claims
1. A semiconductor device, characterized in that: include: Package substrate; An interposer is disposed on the packaging substrate, wherein the interposer comprises: A plurality of conventional capacitor arrays are located in the interposer, wherein each of the conventional capacitor arrays comprises a plurality of conventional capacitors, wherein each of the conventional capacitors comprises: Lower electrode; a dielectric layer surrounded by the lower electrode; and an upper electrode surrounded by the dielectric layer; A plurality of redundant capacitor arrays are located in the interposer, wherein each of the redundant capacitor arrays includes a plurality of redundant capacitors, wherein each of the redundant capacitors includes: Lower electrode; a dielectric layer surrounded by the lower electrode; and an upper electrode surrounded by the dielectric layer; an oxide layer disposed on the interposer, wherein the oxide layer isolates the upper electrode of each of the conventional capacitors from the upper electrode of each of the redundant capacitors; and A top conductive layer is located on the oxide layer, wherein the top conductive layer connects the top electrode of each of the conventional capacitors and the top electrode of each of the redundant capacitors.
2. The semiconductor device according to claim 1, wherein: Further including: a first memory chiplet disposed on the top conductive layer; and A second memory chiplet is disposed on the top conductive layer and adjacent to the first memory chiplet.
3. The semiconductor device according to claim 1, wherein: Further including: a first memory chiplet disposed on the top conductive layer; and A second memory chiplet is disposed on and overlaps the first memory chiplet.
4. The semiconductor device according to claim 1, wherein: The conventional capacitor arrays are connected in series.
5. The semiconductor device according to claim 1, wherein: The conventional capacitor arrays are connected in parallel.
6. The semiconductor device according to claim 1, wherein: The redundant capacitor arrays are connected in series.
7. The semiconductor device according to claim 1, wherein: The redundant capacitor arrays are connected in parallel.
8. The semiconductor device according to claim 1, wherein: The conventional capacitor arrays are connected in series with the redundant capacitor arrays.
9. The semiconductor device according to claim 1, wherein: The conventional capacitor arrays are connected in parallel with the redundant capacitor arrays.
10. The semiconductor device according to claim 1, wherein: One of the redundant capacitor arrays is connected to one of the regular capacitor arrays.
11. The semiconductor device according to claim 1, wherein: The redundant capacitor arrays include: A plurality of first redundant capacitor arrays connected to each other; and A plurality of second redundant capacitor arrays are connected to each other, wherein the second redundant capacitor arrays are separated from the first redundant capacitor arrays.
12. The semiconductor device according to claim 1, wherein: The intermediary layer includes: N-well region; An N+ region is disposed in the N-well region, and the N+ region surrounds the conventional capacitor arrays and the redundant capacitor arrays.
13. A semiconductor device, characterized in that: include: Package substrate; An interposer is disposed on the packaging substrate; An oxide layer is located on the interposer, wherein the oxide layer comprises: A plurality of conventional capacitor arrays are located on the interposer, wherein each of the conventional capacitor arrays comprises: A lower electrode, comprising two vertical portions and a lateral portion; a dielectric layer comprising two vertical portions and a lateral portion; and an upper electrode surrounded by the dielectric layer; A plurality of redundant capacitor arrays are located on the interposer, wherein each of the redundant capacitor arrays comprises: A lower electrode, comprising two vertical portions and a lateral portion; a dielectric layer comprising two vertical portions and a lateral portion; and an upper electrode surrounded by the dielectric layer; a bottom conductive layer located between the interposer and the oxide layer; and A top conductive layer is located on the oxide layer.
14. The semiconductor device according to claim 13, wherein: Each of the conventional capacitor arrays and each of the redundant capacitor arrays includes a first capacitor, a second capacitor and a third capacitor, wherein the second capacitor is arranged between the first capacitor and the third capacitor.
15. The semiconductor device according to claim 14, wherein: The first capacitor comprises: the upper electrode; The dielectric layer surrounds the upper electrode; and A portion of the bottom conductive layer, wherein the dielectric layer contacts the portion of the bottom conductive layer.
16. The semiconductor device according to claim 14, wherein: The second capacitor comprises: the upper electrode; the vertical portion of the dielectric layer; and The vertical portion of the lower electrode, wherein the dielectric layer is disposed between the upper electrode and the lower electrode.
17. The semiconductor device according to claim 14, wherein: The third capacitor comprises: the upper electrode; the lateral portion of the dielectric layer; and The lateral portion of the lower electrode, wherein the dielectric layer is disposed between the upper electrode and the lower electrode.