Chip, chip on carrier, transmitter and related equipment

Abstract

The invention discloses a chip, a chip on carrier, a transmitter and related equipment. The chip comprises a conductive substrate, an insulating layer, a quantum well, a first capacitor electrode, a distributed feedback laser (DFB) electrode and an electro-absorption modulator (EAM) electrode, the insulating layer and the quantum well grow on the conductive substrate, the DFB electrode and the EAM electrode grow on the insulating layer and the quantum well, the first capacitor electrode grows on the insulating layer, and the second capacitor electrode grows on the EAM electrode. And the first capacitor electrode is used for forming a first capacitor with the conductive substrate, so that the capacitor is built in the EML chip, the modulation effect of a high-frequency signal on a DFB region can be better eliminated while the COC structure and process are simplified, and differential driving of lower RIN noise is realized.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communication technologies, and particularly to a chip, a chip on a carrier, a transmitter, and related devices. Background Art

[0002] Electro-absorption modulated lasers (EMLs) are widely used in the field of optical communication due to their characteristics such as low cost, high bandwidth, and good linearity.

[0003] An EML chip usually includes two parts. One part is a distributed feedback laser (DFB) region for generating laser with a specific wavelength, and the other part is an electro-absorption modulator (EAM) region. Currently, the mainstream EML chips adopt a common cathode chip architecture for these two parts, and the optical coupling is carried out in a butt-joint manner.

[0004] The chips with such a structure are usually driven in a single-ended manner at the periphery. At the same time, such chips can also achieve differential driving through the design of a chip on carrier (COC). When realizing differential driving, an external capacitor C needs to be added outside the EML chip to eliminate the modulation of the signal on the differential signal connection line on the distributed feedback laser (DFB) region. Otherwise, the relative intensity noise (RIN) of the laser will deteriorate severely.

[0005] However, in the above solution, the requirements for the external capacitor C are relatively high. Ordinary external capacitors are difficult to ensure that the RIN of the EML chip is at a good level. At the same time, this solution has relatively high requirements for the volume of the capacitor C, and the large-sized external capacitor also affects the overall bandwidth of the COC, making the overall complexity of the COC relatively high. Summary of the Invention

[0006] The embodiments of the present application provide a chip. By integrating a capacitor in the chip, while simplifying the structure and process of the COC, it can also better eliminate the modulation effect of high-frequency signals on the DFB region and achieve differential driving with lower RIN noise. The embodiments of the present application also provide corresponding chips on carriers, transmitters, optical components, optical modules, optical line terminals, optical network units, and communication devices.

[0007] A first aspect of the present application provides a chip, which includes a conductive substrate, an insulating layer, a quantum well, a first capacitor electrode, a distributed feedback laser (DFB) electrode, and an electro-absorption modulator (EAM) electrode. Among them, the insulating layer and the quantum well are grown on the conductive substrate, the insulating layer and the quantum well jointly cover the conductive substrate, and the insulating layer covers the side surface of the quantum well. The DFB electrode and the EAM electrode are grown on the insulating layer and the quantum well, and the DFB electrode and the EAM electrode cover the top surface of the quantum well. The first capacitor electrode is grown on the insulating layer, the first capacitor electrode is electrically connected to the DFB electrode, and the first capacitor electrode is used to form a first capacitor with the conductive substrate. The DFB electrode, the EAM electrode, and the first capacitor electrode respectively cover different and non-adjacent parts on the insulating layer.

[0008] In the present application, the chip is an electro-absorption modulated laser (EML) chip, and the conductive substrate serves as the substrate of the entire chip. The specific material thereof can be indium phosphide (InP), etc. The insulating layer and the quantum well are grown on the surface of the conductive substrate.

[0009] In the present application, the insulating layer is non-conductive and needs to cover the side of the quantum well. That is, the height of the quantum well can be the same as that of the insulating layer, or the height of the quantum well can be higher than that of the insulating layer, and the insulating layer covers the side of the part where the quantum well is higher. The quantum well can be divided into two parts, one part is covered by the DFB electrode, and the other part is covered by the EAM electrode.

[0010] In the present application, the quantum well is a thin-layer structure, usually made of thin-layer semiconductor media. The quantum well in the DFB region is used to generate laser. The DFB electrode and the EAM electrode serve as the P pole, and the conductive substrate is shared as the N pole. The DFB electrode, the EAM electrode, the quantum well, and the insulating layer are all inherent structures of the EML chip.

[0011] In the present application, the integrated capacitor (the first capacitor electrode) of the EML chip can be realized by the epitaxial process of the EML chip, such as molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD) method. The two electrodes at both ends of the capacitor are the surface capacitor electrode and the conductive substrate respectively. The capacitance value of the first capacitor can be increased by reducing the thickness of the thin-film material between the two electrodes or selecting a material with a larger dielectric constant, so as to achieve a better effect of controlling the relative intensity noise (RIN) of the EML chip.

[0012] In this application, the growth positions of the DFB electrode, the EAM electrode, and the first capacitor electrode are arbitrary, but the DFB electrode, the EAM electrode, and the first capacitor electrode do not couple with each other or directly contact each other, that is, they exist independently on the insulating layer or the quantum well.

[0013] In this first aspect, the chip includes a conductive substrate, an insulating layer, a quantum well, a first capacitor electrode, a distributed feedback laser (DFB) electrode, and an electro-absorption modulator (EAM) electrode. Among them, the first capacitor electrode is used to form a first capacitor with the conductive substrate, thereby integrating the capacitor into the EML chip. While simplifying the COC structure and process, it can also better eliminate the modulation effect of high-frequency signals on the DFB region and achieve differential driving with lower relative intensity noise (RIN).

[0014] In a possible implementation of the first aspect, the chip further includes a semiconductor optical amplifier (SOA) electrode and a second capacitor electrode. The SOA electrode is grown on the insulating layer and the quantum well, and the SOA electrode covers the top surface of the quantum well. The second capacitor electrode is grown on the insulating layer, and the second capacitor electrode is electrically connected to the SOA electrode. The second capacitor electrode is used to form a second capacitor with the conductive substrate. The DFB electrode, the EAM electrode, the SOA electrode, the first capacitor electrode, and the second capacitor electrode respectively cover different and non-adjacent parts on the insulating layer.

[0015] In this possible implementation, by coupling the semiconductor optical amplifier, the applicable scenarios of the chip are increased, and the feasibility of the solution is improved.

[0016] In a possible implementation of the first aspect, the conductive substrate includes a metallized part, and the first capacitor electrode is used to form a first capacitor with the metallized part.

[0017] In this possible implementation, the size or material of the metallized part in the conductive substrate can be adjusted or set according to the user's needs, so as to more conveniently control the capacitance value of the first capacitor.

[0018] In a possible implementation of the first aspect, the material of the insulating layer is silicon dioxide or titanium dioxide.

[0019] In this possible implementation, silicon dioxide or titanium dioxide is used as a dielectric material, and its dielectric constant is relatively large, which can further increase the capacitance value of the first capacitor.

[0020] In a possible implementation of the first aspect, the chip further includes a first connection line, and the DFB electrode and the first capacitor electrode are electrically connected inside the chip through the first connection line.

[0021] In this possible implementation, the DFB electrode and the first capacitor electrode are connected on the chip, which is beneficial to the miniaturization of the entire chip.

[0022] In a possible implementation of the first aspect, the chip further includes a second connection line, and the SOA electrode and the second capacitor electrode are electrically connected inside the chip through the second connection line.

[0023] In this possible implementation, the SOA electrode and the second capacitor electrode are also connected on the chip, which is beneficial to the miniaturization of the entire chip.

[0024] In the second aspect of this application, a chip on a carrier is provided. The chip on the carrier includes a chip and a differential signal transmission line. The differential signal transmission line is used to provide a driving signal to the chip. The chip includes a conductive substrate, an insulating layer, a quantum well, a first capacitor electrode, a distributed feedback laser (DFB) electrode, and an electro-absorption modulator (EAM) electrode. Among them, the insulating layer and the quantum well are grown on the conductive substrate. The insulating layer and the quantum well jointly cover the conductive substrate, and the insulating layer covers the side surface of the quantum well. The DFB electrode and the EAM electrode are grown on the insulating layer and the quantum well, and the DFB electrode and the EAM electrode cover the top surface of the quantum well. The first capacitor electrode is grown on the insulating layer, and the first capacitor electrode is used to form a first capacitor with the conductive substrate. The DFB electrode, the EAM electrode, and the first capacitor electrode respectively cover different and non-adjacent parts on the insulating layer.

[0025] In this second aspect, the chip of the above first aspect or any possible implementation of the first aspect can be applied to the chip on a carrier, with relatively little modification to the overall structure of the original chip on a carrier, which can avoid high requirements for capacitors and improve the feasibility of the solution.

[0026] In a possible implementation of the second aspect, the chip on a carrier further includes a first conductive block and a first magnetic bead. The first conductive block is connected to the first capacitor electrode through the first magnetic bead.

[0027] In this possible implementation, the first magnetic bead is directly connected to the EML chip. Compared with the original chip-on-carrier solution, the connection length between the two is shortened, which is beneficial to improving the overall bandwidth of the chip on a carrier.

[0028] In a possible implementation of the second aspect, the chip further includes a semiconductor optical amplifier (SOA) electrode and a second capacitor electrode. The SOA electrode is grown on the insulating layer and the quantum well, and the SOA electrode covers the top surface of the quantum well. The second capacitor electrode is grown on the insulating layer, and the second capacitor electrode is electrically connected to the SOA electrode. The second capacitor electrode is used to form a second capacitor with the conductive substrate. The DFB electrode, the EAM electrode, the SOA electrode, the first capacitor electrode, and the second capacitor electrode respectively cover different and non-adjacent parts on the insulating layer.

[0029] In a possible implementation of the second aspect, the chip on the carrier further includes a second conductive block and a second magnetic bead, and the second conductive block is connected to the second capacitor electrode through the second magnetic bead.

[0030] In this possible implementation, the second magnetic bead is directly connected to the SOA, shortening the connection length between the two, which is beneficial to the miniaturization of the chip on the carrier.

[0031] In a possible implementation of the second aspect, the conductive substrate includes a metallized portion, and the first capacitor electrode is used to form a first capacitor with the metallized portion.

[0032] In a possible implementation of the second aspect, the material of the insulating layer is silicon dioxide or titanium dioxide.

[0033] In a possible implementation of the second aspect, the chip further includes a first connection line, and the DFB electrode and the first capacitor electrode are electrically connected inside the chip through the first connection line.

[0034] In a possible implementation of the second aspect, the chip on the carrier further includes a third connection line, and the DFB electrode and the first capacitor electrode are electrically connected outside the chip through the third connection line.

[0035] In this possible implementation, the DFB electrode and the first capacitor electrode can be connected outside the chip, improving the feasibility of the solution.

[0036] In a possible implementation of the second aspect, the chip further includes a second connection line, and the SOA electrode and the second capacitor electrode are electrically connected inside the chip through the second connection line.

[0037] In a possible implementation of the second aspect, the chip on the carrier further includes a fourth connection line, and the SOA electrode and the second capacitor electrode are electrically connected outside the chip through the fourth connection line.

[0038] In this possible implementation, the SOA electrode and the second capacitor electrode can also be connected outside the chip, improving the feasibility of the solution.

[0039] In a possible implementation of the second aspect, the chip on the carrier further includes a detection unit, and the detection unit is used to determine the light emission condition of the chip.

[0040] In this possible implementation, the chip on the carrier does not need to externally dispose a capacitor on the EML chip, avoiding the backlight occlusion of the EML chip by the externally disposed capacitor in the original chip-on-carrier solution, and making it easier to implement backlight detection.

[0041] In a third aspect of the present application, a transmitter is provided. The transmitter includes a transmission signal source and a chip on a carrier as described in the second aspect or any possible implementation manner of the second aspect. The transmission signal source is configured to provide a driving signal to the chip through a differential signal transmission line.

[0042] In a fourth aspect of the present application, an optical component is provided. The optical component includes a chip as described in the first aspect or any possible implementation manner of the first aspect, a chip on a carrier as described in the second aspect or any possible implementation manner of the second aspect, or a transmitter as described in the third aspect.

[0043] In a fifth aspect of the present application, an optical module is provided. The optical module includes a chip as described in the first aspect or any possible implementation manner of the first aspect, a chip on a carrier as described in the second aspect or any possible implementation manner of the second aspect, or a transmitter as described in the third aspect.

[0044] In a sixth aspect of the present application, an optical line terminal is provided. The optical line terminal includes a chip as described in the first aspect or any possible implementation manner of the first aspect, a chip on a carrier as described in the second aspect or any possible implementation manner of the second aspect, or a transmitter as described in the third aspect.

[0045] In a seventh aspect of the present application, an optical network unit is provided. The optical network unit includes a chip as described in the first aspect or any possible implementation manner of the first aspect, a chip on a carrier as described in the second aspect or any possible implementation manner of the second aspect, or a transmitter as described in the third aspect.

[0046] In an eighth aspect of the present application, a communication device is provided. The communication device includes a chip as described in the first aspect or any possible implementation manner of the first aspect, a chip on a carrier as described in the second aspect or any possible implementation manner of the second aspect, or a transmitter as described in the third aspect. Description of the Drawings

[0047] Figure 1 It is a schematic diagram of the architecture of a passive optical network;

[0048] Figure 2 It is a schematic diagram of the architecture of an electro-absorption modulated laser (EML) transmitter;

[0049] Figure 3 It is a cross-sectional schematic diagram of the chip provided by the embodiment of the present application;

[0050] Figure 4 It is a top view schematic diagram of the chip provided by the embodiment of the present application;

[0051] Figure 5 It is a schematic diagram of another embodiment of the chip provided by the embodiment of the present application;

[0052] Figure 6 Another schematic diagram of the chip provided by the embodiment of the present application;

[0053] Figure 7 Another schematic diagram of the chip provided by the embodiment of the present application;

[0054] Figure 8A A schematic diagram of an embodiment of the chip on the carrier provided by the embodiment of the present application;

[0055] Figure 8B A schematic diagram of an embodiment of the transmitter provided by the embodiment of the present application;

[0056] Figure 9 Another schematic diagram of the transmitter provided by the embodiment of the present application;

[0057] Figure 10 A schematic diagram of an embodiment of the passive optical network provided by the embodiment of the present application. Detailed implementation manners

[0058] The embodiments of the present application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Those of ordinary skill in the art will know that with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0059] The terms "first", "second", etc. in the specification, claims and drawings of the present application are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments described here can be implemented in an order different from that shown or described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0060] The special term "exemplary" here means "serving as an example, embodiment or illustrative". Any embodiment described as "exemplary" here does not have to be construed as superior to or better than other embodiments.

[0061] In addition, for a better illustration of the present application, numerous specific details are provided in the following detailed implementation manners. Those skilled in the art should understand that the present application can also be implemented without certain specific details. In some instances, methods, means, elements, and circuits well-known to those skilled in the art are not described in detail to highlight the gist of the present application.

[0062] The application scenarios related to the embodiments of the present application are illustrated by way of example below.

[0063] In the field of optical communication, both Ethernet and passive optical network (PON) need to achieve the mutual conversion between electrical signals and optical signals. Exemplarily, PON is a passive optical network with a point-to-multipoint structure, which is a combination of network elements in an optical access network based on an optical distribution network (ODN), and there are no electronic devices and electronic power supplies in the optical distribution network. Among them, the ODN is entirely composed of passive devices such as optical splitters. A PON includes an optical line termination (OLT) installed in a central control station and multiple optical network units (ONUs) installed in user premises, and implements a set of specific physical medium dependent layers, transmission convergence layers, and management protocols.

[0064] As Figure 1 shown, the optical line termination OLT is connected to two optical network units ONUs through the optical distribution network ODN. The ODN refers to the entire passive optical network between the OLT port and each ONU port. It should be understood that in other networking scenarios, an OLT can also be connected to a larger number of ONUs. Among them, the OLT needs to be docked with the ODN through an optical module. On the one hand, the optical module needs to convert the electrical signal sent by the OLT into an optical signal and transmit it to the ONU through the ODN; on the other hand, the optical module also needs to convert the optical signal transmitted from the ONU through the ODN into an electrical signal and then send the electrical signal to the OLT.

[0065] Specifically, the optical module or the optical component in the optical module includes a transmitter, and the transmitter is used to convert the electrical signal into an optical signal. Due to characteristics such as low cost, high bandwidth, and good linearity, electro-absorption modulated laser (EML) is widely used in the transmitter.

[0066] As Figure 2As shown, a transmitter using an EML generally includes a transmission signal source, a driver, and an EML optical device. The transmission signal source is usually a digital to analog converter (DAC), and the EML optical device is an EML chip and components coupled to the chip. To further reduce the power consumption of the module, the driver is integrated with the transmission signal source to directly drive the EML optical device, which can eliminate the external additional driver chip, achieve lower costs, and generally using an integrated solution is also beneficial to reducing the power consumption of the overall transmitter.

[0067] There are generally two ways to directly drive an EML: single-ended drive and differential drive.

[0068] Single-ended drive: The transmission signal source outputs a single-ended signal, and the EML optical device is driven by the single-ended signal. Since the output of the transmission signal source is a single-ended signal, the signal quality is degraded to a certain extent compared with the differential signal. At the same time, using a single-ended signal to drive the EML optical device requires a higher output amplitude of the single-ended signal and it is difficult to achieve a high extinction ratio (ER), so it is more difficult to apply in application scenarios with high ER requirements.

[0069] Differential drive: The transmission signal source outputs a differential signal, and the EML optical device is driven by the differential signal. The output signal of this scheme is a differential signal, and the signal quality is relatively better. At the same time, when driving the EML optical device differentially, the requirement for the signal output amplitude is relatively low, and lower power consumption can be achieved.

[0070] With the increase in the rate of optical communication, limited by the output ability of the DAC, the single-ended direct drive scheme can no longer meet the requirements, so the differential drive scheme is more widely used. Currently, the EML chip can use a complex differential EML chip or the architecture of a traditional single-ended drive chip. In the packaging of the chip, differential drive is achieved through the design of chip on carrier (COC), that is, the COC differential drive scheme. However, the introduction of differential signal connection lines to modulate the signal will increase the relative intensity noise (RIN) of the EML chip. Therefore, a capacitor needs to be added in the distributed feedback laser (DFB) area of the EML to eliminate the modulation of the high-frequency signal on the differential signal connection line on the DFB area.

[0071] However, in the above solution, in order to ensure a relatively low RIN of the EML chip, the requirements for the external capacitor C are relatively high. It not only requires a relatively small capacitor size, but also requires a relatively large capacitance value, a relatively low equivalent series inductance (ESL), and a relatively low equivalent series resistance (ESR).

[0072] However, in actual situations, it is difficult to achieve a relatively large capacitance and a relatively small size through thin-film capacitor processes in a COC, resulting in serious deterioration of the response of the relative intensity noise of the EML chip in the differential drive structure to the modulation signal. Based on this, an embodiment of the present application provides a chip. By integrating a capacitor in the chip, while simplifying the COC structure and process, it can also better eliminate the modulation effect of high-frequency signals on the DFB region and achieve a differential drive with a lower RIN. Embodiments of the present application also provide corresponding chips on carriers, transmitters, optical components, optical modules, optical line terminals, optical network units, and communication devices. The following will be described in detail respectively.

[0073] The chip, chip on a carrier, and transmitter provided by the embodiments of the present application will be described below in combination with the above application scenarios.

[0074] As Figure 3 and Figure 4 shown, an embodiment of the present application provides a chip. An embodiment of the chip includes a conductive substrate 100, an insulating layer 200, a quantum well 300, a first capacitor electrode 400, a distributed feedback laser (DFB) electrode (pad) 500, and an electro-absorption modulator (EAM) electrode 600.

[0075] Among them, the insulating layer 200 and the quantum well 300 are grown on the conductive substrate 100. The DFB electrode 500 and the EAM electrode 600 ( Figure 3 the EAM electrode 600 in Figure 4 is blocked by the DFB electrode 500, so the EAM electrode 600 is shown

[0076] Specifically, the chip is an electro-absorption modulated laser (EML) chip. The conductive substrate 100 serves as the base of the entire chip, and the conductive substrate 100 can conduct electricity. Its specific material can be indium phosphide (InP), etc. The insulating layer 200 and the quantum well 300 are grown on the conductive substrate 100, that is, the insulating layer 200 and the quantum well 300 jointly cover the entire surface of the conductive substrate 100. For example, the quantum well 300 can be grown in the middle of the conductive substrate 100, and the other surface parts of the conductive substrate 100 are covered by the insulating layer 200.

[0077] The insulating layer 200 is non-conductive, and the insulating layer 200 needs to cover the side of the quantum well 300. That is, the quantum well 300 can have the same height as the insulating layer 200, or the height of the quantum well 300 can be higher than that of the insulating layer 200, and the insulating layer 200 covers the side of the part where the quantum well 300 is higher. The quantum well 300 can be divided into two parts, one part is covered by the DFB electrode 500, and the other part is covered by the EAM electrode 600. The quantum well 300 is used to generate laser. The quantum well 300 is usually made of thin-layer semiconductor media. For example, it can be formed in a semiconductor by sandwiching a material (such as gallium arsenide) between two materials with a wider bandgap (such as aluminum arsenide), and can be prepared by molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD) methods.

[0078] Furthermore, the DFB electrode 500 and the EAM electrode 600 are grown on the insulating layer 200 and the quantum well 300, that is, the DFB electrode 500 covers the quantum well 300 and the insulating layer 200, and the EAM electrode 600 also covers the quantum well 300 and the insulating layer 200. Specifically, both the DFB electrode 500 and the EAM electrode 600 cover the top surface of the quantum well 300. Thus, the side of the quantum well 300 is covered by the insulating layer 200, the bottom surface is covered by the conductive substrate 100, and the top surface is covered by the DFB electrode 500 and the EAM electrode 600.

[0079] Among them, the DFB electrode 500 and the EAM electrode 600 serve as the P pole, and the common conductive substrate 100 serves as the N pole. The DFB electrode 500, the EAM electrode 600, the quantum well 300, and the insulating layer 200 are all inherent structures of the EML chip, and the embodiments of the present application will not elaborate on them.

[0080] In the embodiment of the present application, the first capacitive electrode 400 is grown on the insulating layer 200, and the first capacitive electrode 400 is used to form a first capacitor C with the conductive substrate 100. The DFB electrode 500, the EAM electrode 600, and the first capacitive electrode 400 respectively cover different and non-adjacent parts on the insulating layer 200, that is, the growth positions of the DFB electrode 500, the EAM electrode 600, and the first capacitive electrode 400 are arbitrary, but the DFB electrode 500, the EAM electrode 600, and the first capacitive electrode 400 do not couple with each other or directly contact each other, that is, they exist independently on the insulating layer 200 or the quantum well 300. Exemplarily, the quantum well 300 is located in the middle of the entire chip, the DFB electrode 500 and the EAM electrode 600 are grown on the insulating layer 200 on the right side of the quantum well 300 and on the quantum well 300, the first capacitive electrode 400 is grown on the insulating layer 200 on the left side of the quantum well 300, and the first capacitive electrode 400 does not contact the DFB electrode 500.

[0081] It should be understood that the DFB electrode 500 and the EAM electrode 600 can also be grown on the insulating layer 200 on the left side of the quantum well 300, and the first capacitive electrode 400 is grown on the insulating layer 200 on the right side of the quantum well 300. The embodiment of the present application does not limit the arrangement positions of each element on the chip, as long as it is ensured that elements such as the DFB electrode 500 can achieve their own functions.

[0082] For the parallel plate capacitor formula, there is:

[0083]

[0084] Among them, A is the area of the parallel plate capacitor, that is, the area of the first capacitive electrode 400, d is the distance between the two parallel plates, that is, the distance between the first capacitive electrode 400 and the conductive substrate 100, and ε is the dielectric constant of the medium between the parallel plates, that is, the dielectric constant of the insulating layer 200.

[0085] Through the epitaxial process of the EML chip, such as MBE and MOCVD, a smaller d can be achieved, or a dielectric material with a large dielectric constant is used. For example, the material of the insulating layer 200 is silicon dioxide or titanium dioxide, which can all increase the capacitance value of the first capacitor C, thereby better controlling the relative intensity noise of the EML chip.

[0086] Optionally, as Figure 5As shown, the conductive substrate 100 includes a metallized portion 101, and the first capacitor electrode 400 is used to form a first capacitor C with the metallized portion 101. Specifically, the metallized portion 101 in the conductive substrate 100 is parallel to the first capacitor electrode 400, and the metallized portion 101 and the first capacitor electrode 400 form two parallel plates, that is, the first capacitor C is formed. For the metallized portion 101 in the conductive substrate 100, its size or material can be adjusted or set according to the user's needs, so as to more conveniently control the capacitance value of the first capacitor C.

[0087] Optionally, as Figure 6 shown, the chip further includes a semiconductor optical amplifier (SOA) electrode 700 and a second capacitor electrode 800. The SOA electrode 700 is grown on the insulating layer 200 and the quantum well 300, and the second capacitor electrode 800 is grown on the insulating layer 200. The second capacitor electrode 800 is used to form a second capacitor with the conductive substrate 100.

[0088] At this time, the SOA electrode 700 covers the top surface of the quantum well 300. The quantum well 300 can be divided into three parts. One part is covered by the DFB electrode 500, one part is covered by the EAM electrode 600, and the other part is covered by the SOA electrode 700. The second capacitor electrode 800 is electrically connected to the SOA electrode 700, and the DFB electrode 500, the EAM electrode 600, the SOA electrode 700, the first capacitor electrode 400, and the second capacitor electrode 800 respectively cover different and non-adjacent parts on the insulating layer 200, that is, there is no mutual coupling or direct contact between the DFB electrode 500, the EAM electrode 600, the first capacitor electrode 400, the SOA electrode 700, and the second capacitor electrode 800.

[0089] Specifically, at this time, the chip is an EML-SOA chip. The chip further includes an SOA electrode 700 and a second capacitor electrode 800. The arrangement of the SOA electrode 700 and the second capacitor electrode 800 can refer to the DFB electrode 500 and the first capacitor electrode 400, that is, the SOA 700 electrode is grown on the insulating layer 200 on the right side of the quantum well 300 and on the quantum well 300, and the second capacitor electrode 800 is grown on the insulating layer 200 on the left side of the quantum well 300, and the second capacitor electrode 800 does not contact the SOA electrode 700.

[0090] It should be understood that the SOA electrode 700 can also be replaced by other optical amplifier electrodes, such as an erbium-doped fiber amplifier (EDFA) electrode. The embodiments of the present application do not limit the elements that can be stacked on the EML chip.

[0091] Optionally, as Figure 7As shown, the chip further includes a first connection line and a second connection line. The DFB electrode 500 and the first capacitor electrode 400 are electrically connected inside the chip through the first connection line, and the SOA electrode 700 and the second capacitor electrode 800 are electrically connected inside the chip through the second connection line. That is, the first capacitor electrode 400 and the DFB electrode 500 are connected in a on-chip manner, and the second capacitor electrode 700 and the SOA electrode 800 are connected in a on-chip manner. This avoids the need for the DFB electrode 500 to be connected to the first capacitor electrode 400 outside the chip, and also avoids the need for the SOA electrode 700 to be connected to the second capacitor electrode 800 outside the chip. It should be understood that the off-chip connection method is more complex and is not conducive to the miniaturization of the entire EML chip.

[0092] It should be understood that the first connection line and the second connection line do not need to be used simultaneously, and whether to use the first connection line and / or the second connection line can be selected according to actual needs.

[0093] As Figure 8A shown, an embodiment of the present application further provides a chip on carrier (COC). As Figure 8B shown, the COC can be applied to a transmitter. The transmitter includes a transmission signal source and a chip on carrier (COC). The COC includes a chip and a differential signal transmission line. The differential signal transmission line is used to provide a driving signal to the chip, and the transmission signal source is used to provide a driving signal to the chip through the differential signal transmission line. The chip includes a conductive substrate, an insulating layer, a quantum well, a first capacitor electrode, a distributed feedback laser DFB electrode, and an electro-absorption modulator EAM electrode.

[0094] Among them, the insulating layer and the quantum well are grown on the conductive substrate. The insulating layer and the quantum well jointly cover the conductive substrate, and the insulating layer covers the side of the quantum well. The DFB electrode and the EAM electrode are grown on the insulating layer and the quantum well, and the first capacitor electrode is grown on the insulating layer. The first capacitor electrode is electrically connected to the DFB electrode, and the first capacitor electrode is used to form a first capacitor with the conductive substrate. The DFB electrode, the EAM electrode, and the first capacitor electrode respectively cover different and non-adjacent parts on the insulating layer.

[0095] Specifically, the chip in the transmitter is the chip as Figures 3 to 7 described. Its specific implementation can refer to the corresponding description above. For example, in this chip, optionally, the conductive substrate includes a metallized part, the first capacitor electrode is used to form a first capacitor with the metallized part, and the material of the insulating layer is silicon dioxide or titanium dioxide. This embodiment of the present application will not be elaborated further.

[0096] Exemplarily, the transmission signal source includes a printed circuit board (PCB). The digital-to-analog converter (DAC) on the PCB outputs differential signals. The PCB also includes two radio frequency differential signal lines (RF- and RF+), which serve as the transmission lines of the transmission signal source and transmit the differential signals of P and N respectively. The COC also includes two differential signal transmission lines (AC- and AC+). AC- is connected to RF- through an off-chip connection line, and AC+ and RF+ are also connected in an off-chip manner. In addition, the PCB and the COC are also grounded (GND) through two connection lines. AC- and AC+ are connected to the chip, enabling the transmission signal source to provide a driving signal to the chip, that is, differential driving is achieved.

[0097] Furthermore, the PCB also includes two electrodes B and C, and the COC also includes two electrodes A and D. Electrode B and electrode C on the PCB are respectively connected to RF- and RF+ through beads. The EML chip also includes a first connection line, and the DFB electrode and the first capacitor electrode are electrically connected inside the chip through the first connection line.

[0098] The COC also includes a first conductive block and a first bead. Electrode D is specifically a conductive block, that is, the first conductive block. The first capacitor electrode on the EML chip is connected to electrode D through the first bead. The power supply to the DFB electrode can be controlled by the current between electrode A and electrode B. The first bead is directly placed on the first capacitor electrode of the EML chip, that is, the first bead is directly connected to the EML chip. Compared with the original chip-on-carrier scheme, the connection length between the two is shortened, which is beneficial to improving the overall bandwidth of the chip-on-carrier.

[0099] For the EAM electrode, the COC also includes a second capacitor (capacitor 2). The EAM electrode is respectively connected to AC+ and the second capacitor through off-chip connection lines. The bias voltage of the EAM electrode is achieved by controlling the voltage difference corresponding to electrode B and electrode C.

[0100] Optionally, the DFB electrode and the first capacitor electrode may not be connected inside the chip. At this time, the COC also includes a third connection line. The DFB electrode and the first capacitor electrode are electrically connected outside the chip through the third connection line, that is, the DFB electrode and the first capacitor electrode are connected in an off-chip manner, such as through external wire bonding (the third connection line). At this time, the power supply control method for the DFB electrode remains unchanged.

[0101] Optionally, as Figure 9As shown, the chip in the transmitter further includes a semiconductor optical amplifier (SOA) electrode and a second capacitor electrode. The SOA electrode is grown on the insulating layer and the quantum well, and the SOA electrode covers the top surface of the quantum well. The second capacitor electrode is grown on the insulating layer, and the second capacitor electrode is electrically connected to the SOA electrode. The second capacitor electrode is used to form a second capacitor with the conductive substrate. The DFB electrode, the EAM electrode, the SOA electrode, the first capacitor electrode, and the second capacitor electrode respectively cover different and non-adjacent parts on the insulating layer. The chip at this time can also refer to the EML-SOA chip as shown in Figure 6 which will not be elaborated in this embodiment of the present application.

[0102] Exemplarily, the transmitter can refer to the transmitter as shown in Figure 8B The difference is that the EML-SOA chip further includes a second connection line. The SOA electrode and the second capacitor electrode are electrically connected inside the chip through the second connection line, and the COC further includes a second conductive block (electrode E) and a second magnetic bead. The second conductive block is connected to the second capacitor electrode through the second magnetic bead. The power supply to the SOA electrode can be controlled by the current between electrode E and electrode B.

[0103] Optionally, the SOA electrode and the second capacitor electrode may not be connected inside the chip. At this time, the COC further includes a fourth connection line. The SOA electrode and the second capacitor electrode are electrically connected outside the chip through the fourth connection line, that is, the SOA electrode and the second capacitor electrode are connected by an external wire bonding (the fourth connection line) outside the chip. At this time, the power supply control method for the SOA electrode remains unchanged.

[0104] Optionally, in the transmitter as shown in Figure 8B or Figure 9 the COC further includes a detection unit. The detection unit is used to determine the light emission situation of the chip. The detection unit can specifically be a monitor photodiode (mPD). Since the first capacitor electrode is coupled to the EML chip, the backlight output of the EML chip will no longer be blocked by the external capacitor on the traditional transmitter. Therefore, the detection unit can better implement backlight detection.

[0105] It should be understood that the chip on the carrier provided in this embodiment of the present application is not limited to being applied in a transmitter. All possible implementation manners of the chip on the carrier can be separately implemented on the COC, rather than being limited to being implemented on a transmitter.

[0106] Summarizing the above embodiments, the chip, the chip on the carrier, or the transmitter provided in this embodiment of the present application can bring the following beneficial effects including but not limited to the following four points:

[0107] (1) Adopting a differential driving scheme to avoid the requirements for the output amplitude of the digital-to-analog converter in the single-ended driving scheme;

[0108] (2) Integrate the capacitor on the chip. Through the epitaxial process, it is easier to implement a capacitor with a large capacitance value, avoiding the high requirements for the capacitor in the COC differential drive scheme, and thus better controlling the relative intensity noise of the EML chip.

[0109] (3) The modification to the COC differential drive scheme is small, avoiding the complex structure of the differential EML chip, reducing the chip production complexity, and preventing the large external capacitor from affecting the overall bandwidth of the COC.

[0110] (4) The transmitter does not need an external capacitor for the EML chip, avoiding the backlight occlusion of the EML chip in the COC differential drive scheme and making it easier to implement backlight detection.

[0111] The chip, the chip-on-carrier, and the transmitter provided by the embodiments of the present application are introduced above. Next, the related devices provided by the embodiments of the present application are introduced with reference to the accompanying drawings.

[0112] As Figure 10 shown, an embodiment of the present application provides a passive optical network, which is a 50G PON or may also be the passive optical network as Figure 1 shown. The passive optical network includes an optical line terminal 900, an optical network unit 1000, and an optical distribution network 1100. The optical line terminal 900 and the optical network unit 1000 can also be understood as communication devices.

[0113] The optical line terminal 900 includes an optical module 901, and the optical module 901 includes an optical component 902. The optical network unit 1000 also includes an optical module 1001, and the optical module 1001 includes an optical component 1002. The optical component 902 and / or the optical component 1002 includes the chip, the chip-on-carrier, or the transmitter provided by the embodiments of the present application, or the chip, the chip-on-carrier, or the transmitter provided by the embodiments of the present application is directly integrated into the optical module 901 and / or the optical module 1001. At this time, the optical module 901 and / or the optical module 1001 can adopt packaging forms such as QSFP28, QSFP-DD, and SFP.

[0114] Taking the optical line terminal 900 as an example, in the optical module 901, devices such as a wavelength division multiplexing (WDM) module may also be included. The chip, the chip-on-carrier, or the transmitter provided by the embodiments of the present application can be used as an optoelectronic conversion unit to connect to devices such as WDM. However, the specific internal structure and devices of the optical module 901 are not limited in the embodiments of the present application. The chip, the chip-on-carrier, or the transmitter in the optical module 901 can be connected to other devices or adopt other connection methods.

[0115] In the optical line terminal 900 provided by the embodiments of the present application, the optical line terminal 900 may further include devices such as a medium access control (MAC) chip and a line card. The optical module 901 may be connected through the line card and the MAC chip. However, the embodiments of the present application do not limit the specific internal structure and devices of the optical line terminal 900. The optical module 901 in the optical line terminal 900 may be connected to other devices or adopt other connection methods.

[0116] In addition, the chip, chip on carrier, and transmitter provided by the embodiments of the present application may also be applied to optical modules or optical components in Ethernet networks such as 100G, 200G, or 400G, or to communication devices or electronic devices that require EML chips.

[0117] Those of ordinary skill in the art can realize that the structural units of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the embodiments of the present application.

[0118] In several embodiments provided by the present application, it should be understood that the disclosed structure can be implemented in other ways. For example, the above-described embodiments are merely illustrative. For example, the division of the structure may have other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another structure, or some features may be ignored. One can select some or all of the structures according to actual needs to achieve the purpose of the solution of this embodiment. Another point is that the displayed or discussed couplings, direct couplings, or communication connections to each other may be through some interfaces, indirect couplings, or communication connections of structures or units, and may be in electrical, mechanical, or other forms.

[0119] In addition, the structures in the embodiments of the present application may be integrated into one structure, or each structure may exist physically alone, or two or more structures may be integrated into one structure.

[0120] The above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. And these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip, characterized in that, it includes a conductive substrate, an insulating layer, a quantum well, a first capacitor electrode, a distributed feedback laser (DFB) electrode, and an electro-absorption modulator (EAM) electrode, wherein, the insulating layer and the quantum well are grown on the conductive substrate, the insulating layer and the quantum well jointly cover the conductive substrate, and the insulating layer covers the side surface of the quantum well; the DFB electrode and the EAM electrode are grown on the insulating layer and the quantum well, and the DFB electrode and the EAM electrode cover the top surface of the quantum well; the first capacitor electrode is grown on the insulating layer, the first capacitor electrode is electrically connected to the DFB electrode, and the first capacitor electrode is used to form a first capacitor with the conductive substrate; the DFB electrode, the EAM electrode, and the first capacitor electrode respectively cover different and non-adjacent parts on the insulating layer.

2. The chip according to claim 1, characterized in that, the chip further includes a semiconductor optical amplifier (SOA) electrode and a second capacitor electrode, the SOA electrode is grown on the insulating layer and the quantum well, and the SOA electrode covers the top surface of the quantum well; the second capacitor electrode is grown on the insulating layer, the second capacitor electrode is electrically connected to the SOA electrode, and the second capacitor electrode is used to form a second capacitor with the conductive substrate; the DFB electrode, the EAM electrode, the SOA electrode, the first capacitor electrode, and the second capacitor electrode respectively cover different and non-adjacent parts on the insulating layer.

3. The chip according to claim 1 or 2, characterized in that, the conductive substrate includes a metallized part, and the first capacitor electrode is used to form the first capacitor with the metallized part.

4. The chip according to any one of claims 1 - 3, characterized in that, the material of the insulating layer is silicon dioxide or titanium dioxide.

5. The chip according to any one of claims 1 - 4, characterized in that, the chip further includes a first connection line, and the DFB electrode and the first capacitor electrode are electrically connected inside the chip through the first connection line.

6. The chip according to any one of claims 2 - 5, characterized in that, the chip further includes a second connection line, and the SOA electrode and the second capacitor electrode are electrically connected inside the chip through the second connection line.

7. A chip on a carrier, characterized in that, it includes a chip and a differential signal transmission line, the differential signal transmission line is used to provide a driving signal to the chip, and the chip includes a conductive substrate, an insulating layer, a quantum well, a first capacitor electrode, a distributed feedback laser (DFB) electrode, and an electro-absorption modulator (EAM) electrode, wherein, the insulating layer and the quantum well are grown on the conductive substrate, the insulating layer and the quantum well jointly cover the conductive substrate, and the insulating layer covers the side surface of the quantum well; the DFB electrode and the EAM electrode are grown on the insulating layer and the quantum well, and the DFB electrode and the EAM electrode cover the top surface of the quantum well; The first capacitive electrode is grown on the insulating layer, the first capacitive electrode is electrically connected to the DFB electrode, and the first capacitive electrode is used to form a first capacitor with the conductive substrate; The DFB electrode, the EAM electrode, and the first capacitive electrode respectively cover different and non-adjacent parts on the insulating layer.

8. The chip on a carrier according to claim 7, wherein, The chip on a carrier further includes a first magnetic bead and a first conductive block, and the first conductive block is connected to the first capacitive electrode through the first magnetic bead.

9. The chip on a carrier according to claim 7 or 8, wherein, The chip further includes a semiconductor optical amplifier (SOA) electrode and a second capacitive electrode. The SOA electrode is grown on the insulating layer and the quantum well, and the SOA electrode covers the top surface of the quantum well; The second capacitive electrode is grown on the insulating layer, the second capacitive electrode is electrically connected to the SOA electrode, and the second capacitive electrode is used to form a second capacitor with the conductive substrate; The DFB electrode, the EAM electrode, the SOA electrode, the first capacitive electrode, and the second capacitive electrode respectively cover different and non-adjacent parts on the insulating layer.

10. The chip on a carrier according to claim 9, wherein, The chip on a carrier further includes a second conductive block and a second magnetic bead, and the second conductive block is connected to the second capacitive electrode through the second magnetic bead.

11. The chip on a carrier according to any one of claims 7-10, wherein, The conductive substrate includes a metallized part, and the first capacitive electrode is used to form the first capacitor with the metallized part.

12. The chip on a carrier according to any one of claims 7-11, wherein, The material of the insulating layer is silicon dioxide or titanium dioxide.

13. The chip on a carrier according to any one of claims 7-12, wherein, The chip further includes a first connection line, and the DFB electrode and the first capacitive electrode are electrically connected inside the chip through the first connection line.

14. The chip on a carrier according to any one of claims 7-12, wherein, The chip on a carrier further includes a third connection line, and the DFB electrode and the first capacitive electrode are electrically connected outside the chip through the third connection line.

15. The chip on a carrier according to any one of claims 7-14, wherein, The chip further includes a second connection line, and the SOA electrode and the second capacitive electrode are electrically connected inside the chip through the second connection line.

16. The chip on a carrier according to any one of claims 7-14, wherein, The chip on a carrier further includes a fourth connection line, and the SOA electrode and the second capacitive electrode are electrically connected outside the chip through the fourth connection line.

17. The chip on a carrier according to any one of claims 7-16, wherein, The chip on a carrier further includes a detection unit, and the detection unit is used to determine the light emission condition of the chip.

18. A transmitter Characterized in that, the transmitter includes a transmission signal source and a chip on carrier according to any one of claims 7-17, and the transmission signal source is used to provide a driving signal to the chip through a differential signal transmission line.

19. An optical component, Characterized in that, the optical component includes a chip according to any one of claims 1-6, a chip on carrier according to any one of claims 7-17 or a transmitter according to claim 18.

20. An optical module, Characterized in that, the optical module includes a chip according to any one of claims 1-6, a chip on carrier according to any one of claims 7-17 or a transmitter according to claim 18.

21. An optical line terminal, Characterized in that, the optical line terminal includes a chip according to any one of claims 1-6, a chip on carrier according to any one of claims 7-17 or a transmitter according to claim 18.

22. An optical network unit, Characterized in that, the optical network unit includes a chip according to any one of claims 1-6, a chip on carrier according to any one of claims 7-17 or a transmitter according to claim 18.

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