Method for modulating two parallel converters based on zero common-mode voltage and zero-sequence circulating current suppression

Abstract

The invention discloses a method for modulating two parallel converters based on zero common-mode voltage and zero-sequence circulating current suppression, which comprises the following steps of: firstly, analyzing the influence of 64 switch combinations on zero-sequence circulating current and common-mode voltage, simultaneously considering common-mode voltage elimination and zero-sequence circulating current suppression, and screening out 18 optimal switch combinations; secondly, in order to eliminate the low-frequency zero-sequence circulating current, designing six switch sequence templates which are symmetrical in a quarter period, and limiting the average value of the zero-sequence circulating current of each switch period to be 0; then, on the basis of the sequence template, starting from the angle of zero-sequence circulating current peak value minimization and switching loss optimization, a vector plane is divided into six large sectors, each large sector comprises six sub-sectors, and the optimal switching sequence of each area is obtained; and finally, a modulation wave is calculated for the optimal switching time sequence, a switching action mode is designed, and a driving signal of the switch is obtained. According to the invention, the problems of low-frequency zero-sequence circulating current and large zero-sequence circulating current peak value existing in the existing zero common-mode voltage modulation algorithm are solved.

Description

Technical Field

[0001] The present invention relates to an optimized design of switching timing and its implementation method of carrier modulation, and particularly to a modulation method for two paralleled converters based on zero common-mode voltage and zero-sequence circulating current suppression. Background Technique

[0002] At present, paralleled converters have been widely used in fields such as electric vehicles and new energy power generation. The common-mode voltage is one of the important operating indexes of paralleled converters, which can cause phenomena such as electromagnetic interference, motor bearing current, and increased motor insulation stress, further leading to a decrease in system reliability and even affecting the normal operation of equipment. Therefore, suppressing the common-mode voltage is crucial for improving the stability of the paralleled converter system and extending the service life of equipment. In the literature [D. Jiang, Z. Shen and F. Wang, "Common-Mode Voltage Reduction for Paralleled Inverters", in IEEE Transactions on Power Electronics, vol. 33, no. 5, pp. 3961-3974, May 2018, doi: 10.1109 / TPEL.2017.2712369], in order to eliminate the common-mode voltage, only the switching combinations with a common-mode voltage of 0 are used to synthesize the reference voltage, and a zero common-mode voltage modulation scheme (ZCMV) is proposed. However, this scheme will generate a large zero-sequence circulating current. The existence of the zero-sequence circulating current will increase the operating loss of the system, and in severe cases, it will even cause an overcurrent fault and damage the circuit devices. To reduce the zero-sequence circulating current, a filter inductor is usually required. However, the ZCMV scheme will also cause a large number of low-frequency components in the zero-sequence circulating current, which is not conducive to the design of the filter inductor. Therefore, a new zero common-mode voltage modulation scheme needs to be designed to eliminate the common-mode voltage while suppressing the peak value of the zero-sequence circulating current and eliminating the low-frequency zero-sequence circulating current. Summary of the Invention

[0003] The purpose of the present invention is to provide a modulation method for two paralleled converters based on zero common-mode voltage and zero-sequence circulating current suppression, and solve the problems of large low-frequency zero-sequence circulating current and large peak value of zero-sequence circulating current existing in the existing zero common-mode voltage modulation algorithm.

[0004] The technical solution for realizing the purpose of the present invention is as follows:

[0005] A modulation method for two paralleled converters based on zero common-mode voltage and zero-sequence circulating current suppression includes:

[0006] Step 1, obtain all possible switching state combinations according to the mathematical model of the two paralleled converters, and screen out 18 switching combinations with a common-mode voltage of 0 and the minimum change rate of the circulating current from all possible switching state combinations;

[0007] Step 2: Based on the 18 selected switching combinations in Step 1, ensure that the average value of the zero-sequence circulating current within the switching period is 0 to eliminate the low-frequency zero-sequence circulating current. Design 6 quarter-cycle symmetric switching sequence templates, and further considering the peak value of the circulating current, 4 available switching sequence templates are selected.

[0008] Step 3: Divide the vector plane into 6 sectors evenly. According to the available switching sequence templates and the 18 switching combinations, determine the candidate switching sequences for each sector. Considering the minimization of the peak value of the zero-sequence circulating current and the optimization of the switching times, further divide each sector into 6 sub-sectors and determine the optimal switching sequences for each region.

[0009] Step 4: For the optimal switching sequences obtained in Step 3, design the switching action modes, calculate the required modulation waves and determine the switching action methods corresponding to the modulation waves to obtain the carrier modulation scheme.

[0010] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) This patent proposes a zero common-mode voltage modulation scheme for eliminating the low-frequency component of the zero-sequence circulating current and suppressing the peak value of the zero-sequence circulating current, solving the problem of low-frequency zero-sequence circulating current existing in the existing zero common-mode voltage modulation algorithms; (2) The designed method considers the peak value of the zero-sequence circulating current and the minimization of the switching frequency, and selects the optimal switching sequences. The designed switching sequences are composed of three zero common-mode voltage vectors closest to the reference voltage, and also have excellent ripple performance. This technology can achieve comprehensive optimization of the common-mode voltage, zero-sequence circulating current, current ripple, and switching loss. Description of the Drawings

[0011] Figure 1 It is the topology diagram of two parallel converters.

[0012] Figure 2 It is the flow chart of a modulation method for two parallel converters based on zero common-mode voltage and zero-sequence circulating current suppression proposed by the present invention.

[0013] Figure 3 It is the vector plane diagram of two parallel converters.

[0014] Figure 4 It is the distribution diagram of the sequence with the minimum peak value of the circulating current in the first sector.

[0015] Figure 5 It is the starting and ending switching vector diagrams of the sequences with the minimum circulating current in each region of the first, second, and sixth sectors.

[0016] Figure 6 It is the distribution diagram of the selected switching vectors in the first sector after optimization.

[0017] Figure 7 It is the division diagram of the vector plane.

[0018] Figure 8 Modulation wave and corresponding switching state diagram for regions I-VI.

[0019] Figure 9 Simulation result diagram of the parallel converter under the proposed patent solution and ZCMV when the modulation index is 0.9.

[0020] Figure 10 Spectrum analysis diagram of the zero-sequence circulating current of the parallel converter under the proposed patent solution and ZCMV when the modulation index is 0.9.

[0021] Figure 11 Peak value curve diagram of the zero-sequence circulating current of the parallel converter when using the proposed patent solution and ZCMV under different modulation indices.

[0022] Figure 12 Root mean square curve diagram of the zero-sequence circulating current of the parallel converter when using the proposed patent solution and ZCMV under different modulation indices.

[0023] Figure 13 Root mean square curve diagram of the current ripple of the parallel converter when using the proposed patent solution and ZCMV under different modulation indices.

[0024] Figure 14 Total harmonic distortion (THD) curve diagram of the output current of the parallel converter when using the proposed patent solution and ZCMV under different modulation indices. Detailed implementation manners

[0025] Next, the technologies in the embodiments of the present invention will be elaborated in detail and clearly with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0026] Existing zero - common - mode - voltage modulation algorithms all introduce excessive zero - sequence circulating current and cannot eliminate low - frequency zero - sequence circulating current. To solve this problem, this patent proposes a modulation method for two parallel converters based on zero - common - mode voltage and zero - sequence circulating current suppression. This patent first analyzes the influence of all 64 switching combinations on zero - sequence circulating current and common - mode voltage. Considering both common - mode voltage elimination and zero - sequence circulating current suppression, 18 optimal switching combinations with zero common - mode voltage and the lowest zero - sequence circulating current change rate are selected. Secondly, to achieve the elimination of low - frequency zero - sequence circulating current, 6 kinds of quarter - cycle - symmetric switching sequence templates are designed, which can limit the average value of zero - sequence circulating current in each switching cycle to 0. Then, 4 available switching sequence templates are selected considering the zero - sequence circulating current peak value. Then, based on the obtained sequence templates, from the perspective of minimizing the zero - sequence circulating current peak value and optimizing the switching loss, the vector plane is divided into 6 large sectors, each large sector contains 6 sub - sectors, and the optimal switching sequence for each region is obtained. Finally, for the optimal switching timing, the modulation wave is calculated and the switching action mode is designed to obtain the driving signal of the switch. This scheme can eliminate the common - mode voltage, suppress the negative impact brought by the zero - sequence circulating current, and also has good ripple performance, which is an excellent comprehensive optimization modulation scheme. The method includes:

[0027] (1) According to the mathematical models of two parallel converters, 18 switching combinations with zero common - mode voltage and the minimum circulating current change rate are selected from 64 switching combinations, specifically including:

[0028] To select appropriate switching combinations, it is necessary to deduce the formulas for the circulating current change rate and common - mode voltage corresponding to the switching combinations. The circuit topologies of the two parallel converters are shown in Figure 1 . Among them, L and R represent the grid - side inductor and its parasitic resistance, L 1 , R 1 represent the arm - side inductor and its parasitic resistance, V dc represents the DC - bus voltage, e a , e b , e c represent the three - phase grid - side voltages, i a , i b , i c are the parallel three - phase currents, i a1 , i a2 , i b1 , i b2 , i c1 , i c2 respectively represent the currents of phases A, B, and C of the first and second converters.

[0029] The output voltages of the two parallel converters in the two - phase stationary coordinate system can be expressed as:

[0030]

[0031] Among them, S a1 , S a2 , S b1 , S b2 , S c1 , S c2 respectively represent Figure 1 the switching states of S 1 -S 6 in two parallel converters, , respectively represent the voltage components of the output voltage on the α and β coordinate axes.

[0032] Based on Kirchhoff's theorem, the common-mode voltage V CMV can be calculated from the circuit topologies of the two parallel converters as:

[0033]

[0034] The change rate of the zero-sequence circulating current i ZSCC is:

[0035]

[0036] Each of the two converters has 8 switching states, forming 64 switching combinations of the two parallel converters, which constitute 19 voltage vectors. The vector plane diagram is shown in Figure 3 . Substituting the 64 switching combinations into the above formula, the voltage vectors, common-mode voltages, and zero-sequence circulating current change rates corresponding to each switching combination can be obtained, as shown in Table 1.

[0037] Table 1 Common-mode voltages and zero-sequence circulating current change rates of 64 switching combinations

[0038]

[0039] In Table 1, the two numbers in parentheses after the vector name respectively represent the common-mode voltage and the zero-sequence circulating current change rate. The common-mode voltage is normalized with V dc / 6 as the reference, and the zero-sequence circulating current change rate is normalized with V dc / (2L 1 ) as the reference. Taking the first converter using V 100 , and the second converter selecting vector V 110 as an example. The subscript 100 of V 100 means S a1 =1, S b1 =0 and S c1 =0, and the subscript 100 of V 110 means S a2 =1, S b2 =1 and S c2 =0 as an example, and its output voltage vector is V 7, the calculated common-mode voltage is 0, and the change rate of zero-sequence circulating current is -V dc / (2L 1 ). Therefore, this voltage vector is represented as V 7 (0, -1), as shown in Table 1.

[0040] To eliminate the common-mode voltage and suppress the zero-sequence circulating current simultaneously, switch combinations with a common-mode voltage of 0 and a zero-sequence circulating current change rate of ±1 are used, that is, the voltage vectors marked in dark color in the above table, which are summarized in Table 2.

[0041] Table 2 Candidate Switch Combination Table

[0042]

[0043] Outside the brackets in the table represents the voltage vector, and the first row and the second row inside the brackets represent the switch states S a1 、S b1 、S c1 of the first converter and the switch states S a2 、S b2 、S c2 of the second converter respectively. For example, is the voltage vector V 0 , the switch state of the first converter is S a1 = 1, S b1 = 0, S c1 = 0, and the switch state of the second converter is S a2 = 0, S b2 = 1, S c2 = 1.

[0044] To optimize the current ripple, the vector plane is divided into 6 sectors according to the minimum triangle principle. The voltage vectors corresponding to the three vertices of the sector where the reference voltage is located are used as the basic voltage vectors for synthesis.

[0045] (2) Based on the 18 switch combinations selected in step (1), 6 quarter-switch-period symmetric sequence templates are designed, which can ensure that the average value of the zero-sequence circulating current in a switching period is 0 and eliminate the low-frequency zero-sequence circulating current. Then, considering the peak value of the zero-sequence circulating current and the number of switchings, 4 available sequence templates are further selected. Specifically, including:

[0046] To ensure that the average value of the zero-sequence circulating current in a switching period is 0 and eliminate the low-frequency zero-sequence circulating current, the switching sequence needs to be centrosymmetric about the quarter-switching period center and axially symmetric about the half-switching period. The designed sequence templates are as follows:

[0047]

[0048]

[0049]

[0050] Among them, V a 、V b 、V c are the basic voltage vectors used for synthesis. V a 、V b 、V c The respective proportions corresponding to each sequence period are denoted as d a 、d b 、d c , M i (※) is the name of the sequence template, i = 1, 2, 3 represents three different circulating current modes, and ※ = +, - represents the positive and negative of the zero-sequence circulating current change rate of the starting vector of the sequence. The zero-sequence circulating current peak value of the above template can be calculated as

[0051]

[0052]

[0053]

[0054] The zero-sequence circulating current peak value calculated by the above formula is normalized with V dc T s / (8L 1 ) as the reference. According to the above formula, it can be seen that the zero-sequence circulating current of sequence M 3 is always the largest. Therefore, excluding sequence M 3 , sequences M 1 (+), M 1 (-), M 2 (+), M 2 (-) are used as available sequences. The circulating current peak values of the above 4 available switch sequences are related to the arrangement order of the switch vectors, and will be further analyzed and compared later.

[0055] (3)According to the available switch sequence template, arrange 18 switch combinations into a switch sequence. Taking the first sector as an example, 8 switch sequences are obtained. Considering factors such as the zero-sequence circulating current peak value and switch loss, the optimal sequence is finally determined. Specifically, it includes:

[0056] Take the voltage vectors corresponding to the three vertices of the sector where the reference voltage is located as the basic voltage vectors used for synthesis, and substitute them into sequence templates M 1 、M 2, write down the switching sequence. Note that to minimize the switching losses, the number of switchings between adjacent vectors should be less than or equal to 2. Taking the first sector as an example, the obtained vector sequence is shown in Table 3. Since the positive or negative nature of the starting vector circulating current change rate does not affect the peak value of the zero-sequence circulating current, for simplicity of analysis, only the vector sequence with a positive starting vector circulating current change rate is considered.

[0057] Table 3 - Alternative sequences with 10 switchings within -30° to 30°

[0058]

[0059] According to Table 3, it can be seen that for sequences SQ 5 ~SQ 8 some switches need to be switched 3 times, which is difficult to achieve in practice. Therefore, SQ 5 ~SQ 8 are excluded. To suppress the peak value of the zero-sequence circulating current, the sequence with the minimum peak value should be selected as the switching sequence. The remaining sequences SQ 1 ~SQ 4 will be analyzed below. Their zero-sequence circulating current peak value calculation formula is:

[0060]

[0061]

[0062]

[0063]

[0064] The peak value of the zero-sequence circulating current calculated by the above formula is normalized with V dc T s / (8L 1 ) as the reference. Among them, d 12 , d 7 , d 0 are the duty cycles of the voltage vectors V 12 , V 7 , V 0 respectively, and the calculation formula is:

[0065]

[0066]

[0067] Among them, M is the modulation degree, θ is the angle where the reference voltage is located. Substituting into the zero-sequence circulating current peak value calculation formula, we get:

[0068]

[0069]

[0070]

[0071]

[0072] By comparing the values of the above four expressions, the sequence with the minimum zero-sequence circulating current peak value can be obtained. Figure 4 The distribution of the sequence with the minimum zero-sequence circulating current peak value in the first sector is given. The six dividing lines in the figure are respectively:

[0073]

[0074]

[0075] Among them, the points in the two-phase stationary coordinate system are denoted as , are the per-unit values of the corresponding components on the α and β axes, , . The vector sequences given by Figure 4 are used in each region to ensure the minimum circulating current peak value in the entire vector plane.

[0076] The number of switching operations is a key factor affecting the switching loss. Next, the number of switching operations will be considered to further optimize the selection of the vector sequence. The Figure 4 selected vector sequence is extended to the second and sixth sectors. The starting and ending vectors of the vector sequences selected in each region of the sector are shown in Figure 5 . It can be seen that only 2 switching operations are required for the switching between the internal regions of each sector. However, taking the first sector as an example, if the modulation index M > , when the reference voltage enters the second sector from the first sector, switching from the end vector V 12 of the previous sequence to the starting vector V 8 of the next sequence requires 4 switching operations; similarly, when entering the first sector from the sixth sector, see Figure 5 the region corresponding to the red-marked vectors. This will result in a large switching loss. Therefore, it is necessary to optimize the sequence selection to reduce the number of switching operations at the moment of sector switching. Since the starting vector of the sequence used when the modulation index M > near the 30° boundary in the second sector is V 8 , then the adjacent part of the first sector must start with V 7 . The sequences starting with V 7 are SQ 3 and SQ 4 . In the region corresponding to the original SQ 2 near the 30° boundary, SQ 3 and SQ4 The peak value of the circulating current is:

[0077]

[0078]

[0079] Taking the difference of the above formula gives:

[0080] Therefore, compared with SQ 4 , the peak value of the circulating current of SQ in this area is always smaller. Then, the switching sequence SQ 3 should be used to replace the selected SQ near the sector boundary 3 , which can reduce the number of switching operations while ensuring a lower peak value of the circulating current. Similarly, near the -30° boundary, the vector sequence SQ 2 should be used to replace SQ 1 . To simplify the complexity of the algorithm, this solution considers extending the demarcation lines l 4 , l 3 , l 4 to demarcate the area for sequence replacement. Finally, the division of the first sector and the selection of the vector sequence are shown in Figure 6 . Applying this sequence optimization scheme to sectors 1, 3, and 5 can avoid the phenomenon of four simultaneous switchings in the entire vector plane. Finally, the sector division is shown in Figure 7 , and the corresponding switching sequences for each area are shown in Tables 4.1 and 4.2. For simplicity of description, only the sequences for the first half cycle are given in Tables 4.1 and 4.2, and the second half cycle is completely symmetric to the first half cycle.

[0081] Table 4.1 The First Part of the Switching Sequences Corresponding to Each Area

[0082]

[0083] Table 4.2 The Second Part of the Switching Sequences Corresponding to Each Area

[0084]

[0085] (4) For the switching sequence obtained in step (3), calculate the required modulation wave, set the switching operation mode, and complete the design of the carrier modulation implementation scheme. Specifically, it includes:

[0086] Taking sector I as an example, based on the volt-second balance principle, a system of equations regarding the duty cycles of the three basic voltage vectors in the switching sequence can be obtained:

[0087]

[0088] Among them, V 7α , V 12α are the voltage vectors V7 、V 12 The component on the α-axis in the stationary coordinate system, V 7β 、V 12β They are voltage vector V 7 、V 12 The component on the β axis in the stationary coordinate system, d 7 d 12 d 0 They are the vector V in the switching sequence. 7 、V 12 、V 0 The duty cycle, u a 、u b 、u c is the three-phase reference voltage, u refα 、u refβ is the component of the reference voltage on the α and β axes in the stationary coordinate system. The duty ratios of the three basic voltage vectors are obtained as follows:

[0089]

[0090] , , Indicates the per-unit value of the three-phase reference voltage, , , . According to the duty cycle of the vector, the action time of each vector in the switching sequence can be obtained, and the driving signal of the switch tube can be further obtained. In order to avoid complex online calculations, a carrier implementation scheme needs to be designed. Based on the proposed switching sequence, this patent defines three switching action modes and calculates the corresponding modulation waves. According to the size relationship between the modulation wave and the inverted triangle carrier, the appropriate switching action mode is applied to achieve accurate generation of the switching sequence. The modulation wave of the x phase is recorded as u mx1 、u mx2 , x=a, b, c. The three action modes are:

[0091] Action mode 1: When the carrier wave is smaller than the modulation wave u mx1 Greater than the modulation wave u mx2 When x is on, it needs to output a low level to turn off the switch tube corresponding to x; otherwise, it needs to output a high level to turn on the switch tube corresponding to x. This is recorded as Action 1.

[0092] Action mode 2: When the carrier wave is smaller than the modulation wave u mx1 Greater than the modulation wave u mx2 When x is on, it needs to output a high level to turn on the switch tube corresponding to x; otherwise, it needs to output a high level to turn off the switch tube corresponding to x. This is recorded as Action 2.

[0093] Action mode three, note that this mode umx1 = u mx2 When the carrier wave is less than the modulating wave u mx1 , a low level needs to be output to turn off the switch tube corresponding to x; otherwise, a high level is output to turn on the switch tube corresponding to x. Denote it as Action 3.

[0094] Table 5.1 Modulating Waves and Corresponding Action Modes in the First and Second Sectors - First Part

[0095]

[0096] Table 5.2 Modulating Waves and Corresponding Action Modes in the First and Second Sectors - Second Part

[0097]

[0098] Table 5.3 Modulating Waves and Corresponding Action Modes in the First and Second Sectors - Third Part

[0099]

[0100] Table 5.4 Modulating Waves and Corresponding Action Modes in the First and Second Sectors - Fourth Part

[0101]

[0102] Tables 5.1 to 5.4 give the modulating waves in the first and second sectors and the corresponding action modes. Figure 8 Taking the optimal sequence in regions I - VI as an example, the process of generating switch signals from the modulating wave is given. After summarization, it can be obtained that the modulating waves and corresponding action modes in the entire vector plane can be summarized as:

[0103] When u * mid < 0, corresponding to the large sectors I, III, and V, their modulating waves and action modes can be classified into the following categories:

[0104] If 2u * max – 2u * mid < 1, corresponding to sub - sectors I and II.

[0105]

[0106] If 2u * max – 2u * mid ≥ 1 and 2u * mid – u * min > 0, corresponding to sub - sectors III and VI.

[0107]

[0108] If 2u * max –2u * mid ≥1 and 2u * mid –u * min ≤0, corresponding to sub-sectors IV and V,

[0109]

[0110] When u * mid >0, corresponding to major sectors II, IV, and VI, and their modulation waves and operation modes can be classified into the following categories:

[0111] If u * max –2u * mid >0 and u * max >1 / 4, corresponding to sub-sectors III and IV,

[0112]

[0113] If u * max –2u * mid >0 and u * max ≤1 / 4, corresponding to sub-sectors I and II,

[0114]

[0115] If u * max –2u * mid ≤0 and 2u * max –2u * mid >1, corresponding to sub-sectors IV and V,

[0116]

[0117] If u * max –2u * mid ≤0 and 2u * max –2u * mid≤1, corresponding to sub-sectors I and II,

[0118]

[0119] where u * max is the per-unit value of the three-phase reference voltage u * a , u * b , u * c in the maximum value, u * mid is the intermediate value of the per-unit value of the three-phase reference voltage, u * min is the minimum value of the per-unit value of the three-phase reference voltage; u max1 and u max2 are the two modulation waves corresponding to the maximum in the per-unit value of the three-phase reference voltage u * a , u * b , u * c in the maximum corresponding ones, u mid1 and u mid2 are the two modulation waves corresponding to the intermediate in the per-unit value of the three-phase reference voltage, u min1 and u min2 are the two modulation waves corresponding to the minimum in the per-unit value of the three-phase reference voltage.

[0120] So far, the control scheme and carrier modulation algorithm of this patent are formed, and the algorithm flow is shown in Figure 2 .

[0121] Finally, the effectiveness of the proposed scheme will be verified by simulation. The simulation parameters are shown in Table 6. Figure 9 shows the comparison between this scheme and ZCMV when the modulation index is 0.9. It can be seen that both schemes can ensure that the common-mode voltage is zero, but under the action of this scheme, the root mean square of current ripple, the THD of output current, the root mean square of zero-sequence circulating current, and the peak value of zero-sequence circulating current are all better. In addition, Figure 10 gives the fast Fourier transform calculation results of the zero-sequence circulating current of the parallel converters under the action of ZCMV and this patent scheme. It can be seen that the zero-sequence circulating current corresponding to ZCMV has a large number of low-frequency components, while there is almost no low-frequency zero-sequence circulating current in this scheme. Without loss of generality, Figures 11 - 14 gives the comparison simulation results under different modulation indices. In the 19 groups of comparison simulations with different modulation indices, this scheme has shown better performance, which can fully prove the superiority of this scheme.

[0122] Table 6 Simulation parameters

[0123]

[0124] A modulation method for two parallel converters based on zero common-mode voltage and zero-sequence circulating current suppression, innovatively proposed in this patent, aims to simultaneously eliminate the common-mode voltage, suppress the peak value of the zero-sequence circulating current, and eliminate the low-frequency zero-sequence circulating current. The designed method can not only achieve the elimination of the common-mode voltage, but also suppress the average value of the zero-sequence circulating current within a control period to 0, eliminating the low-frequency zero-sequence circulating current. At the same time, based on minimizing the peak value of the zero-sequence circulating current and the number of switching times, the optimal switching sequence is selected. The designed switching sequence is composed of three zero common-mode voltage vectors closest to the reference voltage and also has excellent ripple performance.

[0125] Those skilled in the art will readily think of other embodiments of the present disclosure after considering the specification and the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include well-known knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the claims.

Claims

1. A modulation method for two parallel converters based on zero common mode voltage and zero sequence circulating current suppression, characterized in that: include: Step 1, obtaining all possible switch state combinations according to the mathematical model of the two parallel converters, and selecting 18 switch state combinations with a common mode voltage of 0 and a minimum circulating current change rate from all possible switch state combinations; Step 2: Based on the 18 switch combinations selected in step 1, ensure that the average value of the zero-sequence circulating current in the switching cycle is 0, eliminate the low-frequency zero-sequence circulating current, design 6 switching sequence templates with quarter-cycle symmetry, consider the zero-sequence circulating current peak value, and further screen out 4 available switching sequence templates; Step 3: Divide the vector plane into 6 sectors, determine the candidate switching sequence for each sector based on the available switching sequence template and 18 switch combinations, and consider minimizing the zero-sequence circulating current peak and optimizing the number of switches. Divide each sector into 6 sub-sectors to determine the optimal switching sequence for each area. Step 4: Design the switch action mode for the optimal switch sequence obtained in step 3, calculate the required modulation wave and determine the switch action mode corresponding to the modulation wave to obtain the carrier modulation scheme.

2. A modulation method for two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 1, characterized in that: The six quarter-cycle symmetrical switching sequence templates are: ； ； ； Among them, V a 、V b 、V c is the basic voltage vector used in the synthesis, V a 、V b 、V c The corresponding proportion in each sequence period is recorded as d a ,d b ,d c , M i (※) is the name of the sequence template, i=1,2 represents two different circulation modes, ※=+,- represents the positive or negative nature of the zero-sequence circulation change rate of the sequence starting vector.

3. A modulation method for two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 1, characterized in that: The 4 available switch sequence templates are: ； 。 4. A modulation method for two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 1, characterized in that: The vector plane is divided into 6 sectors using the minimum triangle principle.

5. The modulation method of two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 1, characterized in that: The optimal switching sequence for each region is: Region II, the optimal switching sequence for half a cycle is: ； In region I-II, the optimal switching sequence for half a cycle is: ； In regions I-III, the optimal switching sequence for half a cycle is: ； Region I-IV, the optimal switching sequence for half a cycle is: ； Region IV, the optimal switching sequence for half a cycle is: ； In region I-VI, the optimal switching sequence for half a cycle is: ； In region II-I, the optimal switching sequence for half a cycle is: ； In region II-II, the optimal switching sequence for half a cycle is: ； Region II-III, the optimal switching sequence for half a cycle is: ； Region II-IV, the optimal switching sequence for half a cycle is: ； Region II-V, the optimal switching sequence for half a cycle is: ； Region II-VI, the optimal switching sequence for half a cycle is: ； In region III-I, the optimal switching sequence for half a cycle is: ； In region III-II, the optimal switching sequence for half a cycle is: ； Region III-III, the optimal switching sequence for half a cycle is: ； Region III-IV, the optimal switching sequence for half a cycle is: ； Region III-V, the optimal switching sequence for half a cycle is: ； Region III-VI, the optimal switching sequence for half a cycle is: ； In region IV-I, the optimal switching sequence for half a cycle is: ； In region IV-II, the optimal switching sequence for half a cycle is: ； In region IV-III, the optimal switching sequence for half a cycle is: ； Region IV-IV, the optimal switching sequence for half a cycle is: ； Region IV-V, the optimal switching sequence for half a cycle is: ； Region IV-VI, the optimal switching sequence for half a cycle is: ； In region VI, the optimal switching sequence for half a cycle is: ； Region V-II, the optimal switching sequence for half a cycle is: ； Region V-III, the optimal switching sequence for half a cycle is: ； Region V-IV, the optimal switching sequence for half a cycle is: ； In region VV, the optimal switching sequence for half a cycle is: ； In region V-VI, the optimal switching sequence for half a cycle is: ； In region VI-I, the optimal switching sequence for half a cycle is: ； In region VI-II, the optimal switching sequence for half a cycle is: ； In region VI-III, the optimal switching sequence for half a cycle is: ； In region VI-IV, the optimal switching sequence for half a cycle is: ； In region VI-V, the optimal switching sequence for half a cycle is: ； In region VI-VI, the optimal switching sequence for half a cycle is: ； Among them, the left side of - in the area is the sector label, the right side is the sub-sector label in the sector, the voltage vector is represented outside the brackets, and the two parameters in the brackets represent the switching states of the first converter and the second converter respectively.

6. A modulation method for two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 1, characterized in that: According to the volt-second balance principle, three switching action modes are designed.

7. A modulation method for two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 6, characterized in that: The first switching action mode is: the modulation wave of phase x is recorded as u mx1 、u mx2 , x=a, b, c, when the carrier is smaller than the modulation wave u mx1 Greater than the modulation wave u mx2 When x is on, the output is low to turn off the switch corresponding to x; otherwise, the output is high to turn on the switch corresponding to x, which is recorded as Action 1.

8. A modulation method for two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 7, characterized in that: The second switching action mode is: when the carrier is less than the modulation wave u mx1 Greater than the modulation wave u mx2 When x is on, the output is high to turn on the switch corresponding to x; otherwise, the output is high to turn off the switch corresponding to x, which is recorded as Action 2.

9. A modulation method for two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 8, characterized in that: The third switch action mode is: mx1 = u mx2 , when the carrier is smaller than the modulation wave u mx1 When x is on, the output is low level to turn off the switch tube corresponding to x; otherwise, the output is high level to turn on the switch tube corresponding to x, which is recorded as Action 3.

10. A modulation method for two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 9, characterized in that: The modulation wave and the switching action mode corresponding to the modulation wave are: When u * mid <0, corresponding to large sectors I, III, V, the modulation wave and switch action mode are: If 2u * max –2 u * mid <1, corresponding to sub-sectors I and II, ； If 2u * max –2 u * mid ≥1 and 2u * mid – u * min >0, corresponding to sub-sectors III and VI, ； If 2u * max –2 u * mid ≥1 and 2u * mid – u * min ≤0, corresponding to sub-sectors IV and V, ； When u * mid When >0, it corresponds to large sectors II, IV, and VI, and its modulation wave and action mode are: If u * max – 2u * mid >0 and u * max >1 / 4, corresponding to sub-sectors III and IV, ； If u * max – 2u * mid >0 and u * max ≤1 / 4, corresponding to sub-sectors I and II, ； If u * max – 2u * mid ≤0 and 2u * max –2 u * mid >1, corresponding to sub-sectors IV and V, ； If u * max – 2u * mid ≤0 and 2u * max –2 u * mid ≤1, corresponding to sub-sectors I and II, ； Among them, u * max is the three-phase reference voltage per unit value u * a 、u * b 、u * c The maximum value in u * mid is the middle value of the three-phase reference voltage per unit value, u * min is the minimum value of the three-phase reference voltage per unit value, , , is the per-unit value of the three-phase reference voltage, , , ,u a 、u b 、u c is the three-phase reference voltage, V dc is the DC bus voltage; u max1 and u max2 is the three-phase reference voltage per unit value u * a 、u * b 、u * c The two largest corresponding modulation waves, u mid1 and u mid2 are the two modulation waves corresponding to the middle of the three-phase reference voltage per unit value, u min1 and u min2 are the two minimum corresponding modulation waves in the three-phase reference voltage per unit value, and "{" is the modulation wave expression.

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