Power switch control circuit, power switch control method, chip and electronic device

Abstract

The application relates to a power switch control circuit, a power switch control method, a chip and an electronic device. The power switch control circuit comprises a power domain, the power domain comprising P power switch units arranged into Q parallelly connected power switch chains; a control signal input end for receiving a control signal and outputting the control signal to the Q power switch chains to control the power switch units in each power switch chain; and Q confirmation signal output ends for outputting confirmation signals of the Q power switch chains, the confirmation signals being used to represent the switching states of the Q power switch chains. The power switch control circuit can accelerate the opening and closing speeds of the whole power domain, save the power-on and power-off time of the power domain, and facilitate the judgment of whether the power-on and power-off of the power domain are completed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power switch control, and in particular to a power switch control circuit, a power switch control method, a chip and an electronic device. BACKGROUND

[0002] With the continuous progress of chip technology in electronic devices, power consumption problems become increasingly important. Power switch is one of the important means to achieve low-power design, which can effectively save chip power consumption by independently controlling the power-on or power-off of the power domain not in use in the chip. Compared with directly controlling the external power switch, the on-chip power switch has faster control speed and finer division granularity, and can complete the rapid switching of the power domain within microseconds or even nanoseconds. Although the power switch performs well in power consumption management, its control speed needs to be improved. SUMMARY

[0003] The present application provides a power switch control circuit, a power switch control method, a chip and an electronic device. The technical solutions of the present application are as follows:

[0004] In one aspect, an embodiment of the present application provides a power switch control circuit, comprising:

[0005] a power domain, the power domain comprising P power switch units, the P power switch units being arranged into Q parallel connected power switch chains;

[0006] a control signal input end for receiving a control signal and outputting the control signal to the Q power switch chains to control the power switch units in each of the power switch chains;

[0007] Q confirmation signal output ends for outputting confirmation signals of each of the power switch chains, the confirmation signals being used to represent the switching states of each of the power switch chains;

[0008] wherein P is greater than or equal to Q, and P and Q are positive integers.

[0009] Another aspect of an embodiment of the present application provides a power switch control method, characterized in that it comprises:

[0010] receiving a control signal through a control signal input end and outputting the control signal to Q parallel connected power switch chains arranged by P power switch units in a power domain to control the power switch units in each of the power switch chains;

[0011] outputting, through Q confirmation signal output ends, confirmation signals corresponding to each of the power switch chains, the confirmation signals being used to represent the switching states of each of the power switch chains;

[0012] Wherein, P≥Q, P and Q are both positive integers.

[0013] Another aspect of the present application provides a chip, which comprises the power switch control circuit.

[0014] Another aspect of the present application provides an electronic device, which comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the power switch control method when executing the program.

[0015] Another aspect of the present application provides a non-transitory computer readable storage medium, which stores a computer program, and the computer program is executable on a processor to implement the power switch control method.

[0016] The power switch control circuit, chip, electronic device and power switch control method provided by the present application arrange P power switch units in a power domain comprising P power switch units into Q parallel connected power switch chains, receive control signals through the control signal input end, output the control signals to the Q power switch chains, and control the power switch units in each power switch chain, output the confirmation signals of each power switch chain through the Q confirmation signal output end, and the confirmation signals represent the switch state of each power switch chain. Therefore, the power switch control circuit of the present application can accelerate the opening and closing speed of the whole power domain, save the power-on and power-off time of the power domain, and facilitate the judgment of whether the power domain is powered on or powered off.

[0017] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 A schematic diagram of a power switch control circuit provided by an embodiment of the present application;

[0020] Figure 2 A schematic diagram of another power switch control circuit provided by an embodiment of the present application;

[0021] Figure 3 A schematic diagram of another power switch control circuit provided by an embodiment of the present application;

[0022] Figure 4 A schematic diagram of another power switch control circuit provided by an embodiment of the present application;

[0023] Figure 5 A flowchart of a power switch control method provided in an embodiment of this application;

[0024] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0025] Figure 7 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0026] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0027] The power switch control circuit, power switch control method, chip, and electronic device according to embodiments of this application are described below with reference to the accompanying drawings.

[0028] Figure 1 This is a schematic diagram of a power switch control circuit provided in an embodiment of this application.

[0029] like Figure 1 As shown, the power switch control circuit of this application embodiment includes:

[0030] Power domain 100 includes P power switch units 101. Each power switch unit 101 has a control input terminal and an acknowledgment output terminal, forming a set of control signal-acknowledgment signal (Ctrl-Ack signal). The P power switch units 101 are arranged into Q parallel power switch chains (4 chains are used as an example in the figure).

[0031] The control signal input terminal is used to receive the control signal Ctrl and output the control signal Ctrl to Q power switch chains to control the switching of the power switch unit 101 in each power switch chain.

[0032] Q confirmation signal output terminals are provided. Each power switch chain is provided with one confirmation signal output terminal. The confirmation signal output terminal is used to output the confirmation signal Ack (such as Ack1-Ack4) of each power switch chain. The confirmation signal Ack is used to characterize the switching state of each power switch chain.

[0033] Where P ≥ Q, and P and Q are both positive integers.

[0034] In the embodiments of the present application, the number of power switch units 101 in each power switch chain of the Q parallelly connected power switch chains can be different, and the specific number is set according to actual needs. This flexibility enables the power switch chain to be optimally configured according to different application scenarios.

[0035] The power switch units 101 in each power switch chain are connected and controlled in the following manner:

[0036] The first power switch unit 101: the control input end of the first power switch unit 101 in each power switch chain receives a global control signal Ctrl and performs switching operation according to the control signal Ctrl. The confirmation output end of the first power switch unit 101 outputs a confirmation signal Ack, which is used to represent the state of the first power switch unit 101.

[0037] The subsequent power switch units: the control input end of the second power switch unit 101 takes the confirmation signal Ack output by the confirmation output end of the previous power switch unit as its own control signal Ctrl, and performs switching operation according to the control signal Ctrl. The confirmation output end of the second power switch unit 101 outputs a confirmation signal Ack, which is used to represent the state of the second power switch unit 101. In this way, the last power switch unit 101 outputs a confirmation signal Ack.

[0038] Thus, the power switch control circuit of the embodiments of the present application enables all power switch chains to simultaneously receive the same control signal Ctrl through the parallelly connected power switch chain mode, thereby realizing fast power domain power-on or power-off operation. Through this cascading control mechanism, the power switch units on the power switch chain can perform switching operation in sequence, ensuring that the switching state of each power switch chain can be accurately fed back, thereby enhancing the reliability and stability of the system. The number of power switch chains and the number of power switch units on each power switch chain can be flexibly configured according to actual needs, thereby adapting to different chip design requirements. By independently controlling the power-on or power-off of the power domains not used inside the chip, the power consumption of the chip is effectively saved, thereby meeting the dual requirements of low power consumption and high performance of electronic devices.

[0039] In the multiple parallelly connected power switch chains, all power switch chains simultaneously receive the same control signal Ctrl, which may cause multiple power switch units 101 to be turned on or off almost simultaneously. This synchronous operation may cause large transient current changes, thereby causing voltage fluctuations, current spikes and other problems, which affect the stability and reliability of the system. Therefore, the present application inserts a delay unit 102 before the first power switch unit 101 of each power switch chain to delay the turn-on and turn-off time of each power switch chain, thereby smoothing the transient current changes.

[0040] As Figure 2 shown, the power switch control circuit further comprises: Q delay units 102, each delay unit 102 is connected with the first power switch unit 101 in each power switch chain, and the delay unit 102 is used for delaying and outputting the control signal Ctrl to the first power switch unit 101 in the corresponding connected power switch chain after receiving the control signal Ctrl; wherein the first power switch unit 101 in the power switch chain refers to the first power switch unit 101 counted from the control signal input end, in other words, the first power switch unit 101 in the power switch chain is the first power switch unit 101 directly connected to the control signal input end, which is located closest to the control signal input end in the power switch chain. By setting the extension unit, the opening and closing time of different power switch chains are staggered, so that the transient current change can be smoothed.

[0041] In the embodiment of the present application, each delay unit 102 comprises at least one delay sub-unit, and the delay sub-unit is used to provide a fixed or configurable delay time, usually in nanoseconds. However, in actual chips, due to the changes of process, voltage and temperature, the delay time will also fluctuate. Among them,

[0042] The number of delay sub-units in series in each delay unit 102 is determined according to the total delay time required by the corresponding power switch chain.

[0043] Example: The delay sub-unit provides a fixed delay time.

[0044] The first power switch chain: contains 10 power switch units 101, the delay time of each delay sub-unit is 3 nanoseconds, and the total delay time required is 18 nanoseconds, so 6 delay sub-units need to be connected in series in the corresponding delay unit 102.

[0045] The second power switch chain: contains 8 power switch units 101, the delay time of each delay sub-unit is 3 nanoseconds, and the total delay time required is 15 nanoseconds, so 5 delay sub-units need to be connected in series in the corresponding delay unit 102.

[0046] The third power switch chain: contains 6 power switch units 101, the delay time of each delay sub-unit is 3 nanoseconds, and the total delay time required is 12 nanoseconds, so 4 delay sub-units need to be connected in series in the corresponding delay unit 102.

[0047] The fourth power switch chain: contains 5 power switch units 101, the delay time of each delay sub-unit is 3 nanoseconds, and the total delay time required is 9 nanoseconds, so 3 delay sub-units need to be connected in series in the corresponding delay unit 102.

[0048] In multiple parallel power switch chains, each chain typically has an acknowledgment signal (Ack) to indicate whether the chain has successfully powered on or off. However, when supporting an arbitrary number of power switch chains, having an independent acknowledgment signal (Ack) for each chain complicates the external interface and increases design complexity. To address this issue, logic gate 103 can be used outside the power domain 100. Logic gate 103 aggregates the acknowledgment signals from all power switch chains into a unified power-on acknowledgment signal (Ack_pu) and a power-off acknowledgment signal (Ack_pd), thereby simplifying the external interface design.

[0049] like Figure 3 As shown, the power switch control circuit also includes:

[0050] Logic gate 103 receives Q acknowledgment signals Ack and generates corresponding power-on acknowledgment signals Ack_pu and / or power-off acknowledgment signals Ack_pd based on the Q acknowledgment signals Ack. In this way, regardless of the number of power switch chains in the system, the external interface only needs to process two unified acknowledgment signals Ack, greatly simplifying the external function design.

[0051] As an example, such as Figure 3 As shown, the logic gate circuit 103 includes: AND gate 103a and OR gate 103b.

[0052] The AND gate 103a has Q first input terminals and one first output terminal. It generates a power-on confirmation signal Ack_pu based on the Q confirmation signals Ack input to the Q first input terminals and outputs it through the first output terminal. The AND gate 103a operates by outputting a high-level power-on confirmation signal Ack_pu only when all Q confirmation signals Ack are high (i.e., all power switch chains have successfully powered on). If any confirmation signal is low, the AND gate 103a outputs a low level, indicating that at least one power switch chain has failed to power on.

[0053] OR gate 103b has Q second inputs and one second output. It generates and outputs a power-down confirmation signal Ack_pd based on the Q confirmation signals Ack input to the Q second inputs. The OR gate 103b operates as follows: if any one confirmation signal Ack is high (i.e., any power switch chain is not powered down), it outputs a high-level power-down confirmation signal Ack_pd. If all confirmation signals are low, the OR gate outputs a low level, indicating that all power switch chains are powered down.

[0054] For example:

[0055] First power switch chain: Acknowledgement signal Ack_1;

[0056] Second power switch chain: Acknowledgement signal Ack_2;

[0057] Third power switch chain: Acknowledgement signal Ack_3;

[0058] …;

[0059] Qth power switch chain: Acknowledgement signal Ack_Q.

[0060] Suppose there are Q power switch chains, and the acknowledgement signals of each power switch chain are Ack_1, Ack_2, …, Ack_Q respectively. The working process of the logic gate circuit 103 is as follows:

[0061] Power-up acknowledgement signal Ack_pu: When and only when all the acknowledgement signals Ack_1, Ack_2, …, Ack_Q are high, the AND gate 103a outputs a high power-up acknowledgement signal Ack_pu, indicating that all power switch chains have been successfully powered up. If any one of the acknowledgement signals Ack_1, Ack_2, …, Ack_Q is low, the AND gate 103a outputs a low power-up acknowledgement signal Ack_pu, indicating that at least one power switch chain has failed to be successfully powered up.

[0062] Power-down acknowledgement signal Ack_pd: When and only when all the acknowledgement signals Ack_1, Ack_2, …, Ack_Q are low, the OR gate 103b outputs a low power-down acknowledgement signal Ack_pd, indicating that all power switch chains have been successfully powered down. If any one of the acknowledgement signals Ack_1, Ack_2, …, Ack_Q is high, the OR gate 103b outputs a high power-down acknowledgement signal Ack_pd, indicating that at least one power switch chain has failed to be successfully powered down.

[0063] For the circuit structure shown in Figure 3 , an additional selector 104 can be added to complete the selection of the power-up and power-down acknowledgement signals. As shown in Figure 4 , the power switch control circuit further includes:

[0064] The selector 104 (labeled as MUX) has a third input (labeled as sel), a fourth input (labeled as 1), a fifth input (labeled as 0), and a third output. The selector 104 is configured to select one of the power-up confirmation signal Ack_pu received from the fourth input and the power-down confirmation signal Ack_pd received from the fifth input as a target signal according to a control signal Ctrl received from the third input, and output the target signal through the third output.

[0065] In the embodiment of the present application, the selector 104 selects an appropriate confirmation signal as the target signal according to the state of the received control signal Ctrl. The specific working principle is as follows:

[0066] When the control signal Ctrl is a high-level signal, the selector 104 determines the power-up confirmation signal Ack_pu as the target signal, and outputs the target signal through the third output. This indicates that the battery domain 100 is currently in the power-up operation, and the selector 104 will output a signal indicating whether all power switch chains have been successfully powered up.

[0067] When the control signal Ctrl is a low-level signal, the power-down confirmation signal Ack_pd is determined as the target signal, and the target signal is output through the third output. This indicates that the power domain 100 is currently in the power-down operation, and the selector 104 will output a signal indicating that at least one power switch chain has been powered down.

[0068] In the embodiment of the present application, by introducing the selector 104, the selector 104 can select the power-up confirmation signal Ack_pu or the power-down confirmation signal Ack_pd as the target signal according to the state of the control signal Ctrl, effectively simplifying the external interface design, and improving the flexibility and reliability of the system.

[0069] In order to ensure that the timing check of the input signal of the selector 104 can effectively prevent unexpected signal glitches, correctly respond to the control signal Ctrl and select the appropriate confirmation signal Ack, certain timing requirements must be met. In the embodiment of the present application, the signals input to the third input, the fourth input and the fifth input of the selector meet the following conditions:

[0070] The sum of the path time of the control signal Ctrl to the third input and the set time is less than the minimum value of the path time of the control signal Ctrl to the third input and the fourth input, respectively;

[0071] The absolute value of the difference between the path time of the control signal Ctrl to the third input and the fourth input is less than the set time.

[0072] In the embodiments of the present application, the path time is used to represent the transmission time of the signal from the source to the target input end; and the set time is used to represent a preset time threshold, which is used to ensure the synchronization of signal transmission.

[0073] Time constraint 1:

[0074] The sum of the path time of the control signal Ctrl to the third input end and the set time is less than the minimum value of the path times of the control signal Ctrl to the third input end and the fourth input end, respectively. This means that the time for the control signal Ctrl to reach the third input end of the selector plus the set time must be less than the minimum value of the path times of the control signal Ctrl to the third input end and the fourth input end, respectively. In this way, it can be ensured that the selector 104 has sufficient time to wait for the arrival of the power-up confirmation signal Ack_pu after receiving the control signal Ctrl, thereby avoiding misjudgment.

[0075] Time constraint 2:

[0076] The absolute value of the difference between the path times of the control signal Ctrl to the third input end and the fourth input end is less than the set time. This means that the difference between the path times of the control signal Ctrl to the third input end and the fourth input end cannot exceed the set time. In this way, it can be ensured that the timing relationship between the control signal and the power-up confirmation signal remains consistent, thereby avoiding misoperation of the selector 104 due to different path delays.

[0077] In summary, the power switch control circuit proposed in the present application arranges P power switch units in the power domain including P power switch units into Q parallel-connected power switch chains, receives a control signal through a control signal input end, and outputs the control signal to the Q power switch chains to control the power switch units in each power switch chain. The power switch control circuit outputs a confirmation signal of each power switch chain through Q confirmation signal output ends, and the confirmation signal is used to represent the switching state of each power switch chain. The power switch control circuit of the embodiments of the present application is relatively simple and does not require additional registers and special clocks. By arranging P power switch units into Q parallel-connected power switch chains, all the power switch chains receive the same control signal, thereby speeding up the opening and closing of the entire power domain, saving the power-up and power-down time of the power domain, and outputting a confirmation signal for each power switch chain, thereby facilitating the determination of whether the power domain has completed power-up and power-down.

[0078] Figure 5 A flowchart of a power switch control method provided by the embodiments of the present application.

[0079] As Figure 5 shown, the power switch control method of the embodiments of the present application includes:

[0080] S1, receiving a control signal through a control signal input end and outputting the control signal to Q parallel connected power switch chains arranged by P power switch units in the power domain, to control the power switch units in each power switch chain.

[0081] S2, outputting a confirmation signal corresponding to each power switch chain through Q confirmation signal output ends, the confirmation signal being used to represent the switch state of each power switch chain. Wherein, P≥Q, and P and Q are positive integers.

[0082] It should be noted that details not disclosed in the power switch control method of the embodiments of the present application can refer to the details disclosed in the power switch control circuit of the embodiments of the present application, which will not be described here.

[0083] According to the power switch control method of the embodiments of the present application, a control signal is received through a control signal input end, and the control signal is output to Q parallel connected power switch chains arranged by P power switch units, to control the power switch units in each power switch chain, and a confirmation signal corresponding to each power switch chain is output through Q confirmation signal output ends, the confirmation signal being used to represent the switch state of each power switch chain. The method can accelerate the opening and closing speed of the whole power domain, save the power-on and power-off time of the power domain, and facilitate the judgment of whether the power domain is powered on or powered off.

[0084] In order to realize the above-mentioned embodiments, the present application further provides an electronic device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to realize the method as described in the foregoing method embodiments.

[0085] Figure 6 A structural schematic diagram of an electronic device provided by the embodiments of the present application is shown. For example, the electronic device 800 can be a mobile phone, a computer, a digital broadcast terminal, a message transmission device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0086] Referring to Figure 6 , the electronic device 800 can include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0087] The processing component 802 generally controls the overall operations of the electronic device 800, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 802 can include one or more processors 820 to execute instructions to complete the steps of the methods described above, in whole or in part. Moreover, the processing component 802 can include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 can include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0088] The memory 804 is configured to store various types of data to support the operations of the electronic device 800. Examples of these data include instructions to operate any applications or methods on the electronic device 800, contact data, phonebook data, messages, pictures, videos, and the like. The memory 804 can be realized by any type of volatile or non-volatile storage devices, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disc, or optical disc.

[0089] The power component 806 provides power to the various components of the electronic device 800. The power component 806 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 800.

[0090] The multimedia component 808 includes a screen to provide an output interface between the electronic device 800 and a user. In some embodiments, the screen can include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes the touch panel, the screen can be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense a touch, a slide, and a gesture on the touch panel. The touch sensors can not only sense a boundary of a touching or sliding action, but also detect duration and pressure related to the touching or sliding action. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. The front camera and / or the rear camera can receive external multimedia data when the electronic device 800 is in an operation mode, such as a shooting mode or a video mode. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0091] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC) that is configured to receive an external audio signal when the electronic device 800 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0092] The I / O interface 812 provides an interface between the processing component 802 and peripheral interface modules, which can be a keypad, a click wheel, buttons, and the like. The buttons can include, but are not limited to, a home button, a volume button, a start button, and a lock button.

[0093] The sensor component 814 includes one or more sensors for providing status assessments of various aspects of the electronic device 800. For example, the sensor component 814 can detect an open / closed position of the electronic device 800, relative positioning of components, such as a display and a keypad of the electronic device 800, a change of position of the electronic device 800 or a component of the electronic device 800, presence or absence of user contact with the electronic device 800, orientation or acceleration / deceleration of the electronic device 800, and a temperature change of the electronic device 800. The sensor component 814 can include a proximity sensor configured to detect presence of a nearby object without any physical touch. The sensor component 814 can also include a light sensor, such as a CMOS or CCD image sensor, for use in an imaging application. In some embodiments, the sensor component 814 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0094] The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 can access a wireless network based on a communication standard, such as WiFi, 4G, or 5G, or a combination thereof. In an example embodiment, the communication component 816 receives broadcast signals or broadcast-related information from an external broadcasting management system via a broadcast channel. In an example embodiment, the communication component 816 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technology.

[0095] In an example embodiment, the electronic device 800 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors, or other electronic elements for performing the above-described methods.

[0096] To implement the above-described embodiments, the present application further provides a chip, comprising: a power switch control circuit.

[0097] In an example embodiment, the chip comprising the power switch control circuit provided by the present application is configured to perform the power switch control method described above.

[0098] Figure 7 A structural schematic diagram of a chip provided by an embodiment of the present application is shown in FIG. 11. Figure 7 The chip 1100 shown in FIG. 11 is a structural schematic diagram, but is not limited thereto.

[0099] The chip 1100 comprises a power switch control circuit 1101, which is configured to perform the power switch control method described above.

[0100] In some embodiments, as shown in FIG. 11, the chip 1100 further comprises one or more interface circuits 1102. Figure 7 Optionally, the interface circuit 1102 is connected with the memory 1103, and the interface circuit 1102 can be used to receive signals from the memory 1103 or other devices, and the interface circuit 1102 can be used to send signals to the memory 1103 or other devices. For example, the interface circuit 1102 can read instructions stored in the memory 1103 and send the instructions to the power switch control circuit 1101.

[0101] In some embodiments, the interface circuit 1102 performs at least one of the communication steps such as sending and / or receiving in the above-described method, and the power switch control circuit 1101 performs other steps.

[0102] In some embodiments, the terms interface circuit, interface, transceiving pin, transceiver, etc. can be replaced with each other.

[0103] In some embodiments, as shown in FIG. 11, the chip 1100 further comprises one or more memories 1103 for storing instructions. Figure 7 Optionally, all or part of the memory 1103 can be outside the chip 1100.

[0104] In an exemplary embodiment, a non-transitory computer readable storage medium including instructions, such as the memory 804 including instructions, is also provided, which can be executed by the processor 820 of the electronic device 800 to complete the above method. For example, the non-transitory computer readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0105] To achieve the above-mentioned embodiments, the present application further provides a non-transitory computer readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-mentioned method.

[0106] To achieve the above-mentioned embodiments, the present application further provides a computer program product comprising a computer program, which, when executed by a processor, implements the above-mentioned method.

[0107] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.

[0108] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0109] Any process or method descriptions in flow charts or described elsewhere herein can be understood as representing code modules, segments, or portions of code which include one or more executable instructions for implementing specific logic functions (or steps) in the process, and that the various embodiments of the preferred application can include additional or fewer steps or codes, and that the method can be implemented by a computer, processor or controller, or other processing device as a set of machine readable instructions stored in a memory of the computer, processor or controller, or other processing device, for execution by the computer, processor or controller, or other processing device. Furthermore, although the subject matter has been described in language specific to structural features, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the described features or described order of features, and specific features can be implemented in other specific contexts.

[0110] The logic and / or steps represented in flow diagrams or otherwise described herein, for example, can be considered as a sequence of instructions to implement logic functions, and can be embodied in any computer-readable medium for use by an instruction execution system, apparatus, or device, such as a computer-based system, processor- containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. In the context of this specification, a "computer-readable medium" can be any means that can contain, store, communicate, propagate or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be a machine-readable storage device (e.g., magnetic, optical or other) a machine-readable storage diskette (e.g., floppy disk, optical disk, etc.), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), optical fibers, and a portable compact disc read-only memory (CDROM). Further, the computer-readable medium can even be paper or other suitable medium upon which the program is printed, as the program can be electronically captured, for example via the optical scanner of a device or other electronic capture device, and then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and stored in a computer memory.

[0111] It should be understood that aspects of the application can be implemented in hardware, software, firmware or combinations thereof. In the above embodiments, various steps or methods can be implemented in software or firmware that is stored in memory and executed by a suitable instruction execution system. As such, in some embodiments, the steps or methods can be implemented in a combination of hardware and software. If implemented in hardware, as in another embodiment, any of the above techniques can be implemented with or without the use of a programmable digital signal processor (DSP) or other programmable device. In some embodiments, the steps or methods can be implemented using a combination of different hardware devices.

[0112] Those of skill in the art would understand that information and signals can be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0113] In addition, each of the functional units in each embodiment of the present application can be integrated in one processing module, or each unit can exist physically separately, or two or more units can be integrated in one module. The integrated module can be realized in the form of hardware, or in the form of a software functional module. When the integrated module is realized in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer readable storage medium.

[0114] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

[0115] Other embodiments of the present application will be apparent to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. The present application is intended to cover any variations, uses or adaptive changes of the present application following the general principles of the present application and including common knowledge or conventional technical means in the art not disclosed in the present application. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present application are indicated by the appended claims.

[0116] It should be understood that the present application is not limited to the precise structures described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A power switch control circuit, characterized in that, include: The power domain includes P power switching units, and the P power switching units are arranged into Q parallel power switching chains. The control signal input terminal is used to receive control signals and output the control signals to Q power switch chains to control the switching of the power switch units in each power switch chain. Q confirmation signal output terminals are used to output confirmation signals for each of the power switch chains, and the confirmation signals are used to characterize the switching state of each of the power switch chains; A logic gate circuit, wherein the logic gate circuit is used to receive Q of the confirmation signals and generate corresponding power-on confirmation signals and / or power-off confirmation signals based on the Q of the confirmation signals; Where P ≥ Q, and P and Q are both positive integers.

2. The power switch control circuit according to claim 1, characterized in that, The power switch control circuit also includes: Q delay units, each of the delay units being connected to the first power switch unit in each power switch chain, wherein the delay unit is used to delay the output of the control signal to the first power switch unit in the corresponding connected power switch chain after receiving the control signal; The first power switch unit in the power switch chain refers to the first power switch unit counted from the control signal input terminal.

3. The power switch control circuit according to claim 2, characterized in that, Each of the aforementioned delay units includes at least one delay subunit, the delay subunit being used to provide a fixed or configurable delay time; wherein, The number of delay sub-units connected in series in each delay unit is determined based on the total delay time required for the corresponding power switch chain.

4. The power switch control circuit according to claim 1, characterized in that, The logic gate circuit includes: An AND gate, having Q first input terminals and one first output terminal, is used to generate and output a power-on confirmation signal based on the Q confirmation signals input at the Q first input terminals and through the first output terminal. An OR gate, having Q second input terminals and one second output terminal, is used to generate and output the power-off confirmation signal based on the Q confirmation signals input at the Q second input terminals and through the second output terminal.

5. The power switch control circuit according to claim 4, characterized in that, The power switch control circuit also includes: The selector has a third input terminal, a fourth input terminal, a fifth input terminal, and a third output terminal. The selector is used to select one of the power-on confirmation signal received from the fourth input terminal and the power-off confirmation signal received from the fifth input terminal as a target signal according to the control signal received from the third input terminal, and output the target signal through the third output terminal.

6. The power switch control circuit according to claim 5, characterized in that, The selector is used for: In response to the control signal being a high-level signal, the power-on confirmation signal is determined as the target signal; In response to the control signal being a low-level signal, the power-down confirmation signal is determined as the target signal.

7. The power switch control circuit according to claim 5, characterized in that, The signals input to the third, fourth, and fifth input terminals of the selector satisfy the following time constraints: The sum of the path time of the control signal to the third input terminal and the set time is less than the minimum value of the path time of the control signal to the third input terminal and the fourth input terminal respectively; The absolute value of the path time difference between the control signal and the third input terminal and the fourth input terminal is less than the set time.

8. A power switch control method, characterized in that, include: The system receives control signals through the control signal input terminal and outputs the control signals to Q parallel power switch chains composed of P power switch units in the power domain, so as to control the switching of the power switch units in each power switch chain. The Q confirmation signal output terminals output confirmation signals corresponding to each of the power switch chains, and the confirmation signals are used to characterize the switching state of each of the power switch chains. The system receives Q confirmation signals through logic gate circuits and generates corresponding power-on confirmation signals and / or power-off confirmation signals based on the Q confirmation signals. Where P ≥ Q, and P and Q are both positive integers.

9. A chip, characterized in that, The chip includes a power switch control circuit as described in any one of claims 1-7.

10. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the method as described in claim 8.

11. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in claim 8.

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