High-reliability current mode two-phase oscillator circuit

Abstract

The invention discloses a high-reliability current mode dual-phase oscillator circuit. The circuit comprises an optical trimmer current mirror circuit, a two-phase charging and discharging circuit, a fully differential comparator, an anti-self-locking circuit, an SR latch and buffer output, a trimmer current mirror is used for generating charging current of the charging and discharging circuit, process deviations under different process corners can be coped with by adding trimming, and therefore the frequency of an oscillator is adjusted. The double-phase charging and discharging circuit alternately charges and discharges the first capacitor and the second capacitor, voltage of an upper electrode plate of the capacitor is input into the input end of the fully-differential comparator, the voltage of the capacitor is amplified to enable output to be overturned, and the output of the comparator is connected with the self-locking prevention circuit. The anti-self-locking circuit is used for ensuring that the oscillator can be quickly separated from a metastable state during power-on, normal oscillation starting is realized, and the reliability of the circuit is improved; and meanwhile, the output signal of the comparator is reversed to control the SR latch, and the output end of the SR latch controls the charging and discharging of the charging and discharging circuit, so that the cycle is repeated, and periodic oscillation is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuits, and particularly relates to a highly reliable current-mode two-phase oscillator circuit. Background Art

[0002] In integrated circuits, an oscillator is a key circuit module for data transceiver, logic control, etc. Oscillators generally include ring oscillators and relaxation oscillators. The ring oscillator has a simple structure and does not require a reference voltage. Only by connecting multiple inverters in series and connecting the head and tail can an oscillating clock signal be generated. However, the oscillation frequency will shift with different temperatures and process corners. The relaxation oscillator uses a reference level to compare with the capacitor voltage to generate an oscillation signal. However, the circuit is relatively complex. The delay of the comparator affects the accuracy of the oscillation frequency. At the same time, in the case of high frequency, the oscillation signal will affect the magnitude of the reference voltage through the comparator, which also affects the accuracy of the oscillation frequency. Summary of the Invention

[0003] The object of the present invention: Aiming at the problems existing in the above-mentioned ring oscillator and relaxation oscillator, a highly reliable current-mode two-phase oscillator circuit is proposed. Compared with the traditional structure, it can generate a relatively high-precision oscillation frequency without using a reference level. At the same time, a trimming current is added to adjust the magnitude of the oscillation frequency under different process corners. Finally, an anti-locking circuit is added to prevent the circuit from entering the metastable state, ensuring that the oscillator can always oscillate and improving the reliability of the circuit.

[0004] The technical solution of the present invention is: A highly reliable current-mode two-phase oscillator circuit, the oscillator circuit is as Figure 2As shown in the figure, it includes a tunable current mirror circuit, a bi-directional charge and discharge circuit, a fully differential comparator, an anti-latch-up circuit, an SR latch, and a buffer output. The current mirror bias circuit is used to copy the current generated by the current reference to provide current bias for the bi-directional charge and discharge circuit, the fully differential comparator, and the anti-latch-up circuit. The current mirror bias circuit includes an external current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a switch S1, and a switch S2. The bi-directional charge and discharge circuit is used to charge and discharge a first capacitor and a second capacitor. The bi-directional charge and discharge circuit includes a first capacitor, a second capacitor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor. The fully differential comparator is used to compare the on-chip capacitor voltage to generate a comparator output, including a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, and a fifteenth PMOS transistor. The anti-latch-up circuit is used to prevent the oscillator from entering the metastable state during the power-on process, enabling the oscillator to start oscillating when powered on, thereby improving the reliability of the oscillator. It includes a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, and a twenty-first PMOS transistor. The SR latch and the buffer output. The SR latch is used to control the bi-directional charge and discharge circuit, enabling the on-chip capacitor to be alternately charged and discharged. The buffer outputs an oscillating square wave signal, including an SR latch and a Buffer output stage.

[0005] The gate and drain of the first NMOS transistor are short-circuited and connected to the source of the third NMOS transistor. The source of the first NMOS transistor is connected to the GND potential. The gate of the second NMOS transistor is connected to the gate of the first NMOS transistor. The source of the second NMOS transistor is connected to the GND potential. The drain of the second NMOS transistor is connected to the source of the fourth MOS transistor.

[0006] The gate and drain of the third NMOS transistor are short-circuited, connected to the gate of the fourth NMOS transistor, and connected to the external reference current source IREF. The source of the third NMOS transistor is connected to the drain of the first NMOS transistor. The gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor. The drain of the fourth NMOS transistor is connected to the drain of the third PMOS transistor. The source of the fourth NMOS transistor is connected to the drain of the second NMOS transistor.

[0007] The gate of the fifth NMOS transistor is connected to the gate of the first NMOS transistor, the source of the fifth NMOS transistor is connected to the GND potential, and the drain of the fifth NMOS transistor is connected to the drain of the first PMOS transistor; the gate of the sixth NMOS transistor is connected to the QN output of the SR latch, the source of the sixth NMOS transistor is connected to the GND potential, and the drain of the sixth NMOS transistor is connected to the source of the eighth NMOS transistor;

[0008] The gate of the seventh NMOS transistor is connected to the Q output of the SR latch, the source of the seventh NMOS transistor is connected to the GND potential, and the drain of the seventh NMOS transistor is connected to the source of the ninth NMOS transistor; the gate of the eighth NMOS transistor is connected to the external EN enable signal, the source of the eighth NMOS transistor is connected to the drain of the sixth NMOS transistor, and the drain of the eighth NMOS transistor is connected to the drain of the ninth PMOS transistor;

[0009] The gate of the ninth NMOS transistor is connected to the external EN enable signal, the source of the ninth NMOS transistor is connected to the drain of the seventh NMOS transistor, and the drain of the ninth NMOS transistor is connected to the drain of the tenth PMOS transistor; the gate and drain of the tenth NMOS transistor are shorted and connected to the source of the thirteenth PMOS transistor, and the source of the tenth NMOS transistor is connected to the drain of the eighteenth NMOS transistor;

[0010] The upper plate of the first capacitor is connected to the drain of the eighth PMOS transistor, and the lower plate is connected to the GND potential; the upper plate of the second capacitor is connected to the drain of the ninth PMOS transistor, and the lower plate is connected to the GND potential;

[0011] The gate of the eleventh NMOS transistor is connected to the upper plate of the first capacitor, the source of the eleventh NMOS transistor is connected to the GND potential, and the drain of the eleventh NMOS transistor is connected to the source of the fourteenth NMOS transistor; the gate of the twelfth NMOS transistor is connected to the upper plate of the second capacitor, the source of the twelfth NMOS transistor is connected to the GND potential, and the drain of the twelfth NMOS transistor is connected to the source of the fifteenth NMOS transistor;

[0012] The gate and drain of the thirteenth NMOS transistor are shorted and connected to the drain of the eleventh PMOS transistor, and the source of the thirteenth NMOS transistor is connected to the drain of the tenth NMOS transistor; the gate of the fourteenth NMOS transistor is connected to the gate of the thirteenth NMOS transistor, the source of the fourteenth NMOS transistor is connected to the drain of the eleventh NMOS transistor, and the drain of the fourteenth NMOS transistor is connected to the drain of the fourteenth PMOS transistor;

[0013] The gate of the fifteenth NMOS transistor is connected to the gate of the thirteenth NMOS transistor, the source of the fifteenth NMOS transistor is connected to the drain of the twelfth NMOS transistor, and the drain of the fifteenth NMOS transistor is connected to the drain of the fifteenth PMOS transistor; the gate of the sixteenth NMOS transistor is connected to the drain of the fourteenth NMOS transistor and the gate of the eighteenth PMOS transistor, the source of the sixteenth NMOS transistor is connected to the drain of the eighteenth NMOS transistor, and the drain of the sixteenth NMOS transistor is connected to the drain of the eighteenth PMOS transistor;

[0014] The gate of the seventeenth NMOS transistor is connected to the drain of the fifteenth NMOS transistor and the gate of the nineteenth PMOS transistor. The source of the seventeenth NMOS transistor is connected to the drain of the eighteenth NMOS transistor. The drain of the seventeenth NMOS transistor is connected to the drain of the nineteenth PMOS transistor. The gate and drain of the eighteenth NMOS transistor are shorted, and the source of the eighteenth NMOS transistor is connected to the GND potential.

[0015] The gate and drain of the first PMOS transistor are shorted and connected to the drain of the fifth NMOS transistor. The source of the first PMOS transistor is connected to the drain of the second PMOS transistor. The gate and drain of the second PMOS transistor are shorted, and the source of the second PMOS transistor is connected to the VDD potential.

[0016] The gate and drain of the third PMOS transistor are shorted and connected to the drain of the fourth PMOS transistor. The source of the third PMOS transistor is connected to the drain of the fourth PMOS transistor. The gate and drain of the fourth PMOS transistor are shorted, and the source of the fourth PMOS transistor is connected to the VDD potential.

[0017] The gate of the fifth PMOS transistor is connected to the gate of the fourth PMOS transistor. The source of the fifth PMOS transistor is connected to the VDD potential. The drain of the fifth PMOS transistor is connected to the source of the ninth PMOS transistor. The gate of the sixth PMOS transistor is connected to the gate of the fourth PMOS transistor. The source of the sixth PMOS transistor is connected to the VDD potential. The drain of the sixth PMOS transistor is connected to the positive input terminal of the first switch S1.

[0018] The gate of the seventh PMOS transistor is connected to the gate of the fourth PMOS transistor. The source of the seventh PMOS transistor is connected to the VDD potential. The drain of the seventh PMOS transistor is connected to the source of the tenth PMOS transistor. The gate of the eighth PMOS transistor is connected to the gate of the fourth PMOS transistor. The source of the eighth PMOS transistor is connected to the VDD potential. The drain of the eighth PMOS transistor is connected to the positive input terminal of the second switch S2.

[0019] The positive input terminal of the first switch S1 is connected to the drain of the sixth PMOS transistor, and the negative input terminal of the first switch S1 is connected to the drain of the fifth PMOS transistor.

[0020] The positive input terminal of the second switch S2 is connected to the drain of the eighth PMOS transistor, and the negative input terminal of the second switch S2 is connected to the drain of the seventh PMOS transistor.

[0021] The gate of the ninth PMOS transistor is connected to the gate of the first PMOS transistor. The source of the ninth PMOS transistor is connected to the drain of the fifth PMOS transistor. The drain of the ninth PMOS transistor is connected to the drain of the eighth NMOS transistor. The gate of the tenth PMOS transistor is connected to the gate of the first PMOS transistor. The source of the tenth PMOS transistor is connected to the drain of the seventh PMOS transistor. The drain of the tenth PMOS transistor is connected to the drain of the ninth NMOS transistor.

[0022] The gate of the eleventh PMOS transistor is connected to the gate of the fourth PMOS transistor. The source of the eleventh PMOS transistor is connected to the VDD potential. The drain of the eleventh PMOS transistor is connected to the drain of the thirteenth NMOS transistor. The gate of the twelfth PMOS transistor is connected to the gate of the fourth PMOS transistor. The source of the twelfth PMOS transistor is connected to the VDD potential. The drain of the twelfth PMOS transistor is connected to the source of the fourteenth PMOS transistor.

[0023] The gate of the thirteenth PMOS transistor is connected to the gate of the fourth PMOS transistor. The source of the thirteenth PMOS transistor is connected to the VDD potential. The drain of the thirteenth PMOS transistor is connected to the source of the fifteenth PMOS transistor. The gate of the fourteenth PMOS transistor is connected to the gate of the third PMOS transistor. The source of the fourteenth PMOS transistor is connected to the drain of the twelfth PMOS transistor. The drain of the fourteenth PMOS transistor is connected to the drain of the fourteenth NMOS transistor.

[0024] The gate of the fifteenth PMOS transistor is connected to the gate of the third PMOS transistor. The source of the fifteenth PMOS transistor is connected to the drain of the thirteenth PMOS transistor. The drain of the fifteenth PMOS transistor is connected to the drain of the fifteenth NMOS transistor. The gate of the sixteenth PMOS transistor is connected to the gate of the fourth PMOS transistor. The source of the sixteenth PMOS transistor is connected to the VDD potential. The drain of the sixteenth PMOS transistor is connected to the source of the eighteenth PMOS transistor.

[0025] The gate of the seventeenth PMOS transistor is connected to the gate of the fourth PMOS transistor. The source of the seventeenth PMOS transistor is connected to the VDD potential. The drain of the seventeenth PMOS transistor is connected to the source of the nineteenth PMOS transistor. The gate of the eighteenth PMOS transistor is connected to the gate of the sixteenth NMOS transistor. The source of the eighteenth PMOS transistor is connected to the drain of the sixteenth PMOS transistor. The drain of the eighteenth PMOS transistor is connected to the drain of the sixteenth NMOS transistor.

[0026] The gate of the nineteenth PMOS transistor is connected to the gate of the seventeenth NMOS transistor. The source of the nineteenth PMOS transistor is connected to the drain of the seventeenth PMOS transistor. The drain of the nineteenth PMOS transistor is connected to the drain of the seventeenth NMOS transistor. The gate and the drain of the twentieth PMOS transistor are shorted. The source of the twentieth PMOS transistor is connected to the VDD potential.

[0027] The gate and the drain of the twenty-first PMOS transistor are shorted. The source of the twenty-first PMOS transistor is connected to the VDD potential.

[0028] The SN terminal of the SR latch is connected to the drain of the sixteenth NMOS transistor. The RN terminal is connected to the drain of the seventeenth NMOS transistor. The Q output terminal is connected to the gate of the seventh NMOS transistor. The QN output terminal is connected to the gate of the sixth NMOS transistor.

[0029] The input of the BUF is connected to the Q output terminal of the SR latch. The output is the CLK signal.

[0030] The beneficial effects of the present invention are as follows: The present invention proposes a current-mode dual-phase oscillator circuit that compares the voltages of two capacitors without the need for an additional reference voltage, simplifying the circuit complexity. At the same time, the comparator of the present invention is also simplified, and the propagation delay of the comparator is lower. Finally, the present invention provides an anti-locking circuit to prevent entering the metastable state during the power-on process, improving the circuit reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic structural framework diagram of the highly reliable current-mode dual-phase oscillator proposed by the present invention.

[0032] Figure 2 It is a circuit diagram of the highly reliable current-mode dual-phase oscillator proposed by the present invention.

[0033] Figure 3 It is a simulation diagram of the comparator input and output of the highly reliable current-mode dual-phase oscillator proposed by the present invention.

[0034] Figure 4 It is a simulation diagram of the power-on process of the highly reliable current-mode dual-phase oscillator proposed by the present invention.

[0035] Figure 5 It is a simulation diagram of the steady-state process of the highly reliable current-mode dual-phase oscillator proposed by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] The technical solution of the present invention will be described in detail below with reference to the drawings:

[0037] Figure 1 Shown is a schematic structural framework diagram of the highly reliable current-mode dual-phase oscillator of the present invention, including a tunable current mirror circuit, a dual-phase charge and discharge circuit, a fully differential comparator, an anti-locking circuit, an SR latch, and a buffer output.

[0038] Figure 2 It is a circuit diagram of the highly reliable current-mode dual-phase oscillator, including six parts of circuits I, II, III, IV, V, and VI. Circuit I provides a reference current for the current reference circuit, circuit II is a tunable current mirror circuit, circuit III is a dual-phase charge and discharge circuit, circuit IV is a fully differential comparator, circuit V is an anti-locking circuit, and circuit VI is an SR latch and a buffer output.

[0039] In the tunable current mirror circuit, MN1 to MN4 form a cascode structure to copy the reference current. The cascode structure can improve the current copying accuracy. MN5 and MN1 form a current mirror to copy the reference current again to increase the current for MP1 and MP2, and MP1 provides a voltage reference for MP9 and MP10.

[0040] In the bidirectional charge and discharge circuit, MP3 to MP5 and MP7 form a current mirror to amplify and copy the reference current to provide a higher charging current for the capacitor. MP9 to MP10 are in a common-gate structure to improve the accuracy of the current mirror. In the oscillator of this example, the charging current is 4 times the reference current, and a higher current is used to charge the capacitor to increase the oscillator frequency. S1 and S2 are trimming switches. When the switches are closed, the charging current is increased by the trimming current on the original basis. At different process corners, the control switches can adjust the oscillator frequency. C1 is the first capacitor, C2 is the second capacitor, MP5 to MP6, S1, and MP9 form the first charging circuit, and MP7 to MP8, S2, and MP10 form the second charging circuit. MN6 and MN8 form the first discharging circuit, and MN7 and MN9 form the second discharging circuit. EN is the enable control signal of the charge and discharge circuit. When EN is at a high level, the charge and discharge circuit operates normally. When EN is at a low level, discharging cannot be performed, and C1 and C2 will be charged to the power supply voltage VDD by the charging circuit. When the input to the gate of MN6 or MN7 is at a low level, MP5 or MP7 charges the capacitor at a constant charging speed, and the charging speed is:

[0041]

[0042] In the fully differential comparator, MP11 to MP13 and MP4 form a current mirror to provide a higher operating current for the comparator. MN10 is diode-connected to MN13 to provide a voltage bias for MN14 to 15. The voltage bias of MP14 to 15 is provided by MP3. MN11 and MN12 are the two input pairs of the comparator, connected to the upper plates of C1 and C2, which are points X and Y respectively. During the oscillation process, X and Y are alternately charged and discharged. The input pairs use NMOS transistors, and the operating state of the NMOS transistors switches between the cut-off region and the linear region. MN11 and MN12 are single-transistor common-source amplifiers. When the voltage of the X node is being charged, the Y node is being discharged. When the voltage of the X node is charged to the threshold voltage, the MN11 transistor turns on. At this time, MN11 and MN14 form a cascode amplifier structure to amplify and transfer the input voltage to the first output node M, and the voltage of the M node drops rapidly, while the second output node N always remains at a high level. When the voltage of the X node is being discharged, the Y node is being charged. When the voltage of the Y node is charged to the threshold voltage, the MN12 transistor turns on. At this time, MN12 and MN15 form a cascode amplifier structure to amplify and transfer the input voltage to the second output node N, and the voltage of the N node drops rapidly, while the first output node M always remains at a high level. The fully differential comparator is used to compare the voltages of the C1 and C2 nodes and amplify and output the capacitor voltages. When the voltage of the X node is higher than the NMOS threshold voltage, the voltage of the output terminal M will be rapidly pulled down; when the voltage of the Y node is higher than the NMOS threshold voltage, the voltage of the output terminal N will be rapidly pulled down. The input and output waveforms of the comparator are asFigure 3 As shown. At 5.43 μs, when the first capacitor is charged and reaches the NMOS transistor threshold, the comparator quickly pulls down the M node.

[0043] In the anti - self - locking circuit, MP16 - MP17 and MP4 form a current mirror to provide the working current for the circuit. MP18 - MP19, MN16 - MN17 are the main parts of the anti - self - locking circuit. One function is to further amplify the voltages of M and N nodes and input them to the SR latch. To prevent entering the self - locking state and not oscillating during power - on, the sizes of MN16 and MN17 transistors are different:

[0044]

[0045] It is the size difference between MN16 and MN17 that can separate the input voltages of SN and RN of the SR latch during power - on, so that the SR latch can get out of the metastable state. In the anti - self - locking circuit, there are also MP20 and MP21 transistors connected in diode - connection. The source of the PMOS transistor is connected to VDD, and the drain is connected to the sources of MP18 and MP19 transistors. The functions of MP20 and MP21 are as follows: when a low level is input to the M or N node, MP18 or MP19 transistor turns on to charge the SN or RN node. At this time, MP20 and MP21 will enter the saturation region, and MP16 and MP20 transistors charge the SN node simultaneously. At this time, the charging current is greater than the working current in the steady state, improving the transient performance of the circuit and reducing the transmission delay. The MN18 transistor is also a limiting transistor to reduce the transmission delay. Since the MP11 branch biasing circuit is always in the working state and injects current into the MN18 transistor, the diode - connected MN18 transistor always works in the saturation region, so as to ensure that the source voltage of the MN16 transistor is higher than the threshold voltage of the MN18 transistor. Therefore, the lower limit amplitude of the SN or RN point will not be lower than the threshold voltage of the MN18 transistor, limiting the voltage amplitude of the SN and RN nodes, improving the flip - flop speed during the transient process, and further reducing the transmission delay of the anti - self - locking circuit.

[0046] Power - on transient analysis: The waveform during the power - on process is as Figure 4As shown, the power supply voltage starts power-on from 0 at 0 μs. Before power-on, the input node voltages of SN and RN are both at low level. Before reaching 940 ns, the potentials at the RN and SN terminals of the RS latch rise synchronously, and the potentials of its outputs Q and QN also rise synchronously. As the power-on progresses, at 940 ns, MN16 and MN17 gradually turn on. However, since the width-to-length ratio of the MN16 transistor is smaller than that of MN17, the pull-down ability of the SN node is weaker than that of the RN node, resulting in a separation trend between the potentials at the RN and SN terminals during the power-on process. This difference will cause the RS latch to enter the positive feedback working state. At 1.25 μs, the voltage difference between SN and RN reaches 167 mV, directly dividing the outputs Q and QN into "0" and "1". Since then, it has escaped from the metastable state and entered the normal state, waiting for the capacitor to charge and discharge for oscillation. At this time, the second capacitor is charged. At 2.347 μs, it reaches the threshold voltage of the comparator input transistor MN12. At this time, the N node is quickly pulled down, changing the voltage state of the RN node, causing the second capacitor to discharge and the first capacitor to charge. Thus, the normal power-on is completed. After the normal power-on is completed, each point gradually enters the periodic steady state, forming a stable clock frequency.

[0047] Analysis of the steady-state process: The waveform of the steady-state process is as Figure 5 shown. After the oscillator circuit completes power-on, the RS latch outputs a periodic square-wave signal, which serves as the charge and discharge control signal for capacitors C1 and C2, controlling the potential rise and fall of the X and Y nodes. When Q = 1 and QN = 0, MN6 is cut off and MN7 is turned on. Capacitor C2 discharges, and capacitor C1 charges. The potential of the X node rises, the potential of the Y node drops, the potential of the M node drops, the potential of the N node rises, the potential of the SN node rises, and the RN node always remains at low level until the potential of the SN node is pulled to a high enough position and maintained for a certain time, then the levels of Q and QN will flip. At this time, Q = 0 and QN = 1. MN7 is turned on and MN6 is cut off. Capacitor C1 discharges, and capacitor C2 charges. The potential of the X node drops, the potential of the Y node rises, the potential of the N node drops, the potential of the M node rises, the potential of the RN node rises, and the potential of the SN node drops until the potential of the RN node is pulled to a high enough position and maintained for a certain time, then the levels of Q and QN will flip again, and the situation of Q = 1 and QN = 0 will occur again, and so on in a cycle to achieve periodic oscillation.

Claims

1. A high reliability current mode dual phase oscillator circuit, characterized in that: It includes a current mirror bias circuit, a dual-phase charge and discharge circuit, a fully differential comparator, an anti-self-locking circuit, and an SR latch and buffer output; The current mirror bias circuit is used to copy the current generated by the current reference to provide current bias for the dual-phase charge and discharge circuit, the full differential comparator, and the anti-self-locking circuit. The current mirror bias circuit includes an external current source, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a first switch S1, and a second switch S2; The two-phase charge and discharge circuit is used to charge and discharge its own capacitor, including a first capacitor, a second capacitor, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a ninth PMOS tube, and a tenth PMOS tube; The fully differential comparator is used to compare the on-chip capacitor voltage to generate a comparator output, including a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, and a fifteenth PMOS tube; The anti-self-locking circuit is used to prevent the oscillator from entering a metastable state during power-on, and includes a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, and a twenty-first PMOS tube; In the SR latch and buffer output, the SR latch is used to control the two-phase charge and discharge circuit, so that the on-chip capacitor is alternately charged and discharged, and the buffer outputs an oscillating square wave signal, including the SR latch and the buffer output stage; The gate and drain of the first NMOS tube are short-circuited and connected to the source of the third NMOS, and the source of the first NMOS is connected to the GND potential; The gate of the second NMOS tube is connected to the gate of the first NMOS tube, the source of the second NMOS tube is connected to the GND potential, and the drain of the second NMOS tube is connected to the source of the fourth MOS tube; The gate and drain of the third NMOS tube are short-circuited, connected to the gate of the fourth NMOS tube, and connected to the external reference current source IREF; the source of the third NMOS tube is connected to the drain of the first NMOS tube; the gate of the fourth NMOS tube is connected to the gate of the third NMOS tube, the drain of the fourth NMOS tube is connected to the drain of the third PMOS tube, and the source of the fourth NMOS tube is connected to the drain of the second NMOS tube; The gate of the fifth NMOS tube is connected to the gate of the first NMOS tube, the source of the fifth NMOS tube is connected to the GND potential, and the drain of the fifth NMOS tube is connected to the drain of the first PMOS tube; the gate of the sixth NMOS tube is connected to the output of the SR latch QN, the source of the sixth NMOS tube is connected to the GND potential, and the drain of the sixth NMOS tube is connected to the source of the eighth NMOS tube; The gate of the seventh NMOS tube is connected to the Q output of the SR latch, the source of the seventh NMOS tube is connected to the GND potential, and the drain of the seventh NMOS tube is connected to the source of the ninth NMOS tube; the gate of the eighth NMOS tube is connected to the external EN enable signal, the source of the eighth NMOS tube is connected to the drain of the sixth NMOS tube, and the drain of the eighth NMOS tube is connected to the drain of the ninth PMOS tube; The gate of the ninth NMOS tube is connected to the external EN enable signal, the source of the ninth NMOS tube is connected to the drain of the seventh NMOS tube, and the drain of the ninth NMOS tube is connected to the drain of the tenth PMOS tube; the gate and drain of the tenth NMOS tube are short-circuited, connected to the source of the thirteenth PMOS tube, and the source of the tenth NMOS tube is connected to the drain of the eighteenth NMOS tube; The upper plate of the first capacitor is connected to the drain of the eighth PMOS tube, and the lower plate is connected to the GND potential; the upper plate of the second capacitor is connected to the drain of the ninth PMOS tube, and the lower plate is connected to the GND potential; The gate of the eleventh NMOS tube is connected to the upper plate of the first capacitor, the source of the eleventh NMOS tube is connected to the GND potential, and the drain of the eleventh NMOS tube is connected to the source of the fourteenth NMOS tube; the gate of the twelfth NMOS tube is connected to the upper plate of the second capacitor, the source of the twelfth NMOS tube is connected to the GND potential, and the drain of the twelfth NMOS tube is connected to the source of the fifteenth NMOS tube; The gate and drain of the thirteenth NMOS tube are short-circuited and connected to the drain of the eleventh PMOS tube, and the source of the thirteenth NMOS tube is connected to the drain of the tenth NMOS tube; the gate of the fourteenth NMOS tube is connected to the gate of the thirteenth NMOS tube, the source of the fourteenth NMOS tube is connected to the drain of the eleventh NMOS tube, and the drain of the fourteenth NMOS tube is connected to the drain of the fourteenth PMOS tube; The gate of the fifteenth NMOS tube is connected to the gate of the thirteenth NMOS tube, the source of the fifteenth NMOS tube is connected to the drain of the twelfth NMOS tube, and the drain of the fifteenth NMOS tube is connected to the drain of the fifteenth PMOS tube; the gate of the sixteenth NMOS tube is connected to the drain of the fourteenth NMOS tube and the gate of the eighteenth PMOS tube, the source of the sixteenth NMOS tube is connected to the drain of the eighteenth NMOS tube, and the drain of the sixteenth NMOS tube is connected to the drain of the eighteenth PMOS tube; The gate of the seventeenth NMOS tube is connected to the drain of the fifteenth NMOS tube and the gate of the nineteenth PMOS tube, the source of the seventeenth NMOS tube is connected to the drain of the eighteenth NMOS tube, and the drain of the seventeenth NMOS tube is connected to the drain of the nineteenth PMOS tube; the gate and drain of the eighteenth NMOS tube are short-circuited, and the source of the eighteenth NMOS tube is connected to the GND potential; The gate and drain of the first PMOS tube are short-circuited and connected to the drain of the fifth NMOS, and the source of the first PMOS tube is connected to the drain of the second PMOS tube; the gate and drain of the second PMOS tube are short-circuited, and the source of the second PMOS tube is connected to the VDD potential; The gate and drain of the third PMOS tube are short-circuited and connected to the drain of the fourth PMOS tube; The source of the third PMOS tube is connected to the drain of the fourth PMOS tube; the gate and the drain of the fourth PMOS tube are short-circuited, and the source of the fourth PMOS tube is connected to the VDD potential; The gate of the fifth PMOS tube is connected to the gate of the fourth PMOS tube, the source of the fifth PMOS tube is connected to the VDD potential, and the drain of the fifth PMOS tube is connected to the source of the ninth PMOS tube; the gate of the sixth PMOS tube is connected to the gate of the fourth PMOS tube, the source of the sixth PMOS tube is connected to the VDD potential, and the drain of the sixth PMOS tube is connected to the positive input terminal of the first switch S1; The gate of the seventh PMOS tube is connected to the gate of the fourth PMOS tube, the source of the seventh PMOS tube is connected to the VDD potential, and the drain of the seventh PMOS tube is connected to the source of the tenth PMOS tube; The gate of the eighth PMOS tube is connected to the gate of the fourth PMOS tube, the source of the eighth PMOS tube is connected to the VDD potential, and the drain of the eighth PMOS tube is connected to the positive input terminal of the second switch S2; The positive input terminal of the first switch S1 is connected to the drain of the sixth PMOS tube, and the negative input terminal of the first switch S1 is connected to the drain of the fifth PMOS tube; The positive input terminal of the second switch S2 is connected to the drain of the eighth PMOS tube, and the negative input terminal of the second switch S2 is connected to the drain of the seventh PMOS tube; The gate of the ninth PMOS tube is connected to the gate of the first PMOS tube, the source of the ninth PMOS tube is connected to the drain of the fifth PMOS tube, and the drain of the ninth PMOS tube is connected to the drain of the eighth NMOS tube; the gate of the tenth PMOS tube is connected to the gate of the first PMOS tube, the source of the tenth PMOS tube is connected to the drain of the seventh PMOS tube, and the drain of the tenth PMOS tube is connected to the drain of the ninth NMOS tube; The gate of the eleventh PMOS tube is connected to the gate of the fourth PMOS tube, the source of the eleventh PMOS tube is connected to the VDD potential, and the drain of the eleventh PMOS tube is connected to the drain of the thirteenth NMOS tube; the gate of the twelfth PMOS tube is connected to the gate of the fourth PMOS tube, the source of the twelfth PMOS tube is connected to the VDD potential, and the drain of the twelfth PMOS tube is connected to the source of the fourteenth PMOS tube; The gate of the thirteenth PMOS tube is connected to the gate of the fourth PMOS tube, the source of the thirteenth PMOS tube is connected to the VDD potential, and the drain of the thirteenth PMOS tube is connected to the source of the fifteenth PMOS tube; the gate of the fourteenth PMOS tube is connected to the gate of the third PMOS tube, the source of the fourteenth PMOS tube is connected to the drain of the twelfth PMOS tube, and the drain of the fourteenth PMOS tube is connected to the drain of the fourteenth NMOS tube; The gate of the fifteenth PMOS tube is connected to the gate of the third PMOS tube, the source of the fifteenth PMOS tube is connected to the drain of the thirteenth PMOS tube, and the drain of the fifteenth PMOS tube is connected to the drain of the fifteenth NMOS tube; the gate of the sixteenth PMOS tube is connected to the gate of the fourth PMOS tube, the source of the sixteenth PMOS tube is connected to the VDD potential, and the drain of the sixteenth PMOS tube is connected to the source of the eighteenth PMOS tube; The gate of the seventeenth PMOS tube is connected to the gate of the fourth PMOS tube, the source of the seventeenth PMOS tube is connected to the VDD potential, and the drain of the seventeenth PMOS tube is connected to the source of the nineteenth PMOS tube; the gate of the eighteenth PMOS tube is connected to the gate of the sixteenth NMOS tube, the source of the eighteenth PMOS tube is connected to the drain of the sixteenth PMOS tube, and the drain of the eighteenth PMOS tube is connected to the drain of the sixteenth NMOS tube; The gate of the nineteenth PMOS tube is connected to the gate of the seventeenth NMOS tube, the source of the nineteenth PMOS tube is connected to the drain of the seventeenth PMOS tube, and the drain of the nineteenth PMOS tube is connected to the drain of the seventeenth NMOS tube; the gate and drain of the twentieth PMOS tube are short-circuited, and the source of the twentieth PMOS tube is connected to the VDD potential; The gate and drain of the twenty-first PMOS tube are short-circuited, and the source of the twenty-first PMOS tube is connected to the VDD potential; The SN terminal of the SR latch is connected to the drain of the sixteenth NMOS tube; the RN terminal is connected to the drain of the seventeenth NMOS tube; the Q output terminal is connected to the gate of the seventh NMOS tube; the QN output terminal is connected to the gate of the sixth NMOS tube; The input of the buffer output is connected to the Q output terminal of the SR latch; the output of the buffer output is the CLK signal.

Images