G-type switched capacitor power amplifier based on cascade switch multiplexing

Abstract

The invention discloses a class-G switched capacitor power amplifier based on cascade switch multiplexing, and relates to the technical field of electronic circuits, the power amplifier comprises a control circuit, a class-G switch, a capacitor array, an output matching network and a load; the control circuit comprises a first control circuit and a second control circuit, and each of the first control circuit and the second control circuit comprises a plurality of power amplifier modules; each power amplifier module comprises a cascade switch multiplexing G-class structure; the capacitor arrays comprise a first capacitor array and a second capacitor array, and each capacitor array comprises a plurality of switched capacitors; the output matching network comprises a first capacitor, a second capacitor and a transformer. According to the voltage type digital power amplifier, the advantage of accurate capacitance value is achieved through the multiple switched capacitors by means of the CMOS technology, the output voltage amplitude is determined according to the capacitance specific value, high linearity of the output voltage amplitude is achieved, meanwhile, high rollback efficiency is achieved, and the layout occupied area of an output matching network of the power amplifier is reduced.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuits, and particularly to a class-G switched-capacitor power amplifier based on cascode switch multiplexing. Background Art

[0002] A radio frequency power amplifier is the main power-consuming device of a mobile wireless terminal. Wireless communication standards usually use spectrum-efficient orthogonal frequency division multiplexing modulation to encode the amplitude and phase information of signals. Using the above non-constant envelope modulation requires a power amplifier with high linearity. However, existing power amplifiers are difficult to meet the requirements of high linearity. Summary of the Invention

[0003] The main purpose of the embodiments of this application is to propose a class-G switched-capacitor power amplifier based on cascode switch multiplexing to improve the linearity of the power amplifier.

[0004] To achieve the above object, on the one hand, an embodiment of this application proposes a class-G switched-capacitor power amplifier based on cascode switch multiplexing. The power amplifier includes a control circuit, a class-G switch, a capacitor array, an output matching network, and a load;

[0005] Wherein, the control circuit includes a first control circuit and a second control circuit. Both the first control circuit and the second control circuit include a plurality of power amplifier modules and a plurality of switched capacitors; each of the power amplifier modules includes a class-G structure with cascode switch multiplexing;

[0006] The capacitor array includes a first capacitor array and a second capacitor array. Each capacitor array includes a plurality of switched capacitors;

[0007] The output matching network includes a first capacitor, a second capacitor, and a transformer;

[0008] The first input end of each of the power amplifier modules in the first control circuit is used to input a first digital phase signal, the second input end is used to input an envelope amplitude signal, and the output end is connected to the first end of one of the switched capacitors in the first capacitor array; the second ends of each of the switched capacitors in the first capacitor array are all connected to the first input end of the transformer in the output matching network;

[0009] The first input end of each of the power amplifier modules in the second control circuit is used to input a second digital phase signal, the second input end is used to input the envelope amplitude signal, and the output end is connected to the first end of one of the switched capacitors in the second capacitor array; the second ends of each of the switched capacitors in the second capacitor array are all connected to the second input end of the transformer in the output matching network; the first digital phase signal and the second digital phase signal are differential signals;

[0010] The first capacitor is connected between the first input terminal and the second input terminal of the transformer as a primary parallel capacitor;

[0011] The second capacitor is connected between the first output terminal and the second output terminal of the transformer as a secondary parallel capacitor;

[0012] The first output terminal of the transformer is further connected to the first end of the load and the radio frequency output terminal;

[0013] The second output terminal of the transformer is further connected to the second end of the load and the reference ground.

[0014] In some embodiments, each of the power amplifier modules includes a non-overlapping clock signal generation module, three OR gates, one NOT gate, one AND gate, two level boosting circuits, four pairs of drive sub-modules, and a class-G structure with cascode switches multiplexed; wherein, each pair of the drive sub-modules includes two serially-connected drive sub-units.

[0015] In some embodiments, the input terminal of the non-overlapping clock signal generation module is used for inputting a digital phase signal, and the output terminal is respectively connected to the input terminals of each of the OR gates;

[0016] Among them, the input terminals of two of the OR gates and the AND gate are used for inputting a first envelope amplitude signal, and the output terminal of one of the OR gates is connected to the input terminal of one pair of the drive sub-modules, and the other is connected to one of the level boosting circuits. The input terminals of the NOT gate and the AND gate are used for inputting a second envelope amplitude signal; the input terminal of the remaining one OR gate is connected to the output terminal of the AND gate, and the output terminal of the remaining one OR gate is connected to the input terminal of one pair of the drive sub-modules;

[0017] The output terminal of the NOT gate is connected to the remaining one level boosting circuit, and the output terminals of the two level boosting circuits are respectively connected to the input terminals of one pair of the drive sub-modules;

[0018] The output terminals of the four pairs of the drive sub-modules are respectively connected to different input terminals of the class-G structure with cascode switches multiplexed.

[0019] In some embodiments, the driving ability of the latter drive sub-unit in each pair of the drive sub-modules is three times that of the former drive sub-unit.

[0020] In some embodiments, the class-G structure with cascode switches multiplexed includes: PMOS transistors MP1, MP2; NMOS transistors MN1, MN2, MN3;

[0021] Among them, the gates of MP1, MP2, MN1, and MN3 are respectively used as the input terminals of the class-G structure of the common-source common-gate switch multiplexing;

[0022] The drain of MN3 is connected to the source of MP1 and the drain of MP2. The source of MP2 is connected to the source of MN2, and the source of MN1 is connected to the drain of MN2. The common connection point of the source of MP2 and the source of MN2 serves as the output terminal of the class-G structure of the common-source common-gate switch multiplexing and is connected to the first end of the switched capacitor;

[0023] The gate of MN2 is connected to VDD, the drain of MP1 is connected to 2VDD, the source of MN3 is connected to VDD, and the drain of MN1 is connected to the reference ground.

[0024] In some embodiments, the gates of MP1 and MN3 are both used to input 2VDD; the gates of MP2 and MN1 are both used to input a square wave with a low level of VSS and a high level of VDD.

[0025] In some embodiments, both the first control circuit and the second control circuit include 2 first power amplifier modules and 31 second power amplifier modules. The input terminals of each of the second power amplifier modules are denoted as T1 to T31; both the first capacitor array and the second capacitor array include 2 first switched capacitors and 31 second switched capacitors;

[0026] Among them, the output terminal of each of the first power amplifier modules is respectively connected to 1 of the first switched capacitors, and the output terminal of each of the second power amplifier modules is respectively connected to 1 of the second switched capacitors;

[0027] T1, T2 to T3, T4 to T7, T8 to T15, and T16 to T31 are respectively connected to the output terminals of 1 pair of inverters; the input terminals of each pair of the inverters are respectively used to input different envelope amplitude signals; each pair of the inverters consists of 2 serially connected inverters.

[0028] In some embodiments, the driving ability of the second power amplifier module is twice that of the first power amplifier module; the capacitance value of the second switched capacitor is twice that of the first switched capacitor.

[0029] In some embodiments, the value of the resistance of the load is 50 ohms.

[0030] To achieve the above object, another aspect of the embodiments of the present application proposes a wireless terminal, and the radio frequency power amplifier of the wireless terminal includes the class-G switched capacitor power amplifier based on common-source common-gate switch multiplexing as described above.

[0031] The embodiments of the present application at least include the following beneficial effects:

[0032] As a voltage - type digital power amplifier of the present application, by using multiple switched - capacitors, the advantage of achieving precise capacitance values with CMOS technology can be realized. The output voltage amplitude is determined by the capacitance ratio, achieving high linearity of the output voltage amplitude. At the same time, high back - off efficiency and reduction of the layout area of the power amplifier are also achieved. Brief Description of the Drawings

[0033] To more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0034] Figure 1 Structural diagram (a) of the class - G switched - capacitor power amplifier based on cascode switch multiplexing and structural diagram (b) of the power amplifier module provided by the embodiments of the present application;

[0035] Figure 2 Structural diagram (a) of a traditional 5 - bit decoder and gated structural diagram (b) of the AM code provided by the embodiments of the present application;

[0036] Figure 3 Structural diagram (a) of a traditional class - G switch and structural diagram (b) of class - G using cascode switch multiplexing provided by the embodiments of the present application;

[0037] Figure 4 Structural diagram (a) of a traditional inductor - based matching network and structural diagram (b) of a recommended transformer matching network provided by the embodiments of the present application. Detailed Description of the Embodiments

[0038] In order to make the purpose, technical solutions and advantages of the present application more clear, the present application will be further described in detail below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application detailed in the appended claims.

[0039] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if", "when" as used herein may be interpreted as "when...", "while...", or "in response to determining".

[0040] The terms "at least one", "a plurality of", "each", "any one", etc. used in this application, where "at least one" includes one, two, or more than two, "a plurality of" includes two or more than two, "each" refers to each of the corresponding plurality, and "any one" refers to any one of the plurality.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0042] Before elaborating on the embodiments of this application in detail, some of the terms and related technologies involved in the embodiments of this application are described as follows:

[0043] 1. CMOS (Complementary Metal Oxide Semiconductor): Complementary Metal Oxide Semiconductor; includes PMOS transistors and NMOS transistors;

[0044] 2. SCPA (Switched Capacitor Power Amplifiers): Switched Capacitor Power Amplifiers;

[0045] 3. PA (Power Amplifiers): Power Amplifiers;

[0046] 4. Cascode: Cascode;

[0047] 5. MSB (Most Significant Bit): Most Significant Bit, the bit in binary that represents the highest value and has the greatest impact on the numerical value;

[0048] 6. LSB (Least Significant Bit): Least Significant Bit, the bit in binary that represents the lowest value;

[0049] 7. OFDM (orthogonal frequency division multiplexing): Orthogonal Frequency Division Multiplexing, which is a parallel transmission method using multiple carriers;

[0050] 8. PBO (power back-off): Power back-off;

[0051] 9. PWM (Pulse Width Modulation): Pulse Width Modulation;

[0052] 10. EFR (Envelope Elimination and Restoration): Envelope Elimination and Restoration;

[0053] 11. SE (Spectral Efficiency): Spectral Efficiency;

[0054] 12. AM (Amplitude Modulation): Amplitude Modulation, which can be modulated to obtain an envelope amplitude signal;

[0055] 13. PM (Phase Modulation): Phase Modulation, which can be modulated to obtain a digital phase signal.

[0056] The radio frequency power amplifier is the main power-consuming device of mobile wireless terminals. Wireless communication standards usually use spectrally efficient OFDM modulation to encode the amplitude and phase information of signals, such as the Wi-Fi application (802.11g / n band) in Table 1. Adopting the above non-constant envelope modulation requires a high-linearity power amplifier (PA), which operates at a signal level lower than the peak power supply voltage to achieve higher linearity.

[0057] Switch-mode power amplifiers are considered a suitable solution due to their more efficient linearization. Existing switch-mode power amplifiers include: Pulse Width Modulation (PWM), Out-Phasing, and Envelope Elimination and Restoration (EER).

[0058] Table 1 802.11g / n Band and Technical Specifications

[0059]

[0060] In the prior art, the PWM type power amplifier is limited by the transmitted output power, so the dynamic range of the power amplifier is related to the minimum pulse width; the minimum output power of the Out-Phasing PA is limited by the load mismatch when the out-phase angle is large, and it also requires two power amplifiers and a passive power combining network that consumes a large layout area; compared with the power amplifiers of PWM and Out-Pashing, the EER power amplifier provides the best performance balance among linearity, output power and efficiency. However, it sacrifices the power consumption (25 mW) index. Linearity, area and efficiency are important parameters of the power amplifier.

[0061] To solve at least one problem in the prior art, an embodiment of the present application provides a class-G switched capacitor power amplifier based on cascode switch multiplexing. The power amplifier includes a control circuit, a class-G switch, a capacitor array, an output matching network and a load;

[0062] Wherein, the control circuit includes a first control circuit and a second control circuit. Both the first control circuit and the second control circuit include a plurality of power amplifier modules and a plurality of switched capacitors; each of the power amplifier modules includes a class-G structure with cascode switch multiplexing;

[0063] The capacitor array includes a first capacitor array and a second capacitor array. Each capacitor array includes a plurality of switched capacitors;

[0064] The output matching network includes a first capacitor, a second capacitor and a transformer;

[0065] The first input end of each power amplifier module in the first control circuit is used to input a first digital phase signal, the second input end is used to input an envelope amplitude signal, and the output end is connected to the first end of one of the switched capacitors in the first capacitor array; the second ends of each of the switched capacitors in the first capacitor array are all connected to the first input end of the transformer in the output matching network;

[0066] The first input end of each power amplifier module in the second control circuit is used to input a second digital phase signal, the second input end is used to input the envelope amplitude signal, and the output end is connected to the first end of one of the switched capacitors in the second capacitor array; the second ends of each of the switched capacitors in the second capacitor array are all connected to the second input end of the transformer in the output matching network; the first digital phase signal and the second digital phase signal are differential signals; the first digital phase signal and the second digital phase signal are differential signals;

[0067] The first capacitor is connected between the first input end and the second input end of the transformer as a primary shunt capacitor;

[0068] The second capacitor is connected between the first output terminal and the second output terminal of the transformer as a secondary parallel capacitor;

[0069] The first output terminal of the transformer is also connected to the first end of the load and the radio frequency output terminal;

[0070] The second output terminal of the transformer is also connected to the second end of the load and the reference ground.

[0071] Furthermore, each of the power amplifier modules includes a non-overlapping clock signal generation module, three OR gates, one NOT gate, one AND gate, two level boosting circuits, four pairs of drive sub-modules, and the class-G structure with cascode switches multiplexed; wherein, each pair of the drive sub-modules includes two serially-connected drive sub-units.

[0072] Furthermore, the input terminal of the non-overlapping clock signal generation module is used for inputting a digital phase signal, and the output terminal is respectively connected to the input terminals of each of the OR gates;

[0073] Among them, the input terminals of two of the OR gates and the AND gate are used for inputting a first envelope amplitude signal, and the output terminal of one of the OR gates is connected to the input terminal of a pair of the drive sub-modules, and the other is connected to one of the level boosting circuits, and the input terminals of the NOT gate and the AND gate are used for inputting a second envelope amplitude signal; the input terminal of the remaining one of the OR gates is connected to the output terminal of the AND gate, and the output terminal of the remaining one of the OR gates is connected to the input terminal of a pair of the drive sub-modules;

[0074] The output terminal of the NOT gate is connected to the remaining one of the level boosting circuits, and the output terminals of the two level boosting circuits are respectively connected to the input terminals of a pair of the drive sub-modules;

[0075] The output terminals of the four pairs of the drive sub-modules are respectively connected to different input terminals of the class-G structure with cascode switches multiplexed.

[0076] As another further embodiment, the driving capability of the latter drive sub-unit in each pair of the drive sub-modules is three times that of the former drive sub-unit.

[0077] Furthermore, the class-G structure with cascode switches multiplexed includes: PMOS transistors MP1, MP2; NMOS transistors MN1, MN2, MN3;

[0078] Among them, the gates of MP1, MP2, MN1, and MN3 are respectively used as the input terminals of the class-G structure with cascode switches multiplexed;

[0079] The drain of MN3 is connected to the source of MP1 and the drain of MP2. The source of MP2 is connected to the source of MN2. The source of MN1 is connected to the drain of MN2. The common connection point of the source of MP2 and the source of MN2 serves as the output terminal of the class-G structure multiplexed by the cascode switch and is connected to the first terminal of the switched capacitor.

[0080] The gate of MN2 is connected to VDD. The drain of MP1 is connected to 2VDD. The source of MN3 is connected to VDD. The drain of MN1 is connected to the reference ground.

[0081] Furthermore, the gates of MP1 and MN3 are both used to input 2VDD. The gates of MP2 and MN1 are both used to input a square wave with a low level of VSS and a high level of VDD.

[0082] As an alternative embodiment, both the first control circuit and the second control circuit include 2 first power amplifier modules and 31 second power amplifier modules. The input terminals of each of the second power amplifier modules are denoted as T1 to T31. Both the first capacitor array and the second capacitor array include 2 first switched capacitors and 31 second switched capacitors.

[0083] Among them, the output terminal of each of the first power amplifier modules is respectively connected to 1 of the first switched capacitors, and the output terminal of each of the second power amplifier modules is respectively connected to 1 of the second switched capacitors.

[0084] T1, T2 to T3, T4 to T7, T8 to T15, T16 to T31 are respectively connected to the output terminals of 1 pair of inverters. The input terminals of each pair of the inverters are respectively used to input different envelope amplitude signals. Each pair of the inverters consists of 2 serially connected inverters.

[0085] More specifically, the driving ability of the second power amplifier module is twice that of the first power amplifier module. The capacitance value of the second switched capacitor is twice that of the first switched capacitor.

[0086] Optionally, the resistance value of the load is 50 ohms.

[0087] Next, the solution of the embodiment of the present application will be introduced and described in detail in combination with specific application examples:

[0088] To solve the problems existing in the prior art, this embodiment proposes a Class-G switched-capacitor power amplifier (SCPA) applicable to operate in the Wi-Fi 802.11g / n frequency band, which mainly includes a control circuit for the Class-G switch, a Class-G switched-capacitor array with cascode switch multiplexing, and an output matching network. The control circuit of the Class-G switch consists of non-overlapping clocks, a level-shifting circuit, several logic gates, and a Class-G driving unit. The control circuit plays a role in switching the Class-G between 2VDD and VDD modes, and can drive the Class-G switch with cascode switch multiplexing at the same time. The switching unit control method using the 5-bit MSB without a decoder reduces the bit-to-bit delay by 31 ps, solves the problem of time differences in the signals of some channels after AM signal decoding, and simplifies the decoding circuit. The Cascode switch multiplexed Class-G SCPA (i.e., the G-class switched-capacitor power amplifier based on cascode switch multiplexing) improves the drain efficiency of the switching device by multiplexing the existing cascode transistors, effectively reducing the parasitic capacitance at the output end. The recommended transformer matching network in this embodiment saves 78.5% of the output matching network layout area compared with the traditional inductive matching network.

[0089] 1. Structure of the G-class switched-capacitor power amplifier based on cascode switch multiplexing:

[0090] Specifically, the structural diagram of the G-class switched-capacitor power amplifier based on cascode switch multiplexing is as shown in Figure 1 (a) of Figure 1(b) of which is the structural diagram of the power amplifier module therein, which includes the input of signals of digital phase (PM) and envelope amplitude (AM) into the SCPA. The PM component is up-converted to the RF carrier frequency to generate a phase input signal (implemented off-chip). The PM signal is converted into non-overlapping switching signals by a non-overlapping clock circuit, reducing the crowbar current during the Class-G switching process, and is applied to the PM signal driver to drive the control circuit of the Class-G switch. The AM digital codeword represents the sampled value of the envelope amplitude. The power resolution is a 7-bit array design, with 5 MSBs controlling the drivers and switches of the binary-weighted capacitor (2C0) bottom plates; 2 LSBs controlling the drivers and switches of the binary-weighted capacitor (C0) bottom plates. The control circuit of the Class-G switch consists of a non-overlapping clock, a level-shifting circuit, several logic gates, and a Class-G driving unit. The control circuit functions to switch the Class-G between 2VDD and VDD modes, and at the same time can drive the Class-G switch multiplexed by the cascode switches. The output signal of the SCPA array is finally impedance-matched and transformed through a transformer matching network to generate a radio frequency signal (i.e., the fundamental frequency) on a 50Ω antenna (load).

[0091] Among them, Figure 1 x1, x2, and x3 in represent the magnification of the driving ability, that is, x1 represents 1 unit of driving ability, and x2 and x3 represent 2 and 3 units of driving ability respectively, which are 2 times and 3 times that of x1. C P is the first capacitor, C S is the second capacitor, RFOUT is the RF output terminal, and 50Ω is the load; Figure 1 In (b), A, B, C, and D are respectively the 4 input terminals of the Class-G structure multiplexed by the cascode switches.

[0092] To optimize the output power and system efficiency (SE) of the Class-G SCPA, it is necessary to first analyze their respective dominant factors. The output power can be expressed as Equation (1), where VDD is the voltage switched on the bottom plate, is the fundamental wave coefficient of the Fourier series; R opt is the optimal terminal resistance of the required output.

[0093]

[0094] The system efficiency (DE) is defined in Equation (2), where Q loaded is the load quality factor. Usually, for a fully integrated CMOS implementation, the typical on-chip Q value (about 10 - 15) limits Q loadedThe value is 2 - 3. The output voltage is scaled from the supply voltage by a ratio of (n / N), where n is the number of unit capacitors that the bottom plate switches between GND and VDD. N is the total number of capacitors. N determines the scaling of the output power resolution, and in this embodiment, N = 31 is taken. The larger n is, the greater the output efficiency and power.

[0095] Structural design of 2.5 - bit MSB without a decoder:

[0096] In Figure 2 (a) of, the traditional 5 - bit decoder is a combinational logic circuit used to decode the amplitude - modulated signal from binary to thermometer - code, as shown in Figure 2 (a) of, there are nearly 70 logic gates (such as NOR, NAND, INV). To simplify the decoding circuit, the decoder - free scheme proposed in this embodiment, the gating structure diagram of the binary AM code on the control circuit is shown in Figure 2 (b) of. Only 10 inverters are used as drivers, greatly simplifying the decoding circuit. In addition, there are signal competition and risks in the combinational logic circuit, resulting in a time difference in the decoded signals of some channels (such as T16 and T31). When inputting a 1 - MHz square - wave analog amplitude - modulated signal, the delay of the two channels T16 and T31 in the traditional scheme is 31 ps, while the delay in the scheme of this embodiment is 0 ps, solving the problem of delay after decoding the amplitude - modulated signal.

[0097] 3. Cascode - switched - multiplexed Class - G SCPA:

[0098] Referring to Figure 3 , Figure 3 (a) of is the traditional Class - G switch structure diagram, Figure 3 (b) of is the Class - G structure diagram using Cascode - switched - multiplexed in this embodiment, which can reduce the use of MOSFETs.

[0099] The high - efficiency Class - G SCPA improves the average drain efficiency by introducing an additional efficiency peak in the power - back - off (PBO) region, and there is no discontinuity in efficiency and linearity. To maximize efficiency, this embodiment proposes a Cascode - switched - multiplexed Class - G SCPA, aiming to save area and improve efficiency. The proposed switch structure removes MP3 from the traditional switch and multiplexes the existing cascode transistor MP2 as the switching device in the VDD mode to reduce the parasitic capacitance at the switch output. When MN3 is turned on, MP2 switches at the carrier frequency, and the output voltage is from VDD to GND. When |V GSMP2 | = VDD and MP1 switches at the carrier frequency, the output voltage is from 2VDD to GND. By changing the AM code, three modes of 2VDD, VDD, and GND are switched.

[0100] In the traditional Cascode scheme, when reducing the power output, the PA sub-unit can only be switched to GND. At this time, the charge leaks from the main signal output path to the grounded capacitor. When reducing the output power, Class-G can be connected to VDD instead of GND, enabling the SCPA to work at the saturated power output as much as possible, thereby improving the 6dB back-off efficiency of the SCPA.

[0101] 4. Output matching network:

[0102] Figure 4 (a) of shows the inductor-based matching network of the traditional scheme. Using L sh to tune the total capacitance C SW At the carrier frequency, L ser and the capacitor C sh constitute a low-pass matching network to achieve impedance conversion and harmonic suppression. The load R L = 50Ω is converted to the resistor R opt through the entire matching network. Three inductors are required, and the layout area consumption is about 1000um × 270um. This embodiment recommends a transformer matching network, as shown in Figure 4 (b) of. Using 1 transformer reduces the layout area of the output matching network by 78.5% compared to 3 inductors. The layout area of the transformer is only 282um × 206um, which can be applied to small mobile devices, reducing the chip manufacturing cost.

[0103] In addition, this embodiment can also be implemented by the following alternative solutions:

[0104] 1. The decoding structure can use a traditional decoder, or it can also decode the AM amplitude-modulated signal from binary coding to thermometer coding, which is a combinational logic circuit composed of independent logic gates (such as NOR, NAND, INV). However, there are signal competitions and hazards in the combinational logic circuit, resulting in a time difference in the signals of some channels after decoding, and the sub-PA units that need to be turned on cannot be turned on simultaneously, thus causing non-linearity of the output signal.

[0105] 2. The traditional Class-G switching scheme can also achieve switching between 2VDD, VDD, and GND, but the transistor output parasitic capacitance is large, which will increase the signal edge time and affect the linearity.

[0106] 3. The inductor-based matching network can also complete the output matching, but three inductors are required, and the layout area consumption is relatively large, about 1000um × 270um.

[0107] The beneficial effects of this embodiment include:

[0108] A Class-G switched-capacitor power amplifier (SCPA) applicable to operate in the Wi-Fi 802.11g / n frequency band is proposed. A switching unit control structure without using a decoder provided in this embodiment is used in its control circuit, reducing the delay between bits by 31 ps, solving the problem of time differences in signals of some channels after AM signal decoding, and simplifying the decoding circuit. In this embodiment, a cascode switch multiplexing structure is adopted, improving the drain efficiency of the switching device, effectively reducing the parasitic capacitance at the output end. At the same time, a transformer-based matching network is applied. Compared with the traditional inductor matching network, this structure saves 78.5% of the layout area of the output matching network.

[0109] An embodiment of this application also provides a wireless terminal, and the radio frequency power amplifier of this wireless terminal includes the foregoing Class-G switched-capacitor power amplifier based on cascode switch multiplexing.

[0110] It can be understood that the content in the above power amplifier embodiments is applicable to this wireless terminal embodiment. The functions specifically implemented in this wireless terminal embodiment are the same as those in the above power amplifier embodiments, and the beneficial effects achieved are also the same as those in the above power amplifier embodiments.

[0111] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" may represent: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (one) of the following" or its similar expression refers to any combination of these items, including any combination of single item (one) or plural items (ones). For example, at least one (one) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0112] The preferred embodiments of the embodiments of this application are illustrated above with reference to the drawings, and thus do not limit the scope of rights of the embodiments of this application. Any modification, equivalent replacement, and improvement made by those skilled in the art without departing from the scope and essence of the embodiments of this application shall be within the scope of rights of the embodiments of this application.

Claims

1. A class G switched capacitor power amplifier based on cascode switch multiplexing, characterized in that: The power amplifier comprises a control circuit, a class G switch, a capacitor array, an output matching network and a load; The control circuit includes a first control circuit and a second control circuit, and the first control circuit and the second control circuit each include a plurality of power amplifier modules; each of the power amplifier modules includes a G-type structure with common source and common gate switch multiplexing; The capacitor array includes a first capacitor array and a second capacitor array, each capacitor array includes a plurality of switch capacitors; The output matching network includes a first capacitor, a second capacitor, and a transformer; The first input end of each power amplifier module in the first control circuit is used to input a first digital phase signal, the second input end is used to input an envelope amplitude signal, and the output end is connected to the first end of a switch capacitor in the first capacitor array; the second end of each switch capacitor in the first capacitor array is connected to the first input end of the transformer in the output matching network; The first input end of each power amplifier module in the second control circuit is used to input the second digital phase signal, the second input end is used to input the envelope amplitude signal, and the output end is connected to the first end of one of the switch capacitors in the second capacitor array; the second end of each switch capacitor in the second capacitor array is connected to the second input end of the transformer in the output matching network; the first digital phase signal and the second digital phase signal are differential signals; The first capacitor is connected between the first input terminal and the second input terminal of the transformer as a primary shunt capacitor; The second capacitor is connected between the first output terminal and the second output terminal of the transformer as a secondary parallel capacitor; The first output end of the transformer is also connected to the first end of the load and the RF output end; The second output terminal of the transformer is also connected to the second terminal of the load and a reference ground.

2. The class G switched capacitor power amplifier based on cascode switch multiplexing according to claim 1, characterized in that: Each of the power amplifier modules includes a non-overlapping clock signal generating module, 3 OR gates, 1 NOT gate, 1 AND gate, 2 level boosting circuits, 4 pairs of driver sub-modules and a G-type structure for common source and common gate switch multiplexing; wherein each pair of the driver sub-modules includes two driver sub-units connected in series.

3. The class G switched capacitor power amplifier based on cascode switch multiplexing according to claim 2, characterized in that: The input end of the non-overlapping clock signal generating module is used to input the digital phase signal, and the output end is respectively connected to the input end of each of the OR gates; The input ends of two of the OR gates and the AND gate are used to input the first envelope amplitude signal, and the output end of one of the OR gates is connected to the input end of a pair of the driving submodules, and the other one is connected to a level boosting circuit, and the input ends of the NOT gate and the AND gate are used to input the second envelope amplitude signal; the input end of the remaining OR gate is connected to the output end of the AND gate, and the output end of the remaining OR gate is connected to the input end of a pair of the driving submodules; The output end of the NOT gate is connected to the remaining one of the level boosting circuits, and the output ends of the two level boosting circuits are respectively connected to the input ends of a pair of the driving sub-modules; The output terminals of the four pairs of driving submodules are respectively connected to different input terminals of the G-type structure multiplexing the common-source and common-gate switches.

4. The class G switched capacitor power amplifier based on cascode switch multiplexing according to claim 2, characterized in that: The driving capability of the latter driving sub-unit in each pair of the driving sub-modules is three times that of the former driving sub-unit.

5. The class G switched capacitor power amplifier based on cascode switch multiplexing according to claim 1, characterized in that: The G-type structure of the cascode switch multiplexing includes: PMOS tubes MP1 and MP2; NMOS tubes MN1, MN2 and MN3; The gates of MP1, MP2, MN1 and MN3 are respectively used as the input terminals of the G-type structure multiplexing of the common-source and common-gate switches; The drain of MN3 is connected to the source of MP1 and the drain of MP2, the source of MP2 is connected to the source of MN2, and the source of MN1 is connected to the drain of MN2; the common connection point between the source of MP2 and the source of MN2 is connected to the first end of the switch capacitor as the output end of the G-type structure of the common source and common gate switch multiplexing; The gate of MN2 is connected to VDD, the drain of MP1 is connected to 2VDD, the source of MN3 is connected to VDD, and the drain of MN1 is connected to the reference ground.

6. The class G switched capacitor power amplifier based on cascode switch multiplexing according to claim 5, characterized in that: The gates of MP1 and MN3 are both used to input 2VDD; the gates of MP2 and MN1 are both used to input a square wave with a low level of VSS and a high level of VDD.

7. The class G switched capacitor power amplifier based on cascode switch multiplexing according to claim 1, characterized in that: The first control circuit and the second control circuit each include two first power amplifier modules and 31 second power amplifier modules, and the input end of each second power amplifier module is denoted as T1 to T31; the first capacitor array and the second capacitor array each include two first switch capacitors and 31 second switch capacitors; The output end of each of the first power amplifier modules is connected to one of the first switch capacitors, and the output end of each of the second power amplifier modules is connected to one of the second switch capacitors; T1, T2-T3, T4-T7, T8-T15, T16-T31 are respectively connected to the output ends of a pair of inverters; the input ends of each pair of inverters are respectively used to input different envelope amplitude signals; each pair of inverters is composed of two inverters connected in series.

8. The class G switched capacitor power amplifier based on cascode switch multiplexing according to claim 7, characterized in that: The driving capability of the second power amplifier module is twice that of the first power amplifier module; and the capacitance of the second switch capacitor is twice that of the first switch capacitor.

9. The class G switched capacitor power amplifier based on cascode switch multiplexing according to any one of claims 1 to 8, characterized in that: The resistance of the load is 50 ohms.

10. A wireless terminal, characterized in that: The radio frequency power amplifier of the wireless terminal comprises a class G switched capacitor power amplifier based on common source and common gate switch multiplexing as described in any one of claims 1 to 9.

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