Multiplication digital-to-analog converter

Abstract

A multiplication digital-to-analog converter includes an analog-to-digital converter, a selection circuit, an operational amplifier, a first switched capacitor circuit, a second switched capacitor circuit, a first switch, a second switch, a first load capacitor, and a second load capacitor. The analog-to-digital converter generates a selection signal according to a first input signal and a second input signal. The selection circuit generates a first reference voltage and a second reference voltage according to the selection signal. The first and second switched capacitor circuits amplify signal components of the first and second input signals. The first switch receives the second reference voltage. The second switch receives the first reference voltage. A first load capacitor receives the second reference voltage through the first switch. A second load capacitor receives the first reference voltage through the second switch.

Description

Technical Field

[0001] The present invention relates to a multiplication digital-to-analog converter of a pipeline ADC (also called pipelined ADC). Background Art

[0002] See also Figure 1 , Figure 1 1 is a circuit diagram of a conventional multiplying digital-to-analog converter (hereinafter referred to as MDAC). MDAC 100 is a 1.5-bit multiplying digital-to-analog converter having an input terminal Vinp, an input terminal Vinn, an output terminal Vp2, and an output terminal Vn2. MDAC 100 includes an analog-to-digital converter (ADC) 110, a selection circuit 120, a sampling and amplifying circuit 130p, a sampling and amplifying circuit 130n, and an operational amplifier 140.

[0003] When the MDAC 100 is applied to a pipeline ADC (also called pipelined ADC), the ADC 110 serves as a sub-ADC of the pipeline ADC. The ADC 110 is coupled to an input terminal Vinp and an input terminal Vinn, and is used to generate a selection signal SEL according to an input signal Vsp and an input signal Vsn. The input signal Vsp (=Vdc+dV) and the input signal Vsn (=Vdc-dV) can be a differential signal pair, wherein Vdc is a common mode voltage of the two, and dV is a signal component.

[0004] The selection circuit 120 is coupled to the ADC 110, and is used to determine the reference voltage VR1 and the reference voltage VR2 from a plurality of preset voltages (including but not limited to the preset voltage Vx, the preset voltage Vy, and the common mode voltage Vcm of the preset voltage Vx and the preset voltage Vy) according to the selection signal SEL, and provide the reference voltage VR1 and the reference voltage VR2 to the sampling and amplifying circuit 130p and the sampling and amplifying circuit 130n respectively. The preset voltage Vx may be Vcm+Vz, the preset voltage Vy may be Vcm-Vz, and Vz is a DC voltage.

[0005] The sampling and amplifying circuit 130p and the sampling and amplifying circuit 130n each include two capacitors (including capacitor C1a or capacitor C1b) and six switches. The sampling and amplifying circuit 130p (sampling and amplifying circuit 130n) samples the input signal Vsp (input signal Vsn) in the sampling phase, and amplifies the signal component dV of the input signal Vsp (input signal Vsn) according to the reference voltage VR1 (reference voltage VR2) and the reference voltage Vref in the amplifying phase. The operation details of the MDAC 100 are well known to those skilled in the art with ordinary knowledge, so they are not repeated here.

[0006] See also Figure 2 , Figure 2 The circuit diagram of the conventional multiplication digital-to-analog converter is shown in FIG. 200 , which is a 2.5-bit multiplication digital-to-analog converter, and includes an ADC 210 , a selection circuit 220 , a sampling and amplification circuit 230 p , a sampling and amplification circuit 230 n , and an operational amplifier 240 .

[0007] The sampling and amplification circuit 230p includes 4 capacitors (including capacitor C1a, capacitor C2a and capacitor C3a) and 10 switches. The sampling and amplification circuit 230n is the differential counterpart of the sampling and amplification circuit 230p, and also includes 4 capacitors and 10 switches (not shown). In the amplification phase, the capacitor C1a, the capacitor C2a and the capacitor C3a each receive one of the preset voltage Vx, the preset voltage Vy and the common mode voltage Vcm. The operation details of the MDAC 200 are well known to those skilled in the art, so they are not repeated here.

[0008] Since the feedback factors of MDAC 100 and MDAC 200 are not large enough (0.5 and 0.25 respectively), the area and power consumption of operational amplifier 140 and operational amplifier 240 are considerable, making the circuits uncompetitive.

[0009] Furthermore, since the capacitance values ​​of the capacitors of the sampling and amplifying circuit 130p, the sampling and amplifying circuit 130n, the sampling and amplifying circuit 230p, and the sampling and amplifying circuit 230n are generally large, these capacitors are less likely to be driven by the reference voltage VR1, the reference voltage VR2, the preset voltage Vx, the preset voltage Vy, or the common mode voltage Vcm. However, if the driving capability of the reference voltage VR1 and the reference voltage VR2 is increased to drive these capacitors, the overall power consumption of the MDAC 100 and the MDAC 200 will increase. Summary of the invention

[0010] In view of the deficiencies of the prior art, an object of the present invention is to provide a multiplying digital-to-analog converter to improve the deficiencies of the prior art.

[0011] An embodiment of the present invention provides a multiplication digital analog converter. The multiplication digital analog converter has a first input terminal, a second input terminal, a first output terminal and a second output terminal. The first input terminal and the second input terminal receive a first input signal and a second input signal respectively. The first input signal is a common mode voltage minus a signal component, and the second input signal is the common mode voltage plus the signal component. The multiplication digital analog converter includes: an analog-to-digital converter, a selection circuit, an operational amplifier, a first switch capacitor circuit, a second switch capacitor circuit, a first switch, a second switch, a first load capacitor and a second load capacitor. The analog-to-digital converter is used to generate a selection signal according to the first input signal and the second input signal. The selection circuit is coupled to the analog-to-digital converter to generate a first reference voltage and a second reference voltage according to the selection signal. The operational amplifier has an input port and an output port. The first switch capacitor circuit is coupled to the first input terminal, the second input terminal, the input port and the output port to amplify the signal component. The second switch capacitor circuit is coupled to the first input terminal, the second input terminal, the input port and the output port to amplify the signal component. The first switch is coupled to the first output terminal and receives the second reference voltage. The second switch is coupled to the second output terminal and receives the first reference voltage. The first load capacitor is coupled to the output port and receives the second reference voltage through the first switch. The second load capacitor is coupled to the output port and receives the first reference voltage through the second switch.

[0012] The technical means embodied in the embodiments of the present invention can improve at least one of the disadvantages of the prior art. Therefore, the present invention can effectively reduce the circuit area and power consumption compared with the prior art.

[0013] The features, practices and effects of the present invention are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a circuit diagram of an existing multiplication digital-to-analog converter;

[0015] Figure 2 is a circuit diagram of an existing multiplication digital-to-analog converter;

[0016] Figure 3 is a circuit diagram of an embodiment of a multiplying digital-to-analog converter of the present invention;

[0017] Figure 4 It is a waveform diagram of the clock of the present invention;

[0018] Figure 5is a schematic diagram of the configuration of the reference voltage;

[0019] Figure 6 is a circuit diagram of another embodiment of a multiplying digital-to-analog converter of the present invention; and

[0020] Figure 7A to Figure 7B is a schematic diagram of the configuration of the reference voltage. DETAILED DESCRIPTION

[0021] The technical terms used in the following descriptions refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification.

[0022] The disclosure of the present invention includes a multiplying digital-to-analog converter. Since some components of the multiplying digital-to-analog converter of the present invention may be known components individually, the following description will omit the details of the known components without affecting the full disclosure and feasibility of the device invention.

[0023] In the following description, a signal at a high level represents active, and at a low level represents inactive, and enabling / disabling a signal represents pulling up / lowering the level of the signal. However, this is only an implementation or illustrative example and is not intended to limit the present invention. In other words, in different implementations, a signal at a high level may represent inactive, and at a low level may represent active, and enabling / disabling a signal represents pulling down / higher the level of the signal. Level conversion or logic level conversion represents a signal changing from enabled (active) to disabled (inactive), or vice versa.

[0024] See also Figure 3 , Figure 3 3 is a circuit diagram of an embodiment of a multiplication digital-to-analog converter of the present invention. MDAC 300 has an input terminal Vin1 and an input terminal Vin2, and includes an ADC 310, a selection circuit 320, an operational amplifier 330, a load capacitor CLp, a load capacitor CLn, a switch capacitor circuit 340p, a switch capacitor circuit 340n, a switch Ss4p, and a switch Ss4n. The switch capacitor circuit 340p couples or electrically connects the input terminal Vin1 and the input terminal Vin2, and includes a capacitor C1p, a switch Ss0p, a switch Ss1p, a switch Ss2p, and a switch Ss3p. The switch capacitor circuit 340n couples or electrically connects the input terminal Vin1 and the input terminal Vin2, and includes a capacitor C1n, a switch Ss0n, a switch Ss1n, a switch Ss2n, and a switch Ss3n.

[0025] The input terminal Vin1 and the input terminal Vin2 receive the input signal Vsn and the input signal Vsp respectively. The input signal Vsp (=Vdc+dV) and the input signal Vsn (=Vdc-dV) can be a differential signal pair, wherein Vdc is the common mode voltage of the two and dV is the signal component. The switched capacitor circuit 340p and the switched capacitor circuit 340n are used to amplify the signal component dV.

[0026] Both ends of the capacitor C1p (capacitor C1n) are a node N1p (node ​​N1n) and a node N2p (node ​​N2n), respectively.

[0027] The operational amplifier 330 has an input port 332 and an output port 334. The input port 332 includes an input node Vp0 and an input node Vn0, which are respectively an inverting input terminal and a non-inverting input terminal of the operational amplifier 330. The output port 334 includes an output node Vp1 and an output node Vn1, which are respectively a non-inverting output terminal and an inverting output terminal of the operational amplifier 330. The signal (e.g., voltage) on the output node Vp1 (output node Vn1) is coupled or output to the output terminal Vp2 (output terminal Vn2) through the load capacitor CLp (load capacitor CLn). In some embodiments, the output terminal Vp2 and the output terminal Vn2 can be the input terminals of the lower circuit.

[0028] The switched capacitor circuit 340p is also coupled or electrically connected to the input port 332 (more specifically, the input node Vp0) and the output port 334 (more specifically, the output node Vp1). The switched capacitor circuit 340n is also coupled or electrically connected to the input port 332 (more specifically, the input node Vn0) and the output port 334 (more specifically, the output node Vn1).

[0029] Both ends of the load capacitor CLp (load capacitor CLn) are the output port 334 (more specifically, the output node Vp1 (output node Vn1)) and the output terminal Vp2 (output terminal Vn2), respectively.

[0030] One end of the switch Ss0p (switch Ss0n) is coupled or electrically connected to the input terminal Vin1 (input terminal Vin2) (ie, receives the input signal Vsn (input signal Vsp)); the other end of the switch Ss0p (switch Ss0n) is coupled or electrically connected to the node N1p (node ​​N1n).

[0031] One end of the switch Ss1p (switch Ss1n) is coupled or electrically connected to the input end Vin2 (input end Vin1); the other end of the switch Ss1p (switch Ss1n) is coupled or electrically connected to the node N2p (node ​​N2n).

[0032] One end of the switch Ss2p (switch Ss2n) is coupled or electrically connected to the node N1p (node ​​N1n); the other end of the switch Ss2p (switch Ss2n) is coupled or electrically connected to the input port 332 (more specifically, the input node Vp0 (input node Vn0)).

[0033] One end of the switch Ss3p (switch Ss3n) is coupled or electrically connected to the node N2p (node ​​N2n); the other end of the switch Ss3p (switch Ss3n) is coupled or electrically connected to the output port 334 (more specifically, the output node Vp1 (output node Vn1)).

[0034] One end of the switch Ss4p (switch Ss4n) is coupled or electrically connected to the output terminal Vp2 (output terminal Vn2); the other end of the switch Ss4p (switch Ss4n) receives the reference voltage VR2 (reference voltage VR1) (ie, coupled or electrically connected to the selection circuit 320).

[0035] When the MDAC 300 is applied to a pipelined analog-to-digital converter, the ADC 310 serves as a sub-analog-to-digital converter of the pipelined analog-to-digital converter. The ADC 310 is coupled or electrically connected to the input terminal Vin1 and the input terminal Vin2 to generate a selection signal SEL according to the input signal Vsp and the input signal Vsn.

[0036] The selection circuit 320 is coupled or electrically connected to the ADC 310. The functions of the ADC 310 and the selection circuit 320 are similar or substantially the same as those of the ADC 110 and the selection circuit 120, respectively, and thus will not be described in detail.

[0037] See also Figure 4 , Figure 4 The clock CLK1, the clock CLK2 and the clock CLK3 are not at the first level (eg, high level) at the same time.

[0038] When the clock CLK1 is at the first level (second level), the switches Ss0p, Ss0n, Ss1p, and Ss1n are turned on (not turned on). When the clock CLK3 is at the first level (second level), the switches Ss2p, Ss2n, Ss3p, Ss3n, Ss4p, and Ss4n are turned on (not turned on).

[0039] During phase Φ1 (i.e., when clock CLK1 is at a first level, and clocks CLK2 and CLK3 are at a second level (e.g., a low level)), switches Ss0p, Ss0n, Ss1p, and Ss1n are turned on, and switches Ss2p, Ss2n, Ss3p, Ss3n, Ss4p, and Ss4n are not turned on, so that capacitors C1p and C1n sample input signals Vsn and Vsp. When phase Φ1 ends, the voltage Vxp across capacitor C1p and the voltage Vxn across capacitor C1n are 2dV and -2dV, respectively (in other words, |Vxp|=|Vxn|=2dV).

[0040] During the phase Φb (ie, when the clock CLK2 is at the first level, and the clocks CLK1 and CLK3 are at the second level), the ADC 310 generates the selection signal SEL, and the selection circuit 320 generates the reference voltages VR1 and VR2 according to the selection signal SEL.

[0041] During phase Φ2 (i.e., when clock CLK3 is at the first level, and clocks CLK1 and CLK2 are at the second level), switches Ss0p, Ss0n, Ss1p, and Ss1n are not conducting, and switches Ss2p, Ss2n, Ss3p, Ss3n, Ss4p, and Ss4n are conducting, so that the voltage Vxp across capacitor C1p and the voltage Vxn across capacitor C1n are applied to the output port 334 of the operational amplifier 330 (more specifically, the output node Vp1 and the output node Vn1), and the reference voltage VR2 and the reference voltage VR1 are applied to the output terminal Vp2 and the output terminal Vn2, respectively.

[0042] Note that the length of phase Φ1 may or may not be equal to the length of phase Φ2.

[0043] A person skilled in the art with ordinary knowledge can know from the above description that the effect achieved by MDAC 300 is equivalent to that achieved by MDAC 100, so MDAC 300 is also a 1.5-bit MDAC. Because the feedback factor (1) of MDAC 300 is twice the feedback factor (0.5) of MDAC 100, the area and power consumption of operational amplifier 330 can be effectively reduced. The above advantages can greatly enhance the competitiveness of MDAC 300.

[0044] Also, see Figure 1 and Figure 3MDAC 100 uses four capacitors to sample input signals Vsn and Vsp, while MDAC 300 uses only two capacitors (capacitor C1p and capacitor C1n) to sample input signals Vsn and Vsp. That is, the MDAC of the present invention uses fewer sampling capacitors, which can reduce circuit area and / or cost.

[0045] See also Figure 5 , Figure 5 is a schematic diagram of the configuration of the reference voltage VR1 and the reference voltage VR2. The configuration of the reference voltage VR1 and the reference voltage VR2 of the MDAC 300 is the same as that of the MDAC 100. However, it should be noted that in the MDAC 100, the reference voltage VR1 and the reference voltage VR2 are applied to the inverting input terminal and the non-inverting input terminal of the operational amplifier 140, respectively, while in the MDAC 300, the reference voltage VR1 and the reference voltage VR2 are applied to the inverting output terminal and the non-inverting output terminal of the operational amplifier 330, respectively.

[0046] See also Figure 6 , Figure 6 6 is a circuit diagram of another embodiment of the multiplication digital-to-analog converter of the present invention. MDAC 600 is a 2.5-bit MDAC. Compared with MDAC 300, MDAC 600 further includes a switched capacitor circuit 640p and a switched capacitor circuit 640n, and ADC 310 and selection circuit 320 are replaced by ADC 610 and selection circuit 620, respectively.

[0047] ADC 610 functions and Figure 2 The selection circuit 620 is similar to the ADC 210, so it will not be repeated. The selection circuit 620 is coupled or electrically connected to the ADC 610, and determines the reference voltage VR1, the reference voltage VR2, the reference voltage VR3 and the reference voltage VR4 from a plurality of preset voltages (including but not limited to the preset voltage Vx, the preset voltage Vy, the common mode voltage Vcm, 2 times Vx (2Vx) and 2 times Vy (2Vy)) according to the selection signal SEL, and provides the reference voltage VR1, the reference voltage VR2, the reference voltage VR3 and the reference voltage VR4 to the load capacitor CLn, the load capacitor CLp, the capacitor C2n and the capacitor C2p respectively. The design of the selection circuit 620 will be coordinated with the following Fig. 7A and Figure 7B Describe in detail.

[0048] The switched capacitor circuit 640p (switched capacitor circuit 640n) includes a capacitor C2p (capacitor C2n), a switch Ss5p (switch Ss5n), a switch Ss6p (switch Ss6n), a switch Ss7p (switch Ss7n), and a switch Ss8p (switch Ss8n).

[0049] Both ends of the capacitor C2p (capacitor C2n) are a node N3p (node ​​N3n) and a node N4p (node ​​N4n), respectively.

[0050] One end of the switch Ss5p (switch Ss5n) is coupled or electrically connected to the input end Vin2 (input end Vin1); the other end of the switch Ss5p (switch Ss5n) is coupled or electrically connected to the node N3p (node ​​N3n).

[0051] One end of the switch Ss6p (switch Ss6n) is coupled or electrically connected to the input end Vin1 (input end Vin2); the other end of the switch Ss6p (switch Ss6n) is coupled or electrically connected to the node N4p (node ​​N4n).

[0052] One end of the switch Ss7p (switch Ss7n) is coupled or electrically connected to the node N3p (node ​​N3n); the other end of the switch Ss7p (switch Ss7n) receives the reference voltage VR4 (reference voltage VR3) (ie, coupled or electrically connected to the selection circuit 620).

[0053] One end of the switch Ss8p (switch Ss8n) is coupled or electrically connected to the node N4p (node ​​N4n); the other end of the switch Ss8p (switch Ss8n) is coupled or electrically connected to the input port 332 (more specifically, the input node Vp0 (input node Vn0)).

[0054] Please also see Figure 4 and Figure 6 When the clock CLK1 is at the first level (second level), the switches Ss5p, Ss5n, Ss6p and Ss6n are turned on (not turned on). When the clock CLK3 is at the first level (second level), the switches Ss7p, Ss7n, Ss8p and Ss8n are turned on (not turned on).

[0055] During phase Φ1, switches Ss5p, Ss5n, Ss6p, and Ss6n are turned on, and switches Ss7p, Ss7n, Ss8p, and Ss8n are turned off, so that capacitor C2p and capacitor C2n sample input signals Vsp and Vsn. Similarly, when phase Φ1 ends, the absolute value of the voltage Vyp across capacitor C2p and the absolute value of the voltage Vyn across capacitor C2n are both 2dV (in other words, |Vyp|=|Vyn|=2dV).

[0056] During the phase Φb, the ADC 610 generates a selection signal SEL, and the selection circuit 620 generates reference voltages VR1 , VR2 , VR3 , and VR4 according to the selection signal SEL.

[0057] During phase Φ2, switch Ss5p, switch Ss5n, switch Ss6p and switch Ss6n are not conducting, and switch Ss7p, switch Ss7n, switch Ss8p and switch Ss8n are conducting, so that capacitor C1p is connected in series with capacitor C2p and capacitor C1n is connected in series with capacitor C2n, so that the voltage across capacitor C1p and capacitor C2p (each is 2dV, a total of 4dV) and the voltage across capacitor C1n and capacitor C2n (each is -2dV, a total of -4dV) are applied to the output port 334 of the operational amplifier 330 (more specifically, the output node Vp1 and the output node Vn1).

[0058] See also Fig. 7A and Figure 7B , Fig. 7A yes Figure 2 configuration of the reference voltage of the MDAC 200 (please note that the capacitor C1b, the capacitor C2b and the capacitor C3b are included in the sampling and amplification circuit 230n), Figure 7B yes Figure 6 Configuration of the reference voltage of the MDAC 600. Fig. 7A Configurations 1 to 7 correspond to Figure 7B Therefore, a person skilled in the art with ordinary knowledge can Fig. 7A and Figure 7B Design selection circuit 620. For example, in case of configuration 4, Figure 2 The capacitors C1a-C3a and C1b-C3b receive voltages Vx, Vx, Vcm, Vy, Vy and Vcm respectively; if Figure 6 The reference voltages VR1 to VR4 are set to Vy, Vx, Vy and Vx respectively. Figure 6 The MDAC600 is equivalent to the MDAC 200.

[0059] A person skilled in the art with ordinary knowledge can know from the above description that the effect achieved by MDAC 600 is equivalent to the effect achieved by MDAC 200. Since the feedback factor (0.5) of MDAC 600 is twice the feedback factor (0.25) of MDAC 200, the area and power consumption of operational amplifier 330 can be effectively reduced. The above advantages can greatly enhance the competitiveness of MDAC 600.

[0060] Also, see Figure 2 and Figure 6MDAC 200 uses 8 capacitors to sample input signal Vsn and input signal Vsp (4 capacitors in sampling and amplifying circuit 230p, and the other 4 in sampling and amplifying circuit 230n), while MDAC 600 uses only 4 capacitors (capacitor C1p, capacitor C1n, capacitor C2p, and capacitor C2n) to sample input signal Vsn and input signal Vsp. That is, the MDAC of the present invention uses fewer sampling capacitors, which can reduce circuit area and / or cost.

[0061] Although the above embodiments take 1.5-bit and 2.5-bit multiplication digital-to-analog converters as examples, this is not a limitation of the present invention. Persons skilled in the art can appropriately apply the present invention to multiplication digital-to-analog converters with more bits (the number of preset voltages will increase accordingly) based on the disclosure of the present invention.

[0062] Please note that in the above-mentioned figures, the shapes, sizes and proportions of the components are merely for illustration purposes, and are provided for those skilled in the art with ordinary knowledge to understand the present invention, and are not intended to limit the present invention.

[0063] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. A person skilled in the art with ordinary knowledge may make changes to the technical features of the present invention based on the explicit or implicit contents of the present invention. All these changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to that defined in the claims of the present invention.

[0064] [Explanation of symbols]

[0065] 100, 200, 300, 600: MDAC (Multiplying Digital-to-Analog Converter)

[0066] 110, 210, 310, 610: ADC (analog-to-digital converter)

[0067] 120, 220, 320, 620: Select circuit

[0068] 130n, 130p, 230n, 230p: Sampling and amplification circuits

[0069] 140, 240, 330: Operational amplifiers

[0070] C1a, C1b, C2a, C3a, C1n, C1p, C2n, C2p, C2b, C3b: capacitors

[0071] SEL: Select signal

[0072] Vcm: common mode voltage

[0073] Vinn, Vinp, Vin1, Vin2: input terminals

[0074] Vn2, Vp2: output end

[0075] VR1, VR2, Vref, VR3, VR4: reference voltage

[0076] Vsn, Vsp: input signal

[0077] Vx, Vy: preset voltage

[0078] 332: Input port

[0079] 334: Output port

[0080] 340n, 340p, 640n, 640p: Switched capacitor circuits

[0081] CLn, CLp: Load capacitors

[0082] N1n, N1p, N2n, N2p, N3n, N3p, N4n, N4p: Node

[0083] Ss0n, Ss0p, Ss1n, Ss1p, Ss2n, Ss2p, Ss3n, Ss3p, Ss4n, Ss4p, Ss5n, Ss5p, Ss6n, Ss6p, Ss7n, Ss7p, Ss8n, Ss8p: Switch

[0084] Vn0, Vp0: input nodes

[0085] Vn1, Vp1: output nodes

[0086] Vxn, Vxp, Vyn, Vyp: cross voltage

[0087] Φ1, Φ2, Φb: Phase

[0088] CLK1, CLK2, CLK3: Clock

Claims

1. A multiplicative digital-to-analog converter having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal and the second input terminal receive a first input signal and a second input signal respectively, the first input signal being a common-mode voltage minus a signal component, and the second input signal being the common-mode voltage plus the signal component, the multiplicative digital-to-analog converter comprises: an analog-to-digital converter for generating a selection signal according to the first input signal and the second input signal; a selection circuit coupled to the analog-to-digital converter for generating a first reference voltage and a second reference voltage according to the selection signal; an operational amplifier having an input port and an output port; a first switched-capacitor circuit coupled to the first input terminal, the second input terminal, the input port, and the output port for amplifying the signal component; a second switched-capacitor circuit coupled to the first input terminal, the second input terminal, the input port, and the output port for amplifying the signal component; a first switch coupled to the first output terminal and receiving the second reference voltage; a second switch coupled to the second output terminal and receiving the first reference voltage; a first load capacitor coupled to the output port and receiving the second reference voltage through the first switch; and a second load capacitor coupled to the output port and receiving the first reference voltage through the second switch.

2. The multiplicative digital-to-analog converter according to claim 1, wherein the first switched-capacitor circuit includes a first capacitor, a third switch, a fourth switch, a fifth switch, and a sixth switch, the second switched-capacitor circuit includes a second capacitor, a seventh switch, an eighth switch, a ninth switch, and a tenth switch, the first capacitor has a first end and a second end, the second capacitor has a third end and a fourth end, the third switch is coupled between the first input terminal and the first end, the fourth switch is coupled between the second end and the second input terminal, the fifth switch is coupled between the first end and the input port, the sixth switch is coupled between the second end and the output port, the seventh switch is coupled between the second input terminal and the third end, the eighth switch is coupled between the fourth end and the first input terminal, the ninth switch is coupled between the third end and the input port, and the tenth switch is coupled between the fourth end and the output port.

3. The multiplicative digital-to-analog converter according to claim 2, wherein the multiplicative digital-to-analog converter operates according to a first clock, a second clock, and a third clock. When the first clock is at a first level and the second clock and the third clock are at a second level, the third switch, the seventh switch, the fourth switch, and the eighth switch are turned on, and the fifth switch, the ninth switch, the sixth switch, the tenth switch, the first switch, and the second switch are not turned on; when the third clock is at the first level and the first clock and the second clock are at the second level, the third switch, the seventh switch, the fourth switch, and the eighth switch are not turned on, and the fifth switch, the ninth switch, the sixth switch, the tenth switch, the first switch, and the second switch are turned on.

4. The multiplication digital-to-analog converter as claimed in claim 2, wherein, the input port includes an inverting input terminal and a non-inverting input terminal, the output port includes a non-inverting output terminal and an inverting output terminal, the first load capacitor is coupled between the non-inverting output terminal and the first output terminal, the second load capacitor is coupled between the inverting output terminal and the second output terminal, the fifth switch is coupled between the first terminal and the inverting input terminal, the ninth switch is coupled between the third terminal and the non-inverting input terminal, the sixth switch is coupled between the second terminal and the non-inverting output terminal, and the tenth switch is coupled between the fourth terminal and the inverting output terminal.

5. The multiplication digital-to-analog converter as claimed in claim 2, wherein, the first capacitor and the second capacitor are used to sample the first input signal and the second input signal. After the sampling is completed, the absolute value of the first voltage across the first capacitor is twice the signal component, and the absolute value of the second voltage across the second capacitor is twice the signal component.

6. The multiplication digital-to-analog converter as claimed in claim 5, further comprising: a third switched-capacitor circuit including a third capacitor, wherein the third capacitor is coupled to the first input terminal and the second input terminal for sampling the first input signal and the second input signal; and a fourth switched-capacitor circuit including a fourth capacitor, wherein the fourth capacitor is coupled to the first input terminal and the second input terminal for sampling the first input signal and the second input signal.

7. The multiplication digital-to-analog converter as claimed in claim 6, wherein, after the sampling is completed, the absolute value of the third voltage across the third capacitor is twice the signal component, and the absolute value of the fourth voltage across the fourth capacitor is twice the signal component.

8. The multiplication digital-to-analog converter as claimed in claim 2, wherein, the selection circuit further generates a third reference voltage and a fourth reference voltage according to the selection signal, and the multiplication digital-to-analog converter further includes: a third capacitor having a fifth terminal and a sixth terminal; a fourth capacitor having a seventh terminal and an eighth terminal; an eleventh switch coupled between the second input terminal and the fifth terminal; a twelfth switch coupled between the first input terminal and the seventh terminal; a thirteenth switch coupled between the first input terminal and the sixth terminal; a fourteenth switch coupled between the second input terminal and the eighth terminal; a fifteenth switch coupled to the fifth terminal and receiving the fourth reference voltage; a sixteenth switch coupled to the seventh terminal and receiving the third reference voltage; a seventeenth switch coupled between the sixth terminal and the input port; and an eighteenth switch coupled between the eighth terminal and the input port.

9. The multiplication digital-to-analog converter as claimed in claim 8, wherein, The multiplication digital-to-analog converter operates according to a first clock, a second clock, and a third clock. When the first clock is at a first level and the second clock and the third clock are at a second level, the third switch, the seventh switch, the fourth switch, the eighth switch, the eleventh switch, the twelfth switch, the thirteenth switch, and the fourteenth switch are turned on, and the fifth switch, the ninth switch, the sixth switch, the tenth switch, the first switch, the second switch, the fifteenth switch, the sixteenth switch, the seventeenth switch, and the eighteenth switch are not turned on; when the third clock is at the first level and the first clock and the second clock are at the second level, the third switch, the seventh switch, the fourth switch, the eighth switch, the eleventh switch, the twelfth switch, the thirteenth switch, and the fourteenth switch are not turned on, and the fifth switch, the ninth switch, the sixth switch, the tenth switch, the first switch, the second switch, the fifteenth switch, the sixteenth switch, the seventeenth switch, and the eighteenth switch are turned on.

10. The multiplication digital-to-analog converter according to claim 8, wherein, the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are used to sample the first input signal and the second input signal. After the sampling is completed, the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor respectively have a first cross voltage, a second cross voltage, a third cross voltage, and a fourth cross voltage. The absolute values of the first cross voltage, the second cross voltage, the third cross voltage, and the fourth cross voltage are twice the signal component.

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