Semiconductor memory device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor memory device and a manufacturing method thereof. The device comprises a substrate; the stacking structures are located on the substrate and are isolated from one another in the vertical direction, each stacking structure comprises a semiconductor layer, and each semiconductor layer comprises a first doped region, a channel region and a second doped region; the bit line extends along the horizontal direction and is connected with the first doped region; the capacitor structure comprises a lower electrode and an upper electrode which are stacked, and the lower electrode is connected with the second doped region; and a support layer disposed around the lower electrode and directly contacting a sidewall, an upper surface, and a lower surface of the lower electrode. The device is used for achieving the effect of reducing bending of the capacitor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular, to a semiconductor memory device and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor technology, semiconductor memory devices are widely used in various electronic devices. A semiconductor memory device includes a word line (abbreviated as WL), a bit line (abbreviated as BL), a transistor, and a capacitor structure. The gate of the transistor is connected to the word line, the drain of the transistor is connected to the bit line, and the source of the transistor is connected to the capacitor structure. The opening or closing of the transistor is controlled by the word line, and data is read and written in the capacitor structure through the bit line.

[0003] With the continuous improvement of the integration degree of semiconductor memory devices, semiconductor memory devices are developing towards a three-dimensional structure with a horizontally placed capacitor structure. However, the capacitor structure is prone to bending, which affects the performance of the semiconductor memory device. Summary of the Invention

[0004] Embodiments of this application provide a semiconductor memory device and a manufacturing method thereof to reduce the bending of the capacitor structure and improve the performance of the semiconductor memory device.

[0005] In a first aspect, embodiments of this application provide a semiconductor memory device, including: a substrate; a plurality of stacked structures located on the substrate and isolated from each other in the vertical direction, the stacked structure including a semiconductor layer, the semiconductor layer including a first doped region, a channel region, and a second doped region; a bit line extending in the horizontal direction and connected to the first doped region; a capacitor structure including a lower electrode and an upper electrode stacked, the lower electrode being connected to the second doped region; a support layer surrounding the lower electrode and directly contacting the side wall, the upper surface, and the lower surface of the lower electrode.

[0006] In some possible implementation manners, the lower electrode includes a first side wall and a second side wall arranged opposite to each other, the first side wall directly contacting the support layer, and the second side wall directly contacting the second doped region.

[0007] In some possible implementation manners, the orthographic projections of the upper electrode and the lower electrode on the support layer are both located within the contour of the corresponding surface of the support layer.

[0008] In some possible implementation manners, a word line is further included, the word line extending in the vertical direction and adjacent to the channel region.

[0009] In some possible embodiments, an insulating layer and a dielectric layer are further included. The insulating layer is disposed between adjacent semiconductor layers. The dielectric layer is disposed between the lower electrode and the upper electrode, and between the support layer and the upper electrode. The dielectric layer covers a partial surface of the lower electrode.

[0010] The semiconductor memory device in the embodiment of the present application includes a substrate, a plurality of stacked structures, bit lines, a capacitive structure, and a support layer. The plurality of stacked structures are located on the substrate and are isolated from each other in the vertical direction. The stacked structure includes a semiconductor layer, and the semiconductor layer includes a first doped region, a channel region, and a second doped region. The bit lines extend in the horizontal direction and are connected to the first doped region. The capacitive structure includes a lower electrode and an upper electrode stacked on each other, and the lower electrode is connected to the second doped region. The support layer is disposed around the lower electrode and directly contacts the side wall, the upper surface, and the lower surface of the lower electrode. By using the support layer to directly contact the lower electrode to support one end of the lower electrode away from the semiconductor layer, bending of the lower electrode can be avoided, and bridging between the lower electrodes can be avoided, ensuring the performance of the semiconductor memory device.

[0011] In a second aspect, an embodiment of the present application provides a semiconductor memory device, including: a substrate; a plurality of stacked structures located on the substrate and isolated from each other in the vertical direction, the stacked structure including a semiconductor layer, the semiconductor layer including a first doped region, a channel region, and a second doped region; bit lines extending in the horizontal direction and connected to the first doped region; a capacitive structure including a lower electrode and an upper electrode stacked on each other, the lower electrode being connected to the second doped region; an insulating layer located between adjacent capacitive structures; and a support layer located between the insulating layers and directly contacting the side wall, the upper surface, and the lower surface of the insulating layer.

[0012] In some possible embodiments, the lower electrode includes a first side wall and a second side wall disposed opposite to each other. The first side wall directly contacts the support layer, and the second side wall directly contacts the second doped region.

[0013] In some possible embodiments, the orthographic projections of the upper electrode and the lower electrode on the support layer are both located within the contour of the corresponding surface of the support layer.

[0014] In some possible embodiments, a word line is further included. The word line extends in the vertical direction and is adjacent to the channel region.

[0015] In some possible embodiments, the bit lines and the support layer are respectively located on opposite sides of the semiconductor layer.

[0016] In some possible embodiments, the insulating layer is also disposed between adjacent semiconductor layers; the semiconductor memory device further includes a dielectric layer disposed between the lower electrode and the upper electrode, and the lower electrode covers a partial surface of the insulating layer.

[0017] The semiconductor memory device in the embodiment of the present application includes a substrate, a plurality of stacked structures, bit lines, capacitive structures, an insulating layer, and a support layer. The plurality of stacked structures are located on the substrate and are isolated from each other in the vertical direction. The stacked structure includes a semiconductor layer, and the semiconductor layer includes a first doped region, a channel region, and a second doped region. The bit lines extend in the horizontal direction and are connected to the first doped region. The capacitive structure includes a lower electrode and an upper electrode stacked, and the lower electrode is connected to the second doped region. The insulating layer is located between adjacent capacitive structures, and the support layer is located between the insulating layers and directly contacts the sidewalls, upper surface, and lower surface of the insulating layer. In this way, one end of the insulating layer extends into the support layer, and the support layer provides support for the insulating layer, which can maintain the stability of the insulating layer, avoid bending of the insulating layer, and thus ensure that the capacitive structure formed subsequently on the insulating layer is bent and bridged, ensuring the performance of the semiconductor memory device.

[0018] In a third aspect, an embodiment of the present application provides a method for manufacturing a semiconductor memory device, including: providing a substrate; forming a plurality of stacked structures, bit lines, capacitive structures, and a support layer; wherein, the plurality of stacked structures are located on the substrate and are isolated from each other in the vertical direction, the stacked structure includes a semiconductor layer, the semiconductor layer includes a first doped region, a channel region, and a second doped region; the bit lines extend in the horizontal direction and are connected to the first doped region; the capacitive structure includes a lower electrode and an upper electrode stacked, and the lower electrode is connected to the second doped region; the support layer is in contact with the sidewall of the capacitive structure.

[0019] In some possible embodiments, the support layer surrounds the lower electrode and directly contacts the sidewalls, upper surface, and lower surface of the lower electrode.

[0020] In some possible embodiments, it further includes: forming an insulating layer located between adjacent capacitive structures, and the support layer is located between the insulating layers and directly contacts the sidewalls, upper surface, and lower surface of the insulating layer.

[0021] In some possible embodiments, the lower electrode covers a partial surface of the insulating layer.

[0022] In some possible embodiments, the insulating layer is also disposed between adjacent semiconductor layers.

[0023] In some possible embodiments, the dielectric layer is disposed between the lower electrode and the upper electrode, and between the support layer and the upper electrode, and the dielectric layer covers a partial surface of the lower electrode.

[0024] The method for manufacturing a semiconductor memory device provided by an embodiment of the present application includes: providing a substrate, and forming a plurality of stacked structures, bit lines, capacitor structures, and a support layer; wherein, the plurality of stacked structures are located on the substrate and are isolated from each other in the vertical direction, and the stacked structure includes a semiconductor layer, and the semiconductor layer includes a first doped region, a channel region, and a second doped region; the bit lines extend in the horizontal direction and are connected to the first doped region; the capacitor structure includes a lower electrode and an upper electrode stacked, and the lower electrode is connected to the second doped region; the support layer is in contact with the side wall of the capacitor structure. The support layer can support during the formation of the capacitor structure, avoid bending of the capacitor structure, and improve the performance of the formed semiconductor memory device. Description of the Drawings

[0025] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0026] Figure 1 It is a schematic diagram of a semiconductor memory device provided by the present application;

[0027] Figure 2 is Figure 1 a schematic diagram after the isolation layer in is hidden;

[0028] Figure 3 It is a schematic diagram after forming the support layer provided by the present application;

[0029] Figure 4 It is a schematic diagram after removing a part of the insulating layer provided by the present application;

[0030] Figure 5 is Figure 4 a schematic diagram after the isolation layer in is shown;

[0031] Figure 6 It is a schematic diagram after forming the upper electrode provided by the present application;

[0032] Figure 7 It is a top view of a semiconductor memory device provided by the present application;

[0033] Figure 8 It is a cross-sectional view of a semiconductor memory device provided by the present application;

[0034] Figure 9 It is another schematic diagram after forming the lower electrode provided by the present application;

[0035] Figure 10Another schematic diagram after forming the upper electrode provided by this application;

[0036] Figure 11 Another cross-sectional view of the semiconductor memory device provided by this application.

[0037] Description of reference numerals:

[0038] 10 - Substrate;

[0039] 20 - Semiconductor layer; 21 - First doped region; 22 - Channel region; 23 - Second doped region;

[0040] 30 - Bit line;

[0041] 40 - Capacitor structure; 41 - Lower electrode; 42 - Upper electrode; 43 - Dielectric layer; 44 - First sidewall; 45 - Second sidewall;

[0042] 50 - Insulating layer;

[0043] 60 - Support layer;

[0044] 71 - First word line; 72 - Second word line; 73 - Gate oxide layer;

[0045] 80 - Mask layer;

[0046] 90 - Isolation layer. Detailed implementation manners

[0047] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with this application. On the contrary, they are merely examples of devices and methods consistent with some aspects of this application as detailed in the appended claims.

[0048] For the semiconductor memory device provided by this application, by providing a support layer to directly support the lower electrode or to support the insulating layer directly used for depositing the lower electrode, the bending of the lower electrode can be reduced, thereby avoiding the bridging of the lower electrode and improving the performance of the semiconductor memory device.

[0049] The following uses specific embodiments to describe in detail the technical solution of this application and how the technical solution of this application solves the above technical problems. These several specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this application will be described below in conjunction with the drawings.

[0050] Refer to Figure 6 、 Figure 7 And Figure 8, embodiments of the present application provide a semiconductor memory device, which is, for example, a Dynamic Random Access Memory (DRAM). The semiconductor memory device includes a substrate 10, a plurality of stacked structures, bit lines 30, capacitor structures 40, and a support layer 60. Among them, the substrate 10 provides support for the structures thereon, such as providing support for the stacked structures, the support layer 60, etc. The substrate 10 is, for example, a silicon substrate, a silicon-containing (such as silicon-germanium) substrate, or a silicon-on-insulator (such as Silicon On Insulator, SOI) substrate, etc.

[0051] A plurality of stacked structures are located on the substrate 10 and are isolated from each other in the vertical direction. The plurality of stacked structures include a semiconductor layer 20, and the semiconductor layer 20 includes a first doped region 21, a channel region 22, and a second doped region 23. Among them, the plurality of stacked structures are arranged at intervals on the substrate 10, and the arrangement direction of the plurality of stacked structures is as Figure 6 shown by D3 in the figure. An isolation layer 90 is filled between at least adjacent stacked structures, and the isolation layer 90 is used to achieve isolation between the stacked structures.

[0052] Exemplarily, the isolation layer 90 is located on the substrate 10 (refer to Figure 8 ), and extends in the vertical direction to ensure that the stacked structures do not conduct with each other in the vertical direction. Among them, the top surface of the isolation layer 90 can be higher than or flush with the top surface of the stacked structure. The top surface refers to the surface away from the substrate 10, and the vertical direction refers to the direction perpendicular to the top surface of the substrate 10, as Figure 6 shown by D2 in the figure. The material of the isolation layer 90 includes insulating materials, such as silicon oxide, silicon nitride, silicon carbonitride, etc.

[0053] Each stacked structure includes at least one semiconductor layer 20, and these semiconductor layers 20 are arranged at intervals in the vertical direction. The semiconductor layer 20 in each stacked structure can be in contact with the substrate 10 or spaced apart from the substrate 10 (as Figure 8 shown). The material of the semiconductor layer 20 includes semiconductor materials, such as single crystal silicon, polycrystalline silicon, amorphous silicon, etc.

[0054] Each semiconductor layer 20 includes a first doped region 21, a channel region 22, and a second doped region 23 arranged in sequence, that is, the two sides of the channel region 22 are respectively connected to the first doped region 21 and the second doped region 23. Among them, the first doped region 21, the channel region 22, and the second doped region 23 are adjacent in sequence and parallel to the top surface of the substrate 10. The arrangement direction of the first doped region 21, the channel region 22, and the second doped region 23 is as Figure 6 and Figure 8 shown by the D1 direction in the figure, and this direction can also be regarded as the extension direction of the semiconductor layer 20.

[0055] The surfaces of the first doped region 21 and the channel region 22 facing each other may overlap, for example, completely coincide. The surfaces of the second doped region 23 and the channel region 22 facing each other may overlap, for example, completely coincide. Both the first doped region 21 and the second doped region 23 may be heavily doped regions, for example, doped by ion implantation. The first doped region 21 can be used as a drain region, which is connected to the bit line 30, and the second doped region 23 can be used as a source region, which is connected to the capacitor structure 40.

[0056] To achieve isolation between adjacent semiconductor layers 20 in the same stacked structure, the stacked structure further includes an insulating layer 50, which is disposed between adjacent semiconductor layers 20. The insulating layer 50 fills at least between adjacent semiconductor layers 20 and is in complete contact with the surfaces of adjacent semiconductor layers 20 facing each other to ensure the isolation effect between semiconductor layers 20. The material of the insulating layer 50 includes, for example, silicon oxide, silicon nitride, phosphosilicate glass, etc.

[0057] Continue to refer to Figure 7 and Figure 8 , the bit line 30 is disposed on the substrate 10 and extends in the horizontal direction, and the horizontal direction is parallel to the top surface of the substrate 10. The bit line 30 is electrically connected to the first doped region 21, that is, electrical conduction can be achieved between the bit line 30 and the first doped region 21. In some possible implementation manners, the height of the bit line 30 is adapted to that of the semiconductor layer 20. The top surface of the bit line 30 is higher than the bottom surface of the connected semiconductor layer 20 and lower than or flush with the top surface of the connected semiconductor layer 20; or, the bottom surface of the bit line 30 is higher than or flush with the bottom surface of the connected semiconductor layer 20 and lower than the top surface of the connected semiconductor layer 20. Specifically, the top surface of the bit line 30 is flush with the top surface of the connected semiconductor layer 20, and the bottom surface of the bit line 30 is flush with the bottom surface of the connected semiconductor layer 20, which is convenient for the manufacture of the bit line 30 and can also improve the transmission performance between the bit line 30 and the corresponding semiconductor layer 20.

[0058] In some possible examples, the extending direction of the bit line 30 is parallel to the arranging direction of multiple stacked structures. In this way, the bit line 30 can be connected to multiple semiconductor layers 20, and these semiconductor layers 20 are located in different stacked structures to simplify the structure of the semiconductor memory device, thereby facilitating the improvement of the storage density. Among them, the extending direction of the bit line 30 is as Figure 6The direction D3 shown in the figure. The bit line 30 can be a single-layer structure or a stacked structure. Exemplarily, the bit line 30 includes a first conductor layer, and the material of the first conductor layer includes a metal material, such as a low-resistance metal material including tungsten, aluminum, or copper. In the embodiments of the present application, the specific structure of the bit line 30 is not limited. There can be multiple bit lines 30, and the multiple bit lines 30 are arranged at intervals in the vertical direction to avoid connection between adjacent bit lines 30. The number of bit lines 30 can be the same as the number of semiconductor layers 20 in the stacked structure, so that each stacked structure can lead out each semiconductor layer 20 therein through multiple bit lines 30 respectively.

[0059] Continue to refer to Figures 6 to 8 , the capacitor structure 40 can store data, which includes a lower electrode 41 and an upper electrode 42 arranged in a stacked manner, and the lower electrode 41 and the upper electrode 42 are also spaced apart. Among them, the lower electrode 41 is connected to the second doped region 23. Exemplarily, the lower electrode 41 is located on the surface of the second doped region 23 facing away from the channel region 22, that is, the first doped region 21, the channel region 22, the second doped region 23, and the lower electrode 41 are arranged in sequence. The surfaces of the lower electrode 41 and the second doped region 23 that face each other are in contact, for example, completely coincide.

[0060] The material of the lower electrode 41 is, for example, the same as the material of the semiconductor layer 20, so that the lower electrode 41 and the semiconductor layer 20 form a whole, that is, the lower electrode 41 can be used as a part of the semiconductor layer 20, which is convenient for the synchronous fabrication of the lower electrode 41 and the semiconductor layer 20. The upper surface and the lower surface of the lower electrode 41 are arranged opposite to each other in the vertical direction, and one end of the lower electrode 41 away from the second doped region 23 is located in the support layer 60. Using the support layer to provide support for the capacitor structure 40 can prevent the capacitor structure 40 from collapsing and ensure the performance of the semiconductor memory device. Exemplarily, the lower electrode 41 includes a first side wall 44 and a second side wall 45 arranged opposite to each other, the first side wall 44 is in direct contact with the support layer 60, and the second side wall 45 is in direct contact with the second doped region 23.

[0061] The upper electrode 42 is located between adjacent lower electrodes 41. In the vertical direction, the upper electrode 42 is staggered from the semiconductor layer 20. The upper electrode 42 is located on the surface of the insulating layer 50 facing the support layer 60, and the upper electrode 42 also surrounds the outer peripheral surface of the lower electrode 41, that is, the upper electrode 42 is sleeved on the lower electrode 41 and is spaced from the lower electrode 41. The upper electrode 42 can be an integral structure, that is, a plurality of lower electrodes 41 share one upper electrode 42. The upper electrode 42 is formed, for example, by a deposition process to facilitate the fabrication of the upper electrode 42. The material of the upper electrode 42 can include a low-resistance metal material such as titanium nitride, aluminum, titanium, copper, or tungsten, a semiconductor material such as silicon germanium, or a combination of the above materials.

[0062] Continue to refer to Figures 6 to 8, the electrode structure further includes a dielectric layer 43. The dielectric layer 43 is disposed between the lower electrode 41 and the upper electrode 42, and between the support layer 60 and the upper electrode 42. The dielectric layer 43 covers a partial surface of the lower electrode 41. For example, the dielectric layer 43 covers a partial outer peripheral surface of the lower electrode 41 adjacent to one end of the second doped region 23. One end of the lower electrode 41 away from the second doped region 23 extends into the support layer 60, and this end is not covered by the dielectric layer 43. The dielectric layer 43 covers the upper electrode 42, for example, to isolate the upper electrode 42 from the lower electrode 41, and the upper electrode 42 from the support layer 60. The material of the dielectric layer 43 includes, for example, silicon oxide, zirconium oxide, aluminum oxide, etc.

[0063] The support layer 60 can extend in the vertical direction. The support layer 60 directly contacts the side wall, the upper surface, and the lower surface of the lower electrode 41. Among them, the upper surface and the lower surface of the lower electrode 41 are disposed opposite to each other in the vertical direction, and the side wall of the lower electrode 41 connects the upper surface and the lower surface of the lower electrode 41. The support layer 60 directly contacts the lower electrode 41 to support one end of the lower electrode 41 away from the semiconductor layer 20, which can prevent the lower electrode 41 from bending and avoid bridging between the lower electrodes 41, ensuring the performance of the semiconductor memory device. The material of the support layer 60 includes, for example, insulating materials with relatively high hardness such as silicon nitride and silicon carbonitride. Among them, the stacked structure can also be disposed oppositely on both sides of the support layer 60, that is, the stacked structure can also be arranged along Figure 8 the D1 direction shown. In this way, the support layer 60 can provide support to the stacked structures on both sides to improve the storage density of the semiconductor memory device.

[0064] In an example where the lower electrode 41 includes a first side wall 44 and a second side wall 45 disposed opposite to each other, the support layer 60 covers one end of the lower electrode 41 away from the second doped region 23, specifically covering the first side wall 44 of the lower electrode 41, and a partial upper surface and a partial lower surface of the lower electrode 41 adjacent to the first side wall 44. As Figure 8 shown, the support layer 60 also directly contacts the surface of the dielectric layer 43 away from the insulating layer 50. It can be understood that one end of the lower electrode 41 away from the second doped region 23 protrudes from one end of the dielectric layer 43 away from the insulating layer 50, so that the support layer 60 covers this end to support the lower electrode 41.

[0065] In some possible implementation manners, the orthographic projections of the upper electrode 42 and the lower electrode 41 on the support layer 60 are both located within the contour of the corresponding surface of the support layer 60. As Figure 7 and Figure 8As shown, the orthographic projection of the lower electrode 41 on the support layer 60 is located within the contour of the corresponding surface of the support layer 60, and the orthographic projections of the upper electrode 42 on the support layer 60 are all located within the contour of the corresponding surface of the support layer 60. In this way, in both the vertical and horizontal directions, the range of the support layer 60 is larger, so that the support layer 60 can support all the lower electrodes 41 and be in full contact with the first sidewall 44 of the lower electrode 41, which can improve the support effect. At the same time, the contact area between the support layer 60 and the dielectric layer 43 can also be increased, further improving the support effect of the support layer 60.

[0066] Continue to refer to Figures 6 to 8 , the semiconductor memory device further includes word lines that extend in the vertical direction and are adjacent to the channel region 22. Specifically, the word lines extend in a direction away from the top surface of the substrate 10. The word lines are adjacent to the channel region 22 and are also used to form gates to control the opening or closing of the channel region 22. The word lines can be opposite to the channel regions 22 of multiple semiconductor layers 20 in the same stacked structure to simultaneously control the opening or closing of multiple channel regions 22.

[0067] In some possible implementation manners, the word lines include a first word line 71 and a second word line 72; the first word line 71 is adjacent to the first side of the channel region 22, and the second word line 72 is adjacent to the second side of the channel region 22, and the second side and the first side of the channel region 22 are opposite along the extension direction of the bit line 30. As Figure 6 shown, the first word line 71 and the second word line 72 are respectively located on the first side and the second side of the channel region 22. Among them, the first word line 71 is adjacent to the first side of the channel region 22 and is opposite to at least part of the channel region 22, and the second word line 72 is adjacent to the second side of the channel region 22 and is opposite to at least part of the channel region 22. The first side and the second side of the channel region 22 are opposite along the extension direction of the bit line 30, so that the channel region 22 can be controlled by two word lines.

[0068] It can be understood that, among the first word line 71 and the second word line 72, the region facing the channel region 22 along the extension direction of the bit line 30 forms a gate. The structures of the first word line 71 and the second word line 72 can be the same or different. The first word line 71 and the second word line 72 can be single-layer or stacked. For example, they include a second conductor layer, and the material of the second conductor layer includes semiconductor materials such as doped polysilicon and doped amorphous silicon, or low-resistance metal materials such as tungsten, aluminum, or copper. The embodiments of the present application are not limited thereto.

[0069] To implement the control functions of the first word line 71 and the second word line 72, the semiconductor memory device further includes a gate oxide layer 73, which is disposed at least between the first word line 71 and the channel region 22, and between the second word line 72 and the channel region 22. Exemplarily, the gate oxide layer 73 extends in the vertical direction, that is, the gate oxide layer 73 is also disposed between the first word line 71 and the insulating layer 50, and between the second word line 72 and the insulating layer 50. The material of the gate oxide layer 73 includes silicon oxide, hafnium oxide, etc.

[0070] The semiconductor memory device in the embodiment of the present application includes a substrate 10, a plurality of stacked structures, bit lines 30, a capacitor structure 40, and a support layer 60. The plurality of stacked structures are located on the substrate 10 and are isolated from each other in the vertical direction. The stacked structure includes a semiconductor layer 20, and the semiconductor layer 20 includes a first doped region 21, a channel region 22, and a second doped region 23. The bit lines 30 extend in the horizontal direction and are connected to the first doped region 21. The capacitor structure 40 includes a lower electrode 41 and an upper electrode 42 stacked, and the lower electrode 41 is connected to the second doped region 23. The support layer 60 is disposed around the lower electrode 41 and directly contacts the side wall, the upper surface, and the lower surface of the lower electrode 41. By using the support layer 60 to directly contact the lower electrode 41, the end of the lower electrode 41 away from the semiconductor layer 20 can be supported, which can avoid the bending of the lower electrode 41 and the bridging between the lower electrodes 41, and ensure the performance of the semiconductor memory device.

[0071] The embodiment of the present application also provides a semiconductor memory device, which is, for example, a dynamic random access memory. Refer to Figure 10 and Figure 11 , the semiconductor memory device includes a substrate 10, a plurality of stacked structures, bit lines 30, a capacitor structure 40, an insulating layer 50, and a support layer 60. Among them, the substrate 10 provides support for the structures thereon, such as providing support for the stacked structures, the support layer 60, etc. The substrate 10 is, for example, a silicon substrate, a silicon-containing (such as silicon germanium) substrate, or a silicon-on-insulator (such as SOI) substrate, etc.

[0072] The plurality of stacked structures are located on the substrate 10 and are isolated from each other in the vertical direction. The plurality of stacked structures include a semiconductor layer 20, and the semiconductor layer 20 includes a first doped region 21, a channel region 22, and a second doped region 23. Among them, the plurality of stacked structures are arranged at intervals on the substrate 10, and the arrangement direction of the plurality of stacked structures is as shown by D3 in Figure 10 . The isolation layer 90 is filled between at least adjacent stacked structures, and the isolation layer 90 is used to realize the isolation between the stacked structures.

[0073] Exemplarily, the isolation layer 90 is located on the substrate 10 and extends in the vertical direction to ensure that the stacked structures do not conduct with each other in the vertical direction. Among them, the top surface of the isolation layer 90 can be higher than or flush with the top surface of the stacked structure. The top surface refers to the surface away from the substrate 10, and the vertical direction refers to the direction perpendicular to the top surface of the substrate 10, such as Figure 10 shown in D2. The material of the isolation layer 90 includes insulating materials, such as silicon oxide, silicon nitride, silicon carbonitride, etc.

[0074] Each stacked structure includes at least one semiconductor layer 20, and these semiconductor layers 20 are arranged at intervals in the vertical direction. The semiconductor layer 20 in each stacked structure can be in contact with the substrate 10 or spaced from the substrate 10. The material of the semiconductor layer 20 includes semiconductor materials, such as single-crystalline silicon, polycrystalline silicon, amorphous silicon, etc.

[0075] Each semiconductor layer 20 includes a first doped region 21, a channel region 22, and a second doped region 23 arranged in sequence, that is, the two sides of the channel region 22 are respectively connected to the first doped region 21 and the second doped region 23. Among them, the first doped region 21, the channel region 22, and the second doped region 23 are adjacent in sequence and parallel to the top surface of the substrate 10. The arrangement direction of the first doped region 21, the channel region 22, and the second doped region 23 is as Figure 10 and Figure 11 shown in the D1 direction, and this direction can also be considered as the extension direction of the semiconductor layer 20.

[0076] The surfaces of the first doped region 21 and the channel region 22 facing each other can overlap, such as completely coinciding. The surfaces of the second doped region 23 and the channel region 22 facing each other can overlap, such as completely coinciding. Both the first doped region 21 and the second doped region 23 can be heavily doped regions, for example, doping is achieved by ion implantation. The first doped region 21 can be used as a drain region, which is connected to the bit line 30, and the second doped region 23 can be used as a source region, which is connected to the capacitor structure 40.

[0077] The bit line 30 is disposed on the substrate 10 and extends in a horizontal direction parallel to the top surface of the substrate 10. The bit line 30 is electrically connected to the first doped region 21, that is, electrical conduction can be achieved between the bit line 30 and the first doped region 21. In some possible implementation manners, the height of the bit line 30 is adapted to that of the semiconductor layer 20. The top surface of the bit line 30 is higher than the bottom surface of the connected semiconductor layer 20 and lower than or flush with the top surface of the connected semiconductor layer 20; or, the bottom surface of the bit line 30 is higher than or flush with the bottom surface of the connected semiconductor layer 20 and lower than the top surface of the connected semiconductor layer 20. Specifically, the top surface of the bit line 30 is flush with the top surface of the connected semiconductor layer 20, and the bottom surface of the bit line 30 is flush with the bottom surface of the connected semiconductor layer 20, so that the bit line 30 and the semiconductor layer 20 are arranged in the same layer, which is convenient for the fabrication of the bit line 30 and can also improve the transmission performance between the bit line 30 and the corresponding semiconductor layer 20.

[0078] In some possible examples, the extending direction of the bit line 30 is parallel to the arranging direction of the plurality of stacked structures. In this way, the bit line 30 can be connected to a plurality of semiconductor layers 20, and these semiconductor layers 20 are located in different stacked structures, so as to simplify the structure of the semiconductor memory device and thus facilitate the improvement of the storage density. Among them, the extending direction of the bit line 30 is as Figure 10 shown in the D3 direction in the figure. The bit line 30 can be a single-layer structure or a stacked structure. Exemplarily, the bit line 30 includes a first conductor layer, and the material of the first conductor layer includes a metal material, such as a low-resistance metal material including tungsten, aluminum or copper. The specific structure of the bit line 30 in the embodiments of the present application is not limited. There can be multiple bit lines 30, and the multiple bit lines 30 are arranged at intervals in the vertical direction to avoid connection between adjacent bit lines 30. The number of bit lines 30 can be the same as the number of semiconductor layers 20 in the stacked structure, so that each stacked structure can lead out each semiconductor layer 20 therein through multiple bit lines 30 respectively.

[0079] Continue to refer to Figure 10 and Figure 11 , the capacitor structure 40 can store data, and it includes a lower electrode 41 and an upper electrode 42 which are stacked and spaced apart from each other. Among them, the lower electrode 41 is connected to the second doped region 23. Exemplarily, the lower electrode 41 is located on the surface of the second doped region 23 facing away from the channel region 22, that is, the first doped region 21, the channel region 22, the second doped region 23 and the lower electrode 41 are arranged in sequence. The surfaces of the lower electrode 41 and the second doped region 23 facing each other are in contact, for example, completely coincide.

[0080] Exemplarily, the lower electrode 41 includes a first sidewall 44 and a second sidewall 45 which are oppositely arranged. The first sidewall 44 is in direct contact with the support layer 60, and the second sidewall 45 is in direct contact with the second doped region 23. The surface of the lower electrode 41 facing away from the second doped region 23 is attached to the support layer 60. The material of the lower electrode 41 may include low-resistance metal materials such as titanium nitride, aluminum, titanium, copper or tungsten, semiconductor materials such as silicon germanium, or a combination of the above materials.

[0081] Part of the upper electrode 42 is located inside the lower electrode 41, that is, the lower electrode 41 surrounds part of the upper electrode 42. The upper electrode 42 is opposite to the lower electrode 41 and is spaced apart from the lower electrode 41. The upper electrode 42 may be an integral structure, that is, a plurality of lower electrodes 41 share one upper electrode 42. The upper electrode 42 is formed, for example, by a deposition process to facilitate the fabrication of the upper electrode 42. The material of the upper electrode 42 may include low-resistance metal materials such as titanium nitride, aluminum, titanium, copper or tungsten, semiconductor materials such as silicon germanium, or a combination of the above materials.

[0082] In some possible implementation manners, the orthographic projections of the upper electrode 42 and the lower electrode 41 on the support layer 60 are both located within the contour of the corresponding surface of the support layer 60. As Figure 10 and Figure 11 shown, the orthographic projection of the lower electrode 41 on the support layer 60 is located within the contour of the corresponding surface of the support layer 60, and the orthographic projections of the upper electrode 42 on the support layer 60 are all located within the corresponding surface contour of the support layer 60. In this way, in both the vertical direction and the horizontal direction, the range of the support layer 60 is larger, so that the support layer 60 can support all the lower electrodes 41 and is in full contact with the first sidewall 44 of the lower electrode 41, which can improve the support effect. At the same time, the contact area between the support layer 60 and the dielectric layer 43 can also be increased, further improving the support effect of the support layer 60.

[0083] The semiconductor memory device further includes a dielectric layer 43, and the dielectric layer 43 is disposed between the lower electrode 41 and the upper electrode 42. The material of the dielectric layer 43 includes, for example, silicon oxide, zirconium oxide, aluminum oxide, etc. In order to achieve the vertical isolation between the capacitor structures 40, an insulating layer 50 is disposed between adjacent capacitor structures 40, specifically between adjacent lower electrodes 41. The material of the insulating layer 50 includes, for example, silicon oxide, silicon nitride, phosphosilicate glass, etc.

[0084] Among them, the insulating layer 50 is also disposed between adjacent semiconductor layers 20. In this way, the insulating layer 50 can also achieve the vertical isolation between adjacent semiconductor layers 20. Further, the insulating layer 50 also extends between adjacent bit lines 30 to be used for achieving the vertical isolation between adjacent bit lines 30. As Figure 11As shown, the lower electrode 41 covers a partial surface of the insulating layer 50, the semiconductor layer 20 covers a partial surface of the insulating layer 50, and the bit line 30 covers a partial surface of the insulating layer 50.

[0085] In some possible examples, the insulating layer 50 includes a first end and a second end that are oppositely arranged. The first end of the insulating layer 50 may protrude from an end of the bit line 30 away from the first doped region 21 or be flush with the end of the bit line 30 away from the first doped region 21, and the second end of the insulating layer 50 protrudes from an end of the lower electrode 41 away from the second doped region 23. The first end and the second end of the insulating layer 50 are oppositely arranged along the arrangement direction of the semiconductor layer 20 and the capacitor structure 40.

[0086] Continue to refer to Figure 10 and Figure 11 As shown in, the support layer 60 is located between the insulating layers 50 and directly contacts the side walls, upper surface, and lower surface of the insulating layer 50. In this way, one end of the insulating layer 50 extends into the support layer 60. By using the support layer 60 to provide support for the insulating layer 50, the stability of the insulating layer 50 can be maintained, and the insulating layer 50 can be prevented from bending, thereby ensuring that the capacitor structure 40 formed on the insulating layer 50 bends and bridges, and ensuring the performance of the semiconductor memory device. Among them, the upper surface and the lower surface of the insulating layer 50 are spaced apart in the vertical direction, and the side wall of the insulating layer 50 is the surface of the insulating layer 50 away from the bit line 30. The stacked structures can also be oppositely arranged on both sides of the support layer 60, that is, the stacked structures can also be arranged along the Figure 8 shown D1 direction. In this way, the support layer 60 can provide support for the stacked structures on both sides to improve the storage density of the semiconductor memory device.

[0087] In some possible embodiments, the bit line 30 and the support layer 60 are respectively located on opposite sides of the semiconductor layer 20. The bit line 30 is located on one side of the semiconductor layer 20, the capacitor structure 40 is located on the other side of the semiconductor layer 20, and the support layer 60 is located on the side of the capacitor structure 40 away from the semiconductor layer 20. Specifically, the support layer 60 directly contacts the surface of the lower electrode 41 away from the second doped region 23, and also directly contacts the side wall, part of the upper surface, and part of the lower surface of the insulating layer 50 away from the bit line 30.

[0088] Continue to refer to Figure 10 and Figure 11 As shown in, the semiconductor memory device further includes a word line that extends in the vertical direction and is adjacent to the channel region 22. Specifically, the word line extends in a direction away from the top surface of the substrate 10. The word line is adjacent to the channel region 22 and is also used to form a gate to control the opening or closing of the channel region 22. The word line can be opposite to the channel regions 22 of multiple semiconductor layers 20 in the same stacked structure to simultaneously control the opening or closing of multiple channel regions 22.

[0089] In some possible embodiments, the word line includes a first word line 71 and a second word line 72; the first word line 71 is adjacent to the first side of the channel region 22, the second word line 72 is adjacent to the second side of the channel region 22, and the second side and the first side of the channel region 22 are opposite to each other along the extending direction of the bit line 30. As shown in the figure, the first word line 71 and the second word line 72 are respectively located on the first side and the second side of the channel region 22, wherein the first word line 71 is adjacent to the first side of the channel region 22 and is opposite to at least a part of the channel region 22, and the second word line 72 is adjacent to the second side of the channel region 22 and is opposite to at least a part of the channel region 22. The first side and the second side of the channel region 22 are opposite to each other along the extending direction of the bit line 30, so that the channel region 22 can be controlled by two word lines.

[0090] It can be understood that, among the first word line 71 and the second word line 72, the region facing the channel region 22 along the extending direction of the bit line 30 forms a gate. The structures of the first word line 71 and the second word line 72 may be the same or different. The first word line 71 and the second word line 72 may be single-layer or stacked. For example, they include a second conductor layer, and the material of the second conductor layer includes semiconductor materials such as doped polysilicon and doped amorphous silicon, or low-resistance metal materials such as tungsten, aluminum or copper. The embodiments of the present application are not limited thereto.

[0091] In order to implement the control functions of the first word line 71 and the second word line 72, the semiconductor memory device further includes a gate oxide layer 73, and the gate oxide layer 73 is at least disposed between the first word line 71 and the channel region 22, and between the second word line 72 and the channel region 22. Exemplarily, the gate oxide layer 73 extends in the vertical direction, that is, the gate oxide layer 73 is also disposed between the first word line 71 and the insulating layer 50, and between the second word line 72 and the insulating layer 50. The material of the gate oxide layer 73 includes silicon oxide, hafnium oxide, etc.

[0092] The semiconductor memory device in the embodiment of the present application includes a substrate 10, a plurality of stacked structures, bit lines 30, capacitor structures 40, an insulating layer 50, and a support layer 60. The plurality of stacked structures are located on the substrate 10 and are isolated from each other in the vertical direction. The stacked structure includes a semiconductor layer 20, and the semiconductor layer 20 includes a first doped region 21, a channel region 22, and a second doped region 23. The bit lines 30 extend in the horizontal direction and are connected to the first doped region 21. The capacitor structure 40 includes a lower electrode 41 and an upper electrode 42 stacked, and the lower electrode 41 is connected to the second doped region 23. The insulating layer 50 is located between adjacent capacitor structures 40, and the support layer 60 is located between the insulating layers 50 and directly contacts the side walls, upper surface, and lower surface of the insulating layer 50. In this way, one end of the insulating layer 50 extends into the support layer 60, and the support layer 60 provides support for the insulating layer 50, which can maintain the stability of the insulating layer 50 and prevent the insulating layer 50 from bending, so as to ensure that the capacitor structure 40 formed subsequently on the insulating layer 50 bends and bridges, and ensure the performance of the semiconductor memory device.

[0093] The embodiment of the present application also provides a manufacturing method of a semiconductor memory device. Refer to Figures 1 to 11 , the manufacturing method specifically includes: providing a substrate 10; forming a plurality of stacked structures, bit lines 30, capacitor structures 40, and a support layer 60; wherein, the plurality of stacked structures are located on the substrate 10 and are isolated from each other in the vertical direction, the stacked structure includes a semiconductor layer 20, and the semiconductor layer 20 includes a first doped region 21, a channel region 22, and a second doped region 23; the bit lines 30 extend in the horizontal direction and are connected to the first doped region 21; the capacitor structure 40 includes a lower electrode 41 and an upper electrode 42 stacked, and the lower electrode 41 is connected to the second doped region 23; the support layer 60 is in contact with the side walls of the capacitor structure 40.

[0094] Among them, the substrate 10 is used to provide support. The substrate 10 is, for example, a silicon substrate, a silicon-containing (such as silicon-germanium) substrate, or a silicon-on-insulator (such as SOI) substrate, etc. A plurality of stacked structures, bit lines 30, capacitor structures 40, and a support layer 60 are formed on the substrate 10. The plurality of stacked structures are arranged at intervals on the substrate 10 to facilitate the isolation between the stacked structures. The arrangement direction of the plurality of stacked structures is as shown in D3 in Figure 6 and Figure 10 . An isolation layer 90 is filled between at least adjacent stacked structures, and the isolation layer 90 is used to achieve the isolation between the stacked structures.

[0095] Exemplarily, the isolation layer 90 is located on the substrate 10 and extends in the vertical direction to ensure that the stacked structures do not conduct with each other in the vertical direction. Among them, the top surface of the isolation layer 90 can be higher than or flush with the top surface of the stacked structure. The top surface refers to the surface away from the substrate 10, and the vertical direction refers to the direction perpendicular to the top surface of the substrate 10, as shown in Figure 6 andFigure 10 As shown in D2. The material of the isolation layer 90 includes insulating materials, such as silicon oxide, silicon nitride, silicon carbonitride, etc.

[0096] Each stacked structure includes at least one semiconductor layer 20, and these semiconductor layers 20 are arranged at intervals in the vertical direction. The semiconductor layers 20 in each stacked structure can be in contact with the substrate 10 or spaced apart from the substrate 10. The material of the semiconductor layer 20 includes semiconductor materials, such as single crystal silicon, polycrystalline silicon, amorphous silicon, etc.

[0097] Each semiconductor layer 20 includes a first doped region 21, a channel region 22, and a second doped region 23 arranged in sequence, that is, the two sides of the channel region 22 are respectively connected to the first doped region 21 and the second doped region 23. Among them, the first doped region 21, the channel region 22, and the second doped region 23 are adjacent in sequence and parallel to the top surface of the substrate 10. The arrangement direction of the first doped region 21, the channel region 22, and the second doped region 23 is as Figure 6 and Figure 10 shown in the D1 direction, and this direction can also be regarded as the extension direction of the semiconductor layer 20.

[0098] The surfaces of the first doped region 21 and the channel region 22 facing each other can overlap, for example, completely coincide, and the surfaces of the second doped region 23 and the channel region 22 facing each other can overlap, for example, completely coincide. Both the first doped region 21 and the second doped region 23 can be heavily doped regions, for example, doped by ion implantation. The first doped region 21 can be used as a drain region, which is connected to the bit line 30, and the second doped region 23 can be used as a source region, which is connected to the capacitor structure 40.

[0099] Continuing to refer to Figure 2 , the manufacturing method further includes: forming a word line, and the word line extends in the vertical direction and is adjacent to the channel region 22. Specifically, the word line extends in the direction away from the top surface of the substrate 10. The word line is adjacent to the channel region 22 and is also used to form a gate to control the opening or closing of the channel region 22. The word line can be opposite to the channel regions 22 of multiple semiconductor layers 20 in the same stacked structure to simultaneously control the opening or closing of multiple channel regions 22.

[0100] In some possible embodiments, the word lines include a first word line 71 and a second word line 72; the first word line 71 is adjacent to a first side of the channel region 22, and the second word line 72 is adjacent to a second side of the channel region 22, and the second side and the first side of the channel region 22 are opposite to each other along the extending direction of the bit line 30. As shown in the figure, the first word line 71 and the second word line 72 are respectively located on the first side and the second side of the channel region 22, wherein the first word line 71 is adjacent to the first side of the channel region 22 and is opposite to at least a part of the channel region 22, and the second word line 72 is adjacent to the second side of the channel region 22 and is opposite to at least a part of the channel region 22. The first side and the second side of the channel region 22 are opposite to each other along the extending direction of the bit line 30, so that the channel region 22 can be controlled by two word lines.

[0101] It can be understood that, among the first word line 71 and the second word line 72, the regions facing the channel region 22 along the extending direction of the bit line 30 form a gate. The structures of the first word line 71 and the second word line 72 may be the same or different. The first word line 71 and the second word line 72 may be single-layer or stacked. For example, they include a second conductor layer, and the material of the second conductor layer includes semiconductor materials such as doped polysilicon and doped amorphous silicon, or low-resistance metal materials such as tungsten, aluminum or copper. The embodiments of the present application are not limited thereto.

[0102] To implement the control functions of the first word line 71 and the second word line 72, the semiconductor memory device further includes a gate oxide layer 73, and the gate oxide layer 73 is at least disposed between the first word line 71 and the channel region 22, and between the second word line 72 and the channel region 22. Exemplarily, the gate oxide layer 73 extends in the vertical direction, that is, the gate oxide layer 73 is also disposed between the first word line 71 and the insulating layer 50, and between the second word line 72 and the insulating layer 50. The material of the gate oxide layer 73 includes silicon oxide, hafnium oxide, etc.

[0103] The bit line 30 is disposed on the substrate 10 and extends in the horizontal direction, and the horizontal direction is parallel to the top surface of the substrate 10. The bit line 30 is electrically connected to the first doped region 21, that is, electrical conduction can be achieved between the bit line 30 and the first doped region 21. In some possible implementation manners, the height of the bit line 30 is adapted to the semiconductor layer 20. The top surface of the bit line 30 is higher than the bottom surface of the connected semiconductor layer 20 and lower than or flush with the top surface of the connected semiconductor layer 20; or, the bottom surface of the bit line 30 is higher than or flush with the bottom surface of the connected semiconductor layer 20 and lower than the top surface of the connected semiconductor layer 20. Specifically, the top surface of the bit line 30 is flush with the top surface of the connected semiconductor layer 20, and the bottom surface of the bit line 30 is flush with the bottom surface of the connected semiconductor layer 20, so that the bit line 30 and the semiconductor layer 20 are disposed in the same layer, which is convenient for the fabrication of the bit line 30 and can also improve the transmission performance between the bit line 30 and the corresponding semiconductor layer 20.

[0104] In some possible examples, the extending direction of the bit line 30 is parallel to the arranging direction of the plurality of stacked structures. In this way, the bit line 30 can be connected to a plurality of semiconductor layers 20, and these semiconductor layers 20 are located in different stacked structures, so as to simplify the structure of the semiconductor memory device, thereby facilitating the improvement of the storage density. Among them, the extending direction of the bit line 30 is as shown in the D3 direction in Figure 6 and Figure 10 . The bit line 30 can be a single-layer structure or a stacked structure. Exemplarily, the bit line 30 includes a first conductor layer, and the material of the first conductor layer includes a metal material, such as a low-resistance metal material including tungsten, aluminum, or copper, etc. The specific structure of the bit line 30 in the embodiments of the present application is not limited. There can be multiple bit lines 30, and the multiple bit lines 30 are arranged at intervals in the vertical direction to avoid connection between adjacent bit lines 30. The number of bit lines 30 can be the same as the number of semiconductor layers 20 in the stacked structure, so that each stacked structure can lead out each semiconductor layer 20 therein through multiple bit lines 30 respectively.

[0105] Continuing to refer to Figures 1 to 11 , the capacitor structure 40 can store data, and it includes a lower electrode 41 and an upper electrode 42 which are stacked, and the lower electrode 41 and the upper electrode 42 are spaced apart from each other. The lower electrode 41 is also connected to the second doping region 23. For example, the lower electrode 41 is located on the surface of the second doping region 23 away from the channel region 22, that is, the first doping region 21, the channel region 22, the second doping region 23, and the lower electrode 41 are arranged in sequence. The surfaces of the lower electrode 41 and the second doping region 23 that face each other are in contact, for example, completely coincide. The materials of the lower electrode 41 and the upper electrode 42 include, for example, low-resistance metal materials such as titanium nitride, aluminum, titanium, copper, or tungsten, semiconductor materials such as silicon germanium, or a combination of the above materials. In order to realize the storage function of the capacitor structure 40, a dielectric layer 43 is further formed between the upper electrode 42 and the lower electrode 41, and the material of the dielectric layer 43 includes, for example, silicon oxide, zirconium oxide, aluminum oxide, etc.

[0106] The support layer 60 is disposed on the side of the semiconductor layer 20 away from the bit line 30, that is, the support layer 60 and the bit line 30 are respectively located on both sides of the semiconductor layer 20, and the above capacitor structure 40 can also be formed between the support layer 60 and the semiconductor layer 20. The support layer 60 can extend in the vertical direction and be in contact with the side wall of the capacitor structure 40. For example, the support layer 60 at least directly contacts the surface of the lower electrode 41 away from the second doping region 23 to provide support for the capacitor structure 40, avoid bending of the capacitor structure 40, and improve the performance of the formed semiconductor memory device. The material of the support layer 60 includes, for example, insulating materials with relatively high hardness such as silicon nitride and silicon carbonitride. Stacked structures can be formed on both sides of the support layer 60, that is, the stacked structure can also extend along Figure 8 and Figure 11The arrangement in the D1 direction as shown. The support layer 60 can provide support for the stacked structures on both sides to improve the storage density of the semiconductor memory device.

[0107] In some possible embodiments, referring to Figures 1 to 8 , the support layer 60 is disposed around the lower electrode 41 and directly contacts the sidewall, upper surface, and lower surface of the lower electrode 41. Among them, the upper surface and the lower surface of the lower electrode 41 are oppositely disposed in the vertical direction. One end of the lower electrode 41 away from the second doped region 23 is located within the support layer 60. By using the support layer 60 to provide support for the capacitor structure 40, the bending of the lower electrode 41 can be avoided, and the bridging between the lower electrodes 41 can be avoided, ensuring the performance of the semiconductor memory device.

[0108] For example, the lower electrode 41 includes a first sidewall 44 and a second sidewall 45 that are oppositely disposed. The first sidewall 44 is in direct contact with the support layer 60, and the second sidewall 45 is in direct contact with the second doped region 23. The material of the lower electrode 41 is, for example, the same as the material of the semiconductor layer 20, so that the lower electrode 41 and the semiconductor layer 20 form an integral body, facilitating the synchronous fabrication of the lower electrode 41 and the semiconductor layer 20. The lower electrode 41 and the semiconductor layer 20 are disposed in the same layer, and the lower electrode 41 can be a part of the semiconductor layer 20. The upper electrode 42 is located between adjacent lower electrodes 41. In the vertical direction, the upper electrode 42 is staggered from the semiconductor layer 20.

[0109] In this embodiment, the manufacturing method of the semiconductor memory device further includes: forming an insulating layer 50, and the insulating layer 50 is located between adjacent semiconductor layers 20 to achieve mutual isolation between adjacent semiconductor layers 20 in the same stacked structure. The insulating layer 50 is at least filled between adjacent semiconductor layers 20 and is in complete contact with the surfaces of adjacent two semiconductor layers 20 that face each other to ensure the isolation effect between the semiconductor layers 20. The material of the insulating layer 50 includes, for example, silicon oxide, silicon nitride, phosphosilicate glass, etc. The upper electrode 42 is specifically formed on the surface of the insulating layer 50 facing the support layer 60. The upper electrode 42 surrounds the outer peripheral surface of the lower electrode 41, that is, the upper electrode 42 is sleeved on the lower electrode 41 and is spaced from the lower electrode 41. The upper electrode 42 can be an integral structure, that is, a plurality of lower electrodes 41 share one upper electrode 42. The upper electrode 42 is formed by, for example, a deposition process to facilitate the fabrication of the upper electrode 42.

[0110] In this embodiment, the dielectric layer 43 is disposed between the lower electrode 41 and the upper electrode 42, and between the support layer 60 and the upper electrode 42. The dielectric layer 43 covers a partial surface of the lower electrode 41. For example, the dielectric layer 43 covers a partial outer peripheral surface of the lower electrode 41 adjacent to one end of the second doped region 23. One end of the lower electrode 41 away from the second doped region 23 extends into the support layer 60, and no dielectric layer 43 is formed at this end. Specifically, the lower electrode 41 and the dielectric layer 43 are in contact with the support layer 60, and the dielectric layer covers this partial surface of the lower electrode 41 facing the upper electrode 42. The upper electrode 42 is spaced apart from the support layer 60.

[0111] As a possible implementation, a specific process of the manufacturing method in the embodiments of the present application is as follows:

[0112] Referring to Figure 1 and Figure 2 , a stacked initial structure is formed. The stacked initial structure includes an insulating initial layer and a semiconductor initial layer that are alternately arranged in sequence, and a mask layer 80 is formed on the stacked initial structure. Among them, the insulating initial layer and the semiconductor initial layer are respectively formed into an insulating layer 50 and a semiconductor layer 20 subsequently. The insulating initial layer, the semiconductor initial layer, and the mask layer 80 can all be formed by a deposition process, and they are complete film layers.

[0113] A patterning process is performed on the mask layer 80, and the stacked initial structure is etched using the patterned mask layer 80 as a mask to form a stacked structure and isolation trenches for isolating the stacked structures. Among them, through photolithography and etching, a required pattern is formed in the mask layer 80, and the pattern is transferred downward. The formed stacked structure includes an insulating layer 50 and a semiconductor layer 20 that are alternately arranged in sequence. The mask layer 80 can be consumed during the process of etching the stacked initial structure, or can be removed after the stacked structure is formed, or can be removed after the capacitor structure is formed. After the stacked structure is formed, an isolation layer 90 can also be formed in the isolation trenches to make the stacked structures independent of each other.

[0114] As Figure 1 and Figure 2 shown, a bit line 30 is formed on one side of the semiconductor layer 20, and the bit line 30 is connected to the semiconductor layer 20. Among them, the bit line 30 can be formed by removing a part of the semiconductor layer 20 and then depositing a bit line material; or the bit line 30 can be formed by depositing a bit line material after adjacent to other film layers of the semiconductor layer 20.

[0115] Referring to Figure 3 and Figure 9, a part of the insulating layer 50 far from one end of the bit line 30 is removed to form a support layer 60. Before removing the part of the insulating layer 50, a part of the isolation layer 90 far from the bit line 30 can also be removed. In this way, the exposed area of the insulating layer 50 can be increased, facilitating the removal of the part of the insulating layer 50. The support layer 60 can be formed by deposition. The support layer 60 fills the space between adjacent semiconductor layers 20 and is also formed on the side of the semiconductor layer 20 far from the bit line 30. Before or after forming the support layer 60, gate oxide layers 73 are respectively formed on both sides of the stacked structure, and a first word line 71 and a second word line 72 are correspondingly formed on the side of the gate oxide layer 73 facing away from the stacked structure. Exemplarily, after forming the support layer 60, a part of the isolation layer 90 is removed to expose at least part of the semiconductor layer 20, and a gate oxide material and a word line material are sequentially deposited there to form the gate oxide layer 73, the first word line 71, and the second word line 72.

[0116] Refer to Figures 4 to 7 , a part of the insulating layer 50 adjacent to the support layer 60 is removed, and a dielectric layer 43 and an upper electrode 42 are sequentially deposited. The dielectric layer 43 and the upper electrode 42 fill the gap between adjacent semiconductor layers 20, that is, part of the semiconductor layer 20 serves as the lower electrode 41. Among them, as Figure 4 and Figure 5 shown, before removing the part of the insulating layer 50, a part of the isolation layer 90 far from the support layer 60 can also be removed. In this way, the exposed area of the insulating layer 50 can be increased, facilitating the removal of the part of the insulating layer 50. As Figure 6 and Figure 7 shown, a dielectric layer 43 is deposited on the surface of the exposed semiconductor layer 20. The dielectric layer 43 does not fill the gap between adjacent semiconductor layers 20 in the vertical direction; then an upper electrode 42 is deposited on the surface of the dielectric layer 43, and the upper electrode 42 fills the remaining gap between adjacent semiconductor layers 20 in the vertical direction.

[0117] In some other possible embodiments, refer to Figures 9 to 11 , the manufacturing method further includes forming an insulating layer 50. The insulating layer 50 is located between adjacent capacitor structures 40. The support layer 60 is located between the insulating layers 50 and directly contacts the side walls, upper surface, and lower surface of the insulating layer 50. The insulating layer 50 is specifically formed between adjacent lower electrodes 41. The material of the insulating layer 50 includes, for example, silicon oxide, silicon nitride, phosphosilicate glass, etc. The insulating layer 50 includes a first end and a second end arranged oppositely. The first end of the insulating layer 50 can protrude from or be flush with the end of the bit line 30 far from the first doping region 21, and the second end of the insulating layer 50 protrudes from the end of the lower electrode 41 far from the second doping region 23. The first end and the second end of the insulating layer 50 are arranged oppositely along the arrangement direction of the semiconductor layer 20 and the capacitor structure 40.

[0118] The support layer 60 covers one end of the insulating layer 50. By using the support layer 60 to provide support for the insulating layer 50, the stability of the insulating layer 50 can be maintained, and the insulating layer 50 can be prevented from bending, so as to ensure that the capacitor structure 40 formed subsequently on the insulating layer 50 does not bend and bridge, thus ensuring the performance of the semiconductor memory device. Among them, the upper surface and the lower surface of the insulating layer 50 are arranged at intervals in the vertical direction, and the side wall of the insulating layer 50 is the surface on the side of the insulating layer 50 away from the bit line 30. Specifically, the lower electrode 41 contacts the support layer 60 to support the support layer 60, and the dielectric layer covers all the surfaces of the lower electrode 41 facing the upper electrode 42. The dielectric layer 43 and the upper electrode 42 are both arranged at intervals from the support layer 60.

[0119] In this embodiment, the insulating layer 50 is also arranged between adjacent semiconductor layers 20. In this way, the insulating layer 50 can also achieve the vertical isolation between adjacent semiconductor layers 20. Further, the insulating layer 50 also extends between adjacent bit lines 30 to be used for achieving the vertical isolation between adjacent bit lines 30. As Figure 11 shown, the lower electrode 41 covers a part of the surface of the insulating layer 50, the semiconductor layer 20 covers a part of the surface of the insulating layer 50, and the bit line 30 covers a part of the surface of the insulating layer 50.

[0120] As a possible implementation, refer to Figures 1 to 3 and Figures 9 to 11 A specific process of the manufacturing method in the embodiment of the present application is as follows:

[0121] A stacked initial structure is formed. The stacked initial structure includes an insulating initial layer and a semiconductor initial layer that are alternately arranged in sequence, and a mask layer 80 is formed on the stacked initial structure. Among them, the insulating initial layer and the semiconductor initial layer are respectively formed into the insulating layer 50 and the semiconductor layer 20 subsequently. The insulating initial layer, the semiconductor initial layer, and the mask layer 80 can all be formed by a deposition process, and they are complete film layers.

[0122] A patterning process is performed on the mask layer 80, and the stacked initial structure is etched using the patterned mask layer 80 as a mask to form a stacked structure and isolation trenches for isolating the stacked structures. Among them, through photolithography and etching, a required pattern is formed in the mask layer 80, and the pattern is transferred downward. The formed stacked structure includes the insulating layer 50 and the semiconductor layer 20 that are alternately arranged in sequence. The mask layer 80 can be consumed during the process of etching the stacked initial structure, can also be removed after forming the stacked structure, or can be removed after forming the capacitor structure. After forming the stacked structure, an isolation layer 90 can also be formed in the isolation trenches to make the stacked structures independent of each other.

[0123] A bit line 30 is formed on one side of the semiconductor layer 20, and the bit line 30 is connected to the first doped region 21 in the semiconductor layer 20. Among them, the bit line 30 can be formed by removing a part of the semiconductor layer 20 and then depositing a bit line material; or the bit line 30 can be formed by depositing a bit line material after adjoining other film layers of the semiconductor layer 20.

[0124] Remove a part of the semiconductor layer 20 at one end away from the bit line 30 to form a support layer 60. Before removing a part of the insulating layer 50, a part of the isolation layer 90 away from the bit line 30 can also be removed. In this way, the exposed area of the insulating layer 50 can be increased, which is convenient for removing a part of the insulating layer 50 to expose a part of the semiconductor layer 20. The support layer 60 can be deposited and formed. The support layer 60 fills the space between adjacent semiconductor layers 20 and is also formed on the side of the semiconductor layer 20 away from the bit line 30. Before or after forming the support layer 60, gate oxide layers 73 are respectively formed on both sides of the stacked structure, and a first word line 71 and a second word line 72 are correspondingly formed on the side of the gate oxide layer 73 facing away from the stacked structure. Exemplarily, after forming the support layer 60, a part of the isolation layer 90 is removed to expose at least a part of the semiconductor layer 20, and a gate oxide material and a word line material are sequentially deposited there to form the gate oxide layer 73, the first word line 71, and the second word line 72.

[0125] Remove a part of the semiconductor layer 20 adjacent to the support layer 60, and sequentially deposit a lower electrode 41, a dielectric layer 43, and an upper electrode 42 to form a capacitor structure 40. The lower electrode 41, the dielectric layer 43, and the upper electrode 42 fill the gap between adjacent insulating layers 50. As Figure 9 shown, before removing a part of the semiconductor layer 20, a part of the isolation layer 90 away from the support layer 60 can also be removed. In this way, the exposed area of the semiconductor layer 20 can be increased, which is convenient for removing a part of the semiconductor layer 20 to expose a part of the insulating layer 50. Deposit the lower electrode 41 on the surface of the exposed insulating layer 50. The lower electrode 41 does not fill the gap between adjacent insulating layers 50 in the vertical direction; then deposit the dielectric layer 43. The dielectric layer 43 does not fill the gap between adjacent insulating layers 50 in the vertical direction; deposit the upper electrode 42 on the surface of the dielectric layer 43. The upper electrode 42 fills the remaining gap between adjacent insulating layers 50 in the vertical direction.

[0126] In the above two embodiments and other possible embodiments, the orthographic projections of the upper electrode 42 and the lower electrode 41 on the support layer 60 are both located within the contour of the corresponding surface of the support layer 60. As Figure 7 and Figure 8As shown, the orthographic projection of the lower electrode 41 on the support layer 60 is located within the contour of the corresponding surface of the support layer 60, and the orthographic projection of the upper electrode 42 on the support layer 60 is also located within the contour of the corresponding surface of the support layer 60. In this way, the range of the support layer 60 is larger both in the vertical direction and in the horizontal direction, so that the support layer 60 can support all the lower electrodes 41 and be in full contact with the first sidewall 44 of the lower electrode 41, which can improve the support effect. At the same time, the contact area between the support layer 60 and the dielectric layer 43 can also be increased, further improving the support effect of the support layer 60.

[0127] The manufacturing method of the semiconductor memory device provided by the embodiment of the present application includes: providing a substrate 10, and forming a plurality of stacked structures, bit lines 30, capacitor structures 40, and a support layer 60; wherein, the plurality of stacked structures are located on the substrate 10 and are isolated from each other in the vertical direction, and the stacked structure includes a semiconductor layer 20, and the semiconductor layer 20 includes a first doped region 21, a channel region 22, and a second doped region 23; the bit lines 30 extend in the horizontal direction and are connected to the first doped region 21; the capacitor structure 40 includes a lower electrode 41 and an upper electrode 42 stacked, and the lower electrode 41 is connected to the second doped region 23; the support layer 60 is in contact with the sidewall of the capacitor structure 40. The support layer 60 can support during the formation of the capacitor structure 40, avoid the bending of the capacitor structure 40, and improve the performance of the formed semiconductor memory device.

[0128] Finally, it should be noted that: those skilled in the art will easily think of other implementation manners of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses, or adaptations of the present invention, and these variations, uses, or adaptations follow the general principles of the present invention and include the common general knowledge or conventional technical means in the technical field not disclosed in the present invention. It is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.

Claims

1. A semiconductor memory device, characterized in that: include: substrate; A plurality of stacked structures, located on the substrate and isolated from each other in a vertical direction, the stacked structures comprising a semiconductor layer, the semiconductor layer comprising a first doping region, a channel region, and a second doping region; A bit line extending in a horizontal direction and connected to the first doped region; A capacitor structure, comprising a lower electrode and an upper electrode stacked together, wherein the lower electrode is connected to the second doped region; The supporting layer is disposed around the lower electrode and directly contacts the side wall, the upper surface and the lower surface of the lower electrode.

2. The semiconductor memory device according to claim 1, wherein: The lower electrode includes a first side wall and a second side wall that are opposite to each other, the first side wall is in direct contact with the support layer, and the second side wall is in direct contact with the second doping region.

3. The semiconductor memory device according to claim 2, wherein: The orthographic projections of the upper electrode and the lower electrode on the support layer are both located within the contour of the corresponding surface of the support layer.

4. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: Also included is a word line extending along the vertical direction and adjacent to the channel region.

5. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: Also includes an insulating layer and a dielectric layer, wherein the insulating layer is disposed between adjacent semiconductor layers; The dielectric layer is disposed between the lower electrode and the upper electrode, and between the support layer and the upper electrode, and the dielectric layer covers a portion of the surface of the lower electrode.

6. A semiconductor memory device, characterized in that: include: substrate; A plurality of stacked structures, located on the substrate and isolated from each other in a vertical direction, the stacked structures comprising a semiconductor layer, the semiconductor layer comprising a first doping region, a channel region, and a second doping region; A bit line extending in a horizontal direction and connected to the first doped region; A capacitor structure, comprising a stacked lower electrode and an upper electrode, wherein the lower electrode is connected to the second doped region; An insulating layer, located between adjacent capacitor structures; The support layer is located between the insulating layers and directly contacts the sidewalls, the upper surface and the lower surface of the insulating layer.

7. The semiconductor memory device according to claim 6, wherein: The lower electrode includes a first side wall and a second side wall that are opposite to each other, the first side wall is in direct contact with the support layer, and the second side wall is in direct contact with the second doping region.

8. The semiconductor memory device according to claim 7, wherein: The orthographic projections of the upper electrode and the lower electrode on the support layer are both located within the contours of the corresponding surfaces of the support layer.

9. The semiconductor memory device according to any one of claims 6 to 8, characterized in that: Also included is a word line extending along the vertical direction and adjacent to the channel region.

10. The semiconductor memory device according to any one of claims 6 to 8, characterized in that: The bit line and the support layer are respectively located on two opposite sides of the semiconductor layer.

11. The semiconductor memory device according to any one of claims 6 to 8, characterized in that: The insulating layer is also arranged between adjacent semiconductor layers; The semiconductor memory device further includes a dielectric layer disposed between the lower electrode and the upper electrode, and the lower electrode covers a portion of a surface of the insulating layer.

12. A method for manufacturing a semiconductor memory device, characterized in that: include: providing a substrate; forming a plurality of stacked structures, bit lines, capacitor structures and support layers; Wherein, the plurality of stacked structures are located on the substrate and isolated from each other in a vertical direction, the stacked structures include a semiconductor layer, and the semiconductor layer includes a first doping region, a channel region, and a second doping region; The bit line extends in a horizontal direction and is connected to the first doped region; The capacitor structure comprises a lower electrode and an upper electrode which are stacked, and the lower electrode is connected to the second doping region; The supporting layer contacts the sidewall of the capacitor structure.

13. The manufacturing method according to claim 12, characterized in that: The supporting layer is disposed around the lower electrode and directly contacts the sidewall, the upper surface and the lower surface of the lower electrode.

14. The manufacturing method according to claim 12, characterized in that: Also includes: An insulating layer is formed, wherein the insulating layer is located between adjacent capacitor structures, and the supporting layer is located between the insulating layers and directly contacts the sidewalls, the upper surface and the lower surface of the insulating layer.

15. The manufacturing method according to claim 14, characterized in that: Also includes: A dielectric layer is formed, wherein the dielectric layer is disposed between the lower electrode and the upper electrode, and the lower electrode covers a portion of the surface of the insulating layer.

16. The manufacturing method according to claim 15, characterized in that: The insulating layer is also disposed between adjacent semiconductor layers.

17. The manufacturing method according to claim 16, characterized in that: The dielectric layer is disposed between the lower electrode and the upper electrode, and between the support layer and the upper electrode, and the dielectric layer covers a portion of the surface of the lower electrode.

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