Chip packaging structure

Abstract

The invention discloses a chip packaging structure, and the structure comprises a first chip which comprises a substrate and a capacitor structure, and the surface of the substrate is provided with at least one groove; the capacitor structure comprises a plurality of capacitors which are arranged in a stacked mode. The capacitor comprises a first electrode layer, a second electrode layer and a capacitor dielectric layer, wherein the first electrode layer and the second electrode layer are oppositely arranged, and the capacitor dielectric layer is located between the first electrode layer and the second electrode layer. The first electrode layer, the second electrode layer and the capacitor dielectric layer extend along the surface of the substrate and the interior of the groove; a power supply is arranged in the second chip and is used for supplying power to the second chip; and the second chip is electrically connected with the first chip. According to the technical scheme, the capacitor structure in the second chip is arranged on the side close to the internal power supply of the first chip, so that the distance between the capacitor structure and the internal power supply of the first chip is reduced, and the coupling capacitance is reduced.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a chip packaging structure. Background Art

[0002] Currently, in high-computing power chip packaging structures, although 2.5D packaging and 3D packaging technologies can achieve high-speed interconnection between the main chip and the memory chip, the path between the chip power supply and the external capacitor will introduce additional resistance and inductance, thereby affecting the filtering performance of the capacitor and reducing the working quality of the chip. Summary of the Invention

[0003] The technical solution of this application reduces the coupling capacitance by arranging the capacitor structure in the second chip on the side close to the internal power supply of the first chip, thereby reducing the distance between the capacitor structure and the internal power supply of the first chip.

[0004] This application provides a chip packaging structure, which includes a first chip. The first chip includes a substrate and a capacitor structure. At least one groove is provided on the surface of the substrate; the capacitor structure includes a first electrode layer and a second electrode layer arranged oppositely, and a capacitor dielectric layer located between the first electrode layer and the second electrode layer; the first electrode layer, the second electrode layer, and the capacitor dielectric layer all extend along the surface of the substrate and inside the groove;

[0005] A second chip, with a power supply provided inside the second chip to supply power to the second chip; the second chip is electrically connected to the first chip.

[0006] In some embodiments, an active layer is provided inside the second chip, and the active layer is provided on the side of the second chip close to the capacitor structure;

[0007] The power supply is located inside the active layer.

[0008] In some embodiments, the capacitor structure is a decoupling capacitor; the first electrode layer receives a power signal, and the second electrode layer receives a ground signal; or, the second electrode layer receives a power signal, and the first electrode layer receives a ground signal.

[0009] In some embodiments, the substrate includes a redistribution structure, and the redistribution structure includes a first redistribution layer and a second redistribution layer; the first electrode layer is electrically connected to the second chip through the first redistribution layer; the second electrode layer is electrically connected to the second chip through the first redistribution layer;

[0010] The first chip further includes:

[0011] Multiple metal vias that penetrate the substrate and are electrically connected to the second redistribution layer, which is electrically connected to the second chip.

[0012] In some embodiments, the redistribution structure further includes a third redistribution layer;

[0013] The third redistribution layer is electrically connected to the metal vias and is also used to electrically connect to an interposer;

[0014] Or,

[0015] The third redistribution layer is electrically connected to the metal vias and is used to electrically connect to a third chip;

[0016] Wherein, the third chip and the first chip are the same or different chips.

[0017] In some embodiments, an active layer is provided inside the first chip, and the active layer is disposed at the bottom of the substrate; the power supply is located within the active layer to supply power to the first chip.

[0018] In some embodiments, the chip package structure further includes:

[0019] A package layer for packaging the first chip; wherein, the first redistribution layer and the second redistribution layer pass through the package layer and are electrically connected to the second chip;

[0020] An insulating layer, which is disposed on a side of the capacitor structure close to the substrate and extends along the surface of the substrate and inside the groove.

[0021] In some embodiments, the first electrode layer is located between the insulating layer and the capacitor dielectric layer;

[0022] The second electrode layer is located between the capacitor dielectric layer and the package layer.

[0023] In some embodiments, the orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the capacitor dielectric layer on the substrate;

[0024] The orthographic projection of the capacitor dielectric layer on the substrate covers the orthographic projection of the second electrode layer on the substrate.

[0025] In some embodiments, two side edges of the first electrode layer are respectively configured as a first connection portion and a second connection portion, and the first connection portion and the second connection portion are electrically connected to the second chip through the first redistribution layer;

[0026] Both sides of the second electrode layer are respectively provided with a third connection part and a fourth connection part, and the third connection part and the fourth connection part are electrically connected to the second chip through the first rewiring layer.

[0027] In the embodiment of the present application, during the operation of the power supply in the first chip, the voltage on the power supply line will fluctuate or contain high-frequency noise, thereby affecting the normal operation of the first chip.

[0028] In the present application, by arranging the capacitor structure in the second chip on the side close to the internal power supply of the first chip, the distance between the capacitor structure and the internal power supply of the first chip is reduced. This setting method can not only reduce the coupling capacitance, but also filter out the above-mentioned high-frequency noise, thereby providing a power supply with low ripple, stable voltage and no high-frequency noise for the first chip.

[0029] In addition, the capacitor structure in the second chip can be used to reduce the voltage drop inside the second chip. When the second chip needs a large amount of current at a certain moment (for example, when the second chip switches from the low-power mode to the high-power mode), if the power supply cannot respond to this rapidly changing demand in time, it will cause the voltage inside the second chip to drop temporarily. At this time, the capacitor structure in the second chip can provide the additional current required by the second chip within a short time, which helps to keep the voltage inside the second chip stable, thereby avoiding the functional abnormality of the second chip caused by the sudden drop of the internal voltage.

[0030] Furthermore, the capacitor structure in the second chip has charge and discharge characteristics. That is, the capacitor structure can store charges and release charges when needed to maintain the stability of the power supply in the second chip, thereby helping the second chip to operate normally within the rated voltage range. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and / or additional aspects and advantages of the present application will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, where:

[0032] Figure 1A The structural schematic diagram of a 2.5D chip packaging structure provided for the related art.

[0033] Figure 1B The structural schematic diagram of a 3D chip packaging structure provided for the related art.

[0034] Figure 1 The structural schematic diagram of a chip packaging structure provided for the embodiment of the present application.

[0035] Figure 2 The structural schematic diagram of another chip packaging structure provided for the embodiment of the present application.

[0036] Figure 3 This is a schematic structural diagram of another chip packaging structure provided by the embodiments of the present application. Detailed implementation manners

[0037] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals indicate the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and should not be construed as a limitation of the present application.

[0038] The terms "first", "second", etc. in the description and claims of the present application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type and do not limit the number of objects. For example, the first object can be one or more. In addition, "and / or" in the description and claims means at least one of the connected objects, and the character " / " generally indicates an "or" relationship between the associated objects before and after.

[0039] In the description of the present application, "a plurality" means two or more.

[0040] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0041] When describing some embodiments, the expression "connection" and its derivatives may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral body; it can be directly connected or indirectly connected through an intermediate medium. The term "electrical connection"

[0042] For example, it indicates that two or more components have direct physical contact or electrical contact, and may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0043] Figure 1ASchematic structural diagram of a 2.5D chip packaging structure provided for the related art Figure 1B Schematic structural diagram of a 3D chip packaging structure provided for the related art, refer to Figure 1A , Figure 1A A 2.5D chip packaging structure provided for the related art. In this 2.5D chip packaging structure, the main chip 1a, the chip stack 2a, and the chip stack 3a are connected to the interposer through metal bumps to achieve the mutual connection of the main chip 1a, the chip stack 2a, and the chip stack 3a on the interposer, thereby realizing high-speed data transmission between the main chip 1a and the chip stack 2a. Among them, the chip stack 2a can be used as a high-bandwidth memory (HBM). In addition, the external signals, power supply, and ground of the main chip 1a, the chip stack 2a, and the chip stack 3a can be connected to the packaging organic substrate 5a through the conductive bonding structure 4a.

[0044] In the above 2.5D chip packaging structure, deep trench capacitors are provided in the interposer (not shown). However, due to the large area of the interposer and the relatively small area where deep trench capacitors need to be added, setting deep trench capacitors in the interposer will not only increase the manufacturing cost of the interposer but also affect the yield of the interposer.

[0045] In addition, for the 2.5D chip packaging structure, when deep trench capacitors are provided in the interposer, due to the relatively high stacking of the chip stack 2a and the chip stack 3a, the distance between the chip stack 2a, the chip stack 3a and the deep trench capacitors is relatively large, thus affecting the filtering performance of the deep trench capacitors.

[0046] Refer to Figure 1B , Figure 1B A 3D chip packaging structure provided for the related art. In this 3D chip packaging structure, the power supply of the chips (1b, 2b, 3b, 4b) needs an external capacitor to filter high-frequency noise. However, the path between the power supply of the chips (1b, 2b, 3b, 4b) and the external capacitor is too long, which will introduce additional resistance and inductance, thus affecting the filtering performance of the external capacitor.

[0047] To solve the above problems, the present application proposes a chip packaging structure. By arranging the capacitor structure 3 in the first chip on the side close to the internal power supply of the second chip 2, the distance between the capacitor structure 3 and the internal power supply of the second chip 2 is reduced, thereby reducing the coupling capacitance.

[0048] Figure 1 Schematic structural diagram of a chip packaging structure provided for an embodiment of the present application, as Figure 1As shown, the chip packaging structure provided by the present application includes: a first chip 1 and a second chip 2. Among them, the first chip 1 includes a substrate 20 and a capacitor structure 3, and at least one groove is provided on the surface of the substrate 20. The material of the substrate 20 includes silicon and quartz.

[0049] Furthermore, the capacitor structure 3 includes a plurality of capacitors stacked. In this setting method, by alternately stacking the first electrode layer, the capacitor dielectric layer, and the second electrode layer, a capacitor structure 3 of multiple layers of first electrode layer / capacitor dielectric layer / second electrode layer is formed.

[0050] For example, in one example, the capacitor structure 3 includes a multi-layer stacked structure of first electrode layer / capacitor dielectric layer / second electrode layer / capacitor dielectric layer / first electrode layer / capacitor dielectric layer / second electrode layer.

[0051] This structural design enables the capacitor structure 3 to have the characteristic of high capacitance density, which can significantly increase the capacitance value per unit area while maintaining the stability and reliability of the capacitor structure 3.

[0052] The above capacitor includes a first electrode layer and a second electrode layer arranged opposite to each other, and a capacitor dielectric layer located between the first electrode layer and the second electrode layer. The first electrode layer, the second electrode layer, and the capacitor dielectric layer all extend along the surface of the substrate 20 and inside the groove. A power supply is provided inside the second chip 2 to supply power to the second chip 2. Among them, the second chip 2 is electrically connected to the first chip 1.

[0053] In the embodiment of the present application, during the operation of the power supply in the second chip 2, the voltage on the power supply line will fluctuate or contain high-frequency noise, which will affect the normal operation of the second chip 2.

[0054] The present application sets the capacitor structure 3 in the first chip 1 on one side close to the internal power supply of the second chip 2 to reduce the distance D between the capacitor structure 3 and the internal power supply of the second chip 2. This setting method can not only reduce the coupling capacitance but also filter out the above high-frequency noise, thereby providing a power supply with low ripple, stable voltage, and no high-frequency noise for the second chip 2.

[0055] In addition, the capacitor structure 3 in the first chip 1 can be used to reduce the voltage drop inside the first chip 1. When the first chip 1 requires a large amount of current at a certain moment (for example, when the first chip 1 switches from the low-power mode to the high-power mode), if the power supply cannot respond to this rapidly changing demand in time, it will cause the voltage inside the first chip 1 to drop temporarily. At this time, the capacitor structure 3 in the first chip 1 can provide the additional current required by the first chip 1 within a short time, which helps to keep the voltage inside the first chip 1 stable and thus avoid the functional abnormality of the first chip 1 caused by the sudden drop of the internal voltage.

[0056] Furthermore, the capacitor structure 3 in the first chip 1 has a charge-discharge characteristic, that is, the capacitor structure 3 can store charge and release charge when needed to maintain the stability of the power supply in the first chip 1, thereby helping the first chip 1 to operate normally within the rated voltage range.

[0057] In the embodiment of the present application, an active layer 4a is disposed inside the first chip 1, and the active layer 4a is disposed on one side of the first chip 1 close to the capacitor structure 3. Further, the power supply is located in the active layer 4a. In one example, a transistor and an interconnection structure are also disposed in the active layer 4a.

[0058] In the second chip 2 provided in the embodiment of the present application, the power supply is set in the active layer 4a close to the side of the capacitor structure 3 to reduce the distance between the power supply in the second chip 2 and the capacitor structure 3 in the first chip 1, thereby reducing the coupling capacitance and providing the second chip 2 with a power supply with low ripple, stable voltage and no high-frequency noise.

[0059] Further, in the embodiment of the present application, the capacitor structure 3 is a decoupling capacitor, and the first electrode layer of the capacitor structure 3 receives a power signal, and the second electrode layer receives a ground signal. Alternatively, the second electrode layer receives a power signal, and the first electrode layer receives a ground signal. The material of the first electrode layer includes polysilicon, metal, and / or the material of the second electrode layer includes polysilicon, metal.

[0060] When the first electrode layer is connected to the power signal and the second electrode layer is connected to the ground signal, the decoupling capacitor can bypass the high-frequency noise on the power supply to the ground through the capacitor, thereby reducing the impact of the high-frequency noise on the first chip 1.

[0061] Conversely, when the second electrode layer is connected to the power signal and the first electrode layer is connected to the ground signal, the working principle is the same, but the polarity of the electrodes is opposite. The flexibility of this design allows adjustment according to specific circuit requirements, which will not be described in detail here.

[0062] In some embodiments, a metal part is also provided on the side of the substrate 20 away from the capacitor structure 3, one end of the metal part is electrically connected to the circuit interface in the active layer 3b, and the other end is used to electrically connect to the adapter board 200 through the rewiring structure to realize the transmission of electrical signals between the first chip 1 and the adapter board 200.

[0063] In the embodiment of the present application, the substrate 20 includes a redistribution structure, and the redistribution structure includes a first redistribution layer 6b and a second redistribution layer 6a. The first electrode layer is electrically connected to the second chip 2 through the first redistribution layer 6b, and the second electrode layer is electrically connected to the second chip 2 through the first redistribution layer 6b.

[0064] The first chip 1 further includes a plurality of metal vias 5 that penetrate the substrate 20 and are electrically connected to the second redistribution layer 6a, and the second redistribution layer 6a is electrically connected to the second chip 2.

[0065] Through the synergistic effect of the first redistribution layer 6b and the second redistribution layer 6a, the present application can achieve a more flexible wiring design to reduce the wiring length and resistance, thereby improving the stability of electrical connection and the signal transmission efficiency.

[0066] In some embodiments, as Figure 2 shown, the redistribution structure further includes a third redistribution layer 6c that is electrically connected to the metal via 5, and the third redistribution layer 6c is also used to electrically connect to the interposer 200.

[0067] Alternatively, in some other embodiments, the third redistribution layer 6c is electrically connected to the metal via 5, and the third redistribution layer 6c is used to electrically connect to the third chip 100. Among them, the third chip 100 and the first chip 1 are the same or different chips.

[0068] Furthermore, the first redistribution layer 6b, the second redistribution layer 6a, and the third redistribution layer 6c all include a conductive member 50, and the conductive member 50 can be a Cu / Sn / Cu structure. Alternatively, the conductive member 50 can be a Cu / Cu structure. This setting method can not only ensure that the distance between the capacitor structure 3 and the second chip 2 is closer, but also enable some input / output ports of the circuit in the second chip 2 to be electrically connected to the interposer 200 through the metal via 5 in the first chip 1.

[0069] Through the design of the redistribution structure (the first redistribution layer 6b, the second redistribution layer 6a, and the third redistribution layer 6c), the present application can integrate more functions within a limited chip packaging space, significantly improving the integration degree of the chip packaging structure.

[0070] Among them, the third redistribution layer 6c is electrically connected to the metal via 5 and can be further connected to the interposer 200 or the third chip 100. This design provides multiple electrical connection paths and can flexibly adapt to different circuit design requirements.

[0071] Furthermore, as Figure 2 shown, other chips 500 can also be electrically connected to the interposer 200.

[0072] In addition, as Figure 3 shown, the third redistribution layer 6c is used to connect to the third chip 100, and the third chip 100 can be the same as or different from the first chip 1. This setting method supports heterogeneous chip integration, enables different functional chips to work together, and further improves the overall performance of the system.

[0073] In the embodiments of the present application, the redistribution structure can reduce the parasitic effects in the signal transmission path to reduce the signal transmission delay and improve the integrity and reliability of signal transmission. The redistribution structure can also optimize the wiring path and connection method to reduce the stress concentration inside the chip package structure, thereby reducing the warping and thermal deformation that occur during the chip packaging process and improving the overall reliability of the chip package structure.

[0074] The redistribution structure can also simplify the wiring process and reduce the number of wirings to reduce the material and process costs during the chip packaging process and improve the production efficiency at the same time.

[0075] In the embodiments of the present application, an active layer 4b is provided inside the first chip 1, and the active layer 4b is provided at the bottom of the substrate 20. The power supply is located inside the active layer 4b to supply power to the first chip 1.

[0076] By arranging the power supply inside the active layer 4b at the bottom of the substrate 20 in the first chip 1, the present application provides a stable power supply for the first chip 1 to reduce the loss and interference during the power transmission process and avoid the wiring complexity and reliability problems that may be brought by the traditional external power supply method.

[0077] In the embodiments of the present application, the chip package structure further includes: a packaging layer 8 and an insulating layer 7. The material of the insulating layer 7 includes silicon nitride or silicon dioxide.

[0078] The packaging layer 8 is used to package the first chip 1. Among them, the setting of the packaging layer 8 can effectively protect the first chip 1 from the influence of the external environment, such as humidity, dust, mechanical shock, etc., thereby extending the service life of the first chip 1 and improving the working stability of the first chip 1 in a harsh environment.

[0079] Further, the first redistribution layer 6b and the second redistribution layer 6a pass through the packaging layer 8 and are electrically connected to the second chip 2.

[0080] The insulating layer 7 is provided on one side of the capacitor structure 3 close to the substrate 20 and extends along the surface of the substrate 20 and inside the groove. This setting method can effectively isolate the electrical interference between the capacitor structure 3 and other components, improve the insulation performance and stability of the capacitor structure 3, and further optimize the electrical characteristics of the capacitor structure 3.

[0081] In the embodiments of the present application, as Figure 1 shown, the first electrode layer 301 is located between the insulating layer 77 and the capacitor dielectric layer 302, and the second electrode layer 303 is located between the capacitor dielectric layer 302 and the packaging layer 8. Among them, the material of the capacitor dielectric layer includes hafnium dioxide, and the material of the packaging layer 8 includes silicon nitride.

[0082] By providing the encapsulation layer 8 and the insulation layer 7, this application can effectively encapsulate the first chip 1. At the same time, the first redistribution layer 6b and the second redistribution layer 6a pass through the encapsulation layer 8 to be electrically connected to the second chip 2. This structural arrangement realizes efficient electrical connection between chips and improves the reliability and stability of the encapsulation simultaneously.

[0083] In addition, the insulation layer 7 is disposed on the side of the capacitor structure 3 close to the substrate 20 and extends along the surface and inside the groove of the substrate 20. This arrangement not only enhances the electrical insulation performance of the capacitor structure 3 but also improves the overall mechanical stability through the extended structure of the insulation layer 7.

[0084] In the embodiment of this application, the orthographic projection of the first electrode layer on the substrate 20 covers the orthographic projection of the capacitor dielectric layer on the substrate 20, and the orthographic projection of the capacitor dielectric layer on the substrate 20 covers the orthographic projection of the second electrode layer on the substrate 20. Among them, the part of the first electrode layer that extends beyond the capacitor dielectric layer can provide additional structural support, reducing the damage to the dielectric layer caused by electric field concentration or mechanical stress, thereby improving the long-term stability of the capacitor.

[0085] In addition, the length of the first electrode layer is greater than that of the capacitor dielectric layer, which can effectively shield the interference of the external electric field, optimize the internal electric field distribution, reduce the electric field non-uniformity, and thus improve the performance of the capacitor.

[0086] The length of the capacitor dielectric layer is greater than that of the second electrode layer, making the electric field mainly concentrated within the dielectric layer, reducing the leakage of the edge electric field, and thus reducing the influence of the parasitic capacitance. At the same time, this design can reduce the interaction between the electrode and the external environment, further improving the performance and reliability of the capacitor.

[0087] Certainly, by reasonably designing the length ratio of the electrode and the dielectric layer, the effective overlapping area between the electrode and the dielectric layer can be increased, thereby improving the capacitance value and the charge storage capacity.

[0088] In the embodiment of this application, the two side edges of the first electrode layer are respectively set as the first connection part and the second connection part, and the first connection part and the second connection part are electrically connected to the second chip 2 through the first redistribution layer 6b; the two side edges of the second electrode layer are respectively set as the third connection part and the fourth connection part, and the third connection part and the fourth connection part are electrically connected to the second chip 2 through the first redistribution layer 6b.

[0089] This application effectively reduces the contact resistance during the electrical connection process by respectively setting the first connection part and the second connection part of the first electrode layer on the two side edges of the first electrode layer, setting the third connection part and the fourth connection part of the second electrode layer on the two side edges of the second electrode layer, and using the first redistribution layer 6b to be electrically connected to the second chip 2, so as to improve the stability and reliability of the electrical connection.

[0090] In addition, for the chip packaging structure provided by the present application, the use of the redistribution layer can achieve a more compact wiring layout to increase the packaging density of the chip. Moreover, the design of the first redistribution layer 6b and the second redistribution layer 6a can optimize the wiring path, reduce the spacing between wirings, and thus reduce the risk of short circuits.

[0091] The chip packaging structure provided by the present application can be applied to 2.5D packaging and 3D packaging to reduce the path length from the chip power supply to the capacitor in the packaging, thereby reducing the parasitic capacitance and parasitic inductance and improving the stability of the chip power supply.

[0092] In addition, the chip packaging structure provided by the present application can be used as an alternative to the deep trench capacitor in the large-sized interposer 200 to reduce the manufacturing complexity of the interposer 200 and the manufacturing cost of the interposer 200.

[0093] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application. The scope of the present application is defined by the claims and their equivalents.

Claims

1. A chip packaging structure, characterized in that: include: A first chip, the first chip comprising a substrate and a capacitor structure, at least one groove is arranged on the surface of the substrate; the capacitor structure comprises: a plurality of capacitors arranged in layers; The capacitor comprises a first electrode layer and a second electrode layer which are arranged opposite to each other, and a capacitor dielectric layer located between the first electrode layer and the second electrode layer; the first electrode layer, the second electrode layer and the capacitor dielectric layer all extend along the surface of the substrate and inside the groove; The second chip has a power supply disposed therein for supplying power to the second chip; the second chip is electrically connected to the first chip.

2. The chip packaging structure according to claim 1, characterized in that: An active layer is disposed inside the second chip, and the active layer is disposed on a side of the second chip close to the capacitor structure; The power source is located within the active layer.

3. The chip packaging structure according to claim 1, characterized in that: The capacitor structure is a decoupling capacitor; the first electrode layer receives a power signal, and the second electrode layer receives a ground signal; or, the second electrode layer receives a power signal, and the first electrode layer receives a ground signal.

4. The chip packaging structure according to claim 3, characterized in that: The substrate comprises a redistribution structure, the redistribution structure comprises a first redistribution layer and a second redistribution layer; the first electrode layer is electrically connected to the second chip through the first redistribution layer; The second electrode layer is electrically connected to the second chip through the first redistribution layer; The first chip further includes: A plurality of metal through holes penetrate the substrate and are electrically connected to the second redistribution layer, and the second redistribution layer is electrically connected to the second chip.

5. The chip packaging structure according to claim 4, characterized in that: The rewiring structure further includes a third rewiring layer; The third redistribution layer is electrically connected to the metal through hole, and the third redistribution layer is also used to electrically connect to the adapter board; or, The third redistribution layer is electrically connected to the metal through hole, and the third redistribution layer is used to electrically connect to the third chip; The third chip and the first chip are the same or different chips.

6. The chip packaging structure according to claim 5, characterized in that: An active layer is arranged inside the first chip, and the active layer is arranged at the bottom of the substrate; The power supply is located in the active layer and is used to supply power to the first chip.

7. The chip packaging structure according to claim 4, characterized in that: Also includes: A packaging layer, used to package the first chip; wherein the first redistribution layer and the second redistribution layer are electrically connected to the second chip through the packaging layer; An insulating layer is arranged on a side of the capacitor structure close to the substrate and extends along a surface of the substrate and inside the groove.

8. The chip packaging structure according to claim 7, characterized in that: The first electrode layer is located between the insulating layer and the capacitor dielectric layer; The second electrode layer is located between the capacitor dielectric layer and the packaging layer.

9. The chip packaging structure according to claim 8, characterized in that: The orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the capacitor dielectric layer on the substrate; The orthographic projection of the capacitor dielectric layer on the substrate covers the orthographic projection of the second electrode layer on the substrate.

10. The chip packaging structure according to claim 4, characterized in that: The two side edges of the first electrode layer are respectively configured as a first connection portion and a second connection portion, and the first connection portion and the second connection portion are electrically connected to the second chip through the first redistribution layer; The edges of both sides of the second electrode layer are respectively configured as a third connection portion and a fourth connection portion, and the third connection portion and the fourth connection portion are electrically connected to the second chip through the first redistribution layer.

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