Packaging method of packaging structure

Abstract

The invention discloses a packaging method of a packaging structure, and the method comprises the following steps: S1, preparing a storage chip, S2, preparing an intermediate layer and a sacrificial layer, S3, preparing a storage logic composite chip group through the technologies of surface mounting, arrangement, deposition, photoetching, etching and metal interconnection, and S4, packaging the storage logic composite chip group. S4, the storage logic composite chip set is installed on the substrate through the technologies of surface mounting, RDL manufacturing, UBM manufacturing, ball mounting and welding; S5, the storage logic composite chip set and the substrate are plastically packaged into a whole; the control chip is electrically connected with the outside through the intermediate layer, so that not only can the two sides of the control chip be stacked to obtain a larger storage space, but also a layer of a plurality of placement positions can be additionally obtained below the control chip, and therefore, the overall storage space and storage capability are greatly improved on the basis of a limited area; and meanwhile, different control chips and different storage chips are adapted, so that the number of the storage chips and the control chips and the design of a carrying structure can be conveniently carried out according to actual requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and specifically to a packaging method for a packaging structure. Background Art

[0002] CoWoS (Chip-on-Wafer-on-Substrate) is an advanced packaging technology. It integrates multiple chips using the Through-Silicon Via (TSV) technology. First, the chips are soldered to the silicon substrate through the back side, and then electrical connections are achieved.

[0003] CoWoS is applied to fields such as high-end logic chips, GPUs, deep learning accelerators, and data centers. However, it also faces challenges such as high-precision manufacturing, material adaptation, and testing difficulties.

[0004] During the packaging process of CoWoS, only one high-bandwidth memory chip can be connected to a high-speed data exchange port. This situation greatly limits the connection expansion between the GPU and the high-bandwidth memory chips. Due to the constraints of the packaging technology, it is difficult to connect more HBM chips to the same port, hindering the further improvement of system performance.

[0005] In addition, there are many problems with the interposer manufactured by the Through-Silicon Via technology. Its cost is high, resulting in high overall costs. There is an urgent need to develop low-cost alternative solutions. Moreover, this process faces many difficulties when processing a relatively thick thickness, with a large processing difficulty and it is difficult to meet the growing high-performance and diverse requirements, becoming a technical barrier that needs to be overcome urgently. Summary of the Invention

[0006] The purpose of the present invention is to provide a packaging method for a packaging structure to improve the overall working efficiency in view of the above existing problems and deficiencies.

[0007] The present invention solves at least one of the following technical problems:

[0008] (1) How to increase the number of extended connections of high-bandwidth memory chips to achieve a "one-to-many" capacity expansion structure;

[0009] (2) The interposer of the Through-Silicon Via technology has a high cost, and a low-cost alternative solution is needed;

[0010] (3) The interposer of the Through-Silicon Via technology cannot increase the thickness that can be processed, and has a small applicable range.

[0011] The purpose of the present invention can be achieved through the following technical solutions: A packaging method for a packaging structure, including the following steps:

[0012] Step S1: Prepare a storage chip through processes of glue coating, exposure, development, etching, grinding, electroplating, die bonding, and plastic encapsulation;

[0013] Step S2: Prepare an interposer through processes of electroplating, glue coating, exposure, development, etching, grinding, and plastic encapsulation;

[0014] Step S3: Prepare a storage logic composite chipset. The first layer of the storage logic composite chipset is the interposer and several groups of storage chips, and the second layer of the storage logic composite chipset is the control chip and several groups of storage chips;

[0015] Step S4: Mount each storage logic composite chipset onto a substrate through processes of chip mounting, RDL fabrication, UBM fabrication, ball planting, and soldering:

[0016] Step S5: Apply glue and perform plastic encapsulation on the product obtained in Step S4 to complete the encapsulation.

[0017] As a further solution of the invention, Step S1 includes the following steps:

[0018] Step S10: Respectively fabricate a storage cell layer and a control circuit layer through processes of glue coating, exposure, development, and etching;

[0019] Step S11: Group the storage cell layers by equidistant stacking and stack them into several stacks respectively, and electrically connect the storage cell layers in each stack;

[0020] Step S12: Stack a control circuit layer on both sides of each stack of storage cell layers in Step S11, and electrically connect the control circuit layer to the storage cell layer in the corresponding stack;

[0021] Step S13: Corresponding install a sacrificial layer prepared by TSV technology on the top of the control circuit layer of each stack, and electrically connect the sacrificial layer to the control circuit layer;

[0022] Step S14: Plastic encapsulate the sacrificial layer, the control circuit layer, and the storage cell layer into a whole, and then cut them into several storage chips, and arrange them orderly after passing the inspection.

[0023] As a further aspect of the invention, in step S10, the following steps are sequentially performed: First, through processes such as spin coating, exposure, development, and etching, through-silicon vias are fabricated in the memory cell layer and the control circuit layer respectively. Secondly, through processes such as spin coating, exposure, development, and etching, integrated circuits are fabricated on one side surface of each of the memory cell layer and the control circuit layer. Subsequently, through a grinding and thinning process, the other side surface is thinned respectively to form the required thickness and make the ends of the through-silicon vias flush with the chip surface. Subsequently, RDL layers are respectively provided on the other side surface of each of the memory cell layer and the control circuit layer. Finally, UBM layers and solder balls are provided on both side surfaces of each of the memory cell layer and the control circuit layer respectively.

[0024] As a further aspect of the invention, the surfaces where the integrated circuits of the memory cell layer and the control circuit layer are located are both arranged on the lower surface, and their respective RDL layers are both arranged on the upper surface.

[0025] As a further aspect of the invention, step S2 includes the following steps:

[0026] Step S20: Fabricate the first-level wiring layer through processes such as electroplating, exposure, development, and etching;

[0027] Step S21: Uniformly coat a layer of photoresist on the first-level wiring layer;

[0028] Step S22: On the photoresist, through exposure, development, and etching, form an array of copper pillar grooves;

[0029] Step S23: Through the array electroplating and filling of the copper pillar grooves, generate an array of copper pillars;

[0030] Step S24: Remove the photoresist while retaining the array of copper pillars;

[0031] Step S25: Encapsulate the product obtained in step S24 to form a layer of polymer layer;

[0032] Step S26: Perform a thinning process on the polymer layer until the tops of the array of copper pillars are exposed and the polymer layer is flush with the tops of each array of copper pillars;

[0033] Step S27: Repeat steps S21 to S26 until the height of the copper pillars in the array of copper pillars reaches the designed height and the polymer layer reaches the designed thickness;

[0034] Step S28: On the upper surfaces of the polymer layer and the array of copper pillars, fabricate the second-level wiring layer through processes such as electroplating, exposure, development, and etching;

[0035] Step S29: Cut into rectangular sheets of a quantitative size to complete the fabrication of the interposer.

[0036] As a further aspect of the invention, step S3 includes the following steps:

[0037] Step S300: Prepare a carrier board, obtain a carrier tray, and coat and form a double-sided adhesive layer on the carrier tray;

[0038] Step S301: Place an interposer on the double-sided adhesive layer, and arrange several rows of memory chips on both sides of the interposer;

[0039] Step S302: Encapsulate the interposer and the surrounding memory chips to form a first layer;

[0040] Step S303: Remove the carrier board;

[0041] Step S304: Perform a thinning process on the product obtained in Step S303 until the thinned surface is flush with the upper end faces of the copper pillars at the tops of the memory chips and the interposer;

[0042] Step S305: Perform a film laminating process on the surface of the product obtained in Step S304 that has undergone the thinning process, and apply a first protective film;

[0043] Step S306: Fabricate a first RDL layer on the side of the product obtained in Step S305 that is not covered with the first protective film through processes of electroplating, exposure, development, and etching;

[0044] Step S307: Apply a second protective film to the exposed surface of the first RDL layer fabricated in Step S306, and simultaneously remove the first protective film;

[0045] Step S308: Clean the surface of the product obtained in Step S307 after removing the first protective film, apply a deposition process to the cleaned surface, and further fabricate a second RDL layer through processes of electroplating, exposure, development, and etching;

[0046] Step S309: Apply UBM on the second RDL layer and perform a ball mounting process;

[0047] Step S310: Mount a control chip on the second RDL layer after the ball mounting process is completed, and determine the position of the control chip according to the position of the interposer;

[0048] Step S311: Mount memory chips on the second RDL layer after the ball mounting process is completed again. The memory chips on the second RDL layer are arranged in a triangular pattern with the two memory chips on the first RDL layer directly below it;

[0049] Step S312: Encapsulate to form an array of memory-logic composite chip groups;

[0050] Step S313: Cut and complete the fabrication of the memory-logic composite chip groups.

[0051] As a further aspect of the invention, in step S300, the surface flatness of the double-sided adhesive layer is at most five micrometers.

[0052] As a further aspect of the invention, in step S301, when arranging the memory chips, each sacrificial layer is located on top of the memory chip.

[0053] As a further aspect of the invention, the memory chips on each side of the control chip are evenly divided into several columns, and each column of memory chips is arranged in an S-shaped staggered distribution and electrically connected end to end.

[0054] As a further aspect of the invention, the control circuit layer is arranged on both sides of the memory cell layer, and there are several memory cell layers stacked coaxially in the vertical direction.

[0055] Advantages of the present invention:

[0056] (1) During operation, the control chip is lifted one layer by the interposer, enabling the memory chips to not only be stacked on both sides of the control chip to obtain a larger storage space, but also obtaining a number of placement positions in an additional layer below the control chip, thereby greatly improving the overall storage space and storage capacity on the basis of a limited area;

[0057] (2) During operation, the communication rate of data is increased through the staggered series structure and the shortened connection distance, further promoting the improvement of the overall data throughput and bandwidth;

[0058] (3) During operation, the distance of data communication is further reduced and the communication rate is increased through the stacking of the self-structure of the memory chip. With the control circuit layers on both sides, each memory chip has the ability to communicate with the outside world. The memory chip is protected by the sacrificial layer, enabling the memory chip to be undamaged in the thinning process, and at the same time facilitating the adjustment of the overall thickness and structure, improving the scope of application;

[0059] (4) During operation, through the setting of the copper pillar array, the first rewiring layer, and the second rewiring layer, not only can the overall data communication rate be improved, but also different control chips and different memory chips can be adapted, so as to design the number and mounting structure of the memory chips and control chips according to actual needs, promoting the scope of application. The manufacturing cost of the interposer is reduced through the polymer layer, and at the same time the size of the interposer can be flexibly adjusted;

[0060] (5) During operation, the overall electrical connection structure is reorganized and arranged through the first RDL layer and the second RDL layer, greatly expanding the communication channels between the memory chips, the control chip, and the interposer and arranging them more reasonably, further improving the overall communication rate, and improving the stability of the chip assembly process and the yield of the product;

[0061] (6) During operation, first, the storage chips and the interposer are prepared in batches synchronously. Subsequently, the position of the control chip is elevated through the interposer, so that the storage logic composite chip group has a three-dimensional distribution structure that is more complex than the relative planar distribution, thereby greatly increasing the communication performance and storage performance of the storage logic composite chip group, and expanding the storage capacity, processing performance, and interaction performance of the storage logic composite chip group. Description of the Drawings

[0062] For the convenience of those skilled in the art to understand, the present invention will be further described below in conjunction with the accompanying drawings.

[0063] Figure 1 It is a schematic diagram of the overall process flow of the packaging method of the present invention;

[0064] Figure 2 It is a schematic diagram of the overall process flow of step S1 in the packaging method of the present invention;

[0065] Figure 3 It is a schematic diagram of the preparation process flow of the storage unit layer in step S10 of the packaging method of the present invention;

[0066] Figure 4 It is a schematic diagram of the overall process flow of step S2 in the packaging method of the present invention;

[0067] Figure 5 It is a schematic diagram of the overall process flow of step S3 in the packaging method of the present invention;

[0068] Figure 6 It is a side view of the overall structure after the storage logic composite chip group and the substrate are assembled in the present invention;

[0069] Figure 7 It is a side view of the overall structure of the storage chip in the present invention;

[0070] Figure 8 It is a side view of the overall structure of the interposer in the present invention;

[0071] Figure 9 It is a schematic diagram of the process flow from step S300 to S305 in the present invention;

[0072] Figure 10 It is a schematic diagram of the process flow from step S305 to S310 in the present invention;

[0073] Figure 11 It is a schematic diagram of the process flow from step S310 to S313 in the present invention;

[0074] Figure 12 It is a side view of the overall structure of the storage logic composite chip group in the present invention;

[0075] In the figure: 100, substrate; 200, memory chip; 201, memory cell layer; 202, control circuit layer; 203, sacrificial layer; 300, interposer; 301, first redistribution layer; 302, copper pillar array; 303, polymer layer; 304, second redistribution layer; 400, memory logic composite chipset; 401, first RDL layer; 402, second RDL layer; 500, control chip; 900, carrier board; 901, carrier tray; 902, double-sided adhesive layer; 903, first protective film; 904, second protective film. Detailed implementation manners

[0076] To further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the following, in combination with the accompanying drawings and preferred embodiments, details the specific implementation manners, structures, features, and their effects of the present invention as follows.

[0077] Please refer to Figure 1 , a packaging method for a packaging structure, comprising the following steps:

[0078] Step S1: Prepare the memory chip 200 through processes such as glue coating, exposure, development, etching, grinding, electroplating, soldering, and encapsulation;

[0079] Step S2: Prepare the interposer 300 through processes such as electroplating, glue coating, exposure, development, etching, grinding, and encapsulation;

[0080] Step S3: Prepare the memory logic composite chipset 400. The first layer of the memory logic composite chipset 400 is the interposer 300 and several groups of memory chips 200, and the second layer of the memory logic composite chipset 400 is the control chip 500 and several groups of memory chips 200;

[0081] Step S4: Mount each memory logic composite chipset 400 onto the substrate 100 through processes such as mounting and soldering:

[0082] Step S5: Perform dispensing and encapsulation on the product obtained in step S4 to complete the encapsulation.

[0083] When this embodiment works, first, the memory chip 200 and the interposer 300 are prepared synchronously and in batches. Subsequently, the position of the control chip 500 is elevated through the interposer 300, so that the memory logic composite chipset 400 has a three-dimensional distribution structure that is more complex than the planar distribution, thereby greatly increasing the communication performance and storage performance of the memory logic composite chipset 400, and expanding the storage capacity, processing performance, and interaction performance of the memory logic composite chipset 400.

[0084] Please refer to Figure 2 , step S1 includes the following steps:

[0085] Step S10: Fabricate the memory cell layer 201 and the control circuit layer 202 through the processes of glue coating, exposure, development, and etching respectively;

[0086] Step S11: Group the memory cell layers 201 by equidistant stacking and stack them into several stacks respectively, and electrically connect the respective memory cell layers 201 in each stack;

[0087] Step S12: Stack and arrange the control circuit layers 202 on both sides of each stack of memory cell layers 201 in Step S11, and electrically connect the control circuit layer 202 to the memory cell layer 201 in the corresponding stack;

[0088] Step S13: Correspondingly install the sacrificial layer 203 prepared by the TSV technology on the top of the control circuit layer 202 of each stack, and electrically connect the sacrificial layer 203 to the control circuit layer 202;

[0089] Step S14: Seal the sacrificial layer 203, the control circuit layer 202, and the memory cell layer 201 into a whole, and then cut them into several memory chips 200. After passing the inspection, they are arranged in an orderly manner.

[0090] Please refer to Figure 3 , in Step S10, the following steps are sequentially carried out:

[0091] First, fabricate the through-silicon vias on the memory cell layer 201 through the processes of glue coating, exposure, development, and etching. Secondly, fabricate the integrated circuits on one side surface of the memory cell layer 201 through the processes of glue coating, exposure, development, and etching. Thirdly, respectively thin the other side surface of the memory cell layer 201 through a grinding and thinning process to make the required thickness and make the ends of the through-silicon vias flush with the chip surface. Subsequently, set the RDL layer on the other side surface of the memory cell layer 201. Finally, set the UBM layer and solder balls on both side surfaces of the memory cell layer 201, thereby completing the preparation of the memory cell layer 201;

[0092] At the same time, the logic circuit layer 202 is also fabricated through the above steps;

[0093] When this embodiment works, the fabricated memory chips 200 are stacked and arranged in the manner described in this application, which improves the average quality and storage capacity of the memory chips 200. At the same time, through the application of the through-silicon vias, firstly, high-speed information transmission between each memory chip 200 itself and the outside is realized. Secondly, high-speed information transmission and mutual control between multiple memory chips are realized through the interconnected memory chips 200. Moreover, it is convenient for the control chip 500 to flexibly control each memory chip 200, perform high-speed information transmission, and make calls.

[0094] Please refer to Figure 4 , Step S2 includes the following steps:

[0095] Step S20: Fabricate the first-layer wiring layer 301 through processes of electroplating, exposure, development, and etching.

[0096] Step S21: Uniformly coat a layer of photoresist on the first-layer wiring layer 301.

[0097] Step S22: Perform exposure, development, and etching on the photoresist to fabricate an array of copper pillar grooves.

[0098] Step S23: Through electroplating and filling in the array of copper pillar grooves, generate a copper pillar array 302.

[0099] Step S24: Remove the photoresist while retaining the copper pillar array 302.

[0100] Step S25: Encapsulate the product obtained in Step S24 to form a one-layer polymer layer 303.

[0101] Step S26: Perform a thinning process on the polymer layer 303 until the top of the copper pillar array 302 is exposed and the polymer layer 303 is flush with the top of each copper pillar array 302.

[0102] Step S27: Repeat Steps S21 to S26 until the height of the copper pillars in the copper pillar array 302 reaches the designed height and the polymer layer 303 reaches the designed thickness.

[0103] Step S28: On the upper surfaces of the polymer layer 303 and the copper pillar array 302, fabricate the second-layer wiring layer 304 through processes of electroplating, exposure, development, and etching.

[0104] Step S29: Cut into cuboid sheets of a quantitative size to complete the fabrication of the interposer 300.

[0105] During the operation of this embodiment, the object to be carried can be quickly peeled off from the fabricated interposer 300 without damaging the first-layer wiring layer 301 and the second-layer wiring layer 304. Meanwhile, by using photoresist and polymer glue, the fabrication of a silicon dielectric layer is avoided, reducing the production cost and improving the overall yield. Moreover, since the silicon material is replaced, the thickness of itself can be flexibly increased or decreased, improving the scope of application.

[0106] Please refer to Figure 5 and Figures 9 to 11 , Step S3 includes the following steps:

[0107] Step S300: Prepare a carrier board 900, obtain a carrier tray 901, and coat and form a double-sided adhesive layer 902 on the carrier tray 901.

[0108] Step S301: Place the interposer 300 on the double-sided adhesive layer 902 and arrange several rows of memory chips 200 on both sides of the interposer 300.

[0109] Step S302: Encapsulate the interposer 300 and the surrounding memory chips 200 to form a first layer;

[0110] Step S303: Remove the carrier 900;

[0111] Step S304: Perform a thinning process on the product obtained in Step S303 until the thinned surface is flush with the upper end faces of the copper pillars at the tops of the memory chips 200 and the interposer 300;

[0112] Step S305: Apply a film laminating process to the surface of the product obtained in Step S304 that has undergone the thinning process, and apply a first protective film 903;

[0113] Step S306: Fabricate a first RDL layer 401 on the side of the product obtained in Step S305 that is not covered with the first protective film 903 through processes of electroplating, exposure, development, and etching;

[0114] Step S307: Apply a second protective film 904 to the exposed surface of the first RDL layer 401 fabricated in Step S306, and at the same time remove the first protective film 903;

[0115] Step S308: Clean the surface of the product obtained in S307 after removing the first protective film 903, apply a deposition process to the cleaned surface, and further fabricate a second RDL layer 402 through processes of electroplating, exposure, development, and etching;

[0116] Step S309: Apply UBM on the second RDL layer 402 and perform a ball mounting process;

[0117] Step S310: Mount the control chip 500 on the second RDL layer 402 after completing the ball mounting process, and determine the position of the control chip 500 according to the position of the interposer 300;

[0118] Step S311: Mount the memory chips 200 again on the second RDL layer 402 after completing the ball mounting process. The memory chips 200 on the second RDL layer 402 and the two memory chips 200 on the first RDL layer 401 directly below them are arranged in a triangular pyramid structure;

[0119] Step S312: Apply glue to the second RDL layer 402 of the product obtained in Step S311, and complete the encapsulation of the memory logic composite chip group 400;

[0120] Step S313: Perform dicing on the encapsulated memory logic composite chip group 400 to form single memory logic composite chip groups 400.

[0121] In Step S300, the surface flatness of the double-sided adhesive layer 902 is at most five micrometers;

[0122] In step S301, when arranging the memory chips 200, each sacrificial layer 203 is located at the top of the memory chip 200.

[0123] Please refer to Figures 6 to 8 and Figure 12 : The packaging structure of the present invention includes a substrate 100. A memory logic composite chipset 400 is mounted and encapsulated on the upper surface of the substrate 100. A middle layer 300 is provided in the middle of the bottom layer of the memory logic composite chipset 400. A plurality of memory chips 200 are provided on both sides of the middle layer 300. A control chip 500 is provided on the top of the middle layer 300. A plurality of memory chips 200 are provided on both sides of the control chip 500. The memory chips 200 close to the control chip 500 are electrically connected to the control chip 500. The control chip 500 is electrically connected to the outside through the middle layer 300.

[0124] In an embodiment of the present invention, the interfaces of the control chip 500 are divided into three parts. The interfaces on both sides are symmetric with respect to the middle layer 300. The memory chips 200 on each side of the control chip 500 are evenly divided into several columns. The center line of the orthographic projection of each column of memory chips 200 on the substrate 100 is orthogonally arranged with the center line of the orthographic projection of the middle layer 300 on the substrate 100. The number of interfaces on each side is the same as the number of columns of memory chips 200 on the same side. Each column of memory chips 200 is arranged in an S-shaped staggered distribution and is electrically connected end to end.

[0125] When working in this embodiment, the control chip 500 is lifted by one layer through the middle layer 300, so that the memory chips 200 can not only be stacked on both sides of the control chip 500 to obtain a larger storage space, but also obtain a number of placement positions on an additional layer below the control chip 500, thereby greatly improving the overall storage space and storage capacity on the basis of a limited area. At the same time, the data communication rate is increased through the staggered series structure and the shortened connection distance, further promoting the improvement of the overall data throughput and bandwidth.

[0126] Please refer to Figure 6 , the memory chip 200 includes a memory cell layer 201, a control circuit layer 202 and a sacrificial layer 203. The control circuit layer 202 is provided on both sides of the memory cell layer 201. A plurality of memory cell layers 201 are provided and are coaxially stacked in the vertical direction. A sacrificial layer 203 is provided above the control circuit layer 202 at the top. Electrical connections are maintained between the sacrificial layer 203, the control circuit layer 202 and the memory cell layer 201.

[0127] The surfaces where the integrated circuits of the memory cell layer 201 and the control circuit layer 202 are located are both provided on the lower surface, and their respective RDL layers are provided on the upper surface.

[0128] During the operation of this embodiment, the data communication distance is further reduced and the communication rate is increased by stacking. The control circuit layers 202 on both sides enable each storage chip 200 to have the ability to communicate with the outside world on both sides. The sacrificial layer 203 protects the storage chip 200, enabling the storage chip 200 to be undamaged during the thinning process and maintain stable communication ability. At the same time, it is convenient to adjust the overall thickness and structure, improving the scope of application.

[0129] Please refer to Figure 7 , the interposer 300 includes a polymer layer 303. A copper pillar array 302 is disposed within the polymer layer 303. The upper and lower surfaces of the polymer layer 303 are respectively provided with a first redistribution layer 301 and a second redistribution layer 304, and the two ends of the copper pillars of the copper pillar array 302 are electrically connected to the first redistribution layer 301 and the second redistribution layer 304 respectively;

[0130] During the operation of this embodiment, through the settings of the copper pillar array 302, the first redistribution layer 301, and the second redistribution layer 304, not only can the overall data communication rate be improved, but also it can be adapted to different control chips 500 and different storage chips 200, facilitating the design of the number and mounting structure of the storage chips 200 and control chips 500 according to actual requirements, promoting the scope of application. Through the polymer layer 303, the manufacturing cost of the interposer 300 can be reduced, and at the same time, the size of the interposer 300 can be flexibly adjusted.

[0131] Please refer to Figure 8 , the storage chips 200 of the storage logic composite chip group 400 are electrically connected to each other through a first RDL layer 401 and a second RDL layer 402 respectively. The control chip 500 is electrically connected to the interposer 300 through the second RDL layer 402, and the interposer 300 is electrically connected to the substrate 100 through the first RDL layer 401;

[0132] During the operation of this embodiment, through the first RDL layer 401 and the second RDL layer 402, the overall electrical connection structure is reorganized and arranged, greatly expanding and more reasonably arranging the communication channels between the storage chips 200, the control chip 500, and the interposer 300, further improving the overall communication rate, and enhancing the overall structural strength and heat dissipation efficiency.

[0133] During the operation of the present invention, the control chip 500 is lifted one layer by the interposer 300, enabling the storage chips 200 to not only stack on both sides of the control chip 500 to obtain a larger storage space, but also obtain a number of placement positions in an additional layer below the control chip 500, thereby greatly improving the overall storage space and storage capacity on the basis of a limited area;

[0134] The communication rate of data is improved by means of an interleaved series connection structure and a shortened connection distance, which further promotes the improvement of the overall data throughput and bandwidth;

[0135] The distance of data communication is further reduced and the communication rate is increased by stacking the structure of the storage chip 200 itself. The control circuit layers 202 on both sides enable both sides of each storage chip 200 to have the ability to communicate with the outside world. The storage chip 200 is protected by the sacrificial layer 203, so that the storage chip 200 can be undamaged in the thinning process and maintain a stable communication ability. At the same time, it is convenient to adjust the overall thickness and structure, improving the scope of application;

[0136] By setting the copper pillar array 302, the first rewiring layer 301 and the second rewiring layer 304, the overall data communication rate can be improved, and at the same time, it can be adapted to different control chips 500 and different storage chips 200, so as to facilitate the design of the number and mounting structure of the storage chips 200 and the control chips 500 according to actual needs, promoting the scope of application. The manufacturing cost of the interposer 300 is reduced by the polymer layer 303, and at the same time, the size of the interposer 300 can be flexibly adjusted;

[0137] By reorganizing and arranging the overall electrical connection structure through the first RDL layer 401 and the second RDL layer 402, the communication channels between the storage chip 200, the control chip 500 and the interposer 300 are greatly expanded and more reasonably arranged, further improving the overall communication rate, and enhancing the overall structural strength and heat dissipation efficiency;

[0138] By raising the position of the control chip 500 through the interposer 300, the storage logic composite chip group 400 has a three-dimensional distribution structure that is more complex than the relative planar distribution, thus greatly increasing the communication performance and storage performance of the storage logic composite chip group 400, and expanding the storage capacity, processing performance and interaction performance of the storage logic composite chip group 400;

[0139] The carrier object can be quickly peeled off from the manufactured interposer 300 or sacrificial layer 203 without damaging the first rewiring layer 301 and the second rewiring layer 304. At the same time, by using photoresist and polymer glue, the production of the silicon dielectric layer is avoided, the production cost is reduced, the overall yield is improved, and since the silicon material is replaced, the thickness can be flexibly increased or decreased, improving the scope of application.

[0140] The above are only the preferred embodiments of the present invention and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments with equivalent changes within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A packaging method for a packaging structure, characterized in that: The following steps are involved: Step S1: preparing a memory chip (200); Step S2: preparing an intermediate layer (300); Step S3: preparing a storage logic composite chipset (400), wherein the first layer of the storage logic composite chipset (400) is an intermediate layer (300) and a plurality of groups of storage chips (200), and the second layer of the storage logic composite chipset (400) is a control chip (500) and a plurality of groups of storage chips (200); Step S4: Mounting the storage logic complex chipset (400) on the substrate (100): Step S5: Glue dispensing and plastic sealing to complete the packaging.

2. The packaging method of a packaging structure according to claim 1, characterized in that: The step S1 comprises the following steps: Step S10: manufacturing a storage unit layer (201) and a control circuit layer (202) respectively; Step S11: stacking the storage unit layers (201) in groups and electrically connecting them; Step S12: stacking the control circuit layer (202) and electrically connecting them; Step S13: installing the sacrificial layer (203) accordingly and electrically connecting them; Step S14: Plastic encapsulation, followed by cutting into memory chips (200), inspection and arrangement.

3. The packaging method of a packaging structure according to claim 2, characterized in that: In step S10, the following steps are performed in sequence: first, silicon through vias are made on the storage unit layer 201 and the control circuit layer 202 by means of glue coating, exposure, development, and etching processes, and then integrated circuits are made on one side of the storage unit layer 201 and the control circuit layer 202 by means of glue coating, exposure, development, and etching processes, and then the other side is thinned by means of a grinding and thinning process to produce the required thickness and to make the end of the silicon through via flush with the chip surface, and then an RDL layer is set on the other side of the storage unit layer 201 and the control circuit layer 202, and finally a UBM layer and solder balls are set on both sides of the storage unit layer 201 and the control circuit layer 202.

4. The packaging method of a packaging structure according to claim 2, characterized in that: The surfaces where the integrated circuits of the storage unit layer (201) and the control circuit layer (202) are located are both arranged on the lower surface, and the RDL layers of the respective ones are both arranged on the upper surface.

5. The packaging method of a packaging structure according to claim 1, characterized in that: The step S2 comprises the following steps: Step S20: manufacturing a first redistribution layer (301); Step S21: uniformly coating a layer of photoresist on the first redistribution layer (301); Step S22: exposing, developing, and etching on the photoresist to form copper column grooves in an array; Step S23: electroplating and filling the array of copper pillar grooves to generate a copper pillar array (302); Step S24: removing the photoresist while retaining the copper pillar array (302); Step S25: plastic-sealing the product obtained in step S24 to form a polymer layer (303); Step S26: thinning until the copper pillar array (302) is exposed; Step S27: repeating steps S21 to S26 until the designed thickness is reached; Step S28: fabricating a second redistribution layer (304); Step S29: cutting to complete the production of the intermediate layer (300).

6. The packaging method of a packaging structure according to claim 1, characterized in that: The step S3 comprises the following steps: Step S300: prepare a carrier plate (900), obtain a carrier disc (901), and apply and form a double-sided adhesive layer (902) on the carrier disc (901); Step S301: placing an intermediary layer (300) on the double-sided adhesive layer 902, and arranging a plurality of rows of memory chips (200) on both sides of the intermediary layer (300); Step S302: plastic-encapsulating the intermediate layer (300) and the surrounding memory chips (200) to form a first-layer chipset; Step S303: removing the carrier (900); Step S304: performing a thinning process on the product obtained in step S303 until the thinned surface is flush with the upper end surfaces of the copper pillars on the top of the memory chip (200) and the top of the interposer (300); Step S305: performing a film lamination process on the surface of the product obtained in step S304 after the thinning process, and applying a first protective film (903); Step S306: The first RDL layer (401) is formed on the side of the product obtained in step S305 that is not pasted with the first protective film (903) by electroplating, exposure, development, and etching processes; Step S307: applying a second protective film (904) to the exposed surface of the first RDL layer (401) made in step S306, and removing the first protective film (903); Step S308: cleaning the surface of the product obtained in S307 after removing the first protective film (903), applying a deposition process on the cleaned surface, and further manufacturing a second RDL layer (402) through electroplating, exposure, development, and etching processes; Step S309: applying UBM on the second RDL layer (402) and performing a ball implantation process; Step S310: mounting a control chip (500) on the second RDL layer (402) after the ball implantation process is completed, and determining the position of the control chip (500) according to the position of the intermediate layer (300); Step S311: mounting the memory chip (200) again on the second RDL layer (402) after the ball implantation process is completed, the memory chip (200) on the second RDL layer (402) and the two memory chips (200) on the first RDL layer (401) directly below the memory chip (200) on the second RDL layer (402) are arranged in a herringbone structure; Step S312: plastic packaging to form an array of storage logic complex chipset (400); Step S313: Slice and complete the production of the storage logic complex chipset (400).

7. The packaging method of a packaging structure according to claim 6, characterized in that: In the step S300, the surface flatness of the double-sided adhesive layer (902) is at most five micrometers.

8. The packaging method of a packaging structure according to claim 6, characterized in that: In the step S301, when the memory chips (200) are arranged, each sacrificial layer (203) is located on the top of the memory chip (200).

9. The packaging method of a packaging structure according to claim 6, characterized in that: The memory chips (200) on each side of the control chip (500) are evenly divided into a plurality of columns, and the memory chips (200) in each column are staggeredly distributed in an S shape and are electrically connected end to end.

10. The packaging method of a packaging structure according to claim 2, characterized in that: The control circuit layer (202) is arranged on both sides of the storage unit layer (201), and the storage unit layer (201) is provided with a plurality of storage unit layers (201) in a coaxial stacking structure in the vertical direction.

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