Silicon controlled rectifier device

Abstract

A silicon controlled rectifier device is disclosed. A silicon controlled rectifier (SCR) apparatus, structure, and associated methods. The SCR comprises a first silicon outer layer, a second silicon outer layer, a first silicon middle layer and a second silicon middle layer. The first silicon outer layer is coupled to the first silicon intermediate layer. The first silicon interlayer is coupled to the second silicon interlayer. The second silicon intermediate layer is coupled to the second silicon outer layer. The SCR also includes a cathode terminal coupled to the first silicon outer layer, and a gate terminal coupled to the first silicon intermediate layer. One or more doped regions are formed in the second silicon outer layer. The anode terminal is coupled to at least one of the second silicon outer layer and the one or more doped regions.

Description

Technical Field

[0001] The present disclosure generally relates to the field of solid-state current control devices, and in particular, to silicon controlled rectifier devices. Background Art

[0002] A silicon controlled rectifier (SCR) includes four layers and provides current control. It can be referred to as a type of thyristor. Some SCRs are used in systems that require control of high power and / or high voltage. For example, an SCR can be used in medium- and high-voltage alternating current (AC) power control systems (e.g., power regulators, motor controllers, etc.). In addition, an SCR can be used to rectify high-power AC signals in high-voltage direct current (DC) power transmission. Welding and other similar processes rely on SCRs for current control. An SCR can also be used as a switch.

[0003] Some SCRs can be designed to be unidirectional, where current conducts only in one direction. A positive current entering the gate of an SCR can trigger the operation of the SCR, which is different from triodes for alternating current (TRIACs) used for alternating current, which can be triggered using positive or negative current applied to their gate electrodes. However, the rated current of traditional SCRs decreases, current leakage increases, and they are vulnerable to low breakdown voltage, which degrades the performance of the SCR. Summary of the Invention

[0004] The following summary is provided to introduce a selection of concepts in a simplified form that will be further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to assist in determining the scope of the claimed subject matter.

[0005] In some embodiments, the current subject matter relates to a silicon controlled rectifier (SCR) device. The SCR can include a first silicon outer layer, a second silicon outer layer, a first silicon intermediate layer, and a second silicon intermediate layer. The first silicon outer layer can be coupled to the first silicon intermediate layer. The first silicon intermediate layer can be coupled to the second silicon intermediate layer. The second silicon intermediate layer can be coupled to the second silicon outer layer. The SCR can further include a cathode terminal coupled to the first silicon outer layer and a gate terminal coupled to the first silicon intermediate layer. One or more doped regions can be formed in the second silicon outer layer. The anode terminal can be coupled to the second silicon outer layer and at least one of the one or more doped regions.

[0006] In some embodiments, the present subject matter may include one or more of the following optional features. The first silicon outer layer may be coupled to the first silicon intermediate layer via a first junction. The first silicon intermediate layer may be coupled to the second silicon intermediate layer via a second junction. The second silicon intermediate layer may be coupled to the second silicon outer layer via a third junction.

[0007] In some embodiments, at least a portion of the first silicon outer layer may be doped using at least one dopant of a plurality of dopants. One or more doped regions may be doped using at least another dopant of the plurality of dopants. The at least one dopant may be the same as the at least another dopant. Alternatively or additionally, the at least one dopant may be different from the at least another dopant. At least one dimension of the at least one doped region may be less than at least one corresponding dimension of the second silicon outer layer.

[0008] In some embodiments, the device may be at least one of the following: a PNPN thyristor structure, an NPNP thyristor structure, and any combination thereof.

[0009] In some embodiments, the first outer silicon layer may be an N+ layer. The first intermediate silicon layer may be a P layer. The second intermediate silicon layer may be an N- layer. The second outer silicon layer may be a P layer. The one or more doped regions may be N+ regions.

[0010] In some embodiments, the present subject matter relates to a method for manufacturing a thyristor device. The method may include providing a first silicon outer layer, a second silicon outer layer, a first silicon intermediate layer, and a second silicon intermediate layer; coupling the first silicon outer layer to the first silicon intermediate layer via a first junction, coupling the first silicon intermediate layer to the second silicon intermediate layer via a second junction, and coupling the second silicon intermediate layer to the second silicon outer layer via a third junction; coupling a cathode terminal to the first silicon outer layer and coupling a gate terminal to the first silicon intermediate layer; shortening the second silicon outer layer using one or more predetermined dimensions to generate a shortened second silicon outer layer; forming one or more doped regions in the second silicon outer layer; and coupling an anode terminal to the second silicon outer layer and at least one of the one or more doped regions.

[0011] Details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the following description. Other features and advantages of the subject matter described herein will be apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate certain aspects of the subject matter disclosed herein and, together with the description, help explain some of the principles associated with the disclosed embodiments. In the drawings,

[0013] Figure 1 an exemplary thyristor is shown;

[0014] Figure 2 shows another exemplary thyristor rectifier;

[0015] Figure 3 shows an exemplary thyristor rectifier according to some embodiments of the present subject matter;

[0016] Figure 4a -c shows various example patterns of dopant materials for an outer silicon layer portion and / or a doped region according to some embodiments of the present subject matter;

[0017] Figure 5a -b shows an example current-voltage graph; and

[0018] Figure 6 shows an exemplary process according to some embodiments of the present subject matter.

[0019] The drawings are not necessarily to scale. The drawings are merely illustrative and are not intended to depict specific parameters of the present disclosure. The drawings are intended to depict exemplary embodiments of the present subject matter and should not therefore be considered as limiting the scope. In the drawings, the same numbers represent the same elements.

[0020] In addition, for clarity of illustration, some elements in some of the figures may be omitted and / or not drawn to scale. Cross-sectional views may be in the form of "slices" and / or "close-up" cross-sectional views, and for clarity of illustration, some background lines are omitted that would otherwise be visible in a "true" cross-sectional view. In addition, for clarity, some reference numerals may be omitted in some of the figures. Detailed Description

[0021] Various methods according to the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the systems and methods are shown. Devices, systems, components, etc. may be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present subject matter to those skilled in the art.

[0022] To address these and potentially other deficiencies of current available solutions, one or more embodiments of the present subject matter relate to methods, systems, articles, etc. that can provide, among other possible advantages, a thyristor rectifier device that can be configured to effectively reduce current leakage and provide a hard breakdown for the SCR device, particularly in high breakdown device applications.

[0023] A Silicon Controlled Rectifier (SCR) is typically made of silicon and is used to rectify or convert alternating current (AC) to direct current (DC). SCRs can be used to regulate power, convert, and perform various other functions. SCRs can handle high currents and high voltages, which are useful in various industrial applications.

[0024] The SCR includes three terminals - an anode (A), a cathode (K), and a gate (G). The SCR can be turned on (ON) or off (OFF) by controlling one or more biasing conditions and / or the input to the gate terminal. The SCR is constructed as a four-layer semiconductor device forming an NPNP or PNPN structure. Given these structures, the SCR also includes three junctions J1, J2, and J3. The anode terminal is the positive electrode and is coupled to the P-layer of the structure. The cathode terminal is the negative electrode and is coupled to the N-layer. Finally, the gate terminal is the control terminal.

[0025] The SCR can operate in one or more different modes, depending on the polarity of the voltage and the input to the gate terminal. The operating modes of the SCR can include forward blocking mode, forward conduction mode, and reverse blocking mode. In the forward blocking mode, a positive voltage is applied to the anode terminal and a negative voltage is applied to the cathode terminal. The gate terminal is off and no input signal is applied to it. When the voltage is applied, junctions J1 and J3 become forward biased, and junction J2 becomes reverse biased. Since J2 is reverse biased, the width of the depletion region increases, thus preventing conduction and allowing a small amount of current to flow from J1 to J3.

[0026] In the forward blocking mode, junction J2 becomes depleted due to avalanche breakdown, which is caused by applying a voltage that reaches an increased amount of the breakdown voltage of the SCR. As a result of the avalanche breakdown, the SCR will allow current to flow through it, causing the SCR to be forward biased; otherwise, no current flows through the SCR.

[0027] In the forward conduction mode, the SCR is in the on (ON) state and thus conducts current through it. The SCR can conduct current after the applied forward bias voltage increases beyond the breakdown voltage or a positive voltage is applied to the gate terminal. After a forward bias voltage is applied between the anode and cathode terminals, the J2 junction becomes depleted due to avalanche breakdown, resulting in the SCR conducting; however, this also causes a shortening of the SCR's lifespan.

[0028] In the reverse blocking mode, a positive voltage is applied to the negative cathode terminal and a negative voltage is applied to the positive anode terminal, while no signal is applied to the gate terminal. The application of such a signal causes junctions J1 and J3 to become reverse biased, while junction J2 is forward biased. Therefore, no current flows through the SCR. However, due to the drift charge carriers in the forward biased J2 junction, a small amount of current leakage may occur, but such an amount is not sufficient to turn the SCR on (ON).

[0029] Figure 1 An exemplary silicon controlled rectifier (SCR) 100 is shown. The SCR 100 may include a four-layer structure, which includes an outer N layer 102 and an outer P layer 108, as well as an intermediate P layer 104 and an intermediate N layer 106. The outer layers 102, 108 may be heavily doped and the intermediate layers 104, 106 may be lightly doped. Layer 108 and layer 106 may be separated by a junction J1 107. Layer 106 and layer 104 may be separated by a junction J2 105. Layer 104 and layer 102 may be separated by a junction J3 103.

[0030] The SCR 100 may also include an anode terminal or electrode 110 connected to the P layer 108, which may be a positive terminal. A cathode terminal or electrode 114, which may be a negative terminal, may be connected to the N layer 102, which in turn may be a positive terminal. A gate terminal or electrode 112, which may be a positive terminal, may be connected to the intermediate layer P 104. The heavy doping of the outer layers 102, 108 may allow the connection of the terminals / electrodes 114, 110, respectively.

[0031] As described above, in order for the SCR to conduct current, the forward bias voltage between the anode terminal 110 and the cathode terminal 114 may be increased beyond the breakdown voltage of the SCR and / or a positive voltage may be applied to the gate terminal 112. In the first scenario, free electrons in the anode terminal 110 and holes in the cathode terminal 114 may acquire a large amount of energy and accelerate to higher speeds. Such high-energy, accelerated electrons may collide with atoms and generate additional (e.g., millions) charge carriers. This causes the depletion region in the junction J2 105 to break down, thereby allowing current to flow through the SCR 100, corresponding to the ON state of the SCR 100. As described above, this may cause severe wear of the SCR 100 and reduce its operating life.

[0032] In the second scenario, a positive voltage (e.g., a small voltage) may be applied to the gate terminal 112. This causes the gate terminal 112 to become forward biased, resulting in the narrowing of the depletion region at the junction J2 105. Because of this, applying a positive voltage to the gate terminal 112 and between the anode terminal 110 and the cathode terminal 114 may be configured to allow current to flow through the SCR 100 and through the depletion region at the junction J2 105.

[0033] Figure 2 Another exemplary silicon controlled rectifier (SCR) 200 is shown. Similar to the SCR 100, the SCR 200 may include a four-layer structure, which has an outer N+ layer 202 and an outer P layer 208, as well as an intermediate P layer 204 and an intermediate N- layer 206. As discussed above ( Figure 2(not shown in the figure), the layers 202-208 may be separated by corresponding junctions J1-J3. The layer 202 may be composed of one or more parts 202(a, b, c, d, e, f) to provide an emitter short. Alternatively or additionally, the layer 202 may be a single part layer.

[0034] The SCR 200 may further include an anode terminal or electrode 210, which may be connected to the P layer 208. The SCR 200 may similarly include a cathode terminal or electrode 214, which may be connected to the N+ layer 202. In addition, the gate terminal or electrode 212 of the SCR 200 may be connected to the intermediate P layer 204.

[0035] Figure 2 An exemplary structure of an existing silicon controlled rectifier is shown. In particular, in the SCR 200, the intermediate N+ layer 204 may be configured to lack any doped regions, especially on the back side of the SCR 200. Therefore, the existing structure of the SCR 200 may tend to increased current leakage and / or low breakdown voltage, which may be problematic in cases where a high breakdown voltage device is required. This in turn reduces the immunity of the SCR 200 to noise and degrades its performance.

[0036] Figure 3 An exemplary silicon controlled rectifier (SCR) 300 according to some embodiments of the present subject matter is shown. As Figure 3 shown, the SCR 300 may include a multi-layer structure and one or more regions that may be doped with one or more dopants (e.g., phosphorus and / or any other suitable material).

[0037] As Figure 3 shown, the SCR 300 may include an outer N+ layer 302 and an outer P layer 308. The intermediate P layer 304 may be coupled to the outer layer 302 via, for example, a junction and to the intermediate negative layer N-306 via, for example, another junction. The intermediate N- layer 306 may be coupled via, for example, yet another junction ( Figure 3(not shown in the figure) is coupled to the outer P layer 308. The outer layer 308 may be configured to include one or more N+ doped regions 311(a, b). One or more of the regions 311(a, b) may be doped with dopants such as, for example, phosphorus and / or any other material. The layer 302 may be composed of one or more portions 302(a, b, c, d, e, f) to provide an emitter short. Alternatively or additionally, the layer 302 may be a single partial layer. In some embodiments, one or more of the portions 302 may also be doped with dopants, which may be the same as and / or different from the dopants of the regions 311. The dopant concentration of each region 311 may be the same as and / or different from that of another region 311 and / or one or more of the portions 302(a, b, c, d, e, f). Doping of the portions 302 and / or the regions 311 may help reduce current leakage and improve breakdown voltage parameters (e.g., especially for environments where higher breakdown voltage SCRs are required).

[0038] As described above, the regions 311(a, b) may be configured to form doped regions within the outer P layer 308. Each of the regions 311(a, b) may be configured to be smaller in size than the outer layer 308. Each of the regions 311(a, b) may have equal and / or different lengths. The length of each of the regions 311a and 311b may be determined according to the specific application of the SCR 300. As Figure 3 shown, the regions 311a and 311b may be disposed adjacent to the anode terminal 310. Moreover, the regions 311a and 311b may be positioned at opposite ends of the anode terminal 310. As can be understood, the regions 311 may be positioned relative to the anode terminal 310 and / or within the outer layer 308 in any desired manner. Additionally, any number of regions 311 may be provided within the outer layer 308.

[0039] As Figure 3 shown, one or more of the regions 311(a, b) may have a thickness less than the thickness of the outer P layer 308. As can be understood, regions 311 of any desired thickness may be used.

[0040] In some exemplary embodiments, a single junction may be configured to separate the intermediate N- layer 306 from the outer P layer 308 and the N+ regions 311(a, b). Alternatively or additionally, multiple junctions may be formed to separate one or more or each of the layer 308 and the regions 311(a, b) from the layer 306 (e.g., one junction may separate the layers 306 and 308; another junction may separate the layers 306 and the region 311a; and / or yet another junction may separate the layers 306 and the region 311b).

[0041] In some embodiments, the SCR 300 may include a cathode terminal or electrode 314, which may be coupled to the outer N+ layer 302. The outer layer 302 may have a length that may be greater than the length of the cathode terminal 314. Alternatively or additionally, the length of the outer layer 302 may be the same as and / or shorter than the length of the cathode terminal 314.

[0042] The SCR 300 may also include a gate terminal or electrode 312. The gate terminal 312 may be coupled to the intermediate P layer 304. As Figure 3 shown, the intermediate P layer 304 may be configured to extend over the entire length of the outer N+ layer 302, while the gate terminal 312 may be configured to cover a portion of the intermediate P layer 304. Alternatively or additionally, the intermediate P layer 304 may have any desired length.

[0043] Furthermore, the SCR 300 may include an anode terminal or electrode 310. The anode terminal 310 may be coupled to one or both of the outer P layer 308 and the N+ regions 311(a, b). The length of the anode terminal 310 may be greater than the length of the outer P layer 308. Additionally, the length of the anode terminal 310 may be configured to be long enough to accommodate at least a portion (and / or the whole) of the length of each of the N+ regions 311(a, b).

[0044] In some embodiments, the dopant material (e.g., phosphorus) used in the layers 302 and regions 311(a, b) may be used to getter out one or more non-metallic impurities (e.g., Na+, K+, etc.) in the outer P layers 304 and 308. To perform the gettering function, the dopant material (e.g., phosphorus) may be used to remove the non-metallic impurities by converting them into stable compounds that are insoluble in the liquid metal.

[0045] Figure 4a -c shows various example patterns of the dopant material for the layer portions 302(a-f) and / or the regions 311(a, b). For example, as Figure 4a shown, the dopant material in one or more of the portions 302(a-f) and / or the regions 311(a, b) may form a pattern 402. The pattern 402 may have a solid square / rectangular structure with a bent corner.

[0046] Alternatively or additionally, as Figure 4b shown, the dopant material in one or more of the portions 302(a-f) and / or the regions 311(a, b) may form a pattern 404. The pattern 404 may also be in the form of a square / rectangle with a bent corner, where the square / rectangle may include a solid outer edge and a serrated inner edge, which may include tooth-like structures. The teeth of the inner edge of the square / rectangle may be spaced evenly and / or unevenly throughout the interior of the square / rectangle.

[0047] As Figure 4c shown, the pattern 406 of dopant material in one or more of the portions 302(a-f) and / or regions 311(a, b) can be similar in shape to the patterns 402 and / or 404. However, the pattern 406 can be different from Figure 4b the pattern 404 shown in that it does not include a solid outer edge. Instead, the pattern 406 can include blocks of dopant material that can be evenly and / or unevenly spaced in a square / rectangular shape. As can be appreciated, any other desired pattern can be used. Additionally, each of the portions 302(a-f) and / or regions 311(a, b) can include a pattern that is the same as and / or different from one or more of the other portions 302(a-f) and / or regions 311(a, b).

[0048] Figure 5a -b shows an example current-voltage graph. Figure 5a FIG. 502 shows a graph showing current leakage on the reverse side of an existing SCR device. Figure 5b FIG. 504 shows a graph showing current leakage on the reverse side of an SCR device of the current subject matter (e.g., Figure 3 the SCR 300 shown). As Figure 5b shown, the SCR device 300 of the current subject matter has significantly reduced current leakage.

[0049] Figure 6 FIG. 600 shows an exemplary process for manufacturing a silicon controlled rectifier according to some embodiments of the current subject matter. The process 600 can be used to manufacture, for example Figure 3 the SCR 300 shown.

[0050] At 602, a first silicon outer layer (e.g., outer N+ layer 302), a second silicon outer layer (e.g., outer P layer 308), a first silicon intermediate layer (e.g., intermediate P layer 304), and a second silicon intermediate layer (e.g., intermediate N- layer 306) can be provided. The first silicon outer layer can be doped with one or more dopants (e.g., phosphorus, etc.).

[0051] At 604, the layers 302-308 can be coupled according to the Figure 3 structure of the SCR 300 shown. For example, without a particular order, the outer N+ layer 302 can be coupled to the intermediate P layer 304 via a first junction ( Figure 3 not shown in, but for example, as Figure 1 the junction J3103 shown). The intermediate P layer 304 can in turn be coupled to the intermediate N- layer 306 via a second junction ( Figure 3 not shown in, but for example as Figure 1The shown junction J2 (105) is coupled to the intermediate N-layer 306. The intermediate N-layer 306 can be coupled to the outer P-layer 308 via a third junction ( Figure 3 not shown in, but for example as Figure 1 the shown junction J1 (107)).

[0052] At 606, the cathode terminal (e.g., cathode terminal 314) can be coupled to the first silicon outer layer (e.g., outer N+ layer 302). Additionally, the gate terminal (e.g., gate terminal 312) can be coupled to the first silicon intermediate layer (e.g., intermediate P-layer 304).

[0053] At 608, one or more doped regions (e.g., regions 311(a, b)) can be formed within the second silicon outer layer. The region can be doped using a dopant (e.g., phosphorus and / or any other material). The concentration of the dopant can be determined according to one or more applications of the SCR 300. Additionally, the size and / or configuration of the region (as Figure 4a shown in -c) can also be determined based on a specific application of the SCR 300. As described above, the doped region and the doped portion of the first silicon outer layer can be used as adsorbents for removing impurities.

[0054] At 610, the anode terminal (e.g., anode terminal 310 as shown) can be coupled to the second silicon outer layer and one or more doped regions. For example, the anode terminal 310 can be coupled to the outer P-layer 308 and the doped region 311, as Figure 3 shown.

[0055] As can be understood, operations 602 - 612 can be performed in any desired order. The above process can also be equally applicable to NPNP and PNPN type structures, whereby doped regions of opposite polarities can be formed in the outer P and / or outer N layers (respectively).

[0056] The components and features of the above device can be implemented using any combination of discrete circuits, application - specific integrated circuits (ASICs), logic gates, and / or single - chip architectures. Additionally, the features of the device can be implemented using a microcontroller, programmable logic array, and / or microprocessor or any combination of the foregoing where appropriate. Note that hardware, firmware, and / or software elements can be collectively or individually referred to herein as "logic" or "circuit".

[0057] It should be understood that the exemplary device shown in the above block diagram can represent a functional descriptive example of many potential embodiments. Thus, the partitioning, omission, or inclusion of the block functions depicted in the drawings does not necessarily mean that the hardware components, circuits, software, and / or elements for implementing these functions will be partitioned, omitted, or included in the embodiments.

[0058] Some embodiments may be described using the phrases "an embodiment" or "embodiments" and their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The phrase "in an embodiment" (or its derivatives) that appears in different places in the specification does not necessarily refer to the same embodiment. Further, unless otherwise specified, the above features are considered to be used together in any combination. Thus, any features discussed separately may be used in combination with each other, unless it is noted that the features are incompatible with each other.

[0059] It should be emphasized that the abstract of the disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. The understanding is that it is not to be used to interpret or limit the scope or meaning of the claims. Further, in the foregoing detailed description, it can be seen that for the purposes of simplifying the disclosure, various features are combined in one embodiment. The disclosed method should not be construed as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as reflected in the following claims, the inventive subject matter lies not in all of the features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment. In the appended claims, the terms "comprising" and "wherein" are used as the plain English equivalents of the respective terms "comprising" and "wherein". Further, the terms "first", "second", "third", and the like are used merely as labels and are not intended to impose numerical requirements on their objects. Additionally, the use of the terms "comprising", "including", or "having" and their variants herein is intended to cover the items listed thereafter and their equivalents as well as additional items. Thus, the terms "comprising", "including", or "having" and their variants are open-ended expressions and may be used interchangeably herein.

[0060] For convenience and clarity, terms such as "top", "bottom", "upper", "lower", "vertical", "horizontal", "lateral", "transverse", "radial", "inner", "outer", "left", and "right" may be used herein to describe the relative placement and orientation of features and components, each with respect to the geometry and orientation of other features and components in the perspective views, exploded perspective views, and cross-sectional views provided herein. The terms are not intended to be limiting and include the specifically recited words, their derivatives, and words of similar import.

[0061] The foregoing has described examples of the disclosed architecture. Of course, it is not possible to describe every possible combination of components and / or methods, but one of ordinary skill in the art will recognize that many further combinations and permutations are possible. Accordingly, the novel architecture is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.

[0062] The foregoing description of the exemplary embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the disclosure. It is intended that the scope of the disclosure not be limited by this detailed description, but rather by the appended claims. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner and may generally include any subset of one or more limitations as differently disclosed herein or otherwise evidenced.

[0063] All directional references (e.g., proximal, distal, above, below, upward, downward, left, right, lateral, longitudinal, front, rear, top, bottom, over, under, vertical, horizontal, radial, axial, clockwise, and counterclockwise) are only for identification purposes to assist the reader in understanding the disclosure and do not create a limitation, particularly as to the position, orientation, or use of the disclosure. Unless otherwise noted, connection references (e.g., attached, coupled, connected, and joined) shall be construed broadly and may include intermediate members between elements and relative movement between elements. Thus, a connection reference does not necessarily infer that the two elements are directly connected and in a fixed relationship to each other.

[0064] Moreover, identification references (e.g., primary, secondary, first, second, third, fourth, etc.) are not intended to imply importance or priority but rather are used to distinguish one feature from another. The drawings are for illustrative purposes only, and the dimensions, positions, sequences, and relative dimensions reflected in the drawings may vary.

[0065] The scope of the disclosure is not limited by the specific embodiments described herein. In fact, various other embodiments and modifications of the disclosure will be apparent to those of ordinary skill in the art in light of the foregoing description and drawings, in addition to those described herein. Accordingly, such other embodiments and modifications are intended to fall within the scope of the disclosure. Additionally, the disclosure has been described herein in the context of a particular implementation for a particular purpose in a particular environment. Those of ordinary skill in the art will recognize that the usefulness is not limited thereto and that the disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full scope and spirit of the disclosure as described herein.

Claims

1. A device, comprising: a first silicon outer layer; a second silicon outer layer; a first silicon intermediate layer; a second silicon intermediate layer, wherein the first silicon outer layer is coupled to the first silicon intermediate layer, the first silicon intermediate layer is coupled to the second silicon intermediate layer, and the second silicon intermediate layer is coupled to the second silicon outer layer; a cathode terminal, which is coupled to the first silicon outer layer; a gate terminal, which is coupled to the first silicon intermediate layer; one or more doped regions, which are formed in the second silicon outer layer; and an anode terminal, which is coupled to the second silicon outer layer and at least one of the one or more doped regions.

2. The device according to claim 1, wherein, the first silicon outer layer is coupled to the first silicon intermediate layer via a first junction.

3. The device according to claim 2, wherein, the first silicon intermediate layer is coupled to the second silicon intermediate layer via a second junction.

4. The device according to claim 3, wherein, the second silicon intermediate layer is coupled to the second silicon outer layer via a third junction.

5. The device according to claim 1, wherein, at least a portion of the first silicon outer layer is doped with at least one of a plurality of dopants.

6. The device according to claim 5, wherein, the one or more doped regions are doped with at least one other of the plurality of dopants.

7. The device according to claim 6, wherein, the at least one dopant is the same as the at least one other dopant.

8. The device according to claim 6, wherein, the at least one dopant is different from the at least one other dopant.

9. The device according to claim 1, wherein, at least one dimension of the at least one doped region is smaller than at least one corresponding dimension of the second silicon outer layer.

10. The device according to claim 1, wherein, the device is at least one of the following: a PNPN thyristor structure, an NPNP thyristor structure, and any combination thereof.

11. The device according to claim 1, wherein, the first outer silicon layer is an N+ layer.

12. The device according to claim 11, wherein, the first intermediate silicon layer is a P layer.

13. The device according to claim 12, wherein, the second intermediate silicon layer is an N- layer.

14. The device according to claim 13, wherein, the second outer silicon layer is a P layer.

15. The device according to claim 14, wherein, the one or more doped regions are N+ regions.

16. A thyristor structure, comprising: a first silicon outer layer, wherein at least a portion of the first silicon outer layer is doped with at least one of a plurality of dopants; a second silicon outer layer; a first silicon intermediate layer; a second silicon intermediate layer, wherein the first silicon outer layer is coupled to the first silicon intermediate layer via a first junction, the first silicon intermediate layer is coupled to the second silicon intermediate layer via a second junction, and the second silicon intermediate layer is coupled to the second silicon outer layer via a third junction; a cathode terminal, which is coupled to the first silicon outer layer; a gate terminal, which is coupled to the first silicon intermediate layer; One or more doped regions, which are formed in the second silicon outer layer; and An anode terminal, which is coupled to the second silicon outer layer and at least one of the one or more doped regions.

17. A method, comprising: Providing a first silicon outer layer, a second silicon outer layer, a first silicon intermediate layer, and a second silicon intermediate layer, wherein at least a portion of the first silicon outer layer is doped with at least one dopant from a plurality of dopants; Coupling the first silicon outer layer to the first silicon intermediate layer via a first junction, coupling the first silicon intermediate layer to the second silicon intermediate layer via a second junction, and coupling the second silicon intermediate layer to the second silicon outer layer via a third junction; Coupling a cathode terminal to the first silicon outer layer, and coupling a gate terminal to the first silicon intermediate layer; Shortening the second silicon outer layer using one or more predetermined dimensions to generate a shortened second silicon outer layer; Forming one or more doped regions in the second silicon outer layer; and Coupling an anode terminal to the second silicon outer layer and at least one of the one or more doped regions.

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