Vertical semiconductor device and manufacturing method thereof

Abstract

The invention relates to a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a semiconductor material layer; the first shielding structure is located on the semiconductor material layer and comprises a first shielding dielectric layer and a first shielding electrode surrounded by the first shielding dielectric layer; the first doped region is located on the semiconductor material layer, and the first doped region has a first conductive type; and a first gate structure adjacent to the first impurity region. The depth of the first gate structure is smaller than that of the first shielding structure and larger than that of the first doped region. The first shielding dielectric layer is divided into an upper part and a lower part by taking the bottom of the first gate structure as a boundary line, and the first gate structure is adjacent to the upper part. The upper portion has a first thickness on the first surface of the semiconductor material layer, the first thickness is smaller than a second thickness of the lower portion, and the sum of the first thickness of the upper portion and a third thickness of the first gate structure on the first surface is larger than the second thickness of the lower portion.

Description

Technical Field

[0001] The present invention relates to a vertical semiconductor device and a manufacturing method thereof. More specifically, it relates to a vertical semiconductor device having a gate electrode structure partially located in a mesa region and partially located in a shield trench structure and a manufacturing method thereof. Background Art

[0002] A trench metal-oxide-semiconductor field-effect transistor (trench-MOSFET) having a gate electrode buried in a trench of a substrate can generate a vertical channel. The main advantage of this structure is the absence of a junction field (JFET) effect. In the process of semiconductor development, as the minimum component size that can be manufactured decreases, the number of interconnected devices per unit area increases. The allowable contact area between conductive elements in the current conduction path is limited, resulting in an increase in the device resistance value or a decrease in the reliability of the product. For example, when the gate area of a trench MOSFET is limited, it will result in a relatively large gate resistance, thereby leading to lower efficiency and slower switching speed. If the gate area is increased, the distance between the shield electrode and the gate will be reduced, which will instead lead to a decrease in the sustainable voltage between the gate and the source, resulting in a decrease in reliability. Summary of the Invention

[0003] Embodiments of the present disclosure relate to a vertical semiconductor device, including: a semiconductor material layer having a first surface and a second surface opposite to each other; a first shield structure located in the semiconductor material layer and extending from the first surface toward the second surface, the first shield structure including a first shield dielectric layer and a first shield electrode surrounded by the first shield dielectric layer; a first doped region located in the semiconductor material layer and adjacent to the first surface, wherein the first doped region has a first conductivity type; and a first gate structure located in the semiconductor material layer and extending from the first surface toward the second surface, the first gate structure being adjacent to the first doped region, a depth of the first gate structure being less than a depth of the first shield structure and greater than a depth of the first doped region. The first shield dielectric layer is divided into an upper portion and a lower portion with the bottom of the first gate structure as a boundary, and the first gate structure is adjacent to the upper portion of the first shield dielectric layer. The upper portion of the first shield dielectric layer has a first thickness located at the first surface of the semiconductor material layer. The first thickness is less than a second thickness of the lower portion of the first shield dielectric layer, and a sum of the first thickness of the upper portion of the first shield dielectric layer and a third thickness of the first gate structure located at the first surface is greater than the second thickness of the lower portion of the first shield dielectric layer.

[0004] Embodiments of the present disclosure relate to a method for manufacturing a vertical semiconductor device. The method includes: forming a first shielding structure in a lightly doped region of a semiconductor material layer, wherein the lightly doped region has a first conductivity type, and the first shielding structure includes a first shielding electrode and a first shielding dielectric layer located between the first shielding electrode and the semiconductor material layer; forming a first patterned layer on the semiconductor material layer, wherein the first patterned layer has a first opening, a first sidewall of the first opening is above the first shielding dielectric layer between the first shielding electrode and the semiconductor material layer, and a first sidewall of the first shielding dielectric layer is within the coverage of the opening; performing a first etching process on the first shielding dielectric layer to form a first groove in the first shielding dielectric layer, wherein the first groove exposes a part of the semiconductor material layer; performing a second etching process on the semiconductor material layer to form a second groove in the semiconductor material layer, wherein the depth of the second groove is greater than the depth of the first groove, the second groove exposes the first sidewall of the part of the first shielding dielectric layer located below the first groove, and the first groove communicates with the second groove to define a third groove; and forming a first gate structure in the third groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of several embodiments of the present disclosure may be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that the various structures are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various structures may be arbitrarily enlarged or reduced.

[0006] Figure 1-27 Shown are cross-sectional views of one or more stages in a method for manufacturing a vertical semiconductor device according to certain embodiments of the present case;

[0007] Figure 28 Shown is a top view of a vertical semiconductor device according to certain embodiments of the present case;

[0008] Figure 29 Shown is a cross-sectional view of a vertical semiconductor device according to certain embodiments of the present case.

[0009] The same or similar components are denoted by the same reference numerals in the drawings and the detailed description. From the following detailed description and in conjunction with the drawings, several embodiments of the present disclosure will be immediately understood. DETAILED DESCRIPTION

[0010] Numerous different embodiments or examples are provided below for implementing different features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are merely examples and are not intended to be restrictive. In this disclosure, a reference to forming a first feature above or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and / or letters in the various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations being discussed.

[0011] Embodiments of the present disclosure are discussed in detail below. However, it should be understood that the present disclosure provides many applicable concepts that may be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.

[0012] The present disclosure provides a structure of a semiconductor rectifying device and a manufacturing method thereof. Compared with the manufacturing method of a general semiconductor rectifying device, the semiconductor rectifying device of the present disclosure has a Schottky barrier structure. Further, the Schottky barrier junction rectifier of the present disclosure has a lower electric field strength at the interface between the metal and the semiconductor. Therefore, it can achieve the effect of maintaining a low VF while reducing IR, and has the effect of improving reverse leakage. Therefore, the structure of the present disclosure can achieve the effect of reducing IR without increasing VF, and provides a rectifying device with improved reverse leakage.

[0013] Figures 1 to 28 Shown are one or more stages in a method of manufacturing a vertical semiconductor device 1 according to certain embodiments of the present case. At least some of these drawings have been simplified for a better understanding of aspects of the present disclosure.

[0014] Referring to Figure 1 , the method of manufacturing the vertical semiconductor device 1 includes forming a semiconductor material layer 12 on a surface 11A of a substrate 11, and forming a doped region 25 in the semiconductor material layer 12. The semiconductor material layer 12 is formed, for example, by epitaxial growth on the surface 11A of the substrate 11. The substrate 11 has opposite surfaces 11A and 11B. In some embodiments, the surfaces 11A and 11B may be horizontal planes. For ease of explanation, the direction orthogonal to the surfaces 11A and 11B is defined as the vertical direction, and the direction orthogonal to the vertical direction is defined as the horizontal direction. In some embodiments, the surface 11A is the top surface of the substrate 11, and the surface 11B is the bottom surface of the substrate 11. In some embodiments, the surface 11A is the top surface of a silicon wafer. Figure 1The substrate 11 shown may be only a portion of the silicon wafer near the top surface. The material of the substrate 11 may be polysilicon or single-crystalline silicon. The substrate 11 may include doped regions 24. For example, the substrate 11 includes a p-type doped region and an n-type doped region that may be configured for an n-type transistor and may be configured as a p-type transistor. The n-type doped region is doped with an n-type dopant such as phosphorus, arsenic, other n-type dopants, or a combination thereof. The p-type doped region is doped with a p-type dopant such as boron, indium, other p-type dopants, or a combination thereof. The n-type or p-type doped region may be formed by performing an ion implantation process, a diffusion process, and / or other suitable doping processes. The doped region 24 of the substrate 11 extends from the surface 11A toward the surface 11B. In some embodiments, the doped region 24 of the substrate 11 covers the entire surface 11A. In some embodiments, the doped region 24 of the substrate 11 has a first conductivity type. For ease of explanation, the first type is taken as N-type and the second type is taken as P-type in the following description, but the present disclosure is not limited thereto. The substrate 11 of N-type (first type) or P-type (second type) may be adjusted according to the conductivity type of the vertical semiconductor device 1. It should be noted that, Figure 1 The substrate 11 shown may be only a part of the silicon wafer near the top surface, or rather, Figure 1 only a part of the doped region 24 of the substrate 11 is shown. In some embodiments, the doped region 24 of the substrate 11 serves as the cathode doped region of the vertical semiconductor device 1.

[0015] The semiconductor material layer 12 has the same conductivity type as the substrate 11, that is, first-type doping. The material of the substrate 11 may be polysilicon, single-crystalline silicon, silicon carbide, silicon germanium, or other suitable semiconductor materials. In some embodiments, ions with N-type electrical properties are introduced during epitaxial growth to form the N-type semiconductor material layer 12 without the need for additional ion implantation. Therefore, the ions with N-type electrical properties can be distributed throughout the semiconductor material layer 12 to form a doped region 25 located throughout the semiconductor material layer 12. The semiconductor material layer 12 may have a surface 12A and a surface 12B opposite to the surface 12A. In some embodiments, the surface 12A and the surface 12B may be horizontal planes. In some embodiments, the surface 12A is the top surface of the semiconductor material layer 12 and the surface 12B is the bottom surface of the semiconductor material layer 12. In some embodiments, the surface 12B of the semiconductor material layer 12 is in surface contact with the surface 11A of the substrate 11.

[0016] The thickness and doping concentration of the semiconductor material layer 12 can be adjusted according to the voltage requirements of the device. In some embodiments, the semiconductor material layer 12 may have a uniform doping concentration. In some embodiments, ions with N-type electrical properties are uniformly introduced during the epitaxial growth process to form a semiconductor material layer 12 with a uniform doping concentration, where the concentration of the ions introduced during the epitaxial growth process does not change with time. In some embodiments, the semiconductor material layer 12 may have a doping concentration gradient that increases or decreases from the surface 12A to the surface 12B. In some embodiments, the increasing or decreasing doping concentration gradient can be adjusted according to the breakdown voltage and resistance required by the product. In some embodiments, ions with N-type electrical properties are introduced during the epitaxial growth process, where the concentration of the introduced ions decreases or increases with the time of epitaxial growth to form a semiconductor material layer 12 with a decreasing or increasing doping concentration. Regardless of whether the semiconductor material layer 12 has a uniform or non-uniform doping concentration, the doping concentration of the substrate 11 will still be greater than that of the semiconductor material layer 12. For ease of explanation, the doping region 25 is collectively referred to as the lightly doped region 25 in the following text.

[0017] Referring to Figure 2 , the manufacturing method of the vertical semiconductor device 1 includes forming a patterned layer 51 on the surface 12A of the semiconductor material layer 12 to expose a part of the semiconductor material layer 12. The patterned layer 51 is used to define the position of the trench of the shielding electrode structure formed later. In some embodiments, the patterned layer 51 has openings 511 and 512 to expose a part of the semiconductor material layer 12. The patterned layer 51 can be a photoresist layer, a hardening layer, a dielectric layer (such as an oxide layer or a nitride layer), etc., which are material layers suitable as masks for subsequent etching processes. In some embodiments, the patterned layer 51 includes an oxide (such as silicon oxide). In some embodiments, an oxide layer is formed to entirely cover the surface 12A of the semiconductor material layer 12, a patterned photoresist layer is formed on the oxide layer, the patterned photoresist layer is used to remove a part of the oxide layer, and then the patterned photoresist layer is removed to form the patterned layer 51 that exposes a part of the silicon carbide layer 12.

[0018] Referring to Figure 3, the manufacturing method of the vertical semiconductor device 1 includes etching the semiconductor material layer 12 using the patterned layer 51 as a mask to form a plurality of trenches 65 (for example, including trenches 651 and 652). The plurality of trenches 65 are adjacent to each other and extend from the surface 12A of the semiconductor material layer 12 to the surface 12B. Since they are formed through the same etching step, the trenches 651 and 652 have approximately the same depth D65. In some embodiments, the depth D65 of the trench 651 or the trench 652 is between 5 - 30 μm. In some embodiments, the depth D65 of the trench 651 or the trench 652 is between 8 - 10 μm. The widths of the trenches 651 and 652 can be determined by the openings 511 and 512. In some embodiments, the trenches 651 and 652 have approximately the same width W65. In some embodiments, the width W65 of the trench 651 or the trench 652 is between 0.5 - 5 μm. In some embodiments, the width W65 of the trench 651 or the trench 652 is between 2 - 3 μm. The widths and depths of the trenches 651 and 652 can be set and adjusted according to the voltage required by the device. Within the scope of the embodiments disclosed above, the larger the value of the depth D65 of the trenches 651 and 652, the lower the resistivity of the semiconductor material layer 12.

[0019] Referring to Figure 4 , the manufacturing method of the vertical semiconductor device 1 includes forming a dielectric layer 13 filled in the trenches 651 and the trenches 652. In some embodiments, the dielectric layer 13 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or other deposition processes. In some embodiments, the dielectric layer 13 can be formed by thermal oxidation technology. In some embodiments, the dielectric layer 13 substrates on the trenches 651 and 652. In some embodiments, the dielectric layer 13 can be conformally or coplanarly deposited on the inner surfaces (including the opposite sidewalls and the bottom extending between the sidewalls) of the trenches 651 and 652 and the surface 12A of the semiconductor material layer 12. In some embodiments, the dielectric layer 13 can be filled in the trenches 651 and 652 through a deposition process, and then lithography and etching processes are performed to locally remove the dielectric layer 13 to form at least one groove in the dielectric layer 13. The thickness of the dielectric layer 13 can be set and adjusted according to the voltage required by the device. In some embodiments, the thickness of the dielectric layer 13 is between 0.1 - 2 μm. In some embodiments, the thickness of the dielectric layer 13 is between 0.2 - 1.2 μm. In some embodiments, the thickness of the dielectric layer 13 is between 0.6 - 0.8 μm.

[0020] The voltage of the vertical semiconductor device 1 is generally determined jointly by the doping concentration of the semiconductor material layer 12 and the thickness of the dielectric layer 13. Therefore, Figure 1 , 4 the steps shown will determine the voltage of the vertical semiconductor device 1.

[0021] Referring to Figure 5 , the manufacturing method of the vertical semiconductor device 1 includes forming trench 651 and trench 652 filled with the electrode material layer 14. In some embodiments, the electrode material layer 14 can be formed by physical vapor deposition (PVD), CVD or other deposition processes. In some embodiments, the electrode material layer 14 fills trenches 651 and 652 and covers the surface 12A of the semiconductor material layer 12. In some embodiments, the electrode material layer 14 includes a semiconductor material, such as polysilicon.

[0022] Referring to Figure 6, the manufacturing method of the vertical semiconductor device 1 includes removing a portion of the electrode material layer 14 and the dielectric layer 13 located outside the trenches 651, 652. In some embodiments, the electrode material layer 14 outside the trenches 651, 652 is removed to form a first electrode layer 141 and a second electrode layer 142 in the trenches 651, 652 respectively. In some embodiments, a grinding process, such as a chemical mechanical polishing (CMP) process, is performed on the electrode material layer 14 to remove the electrode material layer 14 outside the trenches 651, 652. In other embodiments, the method of removing a portion of the electrode material layer 14 located outside the trenches 651, 652 may further include an etching process, such as a wet etching or a dry etching process. In some embodiments, after removing the electrode material layer 14 on the surface 12A of the semiconductor material layer 12, a similar process is performed on the dielectric layer 13 to form a first dielectric layer 131 and a second dielectric layer 132 in the trenches 651, 652 respectively. In some embodiments, the top surfaces of the etched dielectric layer 13 and the electrode material layer 14 are located at approximately the same horizontal height. In some embodiments, the top surfaces of the etched dielectric layer 13 and the electrode material layer 14 are aligned with the surface 12A. The vertical semiconductor device 1 includes a double-gate semiconductor power element, wherein the dielectric layer 13 (including the first dielectric layer 131 and the second dielectric layer 132) serves as the shielding dielectric layer of the shielding electrode structure 15, and the electrode material layer 14 (including the first electrode layer 141 and the second electrode layer 142) serves as the shielding electrode layer of the shielding electrode structure 15. The first dielectric layer 131 surrounds the first electrode layer 141, and the second dielectric layer 132 surrounds the second electrode layer 142, respectively defining different shielding structures 15 of the vertical semiconductor device 1. For convenience of description, the first electrode layer 141 and the first dielectric layer 131 are collectively referred to as the first shielding structure 151, and similarly, the second electrode layer 142 and the second dielectric layer 132 are collectively referred to as the second shielding structure 152. In some embodiments, the upper surfaces of the first electrode layer 141 and the second electrode layer 142 are flush with the surface 12A. In some embodiments, the upper surfaces of the first dielectric layer 131 and the second dielectric layer 132 are flush with the surface 12A. In some embodiments, the first electrode layer 141 and the second electrode layer 142 have approximately the same width W14. In some embodiments, the width W14 ranges between 0.3 - 3 μm. In some embodiments, the width W14 ranges between 0.6 - 1 μm. In some embodiments, the ratio of the width W14 to the width W651 of the trench 65 is greater than or equal to 3:1.

[0023] Referring to Figure 7, the manufacturing method of the vertical semiconductor device 1 includes forming a hardening layer 16 on the surface 12A of the semiconductor material layer 12. The hardening layer 16 covers the first shielding structure 151, the second shielding structure 152, and the surface 12A of the semiconductor material layer 12. The hardening layer 16 may include a dielectric material (such as an oxide layer or a nitride layer), etc., which is a material layer suitable as a mask for subsequent etching processes. In the subsequent step of defining the gate structure, part of the dielectric layers 131, 132 will be removed. In some embodiments, in order to simplify the steps and manufacturing costs, the hardening layer 16 can be selected to use the same dielectric material as the dielectric layer 13. In some embodiments, the material of the hardening layer 16 is an oxide (such as silicon oxide).

[0024] Referring to Figure 8 , the manufacturing method of the vertical semiconductor device 1 includes forming a patterned layer 52 on the top surface of the hardening layer 16. The patterned layer 52 has a plurality of openings (such as Figure 8 521, 522, 523, 524 in) above the opposite sidewalls of the shielding structure. For example, the first shielding structure 151 has opposite sidewalls 151C and 151D, the opening 521 of the patterned layer 52 is above the sidewall 151C, and the opening 522 of the patterned layer 52 is above the sidewall 151D. In some embodiments, the sidewall 151C is within the coverage of the vertical projection of the opening 521, and the sidewall 151D is within the coverage of the vertical projection of the sidewall 522. In some embodiments, the opening 521 has opposite sidewalls 521C and 521D, and the extension line of the sidewall 151C in the vertical direction is between the extension lines of the sidewalls 521C and 521D. In some embodiments, the opening 522 has opposite sidewalls 522C and 522D, and the extension line of the sidewall 151D in the vertical direction is between the extension lines of the sidewalls 522C and 522D. Similarly, for example, the second shielding structure 152 has opposite sidewalls 152C and 152D, the opening 523 is above the sidewall 152C, and the opening 524 is above the sidewall 152D. In some embodiments, the sidewall 152C is within the coverage of the vertical projection of the opening 523, and the sidewall 152D is within the coverage of the vertical projection of the sidewall 524. In some embodiments, the opening 523 has opposite sidewalls 523C and 523D, and the extension line of the sidewall 152C in the vertical direction is between the extension lines of the sidewalls 523C and 523D. In some embodiments, the opening 524 has opposite sidewalls 524C and 524D, and the extension line of the sidewall 152D in the vertical direction is between the extension lines of the sidewalls 524C and 524D.

[0025] Referring to Figure 9, the manufacturing method of the vertical semiconductor device 1 includes performing a first etching process on the hardened layer 16 and the dielectric layer 13 using the patterned layer 52 as a mask to form openings in the hardened layer 16 and grooves in the first dielectric layer 131 and the second dielectric layer 132 respectively. Since the first shielding structure 151 and the second shielding structure 152 have similar configurations, and the corresponding positions of the openings 523, 524 and the second shielding structure 152 are similar to the corresponding positions of the openings 521, 522 and the first shielding structure 151, for simplicity of description, the following description of the manufacturing steps is mainly based on the first shielding structure 151, the openings 521, 522, and the subsequent steps of the second shielding structure 152 can refer to the first shielding structure 151.

[0026] The first etching process partially removes the hardened layer 16 and the first dielectric layer 131 under the openings 521, 522 to form a plurality of openings in the hardened layer 16 and a plurality of grooves 61 in the first dielectric layer 131. For example, openings 161, 162 corresponding to the openings 521, 522 are formed in the hardened layer 16, and grooves 611, 612 located under the openings 161, 162 are formed in the first dielectric layer 131. The groove 611 connects the bottom of the opening 161 and communicates with the opening 161, while the groove 612 connects the bottom of the opening 162 and communicates with the opening 162. The groove 611 exposes the semiconductor material layer 12 of the portion adjacent to the surface 12A and adjacent to the sidewall 151C, and the groove 612 exposes the semiconductor material layer 12 of the portion adjacent to the surface 12A and adjacent to the sidewall 151D. The first etching process for removing the dielectric material stops at the semiconductor material layer 12. In some embodiments, the hardened layer 16 and the first dielectric layer 131 have the same dielectric material, or the materials of both the hardened layer 16 and the first dielectric layer 131 have a low selectivity ratio for the etchant of the first etching process, so the hardened layer 16 can be removed together with the first dielectric layer 131. In some embodiments, the first etching process includes a dry etching process, which exposes a partial surface 12 of the semiconductor material layer 12 located in the openings 161, 162 and exposes a partial semiconductor material layer 12 in contact with the sidewalls of the first dielectric layer 131 by the grooves 611, 612.

[0027] Referring to Figure 10 , the manufacturing method of the vertical semiconductor device 1 includes removing the patterned layer 52. In some embodiments, the openings 611, 612 have approximately the same depth D61 in the vertical direction from the surface 12A. In some embodiments, the depth D61 ranges between 0.5 - 1.5 μm. The openings 611, 612 define the positions of part of the gate structure, so the depth D61 of the openings 611, 612 can be determined according to the breakdown voltage (BV) required for the vertical semiconductor device 1 by Figure 9Adjustment of the parameters (such as energy, time, etc.) of the etching step to obtain the desired depth D61. Additionally, the openings 161, 162 expose the surface 12A of a portion of the semiconductor material layer 12. In some embodiments, the exposed portion of the semiconductor material layer 12 has a width D1. In some embodiments, the width D1 ranges from greater than 0 to less than 2 μm. In some embodiments, the width D1 ranges from 0.1 - 0.15 μm. The range of the width D1 can be adjusted according to the distance D2 between the first shielding structure 151 and the second shielding structure 152. In some embodiments, the distance D2 ranges from 0.5 - 3 μm. In some embodiments, the distance D2 ranges from 1 - 2 μm.

[0028] Referring Figure 11 , the manufacturing method includes using the hardening layer 16 and the dielectric layer 13 as masks to perform a second etching process on the semiconductor material layer 12. The semiconductor material layer 12 is locally removed to form a plurality of grooves 62 in the semiconductor material layer 12. In some embodiments, the second etching process includes a dry etching process, such as an isotropic or anisotropic dry etching process. The plurality of grooves 62 have approximately the same depth D62 in the vertical direction from the surface 12A, and the depth D62 is greater than the depth D61 of the grooves 61. In some embodiments, the grooves 62 expose the sidewalls 151C and 151D of a portion of the first dielectric layer 131 located below the grooves 61. Each groove 62 communicates with each groove 61 in the horizontal direction. The plurality of grooves 62 include, for example, grooves 621, 622 located in the first dielectric layer 131. In some embodiments, the groove 621 communicates with the groove 611 in the horizontal direction, and its depth is greater than the depth of the groove 611. In some embodiments, the groove 622 communicates with the groove 612 in the horizontal direction, and its depth is greater than the depth of the groove 612.

[0029] According to the configuration and position of the dielectric layer 13, for example, with the bottom of the groove 62 as the boundary, the dielectric layer 13 can be divided into an upper portion 13U and a lower portion 13L. For example, the first dielectric layer 131 located on one side of the first electrode layer 141 has an upper portion 13U with a configuration that is narrower at the top and wider at the bottom. In other words, the thickness of the top of the upper portion 13U is less than the thickness of the bottom of the upper portion 13U. In some embodiments, the upper portion 13U has a thickness T135 in the horizontal direction at the horizontal height of the surface 12A of the semiconductor material layer 12, and the upper portion 13U has a thickness T136 in the horizontal direction at the junction of the semiconductor material layer 12 and the first dielectric layer 131, where the thickness T135 is less than the thickness T136. In some embodiments, the range of the thickness T135 is between 0.1 - 0.2 μm. Depending on the different second etching processes, the upper portion 13U can be configured with smooth sidewalls having an increasing thickness in the vertical direction from the surface 12A to the surface 12B, or as Figure 11The shown configuration with steps. The lower part 13L of the first dielectric layer 131 has a uniform thickness, and the thickness of the lower part 13L of the first dielectric layer 131 is approximately the same as Figure 4 the thickness of the dielectric layer 13. In some embodiments, the thickness T138 of the lower part 13L is approximately equal to the thickness T136. In other words, the thickness T138 of the lower part 13L is greater than the thickness T135 of the upper part 13U.

[0030] The positions of the grooves 61 and 62 together define the positions of the subsequently formed gate structures, so the grooves 61 and 62 can also be collectively referred to as the gate trenches 63. The depth of the gate trenches 63 is less than the depth of the shielding structure 15. Each gate trench 63 can have a similar configuration. The gate trench 63 has a first sidewall 63G away from the shielding structure 15, a second sidewall (including 63C, 63E, 63D) adjacent to the shielding structure 15, and a bottom surface 63F connecting the first sidewall 63G and the second sidewall, where the first sidewall 63G is a flat sidewall defined by the semiconductor material layer 12, and the second sidewall is a sidewall with a stepped configuration defined by the upper part 13U of the dielectric layer 13.

[0031] Figure 12 is according to some embodiments of the present disclosure, Figure 11 an enlarged view of the position shown by the dashed box. The second sidewall of the gate trench 63 (i.e., the sidewall of the upper part 13U of the dielectric layer 13) includes a first partial sidewall 63C extending in a first direction, a second partial sidewall 63D approximately parallel to the first partial sidewall 63C, and a third partial sidewall 63E connecting the first partial sidewall 63C and the second partial sidewall 63D and extending in a second direction. In some embodiments, the first direction is generally parallel to the vertical direction. In some embodiments, the angle between the first direction and the second direction is between 30 and 90 degrees. In some embodiments, the angle θ1 between the first partial sidewall 63C and the third partial sidewall 63E is between 30 and 90 degrees. In some embodiments, the angle θ2 between the third partial sidewall 63E and the second partial sidewall 63D is between 30 and 90 degrees. The angle θ1 and the angle θ2 can be approximately the same (e.g., within a difference range of less than or equal to 5 degrees) or different (e.g., within a difference range greater than 5 degrees). The bottom surface 63B can extend substantially along the horizontal direction or have an arc-shaped configuration, which is not limited herein. In some embodiments, the sidewall of the lower part 13L of the dielectric layer 13 ( Figure 12 exemplified by 132 therein) adjacent to the semiconductor material layer 12 and the second partial sidewall 63D of the upper part 13U are continuous sidewalls.

[0032] Figure 11 、 12The gate trench 63 with a stepped configuration sidewall is drawn according to some embodiments of the present disclosure. In other embodiments, the openings 61 and 62 formed by controlling the first etching process and the second etching process can have the same depth, so that the gate trench 63 has a columnar configuration.

[0033] Figure 14 The gate trench 63 with a columnar configuration is drawn according to some embodiments of the present disclosure. In Figure 14 the embodiments, the second sidewall of the gate trench 63 is defined by the first partial sidewall 63C, and does not have the second partial sidewall 63D and the third partial sidewall 63E. The first partial sidewall 63C of the gate trench 63 is connected to the bottom surface 63B of the gate trench 63, where the bottom surface 63B is defined by a part of the dielectric layer 13 and a part of the semiconductor material layer 12.

[0034] As described above, the thickness of the dielectric layer 13 will determine the voltage of the vertical semiconductor device 1. If the width of the gate structure in the dielectric layer 13 is too large, it will affect the breakdown voltage performance of the vertical semiconductor device 1. Therefore, the depth D61 of the opening 61 is preferably less than or equal to the depth D62 of the opening 62. In actual operation, there will be more or less over-etching in the etching process. Therefore, to ensure that the depth D61 of the opening 61 is not greater than the depth D62 of the opening 62, the etching depth is set to be less than the etching depth set by the second etching process when controlling the first etching process.

[0035] Referring to Figures 14-15 the manufacturing method includes forming a sacrificial layer 31 on the exposed part of the semiconductor material layer 12 in the gate trench 63 after the second etching process of Figure 12 and removing the sacrificial layer 31 before forming the gate structure. In some embodiments, the sacrificial layer 31 includes an oxide (such as silicon oxide). In some embodiments, the sacrificial layer 31 is formed by performing a thermal oxidation process on the exposed semiconductor material layer 12. The previous multiple processes may damage the surface of the semiconductor material layer 12. The sacrificial layer 31 can flatten the surface of the exposed semiconductor material layer 12, which helps the subsequently formed gate structure to have better performance.

[0036] Referring to Figure 16 the manufacturing method includes forming a gate dielectric layer 32 on the exposed part of the semiconductor material layer 12. The formation method of the gate dielectric layer 32 can refer to the formation methods of the dielectric layer 13, the first dielectric layer 131, and the second dielectric layer 132, and will not be repeated here. In some embodiments, the gate dielectric layer 32 is formed by performing a thermal oxidation process, and the gate dielectric layer 32 is only formed on the exposed part of the semiconductor material layer 12. In some embodiments, the gate dielectric layer 32 is formed by performing a deposition process, and the gate dielectric layer 32 is conformally formed on Figure 16on the surface of the structure shown (including the semiconductor material layer 12 and the dielectric layer 13 formed on the exposed portion). Figure 16 The illustrated embodiment has a gate dielectric layer 32 formed by a thermal oxidation process. In some embodiments, the thickness of the gate dielectric layer 32 is less than Figure 11 the thickness T135 in. In embodiments where a deposition process is performed to form the gate dielectric layer 32, since a portion of the gate dielectric layer 32 will be located on the dielectric layer 13, as long as the total thickness of the gate dielectric layer 32 and the dielectric layer 13 meets the ranges of the thickness T135 and the thickness T136 in the above text.

[0037] Referring to Figures 17-18 , the manufacturing method includes forming a gate electrode 34 in the gate trench 63. The gate dielectric layer 32 surrounds the gate electrode 34. In some embodiments, the gate electrode 34 can be formed by physical vapor deposition, such as sputtering or spraying. In some embodiments, the gate electrode 34 can be formed by electroplating or CVD. In some embodiments, an electrode material layer 33 is formed to fill the gate trench 63 and cover the surface 12A, and then a grinding process, such as chemical mechanical polishing, is performed to grind and remove the electrode material layer 33 outside the gate trench 63 to form a plurality of gate electrodes 34 (including 341, 342, 343, 344) in each gate trench 63. In some embodiments, the gate electrode 34 is adjacent to the upper portion 13U of the dielectric layer 13 of the shielding structure 15.

[0038] In some embodiments, a hardening layer 16 on the surface 12A is removed together with a portion of the electrode material layer 33 to expose the surface 12A. In some embodiments, the electrode material layer includes polysilicon. In some embodiments, the upper surface of the gate electrode 34 is flush with the surface 12A. For convenience of description, each gate electrode 34 and each gate dielectric layer 32 can be collectively referred to as a gate structure 35.

[0039] Each gate structure 35 has a similar configuration, which is defined by the configuration of the gate trench 63. Therefore, the gate structure 35 has a configuration that is wider at the top and narrower at the bottom. For example, taking Figure 11 the third part sidewall 63E of as the boundary, the width T351 of the upper part of the gate structure 35 is greater than the width T352 of the lower part of the gate structure 35. In some embodiments, the width T351 of the upper part of the gate structure 35 ranges between 0.6 - 0.8 μm. In some embodiments, the thickness T137 of the dielectric layer 13 adjacent to the upper part of the gate structure 35 ranges between 0.1 - 0.2 μm. It should be noted that Figure 11 the thickness T135 is measured at the horizontal height of the surface 12A, Figure 18 the thickness T137 can be the thickness of the dielectric layer 13 anywhere above the third part sidewall 63E, including the thickness at the horizontal height of the surface 12A.

[0040] Measured horizontally at the same horizontal height, the sum of the width of the gate structure 35 and the thickness of the upper portion 13U of the dielectric layer 13 is greater than or equal to the thickness T138 of the lower portion 13L of the dielectric layer 13. In some embodiments, the ratio of the sum of the width T351 and the thickness T137 to the thickness T138 of the lower portion 13L of the dielectric layer 13 (i.e., (T351 + T137):T138) is greater than or equal to 1:1. In some embodiments, the width T351 may be the width of the upper portion of the gate structure 35 at the horizontal height of the surface 12A. Since the gate dielectric layer 32 has a uniform thickness, the profile of the gate electrode 34 is consistent with the profile of the gate trench 63, or in other words, there is a conformal or co-shaped relationship between the two spacings. In some embodiments, the sum of the width of the gate electrode 34 at the horizontal height of the surface 12A and the thickness T135 of the upper portion 13U of the dielectric layer 13 at the horizontal height of the surface 12A is greater than or equal to the thickness T138 of the lower portion 13L of the dielectric layer 13.

[0041] The semiconductor material layer 12 between adjacent shielding structures 15 has a mesa-like profile, also known as a mesa region. A portion of the gate structure 35 of the vertical semiconductor device 1 in this case is located in the mesa region, and another portion is located in the dielectric layer 13 of the shielding structure 15. By controlling the width of the gate structure 35 in the mesa region and in the dielectric layer 13, the effective area of the gate structure 35 (i.e., Figure 18 the cross-sectional area seen therein) can be increased without affecting the product specifications, thereby achieving the purpose of improving the gate resistance.

[0042] Refer to Figure 19 , the manufacturing method includes forming an oxide layer 37 on the surface 12A of the semiconductor material layer 12. In some embodiments, the oxide layer 37 covers the semiconductor material layer 12, the gate structure 35, and the shielding structure 15. In some embodiments, the oxide layer 37 can protect the surface of the semiconductor material layer 12 during subsequent ion implantation steps, reduce surface damage, and the thickness control of the oxide layer 37 does not affect the efficiency of ion implantation. In some embodiments, the configuration of the gate structure 35 on both sides of the electrode material layer 14 located in the shielding structure 15 is substantially symmetric. In some embodiments, the configuration of the gate structure 35 on both sides of the mesa region is substantially symmetric.

[0043] Refer to Figures 20-21, the manufacturing method includes performing a first ion implantation process on the semiconductor material layer 12 to form a body doping region 21, and a second ion implantation process to form a source doping region 22. The body doping region 21 has a conductivity type different from that of the lightly doped region 25. The depth of the body doping region 21 determines the channel region. The body doping region 21 is located between adjacent gate structures 35, adjacent to the surface 12A in the vertical direction and adjacent to the gate structures 35 in the horizontal direction. The body doping region 21 has a depth D21 in the vertical direction from the surface 12A, and the depth D21 is less than the depth D62 of the groove 62. In some embodiments, there is a distance D3 (i.e., the difference between the depth D62 and the depth D21) between the bottom of the body doping region 21 and the bottom of the gate structure 35, where the distance D3 ranges from 0.1 - 0.2 μm. The source doping region 22 has the same conductivity type as the lightly doped region 25, and the doping concentration of the first conductivity type ions in the source doping region 22 is greater than the doping concentration of the first conductivity type ions in the lightly doped region 25. The source doping region 22 is located between adjacent gate structures 35 and adjacent to the surface 12A. The source doping region 22 has a depth D22 in the vertical direction from the surface 12A, and the depth D22 is less than the depth D22 of the body doping region 21. In some embodiments, the doping concentration of the first conductivity type ions in the source doping region 22 is greater than the doping concentration of the second conductivity type ions in the body doping region 21. In some embodiments, a thermal annealing process is performed after forming the body doping region 21 to ion-diffuse and activate the body doping region 21. In some embodiments, a thermal annealing process is performed after forming the source doping region 22 to ion-diffuse and activate the source-body doping region 22.

[0044] Referring to Figure 22 , the manufacturing method includes forming an interlayer dielectric layer (ILD) 41 on the surface 12A of the semiconductor material layer 12. The interlayer dielectric layer 41 can be formed by ALD, CVD, or other deposition processes.

[0045] Referring to Figures 23-24, the manufacturing method includes locally removing the interlayer dielectric layer 41, and locally removing the semiconductor material layer 12, the first electrode layer 141, and the second electrode layer 142 by using the interlayer dielectric layer 41 as a mask. In some embodiments, a patterned layer 52 is formed on the interlayer dielectric layer 41, and an etching process is performed on the interlayer dielectric layer 41 using the patterned layer 52 as a mask. The patterned layer 52 can be a photoresist layer. In some embodiments, the materials of the semiconductor material layer 12, the first electrode layer 141, and the second electrode layer 142 include polysilicon, and a single etching process can be used for local removal. In some embodiments, the patterned layer 52 is removed before locally removing the semiconductor material layer 12, the first electrode layer 141, and the second electrode layer 142. In some embodiments, openings 411, 412, and 413 are respectively formed in the first electrode layer 141, the semiconductor material layer 12, and the second electrode layer 142. In some embodiments, the openings 411, 412, and 413 have approximately the same depth. In some embodiments, the depth of the opening 412 is greater than the depth D21 of the source doping region 21.

[0046] Referring to Figure 25 , the manufacturing method includes performing an ion implantation process on the first electrode layer 141, the semiconductor material layer 12, and the second electrode layer 142 according to the openings 411, 412, and 413 to form a plurality of heavily doped regions 23 (such as 231, 232, 233). Ions are implanted vertically into the first electrode layer 141, the semiconductor material layer 12, and the second electrode layer 142 at the bottoms of the openings 411, 412, and 413. The heavily doped regions 231 and 233 are respectively formed in the electrode material layer 14 adjacent to the bottoms of the openings 411 and 413, and the heavily doped region 232 is formed in the semiconductor material layer 12 adjacent to the bottom of the opening 412. In some embodiments, an annealing process is performed after the ion implantation process to form Figure 25 the heavily doped regions 231, 232, and 233 as shown.

[0047] Referring to Figure 26 , the manufacturing method includes forming a plurality of conductive plugs 42 (including 421, 422, and 423) in the openings 411, 412, and 413. The conductive plugs 42 can be formed by electroplating or CVD by filling the conductive material into the openings 411, 412, and 413. The material of the conductive plug 16 can include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), aluminum copper (Al x Cu y )、 silicon copper (Si x Cu y ), its alloy or its combination.

[0048] Referring toFigure 27 The manufacturing method includes forming a source electrode layer 44 and a drain electrode layer 47 on opposite sides of a semiconductor material layer 12. The source electrode layer 44 is formed on an interlayer dielectric layer 41 and a conductive plug 42. The source electrode layer 44 may include a suitable metal material or alloy, such as titanium tungsten (TiW), aluminum (Al), aluminum silicon alloy (AlSi), aluminum silicon copper alloy (AlSiCu), or a combination thereof, without limitation here. After forming the source electrode layer 44, the source electrode layer 44 may be etched to form a desired pattern. Since the etching step is carried out according to the desired circuit design, the etching step is not shown in the figure, and those skilled in the art can adjust the etching step according to the above content of the present disclosure to form the desired pattern of the source electrode layer 44.

[0049] The drain electrode layer 47 is formed on the bottom surface 11B of the substrate 11. The drain electrode layer 47 may include the same metal material or alloy as the source electrode layer 44. After forming the drain electrode layer 47, the drain electrode layer 47 may be etched to form a desired pattern. Since the etching step is carried out according to the desired circuit design, the etching step is not shown in the figure, and those skilled in the art can adjust the etching step according to the above content of the present disclosure to form the desired pattern of the drain electrode layer 47.

[0050] Figure 28 is a top view of a vertical semiconductor device 1 according to some embodiments of the present disclosure. Figures 1-27 is a cross-sectional view of multiple stages in the manufacturing method along the A-A' tangent according to some embodiments of the present disclosure. In the step of forming the conductive plug 42, a plurality of gate conductive plugs 43 are formed simultaneously and electrically connected to the gate structure 35. In the step of forming the source electrode layer 44, the gate electrode layer 45 may be formed simultaneously via an etching step. In some embodiments, the gate electrode layer 45 and the source electrode layer 44 are located at approximately the same horizontal height. From Figure 28 the top view, a part of the gate structure 35 overlaps with the shielding structure 15, and another part of the gate structure 35 is outside the coverage of the shielding structure.

[0051] Figure 29 is according to some embodiments of the present disclosure, along Figure 28Cross-sectional view of the manufacturing method of the B-B' tangent line in []. In some embodiments, the depth of the gate conductive plug 43 and the depth of the conductive plug 42 are approximately the same. In some embodiments, the gate conductive plug 43 includes 431, 432, 433, 434, which are respectively connected to the gate electrodes 341, 342, 343, 344. In some embodiments, the heavily doped region 23 further includes 234, 235, 236, 237, which are respectively formed in the gate electrodes 341, 342, 343, 344 and are respectively adjacent to the bottoms of the gate conductive plugs 431, 432, 433, 434.

[0052] As used herein, spatial relative terms such as "beneath", "below", "lower", "above", "upper", "left", "right", etc. may be used for convenience of description to describe the relationship of one component or feature to another or other components or features as shown in the drawings. In addition to the orientation depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when a component is referred to as "connected to" or "coupled to" another component, it may be directly connected to or coupled to the other component, or there may be intermediate components.

[0053] As used herein, the terms "about", "substantially", "essentially" and "approximately" are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurs precisely as well as instances where the event or situation occurs nearly. As used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1% or ±0.5% of the given value or range. Ranges may be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein include the endpoints unless otherwise specified. The term "substantially coplanar" may mean that the positional difference between two surfaces located in the same plane is within a few micrometers (μm), such as within 10 μm, 5 μm, 1 μm or 0.5 μm of being located in the same plane. When a numerical value or characteristic is referred to as "substantially" the same, the term may refer to a value within ±10%, ±5%, ±1% or ±0.5% of the average value of the said value.

[0054] The foregoing outlines the features of several embodiments and the detailed aspects of the present disclosure. The embodiments described in the present disclosure can be easily used as a basis for designing or modifying other processes and structures in order to facilitate the implementation of the same or similar purposes and / or achieve the same or similar advantages of the embodiments introduced herein. Such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A vertical semiconductor device, characterized in that, comprising: a semiconductor material layer having a first surface and a second surface opposite to each other; a first shielding structure located in the semiconductor material layer and extending from the first surface towards the second surface, the first shielding structure comprising a first shielding dielectric layer and a first shielding electrode surrounded by the first shielding dielectric layer; a first doped region located in the semiconductor material layer and adjacent to the first surface, wherein the first doped region has a first conductivity type; and a first gate structure located in the semiconductor material layer and extending from the first surface towards the second surface, the first gate structure adjacent to the first doped region, the depth of the first gate structure being less than the depth of the first shielding structure and greater than the depth of the first doped region, wherein the first shielding dielectric layer is divided into an upper part and a lower part with the bottom of the first gate structure as the boundary, and the first gate structure is adjacent to the upper part of the first shielding dielectric layer, the upper part of the first shielding dielectric layer has a first thickness at the first surface of the semiconductor material layer, and the first thickness is less than the second thickness of the lower part of the first shielding dielectric layer, and the sum of the first thickness of the upper part of the first shielding dielectric layer and the third thickness of the first gate structure at the first surface is greater than the second thickness of the lower part of the first shielding dielectric layer.

2. The vertical semiconductor device according to claim 1, wherein the first gate structure comprises: a first gate electrode, wherein the first gate electrode contacts the upper part of the first shielding dielectric layer; and a first gate dielectric layer located between the first gate electrode and the semiconductor material layer.

3. The vertical semiconductor device according to claim 2, wherein the width of the top of the first gate electrode is greater than the width of the bottom of the first gate electrode.

4. The vertical semiconductor device according to claim 2, wherein the sum of the width of the first gate electrode at the first surface and the first thickness of the upper part of the first shielding dielectric layer is greater than or equal to the second thickness of the lower part of the first shielding dielectric layer.

5. The vertical semiconductor device according to claim 1, wherein the first gate structure has a first sidewall away from the first shielding structure and a second sidewall adjacent to the first shielding structure, the first sidewall being a flat sidewall, and the second sidewall being a sidewall having a stepped configuration.

6. The vertical semiconductor device according to claim 1, wherein, viewed from a top view, a part of the first gate structure overlaps the first shielding structure, and a part of the first gate structure is located outside the coverage of the first shielding structure.

7. The vertical semiconductor device according to claim 1, wherein the upper portion of the first shielding dielectric layer has a first partial sidewall extending in a first direction, a second partial sidewall approximately parallel to the first partial sidewall, and a third partial sidewall connecting the first partial sidewall and the second partial sidewall and extending in a second direction, and the included angle between the second direction and the first direction is between 30 and 90 degrees.

8. The vertical semiconductor device according to claim 1, further comprising: a second shielding structure located in the semiconductor material layer and extending from the first surface toward the second surface, the second shielding structure being disposed adjacent to the first shielding structure, wherein the first doped region is at least located between the first shielding structure and the second shielding structure, and the second shielding structure includes a second shielding dielectric layer and a second shielding electrode surrounded by the second shielding dielectric layer; and a second gate structure located in the semiconductor material layer and extending from the first surface toward the second surface, and the configuration of the second gate structure is substantially symmetric to the configuration of the first gate structure.

9. The vertical semiconductor device according to claim 1, further comprising: a second doped region located in the semiconductor material layer and adjacent to the first surface, the second doped region being located in the first doped region and having a second conductivity type different from the first conductivity type, and the depth of the first doped region is greater than the depth of the second doped region.

10. The vertical semiconductor device according to claim 1, further comprising: a source electrode layer disposed on the first surface of the semiconductor material layer; a first conductive plug electrically connecting the first shielding structure; and a third doped region located in the first shielding electrode and adjacent to the first conductive plug, wherein the doping concentration of the first conductivity type ions in the third doped region is greater than the doping concentration of the first conductivity type ions in the first doped region.

11. A method for manufacturing a vertical semiconductor device, characterized in that it includes: forming a first shielding structure in a lightly doped region of a semiconductor material layer, wherein the lightly doped region has a first conductivity type, and the first shielding structure includes a first shielding electrode and a first shielding dielectric layer located between the first shielding electrode and the semiconductor material layer; forming a first patterned layer on the semiconductor material layer, wherein the first patterned layer has a first opening, a first sidewall of the first opening is above the first shielding dielectric layer between the first shielding electrode and the semiconductor material layer, and the first sidewall of the first shielding dielectric layer is within the coverage of the opening; performing a first etching process on the first shielding dielectric layer to form a first groove in the first shielding dielectric layer, wherein the first groove exposes a part of the semiconductor material layer; Perform a second etching process on the semiconductor material layer to form a second groove in the semiconductor material layer, wherein the depth of the second groove is greater than the depth of the first groove, the second groove exposes the first sidewall of the portion of the first shielding dielectric layer located below the first groove, and the first groove communicates with the second groove to define a third groove; and Form a first gate structure in the third groove.

12. The manufacturing method according to claim 11, wherein forming the first shielding structure in the semiconductor material layer comprises:[[]] Form a first trench in the semiconductor layer; Form the first shielding dielectric layer along the sidewall of the first trench in the first trench; and Form the first shielding electrode in the first trench, wherein the top surface of the first shielding electrode, the top surface of the first shielding dielectric layer, and the top surface of the semiconductor material layer are located at approximately the same horizontal height.

13. The manufacturing method according to claim 11, which further comprises:[[]] After forming the first gate structure, perform a first ion implantation process on the semiconductor material layer to form a body doping region, wherein the body doping region has a second conductivity type different from that of the lightly doped region.

14. The manufacturing method according to claim 13, wherein the depth of the body doping region is less than the depth of the first gate structure.

15. The manufacturing method according to claim 13, which further comprises:[[]] Perform a second ion implantation process on the semiconductor material layer to form a source doping region, wherein the source doping region has the same first conductivity type as the lightly doped region, and the doping concentration of the first conductivity type ions in the source doping region is greater than the doping concentration of the first conductivity type ions in the lightly doped region.

16. The manufacturing method according to claim 11, wherein the second groove exposes the semiconductor material layer of the portion adjacent to the first shielding structure, and the manufacturing method further comprises:[[]] After the second etching process, form a first sacrificial layer on the exposed portion of the semiconductor material layer in the second groove; and Before forming the first gate structure, remove the first sacrificial layer.

17. The manufacturing method according to claim 11, wherein forming the first gate structure comprises:[[]] Form a first gate dielectric layer on the semiconductor material layer in the third groove; and Form a first gate electrode in the third groove, wherein the width of the upper portion of the first gate electrode is greater than the width of the lower portion of the first gate electrode.

18. The manufacturing method according to claim 17, wherein the width of the upper portion of the first gate electrode is between 0.6 micrometers and 0.8 micrometers.

19. The manufacturing method according to claim 17, wherein the thickness of the first shielding dielectric layer adjacent to the upper portion of the first gate electrode is between 0.1 micrometer and 0.2 micrometer.

20. The manufacturing method according to claim 11, wherein the thickness of the first shielding dielectric layer located below the first gate electrode is between 0.6 micrometers and 0.8 micrometers.

21. The manufacturing method according to claim 11, further comprising: forming a first conductive plug electrically connected to the first shielding structure; and forming a second conductive plug electrically connected to the first gate structure.

22. The manufacturing method according to claim 21, wherein the depth of the first conductive plug or the second conductive plug in the semiconductor material layer is greater than the depth of the source doping region in the semiconductor material layer.

23. The manufacturing method according to claim 11, wherein at least one of the first etching process and the second etching process comprises a dry etching process.

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