Electronic device

Abstract

The invention provides an electronic device. The electronic device comprises a substrate and an electronic element. The electronic component is arranged on the substrate and comprises a first grid electrode, a semiconductor pattern, a source electrode, a drain electrode and a second grid electrode. The semiconductor pattern includes an overlap region, a first side region, and a second side region. A portion where the semiconductor pattern and the first gate overlap is defined as an overlap region. In the first direction, the first side area and the second side area are respectively connected with two opposite sides of the overlapping area. The first side region and the second side region respectively comprise two opposite first edges of the semiconductor pattern. The source electrode and the drain electrode are electrically connected to the first side region and the second side region respectively. At least a portion of the second gate overlaps the second side region of the semiconductor pattern.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and particularly to an electronic device having two gates with different sizes. Background Art

[0002] Currently, thin film transistors are increasingly applied to products with high voltage operations (such as electrophoretic displays, antenna devices, etc.). However, with the increase in the operating voltage, thin film transistors face problems such as increased leakage current and increased size. Summary of the Invention

[0003] The present disclosure provides an electronic device, which helps to improve the problems of increased leakage current or increased size.

[0004] According to an embodiment of the present disclosure, the electronic device includes a substrate and electronic components. The electronic components are disposed on the substrate and include a first gate, a semiconductor pattern, a source electrode, a drain electrode, and a second gate. The semiconductor pattern includes an overlapping region, a first side region, and a second side region. The overlapping portion of the semiconductor pattern and the first gate is defined as the overlapping region. In a first direction, the first side region and the second side region are respectively connected to two opposite sides of the overlapping region. The first side region and the second side region respectively include two opposite first edges of the semiconductor pattern. The source electrode and the drain electrode are respectively electrically connected to the first side region and the second side region. At least a part of the second gate overlaps the second side region of the semiconductor pattern.

[0005] To make the above features and advantages of the present disclosure more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. Brief Description of the Drawings

[0006] Figure 1 is a top view schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0007] Figure 2 is a partial cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0008] Figure 3 is corresponding to Figure 2 a partial top view schematic diagram of an embodiment;

[0009] Figure 4 is a partial cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure;

[0010] Figure 5 and Figure 6 are respectively corresponding to Figure 4 two partial top view schematic diagrams of an embodiment;

[0011] Figure 7 is a partial cross-sectional schematic diagram of an electronic device according to yet another embodiment of the present disclosure;

[0012] Figure 8 is a partial top view corresponding to Figure 7 an embodiment;

[0013] Figure 9 is a partial cross-sectional view of an electronic device according to another embodiment of the present disclosure;

[0014] Figure 10 is corresponding to Figure 9 a partial top view of an embodiment;

[0015] Figures 11 to 16 are respectively partial cross-sectional views of electronic devices according to other embodiments of the present disclosure. Detailed Description of the Embodiments

[0016] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0017] Throughout the specification of the present disclosure and the appended claims, certain terms will be used to refer to particular elements. Those skilled in the art should understand that electronic device manufacturers may refer to the same element by different names. This document is not intended to distinguish between elements that have the same function but different names. In the following specification and claims, words such as "comprising" and "including" are open-ended terms, and thus should be interpreted to mean "including but not limited to...".

[0018] Directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions in the drawings. Therefore, the directional terms used are for illustration and not for limiting the present disclosure. In the drawings, each drawing shows the general characteristics of the methods, structures, and / or materials used in a particular embodiment. However, these drawings should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses, and positions of each film layer, region, and / or structure may be reduced or enlarged.

[0019] A structure (or layer, element, substrate) described in this disclosure being located "above" or "on top of" another structure (or layer, element, substrate) can mean that the two structures are adjacent and directly connected, or it can mean that the two structures are adjacent but not directly connected. Not being directly connected means that there is at least one intermediate structure (or intermediate layer, intermediate element, intermediate substrate, intermediate gap) between the two structures. The lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. And the intermediate structure can be composed of a single-layer or multi-layer solid structure or non-solid structure, without limitation. In this disclosure, when a certain structure is disposed "on" other structures, it may mean that a certain structure is "directly" on other structures, or it may mean that a certain structure is "indirectly" on other structures, that is, there is at least one structure sandwiched between a certain structure and other structures.

[0020] The terms "about", "equal to", "equivalent to" or "the same as", "substantially" or "substantially" are generally interpreted as being within 20% of the given value or range, or as being within 10%, 5%, 3%, 2%, 1% or 0.5% of the given value or range. In addition, the expressions "ranging from a first value to a second value", "ranging between a first value and a second value" mean that the said range includes the first value, the second value and other values therebetween.

[0021] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify elements. They do not themselves imply or represent that the said (or those) elements have any previous ordinal numbers, nor do they represent the order of one element and another element, or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish an element with a certain name from another element with the same name. The same terms may not be used in the claims and the specification. Accordingly, the first component in the specification may be the second component in the claim.

[0022] The electrical connection or coupling described in this disclosure can refer to direct connection or indirect connection. In the case of direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment. In the case of indirect connection, there are switches, diodes, capacitors, inductors, resistors, other suitable components, or combinations of the above components between the endpoints of the components on the two circuits, but not limited thereto.

[0023] In this disclosure, the thickness, length, and width can be measured using an optical microscope (OM), and the thickness or width can be measured from a cross-sectional image in an electron microscope, but this is not limited thereto. Additionally, there may be a certain error between any two values or directions being compared. Further, the terms "equal to", "equal", "the same", "substantially", or "substantially" as used in this disclosure generally represent within 10% of a given value or range. Moreover, the phrases "a given range is from a first value to a second value", "a given range falls within the range from a first value to a second value", or "a given range is between a first value and a second value" mean that the given range includes the first value, the second value, and other values therebetween. If a first direction is perpendicular to a second direction, the angle between the first direction and the second direction can be between 80 degrees and 100 degrees; if a first direction is parallel to a second direction, the angle between the first direction and the second direction can be between 0 degrees and 10 degrees.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this disclosure belongs. It is understood that these terms, such as those defined in a commonly used dictionary, should be interpreted to have a meaning consistent with the relevant technology and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0025] In the present disclosure, the electronic device may include, but is not limited to, a display device, a backlight device, an antenna device, a sensing device, or a splicing device. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The display device may include, for example, liquid crystal, light-emitting diode, fluorescence, phosphor, quantum dot (QD), other suitable display media, or a combination of the foregoing. The antenna device may include, for example, a Frequency Selective Surface (FSS), an RF-Filter, a Polarizer, a Resonator, or an Antenna, etc. The antenna may be an antenna in a liquid crystal form or an antenna in a non-liquid crystal form. The sensing device may be a sensing device for sensing capacitance, light, heat, or ultrasonic waves, but is not limited thereto. In the present disclosure, the electronic device may include electronic components, and the electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. The light-emitting diode may include, for example, an organic light-emitting diode (OLED), a mini LED, a micro LED, or a quantum dot LED, but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any permutation and combination of the foregoing, but is not limited thereto. In addition, the shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a driving system, a control system, and a light source system to support the display device, the antenna device, a wearable device (such as including augmented reality or virtual reality), a vehicle-mounted device (such as including an automotive windshield), or a splicing device.

[0026] It should be noted that, without departing from the spirit of the present disclosure, the features in several different embodiments may be replaced, recombined, and mixed to complete other embodiments in the following embodiments. As long as the features between the embodiments do not violate the spirit of the invention or conflict with each other, they can be arbitrarily mixed and used.

[0027] Figure 1 is a top view schematic diagram of an electronic device according to an embodiment of the present disclosure. Please refer to Figure 1 , the electronic device may include an active region RA and a peripheral region RB. The peripheral region RB may be located on at least one side of the active region RA. In some embodiments, as Figure 1As shown, the peripheral region RB can surround the active region RA on all four sides, but is not limited thereto. Figure 1 In Figure 1 , the boundary IF between the active region RA and the peripheral region RB is marked with a thick solid line to facilitate distinguishing the active region RA and the peripheral region RB. According to some embodiments, the substrate 10 may include the active region RA and the peripheral region RB.

[0028] A plurality of units U ( Figure 1 schematically marked with one) can be disposed in the active region RA. The plurality of units U can be arranged in an array in the first direction D1 and the second direction D2. The types of elements in the unit U can vary according to the application of the electronic device. For example, if the electronic device is a display device, the unit U may include display elements and switching elements, but is not limited thereto. On the other hand, if the electronic device is an antenna device, the unit U may include antenna structures and switching elements, but is not limited thereto.

[0029] A plurality of driving circuits C can be disposed in the peripheral region RB. The plurality of driving circuits C are electrically connected to the plurality of units U in the active region RA. For example, the plurality of driving circuits C can be electrically connected to the plurality of units U in the active region RA through a plurality of wires (not marked). The driving circuit C can include active elements, passive elements, or a combination of the above, but is not limited thereto. The plurality of wires can include wires extending along the first direction D1 (such as scan lines) and wires extending along the second direction D2 (such as data lines). The electronic elements including semiconductor patterns, first gates, and second gates described hereinafter can be implemented in the switching elements in the unit U or the active elements in the driving circuit C, and will not be repeated hereinafter.

[0030] Figure 2 is a partial cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure. Figure 3 is corresponding to Figure 2 a partial top-down schematic diagram of the embodiment, wherein Figure 3 the cross-sectional view along the section line 2-2' can be referred to Figure 2 and Figure 3 only schematically shows Figure 2 the semiconductor pattern, the first gate, the second gate, the source, and the drain in

[0031] Please refer to Figure 2 and Figure 3, the electronic device 1 may include a substrate 10 and electronic components 12. The electronic components 12 are disposed on the substrate 10. The electronic components 12 may be, for example, the switching elements in the aforementioned unit U or the active elements in the aforementioned driving circuit C, and are not limited herein. According to some embodiments, the electronic components 12 may be disposed in the peripheral region RB. According to some embodiments, the electronic components 12 may be disposed in the active region RA. The electronic components 12 include a first gate GE1, a semiconductor pattern CH, a source SE, a drain DE, and a second gate GE2. The semiconductor pattern CH includes an overlapping region R1, a first side region R2, and a second side region R2'. The portion where the semiconductor pattern CH overlaps with the first gate GE1 is defined as the overlapping region R1. In the first direction D1, the first side region R2 and the second side region R2' are respectively connected to two opposite sides of the overlapping region R1. The first side region R2 and the second side region R2' respectively include two opposite first edges (such as the first edge EC1 and the first edge EC2) of the semiconductor pattern CH. The source SE and the drain DE are respectively electrically connected to the first side region R2 and the second side region R2'. At least a portion of the second gate GE2 overlaps with the second side region R2' of the semiconductor pattern CH. Figure 3 is a top view, which can show the plane formed by the first direction D1 and the second direction D2. Figure 2 is a cross-sectional view, and the thickness of each layer in the figure is the thickness along the third direction D3. The first direction D1, the second direction D2, and the third direction D3 are different directions. For example, the first direction D1, the second direction D2, and the third direction D3 may be perpendicular to each other.

[0032] Specifically, the substrate 10 may be a rigid substrate or a flexible substrate. The material of the substrate 10 includes, for example, glass, quartz, ceramics, sapphire, or plastic, etc., but is not limited thereto. The plastic may include polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), other suitable flexible materials, or a combination of the foregoing materials, but is not limited thereto. In addition, the light transmittance of the substrate 10 is not limited, that is, the substrate 10 may be a light-transmitting substrate, a semi-light-transmitting substrate, or an opaque substrate.

[0033] The electronic component 12 is, for example, an active component, such as a low-temperature polycrystalline silicon (LTPS) N-type metal-oxide-semiconductor (NMOS) thin film transistor (TFT), but is not limited thereto.

[0034] The semiconductor pattern CH is disposed on the substrate 10 and is located, for example, between the first gate GE1 and the substrate 10. The material of the semiconductor pattern CH includes, for example, amorphous silicon, polysilicon, or metal oxide, but is not limited thereto. The metal oxide may be, for example, indium gallium zinc oxide (IGZO). For example, the overlapping region R1 of the semiconductor pattern CH may be a channel region (i.e., the region where the semiconductor pattern CH overlaps the first gate GE1 in the third direction D3), and the first side region R2 and the second side region R2' of the semiconductor pattern CH may each include an N-type highly doped region (such as the N-type highly doped region R21 and the N-type highly doped region R21') and an N-type lightly doped region (such as the N-type lightly doped region R22 and the N-type lightly doped region R22') located between the overlapping region R1 and the N-type highly doped region, and the second gate GE2 overlaps at least the N-type lightly doped region of the second side region R2' (for example, at least overlaps the N-type lightly doped region R22'). Taking Figure 2 and Figure 3 as an example, the second gate GE2 may extend from above the overlapping region R1 toward above the N-type highly doped region (including the N-type highly doped region R21 and the N-type highly doped region R21'), such that in the length direction (such as the first direction D1) of the semiconductor pattern CH, the edge of the second gate GE2 is closer to the edge of the semiconductor pattern CH than the edge of the first gate GE1.

[0035] The first gate GE1 and the second gate GE2 may have different sizes. Specifically, according to some embodiments, as Figure 3 shown, in the first direction D1, the first gate GE1 has two opposite second edges (such as the second edge E21 and the second edge E22), and the second gate GE2 has two opposite third edges (such as the third edge E31 and the third edge E32). On a single side of the semiconductor pattern, with the semiconductor edge of the semiconductor pattern on this side as a reference, the distance between the second gate and the semiconductor edge is smaller than the distance between the first gate and the same semiconductor edge. In detail, on a single side of the semiconductor pattern (for example Figure 3 the left side in), with the semiconductor edge (such as the first edge EC1) of the semiconductor pattern on this side as a reference, the distance DT13 between the third edge E31 of the second gate GE2 and the corresponding first edge EC1 of the semiconductor pattern CH is less than the distance DT12 between the second edge E21 of the first gate GE1 and the corresponding first edge EC1 of the semiconductor pattern CH. On the other side of the semiconductor pattern (for example Figure 3on the right side in), taking the semiconductor edge (such as the first edge EC2) of the semiconductor pattern on the other side as a reference, the distance DT13’ between the third edge E32 of the second gate GE2 and the first edge EC2 corresponding to the semiconductor pattern CH is less than the distance DT12’ between the second edge E22 of the first gate GE1 and the first edge EC2 corresponding to the semiconductor pattern CH.

[0036] In Figure 3 In it, the third edge E31 of the second gate GE2 extends beyond the junction IF21 between the N-type highly doped region R21 and the N-type lightly doped region R22, and the third edge E31 is located between the junction IF21 and the first edge EC1 of the semiconductor pattern CH. In addition, the third edge E32 of the second gate GE2 extends beyond the junction IF22 between the N-type highly doped region R21’ and the N-type lightly doped region R22’, and the third edge E32 is located between the junction IF22 and the first edge EC2 of the semiconductor pattern CH. However, the positions of the third edge E31 and the third edge E32 of the second gate GE2 are not limited to this. In other embodiments, although not shown, the third edge E31 may not extend beyond the junction IF21. For example, the third edge E31 may be located between the junction IF11 and the junction IF21 between the overlapping region R1 and the N-type lightly doped region R22, or the third edge E31 may be flush with the junction IF21. In addition, the third edge E32 may not extend beyond the junction IF22. For example, the third edge E32 may be located between the junction IF12 and the junction IF22 between the overlapping region R1 and the N-type lightly doped region R22’, or the third edge E32 may be flush with the junction IF22.

[0037] In some embodiments, such as Figure 2 shown, the electronic device 1 may further include a first dielectric layer 14. The first dielectric layer 14 is disposed between the semiconductor pattern CH and the first gate GE1. The material of the first dielectric layer 14 includes, for example, an organic insulating material, an inorganic insulating material, or a combination of the above. The organic insulating material includes, for example, polymethyl methacrylate (PMMA), epoxy resin, acrylic-based resin, silicone, polyimide polymer, or a combination of the above, but is not limited thereto. The inorganic insulating material includes, for example, silicon oxide or silicon nitride, but is not limited thereto.

[0038] The first gate GE1 is disposed, for example, on the first dielectric layer 14 and above the overlapping region R1. In some embodiments, the second edge E21 and the second edge E22 of the first gate GE1 may be respectively flush with the junction IF11 and the junction IF12, but are not limited thereto. The material of the first gate GE1 includes, for example, a metal or a metal stack, such as aluminum, molybdenum, or titanium / aluminum / titanium, but is not limited thereto.

[0039] In some embodiments, as Figure 2 shown, the electronic device 1 may further include a second dielectric layer 16. The second dielectric layer 16 is disposed on the first dielectric layer 14 and the first gate GE1 and is, for example, located between the first gate GE1 and the second gate GE2. The material of the second dielectric layer 16 includes, for example, an organic insulating material, an inorganic insulating material, or a combination of the above.

[0040] The second gate GE2 is, for example, disposed on the second dielectric layer 16, and in a top view, at least a part of the second gate GE2 is located between the first gate GE1 and the drain DE. By way of Figure 3 example, the second gate GE2 may, for example, cover the overlapping region R1, the N-type lightly doped region R22, the N-type lightly doped region R22', the local N-type highly doped region R21, and the local N-type highly doped region R21', but is not limited thereto. The material of the second gate GE2 includes, for example, a metal or a metal stack, such as aluminum, molybdenum, or titanium / aluminum / titanium, but is not limited thereto.

[0041] The source SE and the drain DE are, for example, disposed on the second dielectric layer 16, and the second gate GE2, the source SE, and the drain DE belong to the same conductive layer, for example. Specifically, the electronic component 12 may include a conductive layer, and the conductive layer includes the second gate GE2, the source SE, and the drain DE. As Figure 2 shown, the source SE may penetrate through the first dielectric layer 14 and the second dielectric layer 16 to be electrically connected to the N-type highly doped region R21. In addition, the drain DE may penetrate through the first dielectric layer 14 and the second dielectric layer 16 to be electrically connected to the N-type highly doped region R21'.

[0042] By the arrangement of the second gate GE2, while reducing the leakage current, the on-current (Ion) of the electronic component 12 can be not significantly reduced. In detail, taking an LTPS NMOS TFT as an example, when the electronic component 12 is in the off state (for example, when the voltage of the first gate GE1 is less than zero), by making the voltage of the second gate GE2 less than zero, the electrons accumulated on the upper surface (the surface facing the first gate GE1) of the N-type lightly doped region (including the N-type lightly doped region R22 and the N-type lightly doped region R22') can be reduced, so that the resistance value of the N-type lightly doped region is increased, which helps to reduce the leakage current of the electronic component 12. On the other hand, when the electronic component 12 is in the on state (for example, when the voltage of the first gate GE1 is greater than zero), by making the voltage of the second gate GE2 greater than zero, electrons can be induced to accumulate on the upper surface of the N-type lightly doped region, so that the resistance value of the N-type lightly doped region is reduced, which helps to increase the on-current of the electronic component 12.

[0043] In Figure 2Under the architecture, the first gate GE1 and the semiconductor pattern CH are separated by the first dielectric layer 14, while the second gate GE2 and the semiconductor pattern CH are separated by the first dielectric layer 14 and the second dielectric layer 16. That is to say, the influence of the first gate GE1 on the carriers in the semiconductor pattern CH is related to the thickness and dielectric constant of the first dielectric layer 14, while the influence of the second gate GE2 on the carriers in the semiconductor pattern CH is related not only to the thickness and dielectric constant of the first dielectric layer 14, but also to the thickness and dielectric constant of the second dielectric layer 16. In some embodiments, the absolute value of the voltage applied to the second gate GE2 is, for example, greater than or equal to the absolute value of the voltage applied to the first gate GE1.

[0044] The electronic device can be a high breakdown voltage product. According to some embodiments, the breakdown voltage between the source and the drain in the electronic device can be between 8 volts and 70 volts, for example, between 10 volts and 60 volts, for example, between 15 volts and 50 volts, for example, between 20 volts and 50 volts, and for example, can be greater than 10 volts. When the electronic component 12 is applied to a product with high-voltage operation (for example, the breakdown voltage between the source SE and the drain DE is greater than 10 volts), such as being applied to an electrophoretic display or an antenna device, the setting of the second gate GE2 helps to miniaturize the electronic component 12. Specifically, taking an LTPS NMOS TFT as an example, when the electronic component 12 is in the off state (for example, when the voltage of the first gate GE1 is less than zero) or in the on state (for example, when the voltage of the first gate GE1 is greater than zero), by making the voltage of the second gate GE2 less than zero, the resistance values of the N-type lightly doped regions (including the N-type lightly doped region R22 and the N-type lightly doped region R22') can be increased, thereby reducing the effect of the channel region electric field and improving the breakdown voltage tolerance of the electronic component 12. In this way, it is not necessary to increase the length of the N-type lightly doped region in the first direction D1 to improve the breakdown voltage tolerance of the electronic component 12, which helps to miniaturize the electronic component 12.

[0045] Figure 4 is a partial cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. Figure 5 and Figure 6 are respectively Figure 4 two partial top-down schematic diagrams corresponding to Figure 5 and Figure 6 The cross-sectional view along the cutting line 4-4' in Figure 4 can be referred to Figure 5 and Figure 6 only schematically show Figure 4 the semiconductor pattern, the first gate, the second gate, the source, and the drain in

[0046] In some embodiments, as Figure 4 and Figure 5As shown in the electronic device 1A, the second gate GE2 may include a first branch GE21 and a second branch GE22. In a top view, as Figure 5 shown, a part of the first branch GE21 may be disposed between the first gate GE1 and the drain DE, and a part of the second branch GE22 may be disposed between the first gate GE1 and the source SE. The first branch GE21 and the second branch GE22 may be electrically independent or electrically connected. In some embodiments, as Figure 6 shown, the second gate GE2 may further include a connecting portion GE23. The first branch GE21 and the second branch GE22 of the second gate GE2 are connected via the connecting portion GE23. In a top view, a recess (such as a U-shaped second gate GE2) is formed by the first branch GE21, the second branch GE22, and the connecting portion GE23. The extending direction of the recess is, for example, parallel to the second direction D2.

[0047] In the electronic device 1A, by reducing the overlapping area between the first gate GE1 and the second gate GE2, the stray capacitance between the first gate GE1 and the second gate GE2 can be reduced, which helps to reduce the signal interference between the first gate GE1 and the second gate GE2.

[0048] In Figure 5 and Figure 6 , a third edge E31 of the second gate GE2 is located between the junction IF21 and a first edge EC1 of the semiconductor pattern CH, a third edge E32 of the second gate GE2 is located between the junction IF22 and a first edge EC2 of the semiconductor pattern CH, a third edge E33 of the second gate GE2 is located between the junction IF11 and a third edge E34 of the second gate GE2, and a third edge E34 of the second gate GE2 is located between the junction IF12 and the third edge E33 of the second gate GE2. However, the positions of the third edge E31, the third edge E32, the third edge E33, and the third edge E34 of the second gate GE2 are not limited thereto. In other embodiments, although not shown, the third edge E31 may be located between the junction IF11 and the junction IF21 or flush with the junction IF21. The third edge E32 may be located between the junction IF12 and the junction IF22 or flush with the junction IF22. The third edge E33 may be located between the junction IF11 and the junction IF21 or flush with the junction IF11. The third edge E34 may be located between the junction IF12 and the junction IF22 or flush with the junction IF12.

[0049] Figure 7 is a partial cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. Figure 8 is corresponding to Figure 7 an embodiment of a partial top view schematic diagram, where Figure 8The cross-sectional view along the line 7-7' can be referred to Figure 7 , and Figure 8 only schematically shows Figure 7 the semiconductor pattern, the first gate, the second gate, the source, and the drain in

[0050] In some embodiments, as shown in the electronic device 1B of Figure 7 and Figure 8 , the second gate GE2 can be located on the side of the first gate GE1 closer to the drain DE.

[0051] In Figure 8 , the third edge E32 of the second gate GE2 is located between the junction IF22 and the first edge EC2 of the semiconductor pattern CH, and the third edge E34 of the second gate GE2 is located between the junction IF12 and the junction IF11. However, the positions of the third edge E32 and the third edge E34 of the second gate GE2 are not limited thereto. In other embodiments, although not shown, the third edge E32 can be located between the junction IF12 and the junction IF22 or flush with the junction IF22. The third edge E34 can be located between the junction IF12 and the junction IF22 or flush with the junction IF12.

[0052] Figure 9 is a partial cross-sectional schematic view of an electronic device according to still another embodiment of the present disclosure. Figure 10 is corresponding to Figure 9 a partial top-down schematic view of an embodiment, where Figure 10 the cross-sectional view along the line 9-9' can be referred to Figure 9 , and Figure 10 only schematically shows Figure 9 the semiconductor pattern, the first gate, the second gate, the source, and the drain in

[0053] In some embodiments, as shown in the electronic device 1C of Figure 9 and Figure 10 , the second gate GE2 can be physically connected to the drain DE. For example, the second gate GE2 is in direct contact with the drain DE, and the second gate GE2 and the drain DE can be formed by the same patterning process, such that there is no obvious junction between the second gate GE2 and the drain DE. In this architecture, in the top-down view, the junction IF22 can be used as the junction between the second gate GE2 and the drain DE.

[0054] In Figure 10 , the third edge E34 of the second gate GE2 is located between the junction IF12 and the junction IF11. However, the position of the third edge E34 of the second gate GE2 is not limited thereto. In other embodiments, although not shown, the third edge E34 can be located between the junction IF12 and the junction IF22 or flush with the junction IF12.

[0055] Figures 11 to 16 Partial cross-sectional schematic diagrams of electronic devices according to other embodiments of the present disclosure. Please first refer to Figure 11 , the main differences between the electronic device 1D and the Figure 2 electronic device 1 are described as follows. In the electronic device 1D, in the cross-sectional view, the second gate GE2 and the first gate GE1 are respectively located on opposite sides of the semiconductor pattern CH. For example, the second gate GE2 and the first gate GE1 are respectively located on opposite sides of the semiconductor pattern CH in the third direction D3. Specifically, the second gate GE2 is disposed on the substrate 10, for example. The electronic device 1D further includes a third dielectric layer 18, where the third dielectric layer 18 is disposed on the substrate 10 and the second gate GE2 and is located between the second gate GE2 and the semiconductor pattern CH, for example. The material of the third dielectric layer 18 includes, for example, an organic insulating material, an inorganic insulating material, or a combination of the above.

[0056] By respectively disposing the second gate GE2 and the first gate GE1 on opposite sides of the semiconductor pattern CH, the distance between the second gate GE2 and the semiconductor pattern CH can be shortened, which helps to reduce the absolute value of the voltage applied to the second gate GE2. In the Figure 11 architecture, the influence of the second gate GE2 on the carriers in the semiconductor pattern CH is related to the thickness and dielectric constant of the third dielectric layer 18, and the absolute value of the voltage applied to the second gate GE2 can be greater than, less than, or equal to the absolute value of the voltage applied to the first gate GE1.

[0057] Figure 11 For the top view of the second gate GE2 in Figure 3 , reference can be made to Figure 11 , which will not be repeated here. In addition, in

[0058] , the third edge E31 of the second gate GE2 is located between the junction IF21 and the junction IF11, and the third edge E32 of the second gate GE2 is located between the junction IF12 and the junction IF22. However, the positions of the third edge E31 and the third edge E32 of the second gate GE2 are not limited thereto. In other embodiments, although not shown, the third edge E31 may be located between the first edge EC1 of the semiconductor pattern CH and the junction IF21 or flush with the junction IF21. The third edge E32 may be located between the first edge EC2 of the semiconductor pattern CH and the junction IF22 or flush with the junction IF22.

[0058] Please refer to Figure 12 , the main differences between the electronic device 1E and the Figure 11 electronic device 1D are described as follows. In the electronic device 1E, the second gate GE2 includes a first branch GE21 and a second branch GE22. In some embodiments, although not shown in Figure 12 , the second gate GE2 may further include a connecting portion GE23 (refer toFigure 6 )。

[0059] Figure 12 The top view of the second gate GE2 in Figure 5 may be referred to, and will not be repeated here. In addition, in Figure 12 , the third edge E31 of the second gate GE2 is located between the junction IF21 and the first edge EC1 of the semiconductor pattern CH, the third edge E32 of the second gate GE2 is located between the junction IF22 and the first edge EC2 of the semiconductor pattern CH, the third edge E33 of the second gate GE2 is located between the junction IF11 and the third edge E34 of the second gate GE2, and the third edge E34 of the second gate GE2 is located between the junction IF12 and the third edge E33 of the second gate GE2. However, the positions of the third edge E31, the third edge E32, the third edge E33, and the third edge E34 of the second gate GE2 are not limited thereto. In other embodiments, although not shown, the third edge E31 may be located between the junction IF21 and the junction IF11 or flush with the junction IF21. The third edge E32 may be located between the junction IF12 and the junction IF22 or flush with the junction IF22. The third edge E33 may be located between the junction IF21 and the junction IF11 or flush with the junction IF11. The third edge E34 may be located between the junction IF12 and the junction IF22 or flush with the junction IF12.

[0060] Please refer to Figure 13 , the main differences between the electronic device 1F and the Figure 12 electronic device 1E are described as follows. In the electronic device 1F, the second gate GE2 is located on the side of the first gate GE1 closer to the drain DE.

[0061] Figure 13 The top view of the second gate GE2 in Figure 8 may be referred to, and will not be repeated here. In addition, in Figure 13 , the third edge E32 of the second gate GE2 is located between the junction IF22 and the first edge EC2 of the semiconductor pattern CH, and the third edge E34 of the second gate GE2 is located between the junction IF12 and the junction IF11. However, the positions of the third edge E32 and the third edge E34 of the second gate GE2 are not limited thereto. In other embodiments, although not shown, the third edge E32 may be located between the junction IF12 and the junction IF22 or flush with the junction IF22. The third edge E34 may be located between the junction IF12 and the junction IF22 or flush with the junction IF12.

[0062] Please refer to Figure 14 , the electronic device 1G and Figure 13The main differences of the electronic device 1F are described as follows. In the electronic device 1G, the second gate GE2 is electrically connected to the drain DE through the N-type highly doped region R21'. For Figure 14 example, the electronic device 1G may further include a via CV, where the via CV electrically connects the second gate GE2 to the N-type highly doped region R21', enabling the second gate GE2 to be electrically connected to the drain DE through the via CV and the N-type highly doped region R21'.

[0063] In Figure 14 , the third edge E34 of the second gate GE2 is located between the junction IF12 and the junction IF11. However, the position of the third edge E34 of the second gate GE2 is not limited thereto. In other embodiments, although not shown, the third edge E34 may be located between the junction IF12 and the junction IF22 or flush with the junction IF12.

[0064] Please refer to Figure 15 , the main differences of the electronic device 1H and the Figure 2 electronic device 1 are described as follows. In the electronic device 1H, the first dielectric layer 14 includes a first portion P1 and a second portion P2 connected to the first portion P1 in the first direction D1, where the first portion P1 is located between the overlapping region R1 of the semiconductor pattern CH and the first gate GE1, and the thickness TH1 of the first portion P1 is less than the thickness TH2 of the second portion P2. By increasing the thickness at the edges of the corresponding overlapping region R1 of the first dielectric layer 14, the N-type highly doped region R21, the N-type highly doped region R21', the N-type lightly doped region R22, and the N-type lightly doped region R22', the electric field between the first gate GE1 and the drain DE can be reduced, which helps to reduce the leakage current.

[0065] Although Figure 15 is for the thickness design of the first dielectric layer 14 under the Figure 2 architecture, it should be understood that this thickness design is applicable to any embodiment of the present disclosure and will not be repeated here.

[0066] Please refer to Figure 16 , the main differences of the electronic device 1I and the Figure 12 electronic device 1E are described as follows. In the electronic device 1I, the electronic component 12 includes, for example, a low-temperature polysilicon P-type metal-oxide-semiconductor (P-MOS) thin-film transistor. In the semiconductor pattern CH, the overlapping region R1 is, for example, a channel region, and the first side region R2 and the second side region R2' each include, for example, a P-type highly doped region, for example, the first side region R2 includes the P-type highly doped region R23, and the second side region R2' includes the P-type highly doped region R23').

[0067] Although Figure 16is to change the type of semiconductor pattern under the architecture of Figure 12 , but it should be understood that the type of semiconductor pattern in any embodiment of the present disclosure can be changed in the same way. Alternatively, the design of the second gate GE2 and / or the first dielectric layer 14 can be changed according to the foregoing embodiments under the architecture of Figure 16 . For example, reference can be made to Figures 2 to 14 to change Figure 16 the configuration of the second gate GE2 in Figure 15 , and / or adopt the thickness design of the first dielectric layer 14 in

[0068] In summary, in the embodiments of the present disclosure, by setting the second gate, the leakage current can be reduced while not significantly reducing the on-current of the electronic component. When the electronic component is applied to a product for high-voltage operation, setting the second gate helps to miniaturize the electronic component.

[0069] The above embodiments are only used to illustrate the technical solutions of the present disclosure, and are not intended to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

[0070] Although the embodiments of the present disclosure and their advantages have been disclosed as above, it should be understood that any person skilled in the art can make changes, substitutions and refinements without departing from the spirit and scope of the present disclosure, and the features between the embodiments can be arbitrarily mixed and replaced to form other new embodiments. In addition, the protection scope of the present disclosure is not limited to the processes, machines, manufactures, compositions of matter, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the processes, machines, manufactures, compositions of matter, devices, methods and steps developed currently or in the future from the disclosure content of the present disclosure, as long as they can perform substantially the same functions or obtain substantially the same results in the embodiments described herein, they can be used according to the present disclosure. Therefore, the protection scope of the present disclosure includes the above processes, machines, manufactures, compositions of matter, devices, methods and steps. In addition, each claim constitutes an individual embodiment, and the protection scope of the present disclosure also includes the combination of each claim and embodiment. The protection scope of the present disclosure shall be defined by the appended claims.

Claims

1. An electronic device, characterized in that, comprising: a substrate; and electronic components, disposed on the substrate and comprising: a first gate; a semiconductor pattern, including an overlapping region, a first side region, and a second side region, wherein a portion where the semiconductor pattern overlaps with the first gate is defined as the overlapping region, in a first direction, the first side region and the second side region are respectively connected to two opposite sides of the overlapping region, and the first side region and the second side region respectively include two opposite first edges of the semiconductor pattern; a source electrode and a drain electrode, electrically connected to the first side region and the second side region respectively; and a second gate, at least a portion of the second gate overlapping with the second side region of the semiconductor pattern.

2. The electronic device according to claim 1, characterized in that, in the first direction, the first gate has two opposite second edges, the second gate has two opposite third edges, a distance between one of the third edges of the second gate and a corresponding one of the first edges of the semiconductor pattern is less than a distance between one of the second edges of the first gate and the corresponding one of the first edges of the semiconductor pattern.

3. The electronic device according to claim 1, characterized in that, each of the first side region and the second side region includes a P-type highly doped region.

4. The electronic device according to claim 1, characterized in that, each of the first side region and the second side region includes an N-type highly doped region and an N-type lightly doped region located between the overlapping region and the N-type highly doped region, and the second gate at least overlaps with the N-type lightly doped region of the second side region.

5. The electronic device according to claim 1, characterized in that, further comprising: a first dielectric layer, disposed between the semiconductor pattern and the first gate, wherein the first dielectric layer includes a first portion and a second portion connected to the first portion in the first direction, the first portion is located between the overlapping region of the semiconductor pattern and the first gate, wherein a thickness of the first portion is less than a thickness of the second portion.

6. The electronic device according to claim 1, characterized in that, in a top view, at least a portion of the second gate is located between the first gate and the drain electrode.

7. The electronic device according to claim 1, characterized in that, the second gate includes a first branch portion and a second branch portion, wherein in a top view, a portion of the first branch portion is disposed between the first gate and the drain electrode, and a portion of the second branch portion is disposed between the first gate and the source electrode.

8. The electronic device according to claim 7, characterized in that, the second gate further comprises: a connecting portion, the first branch portion and the second branch portion of the second gate are connected via the connecting portion, in the top view, a recess is formed by the first branch portion, the second branch portion, and the connecting portion.

9. The electronic device according to claim 1, characterized in that, The electronic component includes a conductive layer, and the conductive layer includes the second gate, the source electrode, and the drain electrode.

10. The electronic device according to claim 9, wherein, the second gate is physically connected to the drain electrode.

11. The electronic device according to claim 1, wherein, in a cross-sectional view, the second gate and the first gate are respectively located on opposite sides of the semiconductor pattern.

12. The electronic device according to claim 1, wherein, the breakdown voltage between the source electrode and the drain electrode is between 8 volts and 70 volts.

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