A ferroelectric semi-floating gate transistor with multi-level storage and logic functions and a method of manufacturing the same

Abstract

The application relates to a ferroelectric semi-floating gate transistor with multi-level storage and logic functions and a preparation method thereof, which comprises a first graphene layer and a second graphene layer which are arranged on a SiO2 / Si substrate; an alpha-In2Se3 thin layer is arranged on the first graphene layer; an h-BN thin layer is arranged on the alpha-In2Se3 thin layer and the second graphene layer; a WSe2 thin layer is arranged on the h-BN thin layer; a source and a drain are arranged at two ends of the WSe2 thin layer respectively, and a gate is arranged on the surface of the second graphene layer; the transistor is prepared through a mechanical stripping process, and the transistor shows excellent storage and photoelectric characteristics: a high programming / erasing ratio and good durability, a retention time of more than 10 seconds, multi-level storage functions with at least 7 controllable programming states are realized through double-gate modulation, and three digital logic gate operations can be performed under an ultra-low bias voltage of 10 mV. 4 ​

Description

Technical Field

[0001] This invention relates to the field of transistors, and more particularly to a ferroelectric semi-floating gate transistor with multi-level storage and logic functions and its fabrication method. Background Technology

[0002] The rapid development of artificial intelligence (AI) technology has led to a surge in model size and complexity, resulting in an ever-increasing demand for efficient data storage and processing capabilities. Traditional von Neumann architectures, due to the separation of storage and computing units, face energy consumption and latency issues, thus limiting processing speed and energy efficiency. To address this challenge, multifunctional devices have been developed that integrate data storage, sensing, and computing into a single device. This is particularly suitable for applications such as deep learning that require massive parallel processing, enabling matrix operations to be performed directly within a single device, reducing external memory access and power consumption, and improving processing speed.

[0003] In recent years, two-dimensional (2D) ferroelectric materials such as α-In₂Se₃ have been increasingly used in ferroelectric floating-gate transistors or ferroelectric field-effect transistors due to their unique ferroelectric polarization characteristics. Ferroelectric polarization allows devices to retain stored charge for extended periods without external interference, even after power is off, thus enabling long-term data storage and reducing the power consumption and latency issues caused by frequent data transfers in traditional von Neumann architectures. However, combining multiple functions such as non-volatile memory and digital logic operations in a single device remains challenging, which is crucial for developing highly integrated and low-power integrated circuit applications. Therefore, exploring the integration of storage and computing functions on a single transistor is a key step in advancing integrated circuits and artificial intelligence. Summary of the Invention

[0004] To address the technical problems existing in the prior art, the primary objective of this invention is to provide a ferroelectric semi-floating gate transistor with multi-level storage and logic functions, which can simultaneously realize multi-level memory and logic operations.

[0005] This invention provides a ferroelectric semi-floating gate transistor with multi-level storage and logic functions, comprising a SiO2 / Si substrate; a first graphene layer and a second graphene layer disposed on the SiO2 layer, with a gap between the first graphene layer and the second graphene layer; an α-In2Se3 thin layer disposed on the first graphene layer without contacting the second graphene layer; an h-BN thin layer disposed on the α-In2Se3 thin layer and the second graphene layer; and a WSe2 thin layer disposed on the h-BN thin layer, the boundary of the WSe2 thin layer not exceeding the boundary range of the h-BN thin layer.

[0006] The source and drain are respectively disposed at both ends of the WSe2 thin layer, and the gate is disposed on the surface of the second graphene layer.

[0007] This invention provides a method for fabricating a ferroelectric semi-floating gate transistor with multi-level storage and logic functions, comprising the following steps:

[0008] A first graphene layer and a second graphene layer are spaced apart on a SiO2 / Si substrate using a mechanical exfoliation process.

[0009] An α-In2Se3 thin layer is deposited on the first graphene layer using a mechanical exfoliation process, and the α-In2Se3 thin layer does not contact the second graphene layer;

[0010] An h-BN thin layer was deposited on the α-In2Se3 thin layer and the second graphene layer using a mechanical exfoliation process;

[0011] A WSe2 thin layer is formed on the h-BN thin layer using a mechanical peeling process, and the boundary of the WSe2 thin layer does not exceed the boundary range of the h-BN thin layer.

[0012] Source and drain metals are disposed at both ends of the WSe2 thin layer, and gate metal is disposed on the surface of the second graphene layer.

[0013] Annealing in an inert gas.

[0014] Furthermore, on the projection surface of this ferroelectric semi-floating gate transistor, the WSe2 thin layer at least partially overlaps with the α-In2Se3 thin layer and the second graphene layer.

[0015] Furthermore, the h-BN thin layer completely covers the α-In2Se3 thin layer and exposes part of the second graphene layer.

[0016] Furthermore, the Si substrate is a bottom gate.

[0017] Furthermore, the first graphene layer is a charge storage layer, and the second graphene layer is a control gate.

[0018] Furthermore, the thickness of the first graphene layer is 2nm~30nm; the thickness of the second graphene layer is 2nm~30nm.

[0019] Furthermore, the thickness of the α-In2Se3 thin layer is 35 nm to 55 nm;

[0020] The thickness of the h-BN thin layer is 2nm~5nm;

[0021] The thickness of WSe2 thin layers ranges from 20 nm to 35 nm.

[0022] Furthermore, the annealing time is 20-40 minutes, and the annealing temperature is 100-150°C.

[0023] Furthermore, the source and drain electrodes are Au electrodes, and the thickness of the Au electrodes is 45~55nm;

[0024] The gate electrode is an Au electrode with a thickness of 45~55nm.

[0025] Furthermore, by applying different programming voltage pulses to the bottom gate and the gate, a multi-level storage function with at least seven programming states can be achieved;

[0026] Using the bottom gate, gate, and optical signal as three logic input terminals and the channel current as the logic output terminal, this ferroelectric semi-floating gate transistor is an optoelectronic logic gate.

[0027] Compared with the prior art, the present invention has at least the following beneficial effects:

[0028] This invention utilizes WSe2, a layered two-dimensional thin film with advantages such as high mobility, good optical response, and easy peeling, and α-In2Se3, a ferroelectric material exhibiting spontaneous polarization, to construct a ferroelectric semi-floating gate transistor (FMT) of tungsten diselenide / boron nitride / indium triselenide / graphene. This FMT consists of two parts: one part implements non-volatile memory functionality based on a WSe2 / h-BN / α-In2Se3 / Graphene heterostructure, and the other part implements conductivity modulation functionality based on the same heterostructure. With the aid of the ferroelectric polarization field, this device achieves improved non-volatile memory performance, exhibiting a higher program / erase ratio, more significant differences between programming and erasing states, and a longer hold time compared to devices without the α-In2Se3 layer. By simultaneously applying voltage pulses to the bottom silicon and graphene gates, multi-level storage functionality can be achieved, and "AND," "NOR," and "OR" logic gate operations can be performed at a low bias of 10 mV. This ferroelectric semi-floating gate structure makes the transistor an ideal choice for integration into artificial intelligence devices when handling complex logic operations. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the device structure of a ferroelectric semi-floating gate transistor according to an embodiment of the present invention.

[0030] Figure 2 An optical microscope image of a ferroelectric semi-floating gate transistor prepared according to an embodiment of the present invention.

[0031] Figure 3 The figures show data curves of a ferroelectric semi-floating gate transistor prepared according to an embodiment of the present invention, wherein (a) is a storage performance tolerance test of the transistor; (b) is a storage performance durability test of the transistor; and (c) is a demonstration of the multi-level storage performance of the transistor.

[0032] Figure 4 The following is a demonstration of the logic gate functions of a ferroelectric semi-floating gate transistor prepared according to an embodiment of the present invention, wherein (a) is a demonstration of the AND gate function; (b) is a demonstration of the NOR gate function; and (c) is a demonstration of the OR gate function. Detailed Implementation

[0033] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. The described embodiments are merely some, not all, of the embodiments of the present invention. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention. Unless otherwise specified, the experimental methods described in the following embodiments are conventional methods; the reagents and materials, unless otherwise specified, can be obtained from publicly available commercial channels.

[0034] This specification uses spatially relative terms such as “below,” “under,” “down,” “above,” “above,” and “upper” to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device, except for those different from those shown in the figures.

[0035] Furthermore, the use of terms such as "first" and "second" to describe various elements, layers, regions, and sections is not intended to be restrictive. The use of terms such as "having," "containing," "including," and "comprises" are open-ended terms, indicating the presence of the stated elements or features, but not excluding additional elements or features, unless the context explicitly states otherwise.

[0036] like Figure 1 As shown, one embodiment of the present invention provides a ferroelectric semi-floating gate transistor with multi-level storage and logic functions, which includes a SiO2 / Si substrate, a WSe2 thin layer, a thin layer of h-BN, an α-In2Se3 thin layer, a thin layer of graphene, and electrodes.

[0037] The thin-layer graphene comprises a first graphene layer and a second graphene layer of equal or different thicknesses, which are alternately disposed on a SiO2 layer on a Si substrate. The thickness of the first and second graphene layers is 2–30 nm. An α-In2Se3 thin layer is disposed on the first graphene layer, with a thickness of 35–55 nm. An h-BN thin layer is disposed on the α-In2Se3 thin layer and the second graphene layer, completely covering the α-In2Se3 thin layer and exposing part of the second graphene layer. The thickness of the h-BN thin layer is 2–5 nm.

[0038] The WSe2 thin layer is disposed on the h-BN thin layer, and the boundary of the WSe2 thin layer does not exceed the boundary range of the h-BN thin layer. The thickness of the WSe2 thin layer is 20nm~35nm. On the projection surface of the ferroelectric semi-floating gate transistor, the WSe2 thin layer, the α-In2Se3 thin layer, and the second graphene layer at least partially overlap.

[0039] The WSe2 thin layer has a source and a drain at both ends, and the gate is disposed on the surface of the second graphene layer. The source and drain are made of Au layers with a thickness of 45~65nm; the gate is also made of Au layers with a thickness of 45~65nm.

[0040] like Figure 1 The ferroelectric semi-floating gate transistor consists of two parts: one part is based on a WSe2 / h-BN / α-In2Se3 / Graphene heterostructure, stacked from top to bottom, serving as the channel, insulator, semi-floating gate, and charge storage layer, respectively; the other part is based on a WSe2 / h-BN / Graphene heterostructure, serving as the channel, insulator, and control gate, respectively. These two parts respectively implement non-volatile memory and conductivity modulation functions.

[0041] An embodiment of the present invention provides a method for fabricating the transistor, comprising the following steps.

[0042] First, the SiO2 / Si growth substrate was soaked in acetone solution, isopropanol solution, and deionized water respectively, with each soaking time being 5 minutes.

[0043] Next, a mechanical exfoliation process was used to obtain a single-crystal tape by adhering a single crystal with blue adhesive tape, and a graphene / PDMS was obtained by adhering the single-crystal tape with PDMS. A 2-5 nm thin layer of graphene was selected under an optical microscope, and the PDMS containing the graphene side was covered on the surface of the SiO2 / Si substrate, forming the first graphene layer on the surface of the SiO2 / Si substrate. Subsequently, following the same exfoliation method, another graphene thin layer was transferred to the surface of the SiO2 / Si substrate without contacting the previous graphene layer, forming the second graphene layer on the surface of the SiO2 / Si substrate.

[0044] The same mechanical exfoliation process was used to transfer a thin layer of α-In2Se3 onto the first graphene layer without contacting the second graphene layer.

[0045] The next step involves using a single crystal to mechanically exfoliate and obtain thin layers of h-BN and WSe2, which includes using PDMS to adhere single crystal tape to obtain h-BN / PDMS, completely covering the α-In2Se3 surface with PDMS containing the h-BN side to improve device stability and reduce interface defects, and covering a portion of the second graphene layer (i.e., a thin layer of graphene without an α-In2Se3 layer on top), exposing enough space for photolithography electrodes.

[0046] When transferring the thin WSe2 layer onto the thin h-BN layer, the WSe2 layer must overlap with the α-In2Se3 layer and the second graphene portion, but must not exceed the boundary portion of the h-BN layer.

[0047] Next, positive photoresist was selected, and the spin coater was set to 4000 rpm mode for 60 seconds. Then, it was baked at 100°C on a heating stage for 5 to 10 minutes, and the source and drain electrode patterns and gate patterns were lithographically formed using ultraviolet laser.

[0048] Next, an Au layer of 45-65 nm was deposited using electron beam evaporation at a rate of 0.01 nm / s. After deposition, the layer was soaked in acetone for ten minutes to dissolve the photoresist and remove excess Au layer. The source and drain electrodes were then formed at both ends of the WSe2 channel surface, and the gate electrode was formed on the surface of the second graphene layer.

[0049] Finally, the device was placed in a glove box and annealed in argon at 150°C for 30 minutes to increase the contact between different materials and improve the stability of the device, thus obtaining the final WSe2 / h-BN / α-In2Se3 / Graphene ferroelectric semi-floating gate transistor.

[0050] Figure 2 An optical microscope image of a WSe2 / h-BN / α-In2Se3 / Graphene ferroelectric semi-floating gate transistor prepared according to an embodiment of the present invention is shown. The source electrode and drain electrode are respectively disposed at both ends of the thin WSe2 layer, and the gate electrode is disposed on one end of the thin Graphene layer. The bottom gate is a substrate Si. The scale bar is 10 μm.

[0051] Figure 3 In the diagram, (a) shows that the device's endurance was further tested by repeatedly switching between programming and erasing states. After 1000 cycles, the current levels in both states remained very stable, indicating that the memory device has excellent endurance; (b) after 10000 seconds, the device's programming / erasing current ratio still exceeded 10. 4 This demonstrates the device's excellent durability; (c) Figure shows a negative V of -60 V.Si A pulse is used for the erase operation, and the resulting low current level is designated as the "0" state. Positive V pulses of different amplitudes (10, 20, 30, 40, 50, and 60 V) are used. Si The pulses are used for programming operations, generating different current levels that can be specified as "1", "2", "3", "4", "5" and "6" states, demonstrating effective multi-level storage capability.

[0052] Figure 4 As shown, the bottom silicon gate (A), graphene gate (B), and 635 nm optical signal (C) are three logic inputs, and the channel current is considered the logic output (S). In short, by adjusting V in either the HRS (high impedance state) or LRS (low impedance state),... Si and V Gr By applying different gate voltage configurations, AND or NOR logic operations can be implemented; furthermore, the OR logic function is implemented by utilizing optical input and varying V... Gr It is achieved through voltage.

[0053] The WSe2 / h-BN / α-In2Se3 / Graphene ferroelectric semi-floating gate transistor described above can realize multi-level storage and optoelectronic logic gates, exhibiting excellent storage and optoelectronic characteristics. Thanks to the ferroelectric polarization of α-In2Se3, the non-volatile storage capability of this device is improved, possessing 10... 6 High program / erase (P / E) ratio and good durability of over 1000 cycles. 10 4 The device exhibits retention times exceeding one second. Through dual-gate modulation with different programming voltage pulses applied to silicon and graphene, it can achieve multi-level memory functionality with at least seven programming states. By using the dual gates and optical signals as inputs, the device can also function as an optoelectronic logic gate, implementing "AND," "NOR," and "OR" digital logic processing at an extremely low bias of 10 mV, offering advantages in low power consumption and versatility. Compared to traditional floating-gate transistor architectures, the ferroelectric semi-floating gate layer provides a promising solution for integrating high-performance multi-level non-volatile memory and various digital logic operations.

[0054] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A ferroelectric semi-floating gate transistor with multi-level storage and logic functions, characterized in that, The system includes a SiO2 / Si substrate; a first graphene layer and a second graphene layer disposed on the SiO2 layer, with a gap between the first graphene layer and the second graphene layer; an α-In2Se3 thin layer disposed on the first graphene layer without contacting the second graphene layer; an h-BN thin layer disposed on the α-In2Se3 thin layer and the second graphene layer; and a WSe2 thin layer disposed on the h-BN thin layer, with the boundary of the WSe2 thin layer not exceeding the boundary range of the h-BN thin layer. The source and drain are respectively disposed at both ends of the WSe2 thin layer, and the gate is disposed on the surface of the second graphene layer.

2. The ferroelectric semi-floating gate transistor according to claim 1, characterized in that, On the projection surface of this ferroelectric semi-floating gate transistor, the WSe2 thin layer at least partially overlaps with the α-In2Se3 thin layer and the second graphene layer.

3. The ferroelectric semi-floating gate transistor according to claim 2, characterized in that, The h-BN thin layer completely covers the α-In2Se3 thin layer and exposes part of the second graphene layer.

4. The ferroelectric semi-floating gate transistor according to claim 2, characterized in that, The Si substrate is a bottom gate.

5. The ferroelectric semi-floating gate transistor according to claim 4, characterized in that, The first graphene layer is a charge storage layer, and the second graphene layer is a control gate; the thickness of the first graphene layer is 2nm~30nm; the thickness of the second graphene layer is 2nm~30nm.

6. The ferroelectric semi-floating gate transistor according to claim 5, characterized in that, The thickness of the α-In₂Se₃ thin layer is 35 nm to 55 nm; The thickness of the h-BN thin layer is 2nm~5nm; The thickness of WSe2 thin layers ranges from 20 nm to 35 nm.

7. The ferroelectric semi-floating gate transistor according to claim 6, characterized in that, The source and drain electrodes are Au electrodes, and the thickness of the Au electrodes is 45~55nm; The gate electrode is an Au electrode with a thickness of 45~55nm.

8. The ferroelectric semi-floating gate transistor according to claim 5, characterized in that, By applying different programming voltage pulses to the bottom gate and the gate, a multi-level storage function with at least 7 programming states can be achieved; Using the bottom gate, gate, and optical signal as three logic input terminals and the channel current as the logic output terminal, this ferroelectric semi-floating gate transistor is an optoelectronic logic gate.

9. A method for fabricating a ferroelectric semi-floating gate transistor with multi-level storage and logic functions, characterized in that, Includes the following steps: A first graphene layer and a second graphene layer are spaced apart on a SiO2 / Si substrate using a mechanical exfoliation process. An α-In2Se3 thin layer is deposited on the first graphene layer using a mechanical exfoliation process, and the α-In2Se3 thin layer does not contact the second graphene layer; An h-BN thin layer was deposited on the α-In2Se3 thin layer and the second graphene layer using a mechanical exfoliation process; A WSe2 thin layer is formed on the h-BN thin layer using a mechanical peeling process, and the boundary of the WSe2 thin layer does not exceed the boundary range of the h-BN thin layer. Source and drain metals are disposed at both ends of the WSe2 thin layer, and gate metal is disposed on the surface of the second graphene layer. Annealing in an inert gas.

10. The preparation method according to claim 9, characterized in that, On the projection surface of this ferroelectric semi-floating gate transistor, the WSe2 thin layer at least partially overlaps with the α-In2Se3 thin layer and the second graphene layer.

11. The preparation method according to claim 10, characterized in that, The h-BN thin layer completely covers the α-In2Se3 thin layer and exposes part of the second graphene layer.

12. The preparation method according to claim 10, characterized in that, The Si substrate is a bottom gate.

13. The preparation method according to claim 12, characterized in that, The first graphene layer is a charge storage layer, and the second graphene layer is a control gate; the thickness of the first graphene layer is 2nm~30nm; the thickness of the second graphene layer is 2nm~30nm.

14. The preparation method according to claim 13, characterized in that, The thickness of the α-In₂Se₃ thin layer is 35 nm to 55 nm; The thickness of the h-BN thin layer is 2nm~5nm; The thickness of WSe2 thin layers ranges from 20 nm to 35 nm.

15. The preparation method according to claim 9, characterized in that, The annealing time is 20-40 minutes, and the annealing temperature is 100-150°C.

16. The preparation method according to claim 14, characterized in that, The source and drain electrodes are Au electrodes, and the thickness of the Au electrodes is 45~55nm; The gate electrode is an Au electrode with a thickness of 45~55nm.

17. The preparation method according to claim 13, characterized in that, By applying different programming voltage pulses to the bottom gate and the gate, a multi-level storage function with at least 7 programming states can be achieved; Using the bottom gate, gate, and optical signal as three logic input terminals and the channel current as the logic output terminal, this ferroelectric semi-floating gate transistor is an optoelectronic logic gate.

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