Semiconductor device

Abstract

The invention discloses a semiconductor device. The semiconductor device includes a semiconductor substrate, a gate structure, and a first well region. The gate structure is disposed on the semiconductor substrate. A first well region having a first conductivity type is in a semiconductor substrate. The first well region overlaps the gate structure. A first bottom of the first well region has a wavy bottom surface. According to the invention, the first well region and the second well region with different doping concentrations can be formed in the same process step by using the same mask, so that the device performance such as the turn-on resistance, the breakdown voltage, the drain-source capacitance and the drain-substrate capacitance of the transistor can be adjusted according to the needs. According to the invention, the well regions with different doping concentrations do not need to be respectively formed in two processing steps through two masks, so that the manufacturing steps and cost can be saved, and the manufacturing efficiency and the manufacturing precision are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a semiconductor device. Background Art

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasting. This places pressure on semiconductor manufacturers to develop RF (Radio Frequency) chip modules for wireless transmission to perform short-range, medium-range, and long-range transmissions in different frequency bands. The RF power amplifier is an important component of the RF chip module located at the transmitting end. The main function of the RF power amplifier is to amplify the signal, which is then transmitted through the antenna.

[0003] Although existing RF power amplifiers are generally adequate for their intended purposes, they are not satisfactory in all aspects. For example, balancing the trade-off between cost and performance is a challenge. Therefore, a new type of RF power amplifier formed by high-voltage metal-oxide-semiconductor (HVMOS) devices is needed. Summary of the Invention

[0004] To solve the above problems, the present invention provides a semiconductor device to solve the above problems.

[0005] An embodiment of the present invention provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a gate structure, and a first well region. The gate structure is disposed on the semiconductor substrate. The first well region having a first conductivity type is located in the semiconductor substrate and overlaps with the gate structure. The first bottom of the first well region has a wavy bottom surface.

[0006] Further comprising: a second well region having a second conductivity type, located in the semiconductor substrate and adjacent to the first well region, wherein the first bottom of the first well region is connected to the second bottom of the first well region and has different profiles. Thus, the first well region and the second well region can be formed simultaneously in the same process step, thereby saving manufacturing steps. And the doping concentration of the first well region is different from that of the second well region, so as to adjust device performances such as the turn-on resistance, breakdown voltage, drain-source capacitance, and drain-body capacitance of the transistor according to requirements.

[0007] Wherein the second bottom of the second well region has an arc-shaped bottom surface. Thus, the first well region and the second well region can be formed simultaneously in the same process step, and the profiles of the bottoms of the first well region and the second well region are different, thereby saving manufacturing steps.

[0008] The wavy bottom surface of the first well region includes a plurality of wave peaks and a plurality of wave valleys, and the wave peaks are closer to the top surface of the semiconductor substrate. Thus, the first well region and the second well region can be formed simultaneously in the same process step, and the bottom profiles of the first well region and the second well region are different, thereby saving manufacturing steps.

[0009] The first well region has a first sub-region and a second sub-region arranged alternately with the first sub-region. The wave valley is the first bottom surface of the first sub-region, and the wave peak is the second bottom surface of the second sub-region. Thus, the first well region and the second well region can be formed simultaneously in the same process step, and the bottom profiles of the first well region and the second well region are different, thereby saving manufacturing steps.

[0010] The first sub-region has a first depth, and the second sub-region has a second depth different from the first depth. The first depth is measured from the lowest point of the wave valley to the top surface of the first well region, and the second depth is measured from the highest point of the wave peak to the top surface of the first well region. Thus, the first well region has a wavy bottom profile.

[0011] The arc-shaped bottom surface of the second well region includes only one wave valley protruding away from the top surface of the semiconductor substrate. Thus, the first well region has an arc-shaped bottom profile.

[0012] The third depth measured from the lowest point of the wave valley of the second well region to the top surface of the second well region is equal to the first depth. Thus, the first well region and the second well region can be formed simultaneously in the same process step, and the bottom profiles of the first well region and the second well region are different, thereby saving manufacturing steps.

[0013] Further comprising: a first high-concentration doping region having the first conductivity type, located on the first well region, wherein in a first direction, a first side of the gate structure is separated from the first high-concentration doping region; and a second high-concentration doping region having the first conductivity type and located on the second well region, wherein the gate structure has a first side directly located on the first well region and a second side adjacent to the second high-concentration doping region.

[0014] The gate structure, the first high-concentration doping region, and the second high-concentration doping region serve as the gate, drain, and source of the first transistor respectively. Thus, device performances such as the turn-on resistance, breakdown voltage, drain-source capacitance, and drain-body capacitance of the transistor can be adjusted according to requirements.

[0015] The gate structure has a first side directly located on the first well region and a second side located on the first well region and opposite to the first side.

[0016] Further comprising: a second high-concentration doped region, having the first conduction type and located on the first well region, wherein in the first direction, the second side of the gate structure is separated from the second high-concentration doped region.

[0017] Wherein the first high-concentration doped region is connected to the second high-concentration doped region, and the gate structure serves as the first electrode of the capacitor, while the first high-concentration doped region and the second high-concentration doped region jointly serve as the second electrode of the capacitor. Thus, a variable capacitor is formed to meet different requirements, and the capacitance value of the variable capacitor can be flexibly adjusted during manufacturing according to requirements.

[0018] Further comprising: a third well region, having the first conduction type and located in a device region of the semiconductor substrate different from the first well region, wherein: the third bottom of the third well region has an arc-shaped bottom surface, and a fourth depth measured from the lowest point of a single trough of the arc-shaped bottom surface of the third well region to the top surface of the third well region is equal to the first depth, and the first well region and the third well region have different doping concentrations.

[0019] An embodiment of the present invention provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a gate structure, and a first well region. The gate structure is disposed on the semiconductor substrate. The first well region having the first conduction type is located in the semiconductor substrate and overlaps with the gate structure. The first well region has a first number of first arc-shaped bottoms. The first number of first arc-shaped bottoms of the first well region is greater than or equal to 2.

[0020] Further comprising: a second well region, having the second conduction type, located in the semiconductor substrate and adjacent to the first well region, wherein the gate structure overlaps the second well region, and the second number of second arc-shaped bottoms of the second well region is equal to 1. Thus, the first well region and the second well region can be formed simultaneously in the same process step, and the profiles of the bottoms of the first well region and the second well region are different, thereby saving manufacturing steps.

[0021] Wherein the first arc-shaped bottoms are interconnected to form a wavy bottom surface of the first well region. Thus, the first well region and the second well region can be formed simultaneously in the same process step, and the profiles of the bottoms of the first well region and the second well region are different, thereby saving manufacturing steps.

[0022] Wherein a first depth measured from the lowest point of one of the first arc-shaped bottoms of the first well region to the top surface of the first well region is equal to a second depth measured from the lowest point of the second arc-shaped bottom of the second well region to the top surface of the second well region. Thus, the first well region and the second well region can be formed simultaneously in the same process step, and the profiles of the bottoms of the first well region and the second well region are different, thereby saving manufacturing steps.

[0023] Further comprising: a first highly doped region of the first conductivity type, located in the first well region; and a second highly doped region of the first conductivity type, located in the second well region, wherein in a first direction, one side of the gate structure is separated from the first highly doped region, and the other side of the gate structure is adjacent to the second highly doped region.

[0024] Wherein two opposite sides of the gate structure are directly located on the first well region.

[0025] The semiconductor device of the present invention includes a semiconductor substrate, a gate structure, and a first well region. The gate structure is disposed on the semiconductor substrate. The first well region having the first conductivity type is located in the semiconductor substrate and overlaps with the gate structure. The first bottom of the first well region has a wavy bottom surface. The present invention can form the first well region and the second well region with different doping concentrations in the same process step using the same mask, so as to adjust device performances such as the turn-on resistance, breakdown voltage, drain-source capacitance, and drain-body capacitance of the transistor as needed. The present invention does not need to form well regions with different doping concentrations in two process steps using two masks respectively, which can save manufacturing steps and costs, and improve manufacturing efficiency and manufacturing accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0027] Figure 2 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0028] Figure 3 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0029] Figure 4A and 4B 5A, 5B, and 6 are schematic cross-sectional views of intermediate stages of a semiconductor device according to some embodiments of the present invention during the formation of Figure 1 ;

[0030] Figure 7A and 7B 8A, 8B, and 9 are schematic cross-sectional views of intermediate stages of a semiconductor device according to some embodiments of the present invention during the formation of Figure 2 ;

[0031] Figure 10A and 10B and 11 are schematic cross-sectional views of intermediate stages of a semiconductor device according to some embodiments of the present invention during the formation of Figure 3 ; and

[0032] Figure 12A and 12B 12C, 12D, and 12E are Figure 4A and 5A a plan view of a first doped region formed in a first well region of 7A, 8A, and 10A, showing an arrangement of discontinuous portions of the first doped region of a semiconductor device according to some embodiments of the present invention Figures 1-3 of the semiconductor device. DETAILED DESCRIPTION

[0033] In the following detailed description of an embodiment according to the present invention, reference is made to the accompanying drawings, which form a part of the present invention, and in which specific preferred embodiments in which the present invention can be practiced are shown by way of illustration. The embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments can be utilized and mechanical, structural, and procedural changes can be made without departing from the spirit and scope of the present invention. The present invention. Accordingly, the following detailed description should not be construed as limiting, and the scope of an embodiment according to the present invention is defined only by the appended claims. The described drawings are merely illustrative and not restrictive. In the drawings, for the purpose of illustration, the dimensions of some elements may be enlarged rather than drawn to scale. In the practice of the present invention, the dimensions and relative dimensions do not correspond to actual dimensions.

[0034] It will be understood that although the terms "first", "second", "third", "primary", "secondary", etc. may be used herein to describe various components, elements, regions, layers, and / or parts, these components, elements, regions, these layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one component, element, region, layer, or part from another region, layer, or part. Thus, without departing from the teachings of the inventive concept, the first or primary component, element, region, layer, or part discussed below may be referred to as a second or secondary component, element, region, layer, or part.

[0035] In addition, for ease of description, spatial relative terms such as "below", "beneath", "under", "above", "over", etc. may be used herein to facilitate describing the relationship of one component or feature to another as shown in the figures. Another component or feature. In addition to the orientation described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will also be understood that when a "layer" is referred to as being "between" two layers, it may be the only layer between the two layers, or there may also be one or more intermediate layers.

[0036] The terms “about,” “substantially,” and “approximately” generally mean within ±20%, or within ±10%, or within ±5%, or within ±3%, or within ±2%, or within ±1%, or within ±0.5% of a specified value. The specified value of the present invention is an approximate value. When not specifically described, the specified value includes the meanings of “about,” “substantially,” and “approximately.” The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the inventive concept. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0037] It will be understood that when a “component” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another component or layer, it can be directly on the other component or layer, connected to, coupled to, or adjacent to it, or there can be intervening components or layers. In contrast, when a component is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another component or layer, there are no intervening components or layers.

[0038] Note: (i) Like features will be represented by like reference numerals throughout the drawings and need not be described in detail in each drawing in which they appear, and (ii) a series of drawings may show different aspects of a single item, each aspect being associated with various reference labels that may appear throughout the sequence or may appear only in selected drawings of the sequence.

[0039] Figure 1Schematic cross-sectional view of a semiconductor device 500A according to some embodiments of the present invention. The semiconductor device 500A may include transistors in different regions of a semiconductor substrate. For example, the semiconductor device 500A may include a high voltage N-type metal-oxide-semiconductor field effect transistor (HV NMOS FET) in a high voltage region and an input / output (I / O) P-type metal-oxide-semiconductor field effect transistor (PMOS FET) in a conventional voltage region. In some embodiments, the HV NMOSFET includes a lateral diffused NMOS FET (LD NMOS FET).

[0040] In some embodiments, the semiconductor device 500A includes a semiconductor substrate 200, a transistor 310N, and a transistor 320P.

[0041] In some embodiments, the semiconductor substrate 200 has a first device region 500-1 and a second device region 500-2 for configuring elements (e.g., transistors 310N and 320P) operating at different voltages therein. The semiconductor substrate 200 may include silicon. In alternative embodiments, SiGe, bulk semiconductor, strained semiconductor, compound semiconductor, semiconductor-on-insulator (SOI), and other commonly used semiconductor substrates may be used as the semiconductor substrate 200. In some embodiments, the semiconductor substrate 200 may have a P-type or N-type conductivity type depending on requirements. In some embodiments, the semiconductor substrate 200 may be a P-type semiconductor substrate 200.

[0042] One or more isolation features 201, such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features, may be provided in the semiconductor substrate 200. Additionally, the isolation features 201 may surround and define active regions in the first device region 500-1 and the second device region 500-2. In some embodiments, the isolation features 201 are configured to provide physical and electrical isolation between the semiconductor device 500A and other semiconductor devices (not shown) in the semiconductor substrate 200.

[0043] The transistor 310N is disposed in a first device region 500-1 in the semiconductor substrate 200. In some embodiments, the transistor 310N may include a first well region NW1-1, a second well region PW1, and a gate structure 250-1.

[0044] The first well region NW1-1 and the second well region PW1 are located in the first device region 500-1 in the semiconductor substrate 200. The first well region NW1-1 and the second well region PW1 are arranged side by side and adjacent along a direction 100 (which is substantially parallel to the top surface 200T of the semiconductor substrate 200). The first well region NW1-1 and the second well region PW1 may extend from the top surface 200T of the semiconductor substrate 200 to a portion of the isolation feature 201 below the substrate 200. In some embodiments, the first bottom NW1-1B of the first well region NW1-1 is connected to and contacts the second bottom PW1B of the second well region PW1.

[0045] In some embodiments, the first well region NW1-1 has a first conductivity type, while the second well region PW1 has a second conductivity type opposite to the first conductivity type. For example, when the first conductivity type is N-type and the second conductivity type is P-type, the first well region NW1-1 is an N-type well region, and the second well region PW1 is a P-type well region. The first well region NW1-1 and the semiconductor substrate 200 may have the same or opposite conductivity types. In addition, the second well region PW1 and the semiconductor substrate 200 may also have the same or opposite conductivity types.

[0046] In some embodiments, the first bottom NW1-1B of the first well region NW1-1 and the second bottom PW1B of the second well region PW1 have different profiles. For example, the first bottom NW1-1B of the first well region NW1-1 may have a wave surface, so the first bottom NW1-1B may also be referred to as a wavy bottom. The second bottom PW1B of the second well region PW1 may have an arc surface, so the second bottom NW2B may also be referred to as a rounded bottom (or an arc bottom). The first bottom NW1-1B of the first well region NW1-1 may have a wave profile as Figure 1 shown. The second bottom PW1B of the second well region PW1 may have an arc profile as Figure 1The arc profile shown. In some embodiments, the bottom surface of the first bottom NW1-1B of the first well region NW1-1 is also referred to as the wave bottom surface, and the bottom surface of the second bottom PW1B of the second well region PW1 is also referred to as the arc bottom surface. In some embodiments, the first well region NW1-1 has first sub-regions NSR1 and second sub-regions NSR2 arranged alternately with the first sub-regions NSR1. In some embodiments, there are two or more first sub-regions NSR1, and there are two or more first sub-regions NSR1. The first sub-region NSR1 may have a first depth H1. The second sub-region NSR2 may have a second depth H2 different from the first depth H1. For example, the first sub-region NSR1 may have a protruding bottom, and the second sub-region NSR2 may have a concave bottom. The protruding bottom of the first sub-region NSR1 protrudes in a direction away from the top surface 200T of the semiconductor substrate 200 (or the top surface of the first well region NW1-1). The concave bottom of the second sub-region NSR2 is recessed in a direction toward the top surface 200T of the semiconductor substrate 200 (or the top surface of the first well region NW1-1). In addition, the first depth H1 of the first sub-region NSR1 having a protruding bottom may be deeper than the second depth H2 of the second sub-region NSR2 having a concave bottom. In some embodiments, the first depth H1 is measured from the lowest point of the protruding bottom of the first sub-region NSR1 to the top surface of the first well region NW1-1. In some embodiments, the second depth H2 is measured from the highest point of the concave bottom of the second sub-region NSR2 to the top surface of the first well region NW1-1. In some embodiments, as Figure 1As shown, the first bottom NW1-1B of the first well region NW1-1 (or the wavy bottom surface of the first well region NW1-1) includes a plurality of wave crests 210 and a plurality of wave troughs 220, where the wave crests 210 are closer to the wave troughs 220 than the top surface of the first well region NW1-1 (or the top surface 200T of the semiconductor substrate 200). In some embodiments, the wave troughs 220 are the contours of the bottoms of the first sub-regions NSR1, and the wave crests 210 are the contours of the bottoms of the second sub-regions NSR2. In some embodiments, the wave troughs 220 are the bottom surfaces of the first sub-regions NSR1, and the wave crests 210 are the bottom surfaces of the second sub-regions NSR2. The first depth H1 is the distance measured from one of the wave troughs 220 (or one of the lowest points of the wave troughs 220) to the top surface of the first well region NW1-1, and the second depth H2 is the distance measured from one of the wave crests 210 (or one of the highest points of the wave crests 210) to the top surface of the first well region NW1-1. In some embodiments, there are two or more wave crests 210 and two or more wave troughs 220. In some embodiments, the first well region NW1-1 has at least two points (the lowest points of the wave troughs 220), each point having the first depth H1; and the first well region NW1-1 has at least two points (the highest points of the wave crests 210), each point having the second depth H2. In some embodiments, Figure 1 the numbers of the wave crests 210 and the wave troughs 220 are for illustration only and are not limited thereto. In some embodiments, as Figure 1 shown, the second bottom PW1B of the second well region PW1 (or the arcuate bottom surface of the second well region PW1) includes only one wave trough 230, and the wave trough 230 protrudes in a direction away from the top surface 200T of the semiconductor substrate 200 (or the top surface of the second well region PW1). In some embodiments, the second bottom PW1B includes only one lowest point of the wave trough 230, and the third depth H3 measured from the lowest point to the top surface of the second well region PW1 may be equal to the first depth H1. In one embodiment, the top surface of the first well region NW1-1 is substantially flush with the top surface of the second well region PW1.

[0047] In some embodiments, as Figure 1As shown, the first well region NW1-1 and the second well region PW1 may have different numbers of arcuate bottoms. For example, the first well region NW1-1 may have a plurality of arcuate bottoms. The second well region PW1 may have a single arcuate bottom. Thus, the number of arcuate bottoms of the first well region NW1-1 may be greater than the number of arcuate bottoms of the second well region PW1. In some embodiments, the end of one arcuate bottom may be connected to the adjacent end of another arcuate bottom. The arcuate bottom of the first well region NW1-1 adjacent to the arcuate bottom of the second well region PW1 is connected to and in contact with the arcuate bottom of the second well region PW1. In some embodiments, the number of arcuate bottoms of the first well region NW1-1 may be greater than or equal to 2. In some embodiments, the plurality of arcuate bottoms are interconnected to form a wavy bottom surface of the first well region NW1-1 (or a wavy profile of the first bottom NW1-1B of the first well region NW1-1). In some embodiments, a first depth H1 measured from the lowest point of one of the arcuate bottoms of the first well region NW1-1 to the top surface of the first well region NW1-1 is equal to a third depth H3 measured from the lowest point of the single arcuate bottom of the second well region PW1 to the top surface of the second well region PW1. In one embodiment, the top surface of the first well region NW1-1 is substantially flush with the top surface of the second well region PW1.

[0048] The gate structure 250-1 is disposed on the top surface 200T of the semiconductor substrate 200, in the first device region 500-1. The gate structure 250-1 is formed over the first well region NW1-1 and the second well region PW1. In addition, the gate structure 250-1 may overlap with the first well region NW1-1 and the second well region PW1. As Figure 1 shown, the gate structure 250-1 may have opposite side edges S1 and S2, directly located on the first well region NW1-1 and the second well region PW1, respectively. In some embodiments, the interface 202 between the first well region NW1-1 and the second well region PW1 may be located directly below the gate structure 250-1. In some embodiments, the gate structure 250-1 includes a gate dielectric layer, a gate electrode on the gate dielectric layer, and gate spacers on the sidewalls of the gate dielectric layer and the gate electrode.

[0049] As Figure 1 shown, the transistor 310N of the semiconductor device 500A further includes a first high-concentration doping region N1 and a second high-concentration doping region N2, respectively located on the first well region NW1-1 and the second well region PW1. Both the first high-concentration doping region N1 and the second high-concentration doping region N2 have a first conductivity type. For example, when the first conductivity type is N-type, the first high-concentration doping region N1 is an N-type high-concentration doping region N1, and the second high-concentration doping region N2 is an N-type high-concentration doping region N2.

[0050] As shown Figure 1 The first high-concentration doping region N1 and the second high-concentration doping region N2 are located on opposite sides S1 and S2 of the gate structure 250-1 and are adjacent to the corresponding isolation features 201. In this embodiment, the first high-concentration doping region N1 and the second high-concentration doping region N2 are asymmetric with respect to the gate structure 250-1. For example, in the direction 100, there is a distance D1 between the side S1 (or the first side) of the gate structure 250-1 and the first high-concentration doping region N1, such that a portion of the first well region NW1-1 is exposed from the gate structure 250-1 and the first high-concentration doping region N1. In addition, the side S2 (or the second side) of the gate structure 250-1 is adjacent to the second high-concentration doping region N2.

[0051] In this embodiment, the gate structure 250-1, the first high-concentration doping region N1, the second high-concentration doping region N2, and the second well region PW1 of the semiconductor device 500A serve as the gate, drain, source, and bulk of the transistor 310N (e.g., a high-voltage NMOS FET), respectively.

[0052] The transistor 320P is disposed in the second device region 500-2 of the semiconductor substrate 200. In some embodiments, the transistor 320P may include a third well region NW1-2, a gate structure 250-2, a third high-concentration doping region P1, and a fourth high-concentration doping region P2.

[0053] The third well region NW1-2 is located in the semiconductor substrate 200. In some embodiments, both the first well region NW1-1 and the third well region NW1-2 have a first conductivity type. For example, when the first conductivity type is N-type, the first and third well regions NW1-1, NW1-2 are N-type.

[0054] The third bottom NW1-2B of the third well region NW1-2 may have an arcuate surface. The third bottom NW1-2B of the third well region NW1-2 may have an arcuate profile as shown Figure 1 In some embodiments, the bottom surface of the third bottom NW1-2B of the third well region NW1-2 may be referred to as an arcuate bottom surface. In some embodiments, as shown Figure 1As shown, the arc-shaped contour of the third bottom NW1-2B of the third well region NW1-2 (or the arc-shaped bottom surface of the third well region NW1-2) includes only one trough 240, and the trough 240 protrudes in a direction away from the top surface 200T of the semiconductor substrate 200 (or the top surface of the third well region NW1-2). In some embodiments, the third bottom NW1-2B includes only one lowest point of the trough 240, and a fourth depth H4 measured from this lowest point to the top surface of the third well region NW1-2 may be equal to the first depth H1. In one embodiment, the top surface of the first well region NW1 is substantially flush with the top surface of the third well region NW1-2. Since the first well region NW1 in the first device region 500-1 and the third well region NW1-2 in the second device region 500-2 are formed in the same process, the first depth H1 is equal to the fourth depth H4. The method of this embodiment can save manufacturing steps and costs (such as photomask costs) and improve manufacturing efficiency and manufacturing accuracy.

[0055] In some embodiments, the first well region NW1-1 having a wavy bottom (the first bottom NW1-1B) and the third well region NW1-2 having a circular (or arc-shaped) bottom (the third bottom NW1-2B) may have different doping concentrations. For example, the doping concentration of the first well region NW1-1 may be less than the doping concentration of the third well region NW1-2.

[0056] In some embodiments, such as Figure 1As shown, the first well region NW1-1 and the third well region NW1-2 may have different numbers of arcuate bottoms. For example, the first well region NW1-1 may have multiple arcuate bottoms. The third well region NW1-2 may have a single arcuate bottom. Thus, the number of arcuate bottoms of the first well region NW1-1 may be greater than the number of arcuate bottoms of the third well region NW1-2. In one embodiment, the first well region NW1-1 and the third well region NW1-2 are formed in the same process rather than in different processes. Thus, the present invention can save mask costs and reduce process steps. In some embodiments, the end of one arcuate bottom may be connected to the adjacent end of another arcuate bottom. In some embodiments, the number of arcuate bottoms of the first well region NW1-1 may be greater than or equal to 2. In some embodiments, the multiple arcuate bottoms are connected to each other to form a wavy bottom surface of the first well region NW1-1 (or a wavy profile of the first bottom NW1-1B of the first well region NW1-1). In some embodiments, a first depth H1 measured from the lowest point of one arcuate bottom of the first well region NW1-1 to the top surface of the first well region NW1-1 is equal to a fourth depth H4 measured from the lowest point of the single arcuate bottom of the third well region NW1-2 to the top surface of the third well region NW1-2. In one embodiment, the top surface of the first well region NW1-1 is substantially flush with the top surface of the third well region NW1-2. Since the first well region NW1-1 and the third well region NW1-2 are formed in the same process, the first depth H1 is equal to the fourth depth H4. The method of this embodiment can save manufacturing steps and costs (such as mask costs) and improve manufacturing efficiency and manufacturing precision.

[0057] The gate structure 250-2 is disposed on the top surface 200T of the semiconductor substrate 200 in the second device region 500-2. The gate structure 250-2 is formed above the third well region NW1-2. In addition, the gate structure 250-1 may overlap the third well region NW1-2. As Figure 1 shown, both opposite (relative) sides (the first side and the second side, or one side and the other side) of the gate structure 250-2 are directly located on the third well region NW1-2. In some embodiments, the gate structure 250-1 and the gate structure 250-2 include the same or similar structures and are formed in the same process.

[0058] The third high-concentration doping region P1 and the fourth high-concentration doping region P2 are located on the third well region NW1-2. In some embodiments, both the third high-concentration doping region P1 and the fourth high-concentration doping region P2 have a second conductivity type. For example, when the first conductivity type is N-type and the second conductivity type is P-type, the third high-concentration doping region P1 is a P-type high-concentration doping region P1, and the fourth high-concentration doping region P2 is a P-type high-concentration doping region P2.

[0059] In this embodiment, the third highest concentration doped region P1 and the fourth highest concentration doped region P2 are asymmetric with respect to the gate structure 250-2. For example, in the direction 100, the third highest concentration doped region P1 and the fourth highest concentration doped region P2 are adjacent to opposite sides of the gate structure 250-2.

[0060] In this embodiment, the gate structure 250-2, the third highest concentration doped region P1, the fourth highest concentration doped region P2, and the transistor 320P of the semiconductor substrate 200 of the semiconductor device 500A respectively serve as the gate, drain, source, and substrate (e.g., a conventional PMOS FET or a core I / O (input / output) PMOS FET) of the transistor 320P. In some embodiments, the transistor 320P has a conductive type opposite to that of the transistor 310N. The operating voltage (working voltage) of the transistor 320P is lower than the operating voltage (working voltage) of the transistor 310N.

[0061] Figure 2 is a schematic cross-sectional view of a semiconductor device 500B according to some embodiments of the present invention. For the sake of brevity, elements that are the same or similar to those in the previously referenced Figure 1 will not be repeated in the embodiments described hereinafter. As Figures 1 to 2 shown, the differences between the semiconductor device 500A and the semiconductor device 500B at least include that the semiconductor device 500B has a conductive type opposite to that of the semiconductor device 500A. For example, in the semiconductor protection device 500A, the element with the first conductive type is an N-type element, and the element with the second conductive type is a P-type element. In the semiconductor protection device 500B, the element with the first conductive type is a P-type element, and the element with the second conductive type is an N-type element. The semiconductor device 500B may include transistors in different regions of the semiconductor substrate. For example, the semiconductor device 500B may include a high-voltage P-type metal oxide semiconductor field effect transistor (HV PMOS FET, high-voltage MOS FET) in a high-voltage (HV) region and an input / output (I / O) N-type metal oxide semiconductor field effect transistor in a regular voltage (regular NMOS FET, regular NMOS FET) region. In some embodiments, the HV PMOS FET includes a laterally diffused LD PMOS FET (LD PMOSFET). The regular voltage may be lower than the high voltage, and the operating voltage of the regular MOS FET is lower than that of the high-voltage MOS FET.

[0062] As Figure 2 shown, the semiconductor device 500B includes a semiconductor substrate 200, a transistor 310P, and a transistor 320N.

[0063] The transistor 310P is disposed in the first device region 500-1 of the semiconductor substrate 200. In some embodiments, the transistor 310P may include a first well region PW2-1, a second well region NW2, and a gate structure 250-1.

[0064] In some embodiments, the first well region PW2-1 and the second well region NW2 are located in the semiconductor substrate 200. The first well region PW2-1 and the second well region NW2 are arranged side by side and adjacent along the direction 100 (a direction substantially parallel to the top surface 200T of the semiconductor substrate 200). In some embodiments, the first bottom PW2-1B of the first well region PW2-1 is connected to and in contact with the second bottom NW2B of the second well region NW2.

[0065] In some embodiments, the first well region PW2-1 has a first conductivity type, while the second well region NW2 has a second conductivity type opposite to the first conductivity type. For example, when the first conductivity type is P-type and the second conductivity type is N-type, the first well region PW2-1 is a P-type well region and the second well region NW2 is an N-type well region. The first well region PW2-1 and the semiconductor substrate 200 may have the same or opposite conductivity types. In addition, the second well region NW2 and the semiconductor substrate 200 may have the same or opposite conductivity types.

[0066] In some embodiments, the first well region PW2-1 of the semiconductor device 500B and the first well region NW1-1 of the semiconductor device 500A may have the same or similar profiles in a cross-sectional view, as Figure 1 and Figure 2 shown. The second well region NW2 of the semiconductor device 500B and the second well region PW1 of the semiconductor device 500A may have the same or similar profiles in a cross-sectional view, as Figure 1 and Figure 2 shown.

[0067] For example, the first bottom PW2-1B of the first well region PW2-1 may have a wavy surface, so the first bottom PW2-1B may also be referred to as a wavy bottom. The second bottom NW2B of the second well region NW2 may have an arc-shaped surface, so the second bottom NW2B may also be referred to as an arc bottom (or arcuate bottom). The first bottom PW2-1B of the first well region PW2-1 may have a wavy profile as Figure 2 shown. The second bottom NW2B of the second well region NW2 may have an arc-shaped profile as Figure 2The arc-shaped profile shown. In some embodiments, the bottom surface of the first bottom PW2-1B of the first well region PW2-1 is also referred to as a wavy bottom surface, and the bottom surface of the second bottom NW2B of the second well region NW2 is also referred to as an arc-shaped bottom surface. In some embodiments, the first well region PW2-1 has first sub-regions PSR1 and second sub-regions PSR2 arranged alternately with the first sub-regions PSR1. In some embodiments, there are two or more first sub-regions PSR1, and there are two or more first sub-regions PSR1. The first sub-region PSR1 may have a first depth H5. The second sub-region PSR2 may have a second depth H6 different from the first depth H5. For example, the first sub-region PSR1 may have a raised bottom, and the second sub-region PSR2 may have a recessed bottom. The raised bottom of the first sub-region PSR1 protrudes in a direction away from the top surface 200T of the semiconductor substrate 200 (or the top surface of the first well region PW2-1). The recessed bottom of the second sub-region PSR2 is recessed in a direction close to the top surface 200T of the semiconductor substrate 200 (or the top surface of the first well region PW2-1). In addition, the first depth H5 of the first sub-region PSR1 with a raised bottom may be deeper than the second depth H6 of the second sub-region PSR2 with a recessed bottom. In some embodiments, the first depth H5 is measured from the lowest point of the raised bottom of the first sub-region PSR1 to the top surface of the first well region PW2-1. In some embodiments, the second depth H6 is measured from the highest point of the recessed bottom of the second sub-region PSR2 to the top surface of the first well region PW2-1. In some embodiments, as Figure 2As shown, the first bottom PW2-1B of the first well region PW2-1 (or the wavy bottom surface of the first well region PW2-1) includes a plurality of wave peaks 310 and a plurality of wave valleys 320, where the wave peaks 310 are closer to the wave valleys 320 than the top surface of the first well region PW2-1 (or the top surface 200T of the semiconductor substrate 200). In some embodiments, the wave valleys 320 are the contours of the bottom of the first sub-region PSR1, and the wave peaks 310 are the contours of the bottom of the second sub-region PSR2. In some embodiments, the wave valleys 320 are the bottom surfaces of the first sub-region PSR1, and the wave peaks 310 are the bottom surfaces of the second sub-region PSR2. The first depth H5 is the distance measured from one of the wave valleys 320 (or one of the lowest points of the wave valleys 320) to the top surface of the first well region PW2-1, and the second depth H6 is the distance measured from one of the wave peaks 310 (or one of the highest points of the wave peaks 310) to the top surface of the first well region PW2-1. In some embodiments, there are 2 or more wave peaks 310, and there are 2 or more wave valleys 320. In some embodiments, the first well region PW2-1 has at least two points (the lowest points of the wave valleys 320), each point having the first depth H5; the first well region PW2-1 has at least two points (the highest points of the wave peaks 310), each point having the second depth H6. In some embodiments, Figure 2 the numbers of the wave peaks 310 and the wave valleys 320 in are for illustrative purposes only and are not limited thereto. In some embodiments, as Figure 2 shown, the second bottom NW2B of the second well region NW2 (or the arcuate bottom surface of the second well region NW2) includes only one wave valley 330, and the wave valley 330 protrudes in a direction away from the top surface 200T of the semiconductor substrate 200 (or the top surface of the second well region NW2). In some embodiments, the second bottom NW2B includes only one lowest point of the wave valley 330, and the third depth H7 measured from this lowest point to the top surface of the second well region NW2 may be equal to the first depth H5. In one embodiment, the top surface of the first well region PW2-1 is substantially flush with the top surface of the second well region NW2.

[0068] In some embodiments, as Figure 2As shown, the first well region PW2-1 and the second well region NW2 may have different numbers of arcuate bottoms. For example, the first well region PW2-1 may have a plurality of arcuate bottoms. The second well region NW2 may have a single arcuate bottom. Thus, the number of arcuate bottoms of the first well region PW2-1 may be greater than the number of arcuate bottoms of the second well region NW2. In some embodiments, the end of one arcuate bottom may be connected to an adjacent end of another arcuate bottom. The arcuate bottom of the first well region PW2-1 adjacent to the arcuate bottom of the second well region NW2 is connected to and in contact with the arcuate bottom of the second well region NW2. In some embodiments, the number of arcuate bottoms of the first well region PW2-1 may be greater than or equal to 2. In some embodiments, the plurality of arcuate bottoms are interconnected to form a wavy bottom surface of the first well region PW2-1 (or a wavy profile of the first bottom PW2-1B of the first well region PW2-1). In some embodiments, a first depth H5 measured from the lowest point of one arcuate bottom of the first well region PW2-1 to the top surface of the first well region PW2-1 is equal to a third depth H7 measured from the lowest point of the single arcuate bottom of the second well region NW2 to the top surface of the second well region NW2. In one embodiment, the top surface of the first well region PW2-1 is substantially flush with the top surface of the second well region NW2.

[0069] The gate structure 250-1 is disposed on the top surface 200T of the semiconductor substrate 200 in the first device region 500-1. The gate structure 250-1 is formed above the first well region PW2-1 and the second well region NW2. In addition, the gate structure 250-1 may overlap the first well region PW2-1 and the second well region NW2. As Figure 2 shown, the gate structure 250-1 may have opposite side edges S1 and S2 directly over the first well region PW2-1 and the second well region NW2. In some embodiments, the interface 302 between the first well region PW2-1 and the second well region NW2 may be located directly under the gate structure 250-1.

[0070] As Figure 2 shown, the semiconductor device 500B further includes a first high-concentration doped region P3 and a second high-concentration doped region P4 respectively located on the first well region PW2-1 and the second well region NW2. The first high-concentration doped region P3 and the second high-concentration doped region P4 both have a first conductivity type. For example, when the first conductivity type is P-type, the first high-concentration doped region P3 is a P-type high-concentration doped region P3, and the second high-concentration doped region P4 is a P-type high-concentration doped region P4.

[0071] As Figure 2As shown, a first high-concentration doping region P3 and a second high-concentration doping region P4 are located on opposite sides S1 and S2 of the gate structure 250-1 and are adjacent to corresponding isolation features 201. In this embodiment, the first high-concentration doping region P3 and the second high-concentration doping region P4 are asymmetric with respect to the gate structure 250-1. For example, in the direction 100, the side S1 of the gate structure 250-1 is separated from the first high-concentration doping region P3 by a distance D2 such that a portion of the first well region PW2-1 is exposed from the gate structure 250-1 and the first high-concentration doping region P3. In addition, the side S2 of the gate structure 250-1 is adjacent to the second high-concentration doping region P4.

[0072] In this embodiment, the gate structure 250-1, the first high-concentration doping region P3, the second high-concentration doping region P4, and the semiconductor substrate 200 of the semiconductor device 500B serve as the gate, drain, source, and body of a transistor 310P (e.g., a high-voltage PMOS FET), respectively.

[0073] A transistor 320N is disposed in a second device region 500-2 of the semiconductor substrate 200. In some embodiments, the transistor 320N may include a third well region PW2-2, a gate structure 250-2, a third high-concentration doping region N3, and a fourth high-concentration doping region N4.

[0074] The third well region PW2-2 is located in the semiconductor substrate 200. In some embodiments, both the first well region PW2-1 and the third well region PW2-2 have a first conductivity type. For example, when the first conductivity type is P-type, the first and third well regions PW2-1, PW2-2 are P-type.

[0075] The third bottom PW2-2B of the third well region PW2-2 may have an arcuate surface. The third bottom PW2-2B of the third well region PW2-2 may have an arcuate profile as Figure 2 shown. In some embodiments, the bottom surface of the third bottom PW2-2B of the third well region PW2-2 may be referred to as an arcuate bottom surface. In some embodiments, as Figure 2As shown, the arc-shaped contour of the third bottom PW2-2B (or the arc-shaped bottom surface of the third well region PW2-2) includes only one trough 340, and the trough 340 protrudes in a direction away from the top surface 200T of the semiconductor substrate 200 (or the top surface of the third well region PW2-2). In some embodiments, the third bottom PW2-2B includes only the lowest point of the trough 340, and the fourth depth H8 measured from the lowest point to the top surface of the third well region PW2-2 may be equal to the first depth H5. In one embodiment, the top surface of the first well region PW2-1 is substantially flush with the top surface of the third well region PW2-2. Since the first well region PW2-1 in the first device region 500-1 and the third well region PW2-2 in the second device region 500-2 are formed in the same process, the first depth H5 is equal to the fourth depth H8. The method of this embodiment can save manufacturing steps and costs (such as mask costs), and improve manufacturing efficiency and manufacturing precision.

[0076] In some embodiments, the first well region PW2-1 having a wavy bottom (the first bottom PW2-1B) and the third well region PW2-2 having a circular (or arc-shaped) bottom (the third bottom PW2-2B) may have different doping concentrations. For example, the doping concentration of the first well region PW2-1 may be less than the doping concentration of the third well region PW2-2.

[0077] In some embodiments, as Figure 2As shown, the first well region PW2-1 and the third well region PW2-2 may have different numbers of arcuate bottoms. For example, the first well region PW2-1 may have multiple arcuate bottoms. The third well region PW2-2 may have a single arcuate bottom. Thus, the number of arcuate bottoms of the first well region PW2-1 may be greater than the number of arcuate bottoms of the third well region PW2-2. In one embodiment, the first well region PW2-1 and the third well region PW2-2 are formed in the same process rather than in different processes. Thus, the present invention can save mask costs and reduce process steps. In some embodiments, the end of one arcuate bottom may be connected to the adjacent end of another arcuate bottom. In some embodiments, the number of arcuate bottoms of the first well region PW2-1 may be greater than or equal to 2. In some embodiments, the multiple arcuate bottoms are interconnected to form a wavy bottom surface of the first well region PW2-1 (or a wavy profile of the first bottom PW2-1B of the first well region PW2-1). In some embodiments, a first depth H5 measured from the lowest point of one of the arcuate bottoms of the first well region PW2-1 to the top surface of the first well region PW2-1 is equal to a fourth depth H8 measured from the lowest point of the single arcuate bottom of the third well region PW2-2 to the top surface of the third well region PW2-2. In one embodiment, the top surface of the first well region PW2-1 is substantially flush with the top surface of the third well region PW2-2. Since the first well region PW2-1 and the third well region PW2-2 are formed in the same process, the first depth H5 is equal to the fourth depth H8. This implementation can save manufacturing steps and costs (such as mask costs), and improve manufacturing efficiency and manufacturing accuracy.

[0078] The gate structure 250-2 is disposed on the top surface 200T of the semiconductor substrate 200 and is located in the second device region 500-2. The gate structure 250-2 is formed above the third well region PW2-2. In addition, the gate structure 250-1 may overlap the third well region PW2-2. As Figure 2 shown, both opposite sides of the gate structure 250-2 are directly located on the third well region PW2-2. In some embodiments, the gate structure 250-1 and the gate structure 250-2 include the same or similar structures and are formed in the same process.

[0079] The third high-concentration doping region N3 and the fourth high-concentration doping region N4 are located on the third well region PW2-2. In some embodiments, both the third high-concentration doping region N3 and the fourth high-concentration doping region N4 have a second conductivity type. For example, when the first conductivity type is P-type and the second conductivity type is N-type, the third high-concentration doping region N3 is a P-type high-concentration doping region P3, and the fourth high-concentration doping region N4 is a P-type high-concentration doping region P4.

[0080] In this embodiment, the third highest concentration doped region N3 and the fourth highest concentration doped region N4 are asymmetric with respect to the gate structure 250-2. For example, in the 100 direction, the third highest concentration doped region N3 and the fourth highest concentration doped region N4 are adjacent to opposite sides of the gate structure 250-2.

[0081] In this embodiment, the gate structure 250-2, the third highest concentration doped region N3, the fourth highest concentration doped region N4, and the transistor 320N of the semiconductor substrate 200 of the semiconductor device 500B serve as the gate, drain, source, and substrate, respectively. In some embodiments, the transistor 320N has a conductive type opposite to that of the transistor 310P. The operating voltage of the transistor 320N is lower than the operating (working) voltage of the transistor 310P.

[0082] The semiconductor devices 500A and 500B include transistors configured in different regions having different operating voltages. For example, the first well regions (e.g., the first well regions NW1-1, PW2-1) on the drain side of the high-voltage transistors (e.g., the transistors 310N, 310P) in the high-voltage region (e.g., the first device region 500-1) and the third well regions (e.g., the third well regions NW1-2, PW2-2) of the input / output transistors (e.g., the transistors 320N, 320P) in the conventional voltage region (e.g., the second device region 500-2) are formed simultaneously, but have different doping concentrations and different profiles. The performance of the high-voltage transistors can be improved while maintaining the performance of the input / output devices, without additional masks and process steps.

[0083] Figure 3 is a schematic cross-sectional view of a semiconductor device 500C according to some embodiments of the present invention. For the sake of brevity, elements that are the same or similar to those described previously with reference to Figure 1 and Figure 2 are not described again. The semiconductor device 500C may include at least one capacitor and at least one transistor, which are disposed in different regions of the semiconductor substrate. For example, the semiconductor device 500C may include a capacitor in the first device region and an input / output N-type metal-oxide-semiconductor field-effect transistor in the second device region.

[0084] As Figure 3 shown, the semiconductor device 500C may include a semiconductor substrate 200, a capacitor 330CP, and a transistor 320N.

[0085] The capacitor 330CP is disposed in the first device region 500-1 of the semiconductor substrate 200. In some embodiments, the capacitor 330CP may include a first well region PW3-1 and a gate structure 250-1.

[0086] As shown Figure 3 in FIG. 1, a first well region PW3-1 is located in a semiconductor substrate 200. The first well region PW3-1 may extend from a top surface 200T of the semiconductor substrate 200 to a part of an isolation feature 201 below the substrate 200.

[0087] In some embodiments, the first well region PW3-1 has a first conductivity type. For example, when the first conductivity type is P-type, the first well region PW3-1 is a P-type well region. In addition, the first well region PW3-1 and the semiconductor substrate 200 may have the same or opposite conductivity types.

[0088] In some embodiments, a first bottom PW3-1B of the first well region PW3-1 may have a wavy surface, so the first bottom PW3-1B may also be referred to as a wavy bottom. The first bottom PW3-1B of the first well region PW3-1 may have a wavy profile as shown in FIG. 2. In some embodiments, a bottom surface of the first bottom PW3-1B of the first well region PW3-1 is also referred to as a wavy bottom surface. In some embodiments, the first well region PW3-1 has first sub-regions PSR3 and second sub-regions PSR4 that are alternately arranged. In some embodiments, there are two or more first sub-regions PSR3, and there are two or more second sub-regions PSR4. The first sub-region PSR3 may have a first depth H9. The second sub-region PSR4 may have a second depth H10 that is different from the first depth H9. For example, the first sub-region PSR3 may have a protruding bottom, while the second sub-region PSR4 may have a recessed bottom. The protruding bottom of the first sub-region PSR3 protrudes in a direction away from the top surface 200T of the semiconductor substrate 200 (or the top surface of the first well region PW3-1). The recessed bottom of the second sub-region PSR4 is recessed in a direction close to the top surface 200T of the semiconductor substrate 200 (or the top surface of the first well region PW3-1). In addition, the first depth H9 of the first sub-region PSR3 having a protruding bottom may be deeper than the second depth H10 of the second sub-region PSR4 having a recessed bottom. In some embodiments, the first depth H9 is measured from the bottommost part of the protruding bottom of the first sub-region PSR3 to the top surface of the first well region PW3-1. In some embodiments, the second depth H10 is measured from the topmost part of the recessed bottom of the second sub-region PSR4 to the top surface of the first well region PW3-1. In some embodiments, as shown in FIG. 3 Figure 3 in FIG. 3 Figure 3As shown, the wavy profile of the first bottom PW3-1B (or the wavy bottom surface of the first well region PW3-1) includes a plurality of wave peaks 410 and a plurality of wave valleys 420, where the wave peaks 410 are closer to the wave valleys 420 than the top surface of the first well region PW3-1 (or the top surface 200T of the semiconductor substrate 200). In some embodiments, the wave valleys 420 are the profiles of the bottoms of the first sub-region PSR3, and the wave peaks 410 are the profiles of the bottoms of the second sub-region PSR4. In some embodiments, the wave valleys 420 are the bottom surfaces of the first sub-region PSR3, and the wave peaks 410 are the bottom surfaces of the second sub-region PSR4. The first depth H9 is the distance measured from one of the wave valleys 420 (or the bottommost point of the wave valleys 420) to the top surface of the first well region PW3-1, and the second depth H10 is the distance measured from one of the wave peaks 410 (or the topmost point of the wave peaks 410) to the top surface of the first well region PW3-1. In some embodiments, there are two or more wave peaks 410, and there are two or more wave valleys 420. In some embodiments, the first well region PW3-1 has at least two points (the bottommost points of the wave valleys 420), each point having the first depth H9; and the first well region PW3-1 has at least two points (the topmost points of the wave peaks 410), each point having the second depth H10. In some embodiments, Figure 3 The numbers of the wave peaks 410 and wave valleys 420 in

[0089] are for illustrative purposes only and are not limited thereto. Figure 3 As shown, the first well region PW3-1 may have a plurality of arcuate bottoms. In some embodiments, the first well region PW3-1 may have two or more arcuate bottoms. In some embodiments, the arcuate bottoms are connected to each other to form the wavy bottom surface of the first well region PW3-1 (or the wavy profile of the first bottom PW3-1B of the first well region PW3-1).

[0090] The gate structure 250-1 is disposed on the top surface 200T of the first device region 500-1 of the semiconductor substrate 200. The gate structure 250-1 is formed above the first well region PW3-1. In addition, the gate structure 250-1 may overlap with the first well region PW3-1. As Figure 3 shown, the gate structure 250-1 may have opposite sides S1 and S2 directly above the first well region PW3-1.

[0091] As Figure 3As shown, the semiconductor device 500C further includes a first high-concentration doped region P5 and a second high-concentration doped region P6 located on the first well region PW3-1. Both the first high-concentration doped region P5 and the second high-concentration doped region P6 have a first conductivity type. For example, when the first conductivity type is P-type, the first high-concentration doped region P5 is a P-type high-concentration doped region P5, and the second high-concentration doped region P6 is a P-type high-concentration doped region P6.

[0092] As Figure 3 shown, the first high-concentration doped region P5 and the second high-concentration doped region P6 are located on opposite sides S1 and S2 of the gate structure 250-1 and are adjacent to the corresponding isolation features 201. In this embodiment, the first high-concentration doped region P5 and the second high-concentration doped region P6 are symmetric with respect to the gate structure 250-1. For example, in the direction 100, the distance D3 between the side S1 of the gate structure 250-1 and the first high-concentration doped region P5 is such that a portion of the first well region PW3-1 is exposed from the gate structure 250-1 and the first high-concentration doped region P5. In addition, in the direction 100, the distance D4 between the side S2 of the gate structure 250-1 and the second high-concentration doped region P6 is such that another portion of the first well region PW3-1 is exposed from the gate structure 250-1 and the second high-concentration doped region P6. In some embodiments, the distance D3 is equal to the distance D4.

[0093] In this embodiment, the first high-concentration doped region P5 is electrically connected (or coupled) to the second high-concentration doped region P6. The gate structure 250-1 can serve as the first electrode of the capacitor 330CP. In addition, the first high-concentration doped region P5 and the second high-concentration doped region P6 can jointly serve as the second electrode of the capacitor 330CP.

[0094] The transistor 320N in the semiconductor device 500A is disposed in the second device region 500-2 of the semiconductor substrate 200. In some embodiments, the transistors 320N of the semiconductor devices 500A and 500C may have the same or similar structures. In some embodiments, the first well region PW3-1 in the first device region 500-1 and the third well region PW2-2 in the second device region 500-2 are formed in the same process, and the first depth H9 is equal to the fourth depth H8. The method of this embodiment can save manufacturing steps and costs (such as mask costs) and improve manufacturing efficiency and manufacturing accuracy.

[0095] The methods of forming the semiconductor devices 500A, 500B, and 500C are described below.

[0096] Figure 4A , 4B , 5A, 5B, and 6 are in accordance with some embodiments in formingFigure 1 Schematic cross-sectional view of an intermediate stage of the semiconductor device 500A in

[0097] Reference Figure 4A 、 4B 、5A and 5B, a semiconductor substrate 200 is provided. The semiconductor substrate 200 has a first device region 500-1 and a second device region 500-2 of the first device region 500-1 separated by an isolation feature 201. The first device region 500-1 may provide a transistor 310N formed therein, and the second device region 500-2 may provide a transistor 320P formed therein.

[0098] Next, a plurality of (ion) implantation processes are performed to form a first doped region ND1-1, a second doped region PD1, and a third doped region ND1-2 in the semiconductor substrate 200. The first doped region ND1-1 and the second doped region PD1 are respectively formed in the same first device region 500-1 of the semiconductor substrate 200. In addition, the first doped region ND1-1 and the third doped region ND1-2 are formed simultaneously in the first device region 500-1 and the entire second device region 500-2. The first doped region ND1-1 and the second doped region PD1 are close to each other. In some embodiments, the first doped region ND1-1 may be separated from the second doped region PD1, as Figure 4A and 4B shown. Alternatively, the first doped region ND1-1 may be connected to (or in contact with) the second doped region PD1, as Figure 5A and 5B shown.

[0099] In some embodiments, there is at least one discontinuous portion DS1 inside the first doped region ND1-1. The conductive type, composition, or doping concentration of the discontinuous portion DS1 may be different from that of the first doped region ND1-1, but the same as that of the semiconductor substrate 200. The second doped region PD1 and the third doped region ND1-2 may be formed without discontinuous portions inside. In some embodiments, the second doped region PD1 and the third doped region ND1-2 are continuous doped regions. There is no other portion inside the second doped region PD1 having a conductive type, composition, or doping concentration different from that of the second doped region PD1. Similarly, there is no other portion inside the third doped region ND1-2 having a conductive type, composition, or doping concentration different from that of the third doped region ND1-2. In some embodiments, the implantation processes are different ion implantation processes and dopants of different conductive types are implanted. For example, the first doped region ND1-1 and the third doped region ND1-2 may have a first conductive type by implanting an N-type dopant, and the N-type dopant may include phosphorus, arsenic, nitrogen, antimony, or a combination thereof. For example, the second doped region PD1 may have a second conductive type (i.e., P-type) by implanting a P-type dopant, and the P-type dopant may include boron, gallium, aluminum, indium, boron trifluoride ions (BF 3 + ), or a combination thereof.

[0100] Next, still referring to Figure 4A 、 4B 、5A and 5B, a deposition process, a patterning process, and an etch-back process are performed to simultaneously form gate structures 250-1 and 250-2 on the semiconductor substrate 200 of the first device region 500-1 and the second device region 500-2. The gate structure 250-1 may overlap the first doped region ND1-1 and the second doped region PD1. The gate structure 250-2 may overlap the third doped region ND1-2.

[0101] Next, referring to Figure 6 ,an annealing process 1020 is performed to form a first well region NW1-1 from the first doped region ND1-1 ( Figure 4A 、 4B 、5A and 5B), a second well region PW1 from the second doped region PD1 ( Figure 4A 、 4B 、5A and 5B), and a third well region NW1-2 from the third doped region ND1-2 ( Figure 4A 、 4B 、5A and 5B). In some embodiments, the first well region NW1-1 is formed by diffusing a part of the dopants (such as N-type dopants) in the first doped region ND1-1 into the discontinuous portion DS1 ( Figure 4A 、 4B、5A, and 5B). Accordingly, the first well region NW1-1 and the adjacent second well region PW1 (or the third well region NW1-2) may have different bottom profiles and doping concentrations. For example, the first well region NW1-1 may have a wavy bottom (the first bottom NW1-1B), while the second well region PW1 (or the third well region NW1-2) may have an arcuate (or circular) bottom (e.g., the second bottom PW1B or the third bottom NW1-2B).

[0102] In some embodiments, the doping concentration of the first well region NW1-1 may be less than the doping concentration of the third well region NW1-2. In some embodiments, since the first well region NW1-1 in the first device region 500-1 and the third well region NW1-2 in the second device region 500-2 have different doping concentrations and are formed simultaneously without additional masks and process steps.

[0103] Compared with the conventional well region formed from a continuous doping region, the first well region NW1-1 formed from the discontinuous doping region ND1-1 may have a lower doping concentration. In addition, the doping concentration of the first well region NW1-1 can be adjusted by the number and size of the discontinuous portion DS1. In some embodiments, since the first well region NW1-1 with an adjustable doping concentration is formed without additional masks and process steps. The method of this embodiment can save manufacturing steps and costs (e.g., mask costs) and improve manufacturing efficiency and manufacturing precision.

[0104] Next, referring to Figure 1 , a lithography process and a subsequent implantation process are performed to form a first high-concentration doping region N1 and a second high-concentration doping region N2. The first high-concentration doping region N1 having a first conductivity type (e.g., N-type) is located on the first well region NW1-1. The second high-concentration doping region N2 having a first conductivity type (e.g., N-type) is located on the second well region NW2. In some embodiments, the first high-concentration doping region N1 and the second high-concentration doping region N2 are adjacent to the corresponding isolation feature 201.

[0105] Next, referring to Figure 1 , another lithography process and a subsequent implantation process may be performed to form a third high-concentration doping region P1 and a fourth high-concentration doping region P2. The third high-concentration doping region P1 and the fourth high-concentration doping region P2 both having a second conductivity type (e.g., P-type) are located on the third well region NW1-2. In some embodiments, the process sequence of forming the first and second high-concentration doping regions N1, N2 and the third and fourth high-concentration doping regions P1, P2 may be exchanged. After the above processes, the semiconductor device 500A is formed.

[0106] Figure 7A, 7B , 8A, 8B, and 9 are schematic cross-sectional views of semiconductor device 500B in an intermediate stage of formation according to some embodiments of the present invention. For the sake of brevity, elements that are the same or similar to those described in the previous references Figure 2 , Figure 4A , 4B , 5A, 5B, and 6 will not be repeated in the following embodiments.

[0107] Referring to Figure 7A , 7B , 8A, and 8B, several implantation processes were performed to form a first doped region PD2-1, a second doped region ND2, and a third doped region PD2-2 in semiconductor substrate 200, respectively. The first doped region PD2-1 and the second doped region ND2 are formed in the same first device region 500-1 of semiconductor substrate 200, respectively. In addition, the first doped region PD2-1 and the third doped region PD2-2 are formed simultaneously in the first device region 500-1 and the entire second device region 500-2. The first doped region PD2-1 and ND1-1 ( Figure 4A , 4B , 5A, and 5B) may have a similar arrangement but have opposite conduction types. The second doped region ND2 and PD1 ( Figure 4A , 4B , 5A, and 5B) may have a similar arrangement but have opposite conduction types. The third doped region PD2-2 and ND1-2 ( Figure 4A , 4B , 5A, and 5B) may have a similar arrangement but have opposite conduction types.

[0108] In some embodiments, there is at least one discontinuous portion DS2 inside the first doped region PD2-1. The second doped region ND2 and the third doped region PD2-2 may be formed without discontinuous portions inside. In some embodiments, the implantation processes are different ion implantation processes and dopants with different conduction types are implanted. For example, the first doped region PD2-1 may have a first conduction type (i.e., P-type) by implanting a P-type dopant, which may include boron, gallium, aluminum, indium, boron trifluoride ions (BF 3 + ), or a combination thereof. For example, the second doped region ND2 may have a second conduction type (i.e., N-type) by implanting an N-type dopant, which may include phosphorus, arsenic, nitrogen, antimony, or a combination thereof.

[0109] Next, still referring to Figure 7A , 7B, 8A, and 8B, perform a similar process as shown in FIGS. 4A, 4B, 5A, and 5B to simultaneously form gate structures 250-1 and 250-2 on the semiconductor substrate 200 in the first device region 500-1 and the second device region 500-2. The gate structure 250-1 may overlap the first doped region PD2-1 and the second doped region ND2. The gate structure 250-2 may overlap the third doped region PD2-2.

[0110] Next, refer to Figure 9 , and perform an annealing process 2020 similar to the annealing process 1020 ( Figure 6 ) to form a first well region PW2-1, a second well region NW2, and a third well region PW2-2 from the first doped region PD2-1 ( Figure 7A , 7B , 8A, and 8B), the second doped region ND2 ( Figure 7A , 7B , 8A, and 8B), and the third doped region PD2-2 ( Figure 7A , 7B , 8A, and 8B). In some embodiments, the first well region PW2-1 is formed by diffusing a portion of the dopants (e.g., P-type dopants) in the first doped region PD2-1 into the discontinuous portion DS2 ( Figure 7A , 7B , 8A, and 8B). Thus, the first well region PW2-1 and the adjacent second well region NW2 (or the third well region PW2-2) may have different bottom profiles and doping concentrations. For example, the first well region PW2-1 may have a wavy bottom (the first bottom PW2-1B), while the second well region NW2 (or the third well region PW2-2) may have an arc-shaped (or circular) bottom (e.g., the second bottom NW2B or the third bottom PW2-2B).

[0111] In some embodiments, the doping concentration of the first well region PW2-1 may be less than the doping concentration of the third well region PW2-2. In some embodiments, since the first well region PW2-1 in the first device region 500-1 and the third well region PW2-2 in the second device region 500-2 have different doping concentrations and are formed simultaneously without additional masks and process steps.

[0112] Compared with the conventional well regions formed from continuous doping regions, the first well region PW2-1 formed from the discontinuous doping region PD2-1 can have a lower doping concentration. In addition, the doping concentration of the first well region PW2-1 can be adjusted by the number and size of the first doping region PD2-1. In some embodiments, the first well region PW2-1 with an adjustable doping concentration is formed without additional masks and process steps. The method of this embodiment can save manufacturing steps and costs (such as mask costs), and improve manufacturing efficiency and manufacturing accuracy.

[0113] Next, referring to Figure 2 , multiple photolithography processes and subsequent implantation processes can be performed to form a first high-concentration doping region P3, a second high-concentration doping region P4, a third high-concentration doping region N3, and a fourth high-concentration doping region N4. The first and second high-concentration doping regions P3, P4 and the first and second high-concentration doping regions N1, N2 ( Figure 1 ) can have a similar arrangement but with opposite conductivity types. The third and fourth high-concentration doping regions N3, N4 and the fourth high-concentration doping regions P1, P2 ( Figure 1 ) can have a similar arrangement but with opposite conductivity types. After the foregoing process, the semiconductor device 500B is formed.

[0114] Figure 10A , 10B and 11 are schematic cross-sectional views of an intermediate stage of the semiconductor device 500C in accordance with some embodiments during the formation of Figure 3 . For the sake of brevity, the same or similar elements described in the previous references Figure 4A , 4B , 5A, 5B, 6, 7A, 7B, 8A, 8B, and 9 will not be repeated hereinafter in the embodiments.

[0115] Referring to Figure 10A and 10B , an implantation process is performed to simultaneously form a first doping region PD3-1 and a third doping region PD2-2 in the entire first device region 500-1 and the entire second device region 500-2 of the semiconductor substrate 200.

[0116] In some embodiments, there is at least one discontinuous portion DS3 inside the first doping region PD3-1. The discontinuous portion DS3 and the discontinuous portion DS2 ( Figure 7A , 7B , 5A, and 5B) can have a similar arrangement and the same conductivity type (i.e., P-type). The third doping region PD2-2 can be formed without a discontinuous portion inside.

[0117] Next, still referring to Figure 10A and10B , perform a process similar to Figure 7A , 7B , 8A and 8B, to form gate structures 250-1 and 250-2 on the semiconductor substrate 200 of the first device region 500-1 and the second device region 500-2. The gate structure 250-1 may overlap the first doped region PD3-1. The gate structure 250-2 may overlap the third doped region PD2-2.

[0118] Next, referring to Figure 11 , perform an annealing process 3020 similar to the annealing process 2020 in Figure 9 to form a first well region PW3-1 from the first doped region PD3-1 ( Figure 10A and 10B ), and form a third well region PW2-2 from the third doped region PD2-2 ( Figure 10A and 10B ). In some embodiments, by diffusing a portion of the dopants (e.g., P-type dopants) in the first doped region PD3-1 into the discontinuous portion DS3 ( Figure 10A and 10B ), the first well region PW3-1 is formed. Thus, the first well region PW3-1 and the third well region PW2-2 may have different bottom profiles and doping concentrations. For example, the first well region PW3-1 may have a wavy bottom (the first bottom PW3-1B), while the third well region PW2-2 may have an arc (or circular) bottom (e.g., the third bottom PW2-2B).

[0119] In some embodiments, the doping concentration of the first well region PW3-1 may be less than the doping concentration of the third well region PW2-2. In some embodiments, since the first well region PW3-1 in the first device region 500-1 and the third well region PW2-2 in the second device region 500-2 are formed simultaneously with different doping concentrations, without additional masks and process steps.

[0120] Compared with the conventional well regions formed from continuous doped regions, the doping concentration of the first well region PW3-1 formed from the discontinuous doped region PD3-1 may be lower. In addition, the doping concentration of the first well region PW3-1 can be adjusted by the number and size of the discontinuous portion DS3. In some embodiments, since the first well region PW3-1 with an adjustable doping concentration is formed, without additional masks and process steps. The method of this embodiment can save manufacturing steps and costs (e.g., mask costs), and improve manufacturing efficiency and manufacturing precision.

[0121] Next, referring to Figure 3 , perform a process similar to Figure 2The processes shown are used to form a first high-concentration doped region P5, a second high-concentration doped region P6, a third high-concentration doped region N3, and a fourth high-concentration doped region N4. The first high-concentration doped region P5 and the second high-concentration doped region P6 both have a first conduction type (e.g., P-type) and are located on the first well region PW3-1. The third high-concentration doped region N3 and the fourth high-concentration doped region N4 both have a second conduction type (e.g., N-type) and are located on the third well region PW2-2.

[0122] In some embodiments, the first high-concentration doped region P5 and the second high-concentration doped region P6 are arranged near corresponding isolation features 201 in the first device region 500-1. The third high-concentration doped region N3 and the fourth high-concentration doped region N4 are arranged near corresponding isolation features 201 in the second device region 500-2. After the foregoing processes, a semiconductor device 500C is formed.

[0123] Figure 12A 、 12B 、12C, 12D, and 12E are Figure 4A 、 5A 、7A, 8A, and 10A are plan views (layouts) of the first doped regions ND1-1, PD2-1, and PD3-1 used to form the first well regions NW1-1, PW2-1, and PW3-1, showing the discontinuous portions DS1, DS2, and DS3 of the first well regions NW1-1, PW2-1, and PW3-1 with a lighter doping concentration in semiconductor devices 500A, 500B, and 500C ( Figures 1-3 ), according to the disclosure of some embodiments. The directions of the first well regions NW1-1, PW2-1, and PW3-1 are only an example and are not limited to the disclosed embodiments.

[0124] In some embodiments, the first doped regions ND1-1, PD2-1, and PD3-1 may surround or be arranged alternately with the discontinuous portions DS1, DS2, and DS3. In some embodiments, the discontinuous portions DS1, DS2, and DS3 may be separated from each other and have various shapes in a top view.

[0125] As Figures 12A to 12C shown, the first doped regions ND1-1, PD2-1, and PD3-1 may have discontinuous portions DS1, DS2, and DS3 arranged periodically along a direction 110 different from the direction 100. In addition, the discontinuous portions DS1, DS2, and DS3 are in a strip shape extending along the direction 100. As Figure 12AAs shown, the first doping regions ND1-1, PD2-1, and PD3-1, as well as the discontinuous portions DS1, DS2, and DS3, may have the same length in the direction 100. Therefore, the first doping regions ND1-1, PD2-1, and PD3-1 can be divided into strip-shaped sub-portions extending along the direction 100. In addition, the widths of the discontinuous portions DS1, DS2, and DS3 in the direction 110 can be smaller than the widths of the sub-portions of the first doping regions ND1-1, PD2-1, and PD3-1. In other words, the sub-portions of the first doping regions ND1-1, PD2-1, and PD3-1 and the discontinuous portions DS1, DS2, and DS3 can be alternately arranged in the direction 110. As Figure 12B shown, in the direction 100, the lengths of the discontinuous portions DS1, DS2, and DS3 can be smaller than the lengths of the first doping regions ND1-1, PD2-1, and PD3-1. The discontinuous portions DS1, DS2, and DS3 can be arranged in the middle portions of the first doping regions ND1-1, PD2-1, and PD3-1. In addition, the discontinuous portions DS1, DS2, and DS3 can be surrounded by the first doping regions ND1-1, PD2-1, and PD3-1. As Figure 12C shown, at least two of the discontinuous portions DS1, DS2, and DS3 are aligned with each other in the direction 100 and are disposed on the opposite sides of the first doping regions ND1-1, PD2-1, and PD3-1. In the direction 100, the lengths of the discontinuous portions DS1, DS2, and DS3 can be smaller than the lengths of the first doping regions ND1-1, PD2-1, and PD3-1. As Figure 12D and 12E shown, the first doping regions ND1-1, PD2-1, and PD3-1 can have at least one of the discontinuous portions DS1, DS2, and DS3. In addition, the discontinuous portions DS1, DS2, and DS3 are in a strip shape extending along the direction 110. As Figure 12D shown, the first doping region ND1-1 / PD2-1 / PD3-1 can have a single discontinuous portion DS1 / DS2 / DS3. The first doping regions ND1-1, PD2-1, and PD3-1 and the discontinuous portions DS1, DS2, and DS3 can have the same width in the direction 110. Therefore, the first doping regions ND1-1, PD2-1, and PD3-1 can be divided into strip-shaped sub-portions extending along the direction 110. In addition, the lengths of the discontinuous portions DS1, DS2, and DS3 in the direction 100 can be smaller than the lengths of the first doping regions ND1-1, PD2-1, and PD3-1. In other words, the sub-portions of the first doping regions ND1-1, PD2-1, and PD3-1 and the discontinuous portions DS1, DS2, and DS3 are alternately arranged in the direction 100. As Figure 12EAs shown, in direction 110, the widths of the discontinuous portions DS1, DS2, and DS3 can be less than the widths of the first doping regions ND1-1, PD2-1, and PD3-1. In addition, the discontinuous portions DS1, DS2, and DS3 can be surrounded by the discontinuous portions DS1, DS2, and DS3.

[0126] Embodiments of the present invention provide a semiconductor device and a method of forming the same. The semiconductor device includes a semiconductor substrate, a first gate structure, and a first well region. The first gate structure is disposed on the substrate. The first well region having a first conductivity type is located in the semiconductor substrate and overlaps with the gate structure. In some embodiments, the first bottom of the first well region has a wavy bottom surface that can be formed without additional masks and process steps. The first well region can be formed by annealing a first doped region within at least one first discontinuous portion. A portion of the first dopant in the first doped region can diffuse into the first discontinuous portion, thereby forming the first well region. In some embodiments, the first gate structure has a first side directly on the first well region. In some embodiments, the semiconductor device further includes a first high-concentration doped region having a first conductivity type and located on the first well region. In a first direction, the first side of the gate structure is spaced apart from the first high-concentration doped region by a certain distance such that a portion of the first well is exposed from the gate structure and the first high-concentration doped region. In some embodiments, the semiconductor device includes a first transistor disposed in a first device region. The first transistor includes the first gate structure and the first well region. The first transistor further includes a second well region having a second conductivity type and located in the semiconductor substrate and adjacent to the first well region. The second well region can be formed by annealing a second doped region within no discontinuous portion. Thus, the first bottom of the first well region and the second bottom of the second well region are connected and have different profiles. For example, in a cross-sectional view, the first bottom of the first well region can have a wavy profile, while the second bottom of the second well region can have an arc profile. In some embodiments, the first transistor of the semiconductor device further includes a second high-concentration doped region having a first conductivity type and located on the second well region. The second side of the gate structure is adjacent to the second high-concentration doped region. In some embodiments, the first gate structure, the first high-concentration doped region, and the second high-concentration doped region serve as the gate, drain, and source of the first transistor, respectively. In some embodiments, the semiconductor device further includes a second transistor disposed in a second device region. The second transistor includes a second gate structure, a second gate structure, a third high-concentration doped region, and a fourth high-concentration doped region. The second gate structure is disposed on the semiconductor substrate. The third well region having a first conductivity type is located in the semiconductor substrate and overlaps with the second gate structure. The third bottom of the third well region has an arc bottom surface. The third high-concentration doped region and the fourth high-concentration doped region have a second conductivity type and are located on the third well region. In a first direction, the third high-concentration doped region and the fourth high-concentration doped region are adjacent to opposite sides of the second gate structure. In some embodiments, the second gate structure, the third high-concentration doped region, and the fourth high-concentration doped region serve as the gate, drain, and source of the second transistor, respectively.

[0127] When the first transistor of a semiconductor device is applied to a high-voltage transistor (e.g., a high-voltage NMOS FET or a high-voltage PMOS FET), the performance of the on-resistance, breakdown voltage, drain-source capacitance, and drain-body capacitance is mainly dominated by the first well region provided on the drain side of the first transistor. In addition, the first well region in the first device region (e.g., the high-voltage device region) and the third well region of the second transistor (e.g., an I / O transistor, including a conventional NMOS FET or a conventional PMOS FET) in the second device region (e.g., the conventional-voltage device region) are formed simultaneously. In addition, the first well region is formed by a discontinuous doping region, while the third well region is formed by a continuous doping region. Therefore, the first well region can have a doping concentration lower than that of the third well region. By adjusting the number and size of the discontinuous portions of the discontinuous doping region, device performances such as the on-resistance, breakdown voltage, drain-source capacitance, and drain-body capacitance of the first transistor can be modified.

[0128] Compared with traditional semiconductor devices, in which the high-voltage and conventional-voltage well regions are formed by different continuous doping regions, the high-voltage transistor has improved device performance, while the device performance of the I / O transistor is maintained without adding additional masks and process steps. The method of forming a semiconductor device can save manufacturing steps and costs (e.g., mask costs) and improve manufacturing efficiency and manufacturing precision.

[0129] When the first transistor is a high-voltage MOS FET in an RF power amplifier of a Wi-Fi network device, the RF power amplifier can have improved power gain, output power, and reliability.

[0130] In some embodiments, a semiconductor device includes a capacitor provided in a first device region and a second transistor provided in a second device region. The capacitor includes a first gate structure and a first well region. The first gate structure has a second side opposite to the first side and is directly located on the first well region. In some embodiments, the capacitor further includes a second high-concentration doping region having a first conductivity type and located on the first well region. In a first direction, the second side of the gate structure and the second high-concentration doping region are separated by a second distance equal to the first distance.

[0131] In some embodiments, the first high-concentration doping region is electrically connected (or coupled) to the second high-concentration doping region. Therefore, the gate structure can serve as the first electrode of the capacitor. The first high-concentration doping region and the second high-concentration doping region can jointly serve as the second electrode of the capacitor.

[0132] When a semiconductor device includes a capacitor and a second transistor, a first well region of the capacitor is formed simultaneously with a third well region of the second transistor (e.g., an I / O transistor including a conventional NMOS FET or a conventional PMOS FET) in a second device region (e.g., a conventional voltage device region) and a first device region. The doping concentration of the first well region formed by the discontinuous doping regions can be adjusted by adjusting the number and size of the discontinuous portions of the discontinuous doping regions. Accordingly, the capacitance of the capacitor is freely adjustable while the performance of the I / O transistor is maintained without adding extra masks and process steps. A method of forming a semiconductor device can save manufacturing steps and costs (e.g., mask costs) and improve manufacturing efficiency and manufacturing precision.

[0133] While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to cover all such modifications and similar arrangements.

Claims

1. A semiconductor device, characterized in that: include: Semiconductor substrates; A gate structure is disposed on the semiconductor substrate; as well as A first well region, having a first conductivity type, is located in the semiconductor substrate and overlaps with the gate structure, wherein a first bottom of the first well region has a wavy bottom surface.

2. The semiconductor device according to claim 1, wherein Further including: The second well region, having a second conductivity type, is located in the semiconductor substrate and adjacent to the first well region, wherein a first bottom of the first well region is connected to a second bottom of the first well region and has different profiles.

3. The semiconductor device according to claim 2, wherein: The second bottom of the second well region has an arc-shaped bottom surface.

4. The semiconductor device according to claim 3, wherein: The wavy bottom surface of the first well region includes a plurality of wave crests and a plurality of wave troughs, wherein the wave crests are closer to the top surface of the semiconductor substrate than to the top surface of the semiconductor substrate.

5. The semiconductor device according to claim 4, wherein: The first well region has a first sub-region and a second sub-region alternately arranged with the first sub-region, wherein the wave valley is a first bottom surface of the first sub-region, and the wave peak is a second bottom surface of the second sub-region.

6. The semiconductor device according to claim 5, wherein: The first sub-region has a first depth and the second sub-region has a second depth different from the first depth, wherein the first depth is measured from the lowest point of the valley to the top surface of the first well region, and the second depth is measured from the highest point of the peak to the top surface of the first well region.

7. The semiconductor device according to claim 6, wherein: The arcuate bottom surface of the second well region includes only one valley protruding away from the top surface of the semiconductor substrate.

8. The semiconductor device according to claim 7, wherein: A third depth measured from the lowest point of the valley of the second well region to the top surface of the second well region is equal to the first depth.

9. The semiconductor device according to claim 2, wherein: Further including: A first high-concentration doped region having the first conductivity type and located on the first well region, wherein the first side of the gate structure is separated from the first high-concentration doped region in a first direction; as well as The second high-concentration doped region has the first conductivity type and is located on the second well region, wherein the gate structure has a first side directly located on the first well region and a second side adjacent to the second high-concentration doped region.

10. The semiconductor device according to claim 9, wherein: The gate structure, the first high-concentration doping region and the second high-concentration doping region serve as a gate, a drain and a source of the first transistor respectively.

11. The semiconductor device according to claim 1, wherein The gate structure has a first side directly on the first well region and a second side on the first well region and opposite the first side.

12. The semiconductor device according to claim 11, wherein Further including: The second high-concentration doped region has the first conductivity type and is located on the first well region, wherein in the first direction, the second side of the gate structure is separated from the second high-concentration doped region.

13. The semiconductor device according to claim 12, wherein: The first high-concentration doping region is connected to the second high-concentration doping region, and the gate structure serves as a first electrode of the capacitor, while the first high-concentration doping region and the second high-concentration doping region serve together as a second electrode of the capacitor.

14. The semiconductor device according to claim 6, wherein: Further including: a third well region having the first conductivity type and located in a device region of the semiconductor substrate different from the first well region, wherein: The third bottom of the third well region has an arc-shaped bottom surface, A fourth depth measured from the lowest point of a single valley of the arcuate bottom surface of the third well region to the top surface of the third well region is equal to the first depth, and The first well region and the third well region have different doping concentrations.

15. A semiconductor device, characterized in that: include: Semiconductor substrates; A gate structure is disposed on the semiconductor substrate; as well as A first well region, having a first conductivity type, is located in the semiconductor substrate and overlaps with the gate structure, wherein the first well region has a first number of first arc-shaped bottoms, wherein the first number of first arc-shaped bottoms of the first well region is greater than or equal to 2.

16. The semiconductor device according to claim 15, wherein: Further including: A second well region, having a second conductivity type, is located in the semiconductor substrate and adjacent to the first well region, wherein the gate structure overlaps the second well region, wherein the second number of second arc bottoms of the second well region is equal to 1.

17. The semiconductor device according to claim 15, wherein: The first arc-shaped bottoms are connected to each other to form a wavy bottom surface of the first well region.

18. The semiconductor device according to claim 16, wherein: A first depth measured from a lowest point of one of the first arcuate bottoms of the first well region to a top surface of the first well region is equal to a second depth measured from a lowest point of the second arcuate bottom of the second well region to a top surface of the second well region.

19. The semiconductor device according to claim 16, wherein: Further including: A first highly doped region having the first conductivity type, located in the first well region; as well as A second highly doped region of the first conductivity type is located in the second well region, wherein in a first direction, one side of the gate structure is separated from the first highly doped region, and another side of the gate structure is adjacent to the second highly doped region.

20. The semiconductor device according to claim 15, wherein Two opposite sides of the gate structure are directly located on the first well region.

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