Solar cell, photovoltaic module and preparation method of solar cell

Abstract

The invention relates to a solar cell, a photovoltaic module and a preparation method of the solar cell. The solar cell comprises a semiconductor substrate, and a first imprinting layer and a first electrode which are arranged on the semiconductor substrate; the first electrode comprises a first sub-part and a second sub-part which are arranged in the direction away from the semiconductor substrate, and the orthographic projection outer contour of the first sub-part on the semiconductor substrate is located in the orthographic projection outer contour of the second sub-part on the semiconductor substrate; a first through hole is formed in the first imprinting layer, the first through hole comprises a first sub-hole and a second sub-hole which are arranged in the direction away from the semiconductor substrate, the orthographic projection outer contour of the first sub-hole on the semiconductor substrate is located in the orthographic projection outer contour of the second sub-hole on the semiconductor substrate, the first sub-part is arranged in the first sub-hole, and the second sub-part is arranged in the second sub-hole. The second sub-part is arranged in the second sub-hole. Therefore, according to the solar cell, the photovoltaic module and the preparation method of the solar cell provided by the invention, the preparation difficulty of the first electrode can be reduced.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and particularly to solar cells, photovoltaic modules, and methods for manufacturing solar cells. Background Art

[0002] A solar cell, also known as a photovoltaic cell, is a semiconductor device that directly converts the light energy of the sun into electrical energy. Since it is a green and environmentally friendly product that does not cause environmental pollution, and solar energy is a renewable resource, solar cells are a new type of battery with broad development prospects.

[0003] For a long time, efforts to improve the photoelectric conversion efficiency and reduce the manufacturing cost have been the main research content of researchers and photovoltaic practitioners. In related technologies, a heterojunction back contact solar cell (HBC for short) has metal electrodes disposed on the backlight side of the cell, so that there is no metal electrode blockage on the light-facing side of the cell, increasing the light absorption area, thereby improving the photoelectric conversion efficiency. It is also the solar cell technology with the highest efficiency in the laboratory and has received wide attention. In HBC solar cells, the patterned preparation of the back electrode is one of the key processes. However, the preparation of the metal electrodes of the above HBC cells is difficult, mainly involving the complexity of electrode design, material selection, and process limitations. Among them, since the electrodes need to be formed on different polar regions in a finger-like shape, the electrode patterns are complex and require high-precision patterning capabilities. Traditional screen printing technology is difficult to achieve micron-level accuracy, and the pattern edges may be blurred and overflow, affecting the electrode performance. Although lithography technology can meet the accuracy requirements, its complex process flow and high cost make it unsuitable for large-scale production. Laser direct writing technology can directly process electrode patterns on metal films or conductive materials, but the presence of thermal effects will damage the functions of the underlying polar regions. Summary of the Invention

[0004] Based on this, it is necessary to provide a solar cell, a photovoltaic module, and a method for manufacturing a solar cell, which can reduce the preparation difficulty of the first electrode.

[0005] In a first aspect, an embodiment of the present application provides a solar cell, including:

[0006] A semiconductor substrate having a first surface and a second surface disposed opposite to each other;

[0007] A first imprinting layer disposed on the first surface;

[0008] A first electrode disposed on the first surface; the first electrode includes a first sub-part and a second sub-part arranged in a direction away from the semiconductor substrate, and the outer contour of the positive projection of the first sub-part on the semiconductor substrate is located within the outer contour of the positive projection of the second sub-part on the semiconductor substrate;

[0009] Among them, a first through hole is provided on the first imprinting layer. The first through hole penetrates the first imprinting layer along the thickness direction of the semiconductor substrate. The first through hole includes a first sub-hole and a second sub-hole arranged in a direction away from the semiconductor substrate. The outer contour of the positive projection of the first sub-hole on the semiconductor substrate is located within the outer contour of the positive projection of the second sub-hole on the semiconductor substrate. The first sub-part is disposed in the first sub-hole, and the second sub-part is disposed in the second sub-hole.

[0010] For the solar cell provided by the embodiment of the present application, the first imprinting layer can be formed by an imprinting method. The imprinting method has the advantages of low difficulty, low cost, short construction period, high yield, high resolution, etc. By restricting the shape of the first electrode through the first imprinting layer, a three-dimensional shaped patterned first electrode can be realized quickly and simply, so as to reduce the preparation difficulty of the first electrode.

[0011] In one embodiment, the solar cell includes a first polarity region and a second polarity region with different polarities. The first electrode and the first imprinting layer are both located in the first polarity region;

[0012] The solar cell includes a second electrode disposed on the first surface. The second electrode is located in the second polarity region; the second electrode includes a third sub-part and a fourth sub-part arranged in a direction away from the semiconductor substrate. The outer contour of the positive projection of the third sub-part on the semiconductor substrate is located within the outer contour of the positive projection of the fourth sub-part on the semiconductor substrate.

[0013] In one embodiment, the solar cell further includes a second imprinting layer disposed on the first surface. The second imprinting layer is located in the second polarity region;

[0014] A second through hole is provided on the second imprinting layer. The second through hole penetrates the second imprinting layer along the thickness direction of the semiconductor substrate. The second through hole includes a third sub-hole and a fourth sub-hole arranged in a direction away from the semiconductor substrate. The outer contour of the positive projection of the third sub-hole on the semiconductor substrate is located within the outer contour of the positive projection of the fourth sub-hole on the semiconductor substrate; the third sub-part is disposed in the third sub-hole, and the fourth sub-part is disposed in the fourth sub-hole.

[0015] In one embodiment, there is an isolation region between the first polarity region and the second polarity region;

[0016] There is a gap between the positive projection of the first imprinting layer on the semiconductor substrate and the positive projection of the second imprinting layer on the semiconductor substrate, and the gap is located in the isolation region.

[0017] In one embodiment, the minimum dimension range of the first sub-part along the direction perpendicular to the thickness direction of the semiconductor substrate is 50 nm - 100 μm; and / or,

[0018] The minimum dimension range of the second sub-part along the direction perpendicular to the thickness direction of the semiconductor substrate is 50 nm - 100 μm; and / or,

[0019] The size range of the first sub - portion along the thickness direction of the semiconductor substrate is 50 nm - 10 μm; and / or,

[0020] The size range of the second sub - portion along the thickness direction of the semiconductor substrate is 50 nm - 10 μm.

[0021] In one embodiment, the minimum size range of the third sub - portion along the direction perpendicular to the thickness direction of the semiconductor substrate is 50 nm - 100 μm; and / or,

[0022] The minimum size range of the fourth sub - portion along the direction perpendicular to the thickness direction of the semiconductor substrate is 50 nm - 100 μm; and / or,

[0023] The size range of the third sub - portion along the thickness direction of the semiconductor substrate is 50 nm - 10 μm; and / or,

[0024] The size range of the fourth sub - portion along the thickness direction of the semiconductor substrate is 50 nm - 10 μm.

[0025] In one embodiment, the solar cell includes a first conductive layer and a first seed layer stacked along the direction away from the semiconductor substrate. Both the first conductive layer and the first seed layer are located in the first polarity region and are between the first imprint layer and the semiconductor substrate; and / or,

[0026] The solar cell includes a second conductive layer and a second seed layer stacked along the direction away from the semiconductor substrate. Both the second conductive layer and the second seed layer are located in the second polarity region and are between the second imprint layer and the semiconductor substrate.

[0027] In a second aspect, an embodiment of the present application provides a photovoltaic module, including the solar cell in the first aspect above.

[0028] In a third aspect, an embodiment of the present application provides a method for manufacturing a solar cell, including:

[0029] Providing a semiconductor substrate; the semiconductor substrate has a first surface and a second surface disposed opposite to each other;

[0030] Forming a first imprint layer on the first surface; a first through - hole is provided on the first imprint layer. The first through - hole penetrates the first imprint layer along the thickness direction of the semiconductor substrate. The first through - hole includes a first sub - hole and a second sub - hole arranged along the direction away from the semiconductor substrate. The outer contour of the orthographic projection of the first sub - hole on the semiconductor substrate is located within the outer contour of the orthographic projection of the second sub - hole on the semiconductor substrate;

[0031] A first electrode is formed on a first surface; the first electrode includes a first sub - portion and a second sub - portion arranged in a direction away from the semiconductor substrate, and the outer contour of the positive projection of the first sub - portion on the semiconductor substrate is located within the outer contour of the positive projection of the second sub - portion on the semiconductor substrate; the first sub - portion is disposed in a first sub - hole, and the second sub - portion is disposed in a second sub - hole.

[0032] In one embodiment, the solar cell includes a first polar region and a second polar region with different polarities;

[0033] Forming a first imprint layer on the first surface includes:

[0034] Forming an imprint resist on the first surfaces of the first polar region and the second polar region;

[0035] Performing nano - imprinting on the imprint resist to form a first through - hole in the imprint resist of the first polar region and a second through - hole in the imprint resist of the second polar region; the second through - hole includes a third sub - hole and a fourth sub - hole arranged in a direction away from the semiconductor substrate, and the outer contour of the positive projection of the third sub - hole on the semiconductor substrate is located within the outer contour of the positive projection of the fourth sub - hole on the semiconductor substrate; the imprint resist located in the first polar region forms a first imprint layer, and the imprint resist located in the second polar region forms a second imprint layer.

[0036] In one embodiment, forming a first electrode on the first surface includes:

[0037] Forming an electrode material layer in the first through - hole and the second through - hole; the electrode material layer located in the first sub - hole forms the first sub - portion, the electrode material layer located in the second sub - hole forms the second sub - portion, the electrode material layer located in the third sub - hole forms the third sub - portion, and the electrode material layer located in the fourth sub - hole forms the fourth sub - portion; the outer contour of the positive projection of the third sub - portion on the semiconductor substrate is located within the outer contour of the positive projection of the fourth sub - portion on the semiconductor substrate, and the third sub - portion and the fourth sub - portion together form a second electrode.

[0038] In one embodiment, there is an isolation region between the first polar region and the second polar region;

[0039] Forming an imprint resist on the first surfaces of the first polar region and the second polar region includes: forming an imprint resist on the first surfaces of the first polar region, the second polar region, and the isolation region;

[0040] After forming the first electrode on the first surface, it includes:

[0041] Removing at least a part of the imprint resist located in the isolation region; there is a gap between the positive projection of the first imprint layer on the semiconductor substrate and the positive projection of the second imprint layer on the semiconductor substrate, and the gap is located in the isolation region. Brief Description of the Drawings

[0042] Figure 1 It is a cross - sectional view of the solar cell provided by the embodiment of the present application.

[0043] Figure 2 Top view of the solar cell provided by the embodiment of the present application.

[0044] Figure 3 Schematic structural diagram after forming the first doped semiconductor layer and the second doped semiconductor layer provided by the embodiment of the present application.

[0045] Figure 4 Schematic structural diagram after forming the conductive material layer provided by the embodiment of the present application.

[0046] Figure 5 Schematic structural diagram after forming the imprinting glue provided by the embodiment of the present application.

[0047] Figure 6 Schematic structural diagram after nano - imprinting the imprinting glue provided by the embodiment of the present application.

[0048] Figure 7 Schematic structural diagram after forming the first electrode and the stacked electrode provided by the embodiment of the present application.

[0049] Figure 8 Cross - sectional view of the imprinting template provided by the embodiment of the present application.

[0050] Figure 9 Schematic flow chart of the preparation method of the solar cell provided by the embodiment of the present application.

[0051] Figure 10 Scanning electron micrograph after separating the imprinting template and the imprinting glue provided by the embodiment of the present application.

[0052] Figure 11 Another scanning electron micrograph after separating the imprinting template and the imprinting glue provided by the embodiment of the present application.

[0053] Explanation of reference numerals:

[0054] 100, solar cell; 100a, first polarity region; 100b, second polarity region; 100c, isolation region; 101a, imprinting glue; 104a, electrode material layer; 107a, conductive material layer; 110, first imprinting layer; 111, first through hole; 1111, first sub-hole; 1112, second sub-hole; 120, second imprinting layer; 122, second through hole; 1223, third sub-hole; 1224, fourth sub-hole; 130, semiconductor substrate; 131, first surface; 132, second surface; 141, first electrode; 1411, first sub-portion; 1412, second sub-portion; 142, second electrode; 1423, third sub-portion; 1424, fourth sub-portion; 151, first passivation layer; 152, second passivation layer; 153, third passivation layer; 154, anti-reflection layer; 161, first doped semiconductor layer; 162, second doped semiconductor layer; 171, first conductive layer; 172, second conductive layer; 200, imprinting template; 210, first protrusion; 220, second protrusion; 230, plate body. Detailed implementation manners

[0055] To make the above objects, features, and advantages of the present application more obvious and understandable, the following will describe the detailed implementation manners of the present application in conjunction with the accompanying drawings. Many specific details are set forth in the following description to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0056] In addition, if the terms "first" and "second" appear, these terms are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of these features. In the description of the present application, if the term "a plurality" appears, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0057] In the present application, unless otherwise clearly specified and limited, if a first feature is described as "above" or "below" a second feature or the like, the meaning may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over", and "on" the second feature may be that the first feature is directly above or obliquely above the second feature, or simply indicates that the first feature has a higher horizontal height than the second feature. The first feature being "below", "beneath", and "under" the second feature may be that the first feature is directly below or obliquely below the second feature, or simply indicates that the first feature has a lower horizontal height than the second feature.

[0058] In the related art, an HBC cell has an N-type region and a P-type region. The HBC cell includes a semiconductor substrate having a first surface and a second surface disposed opposite to each other. On the first surface located in the N-type region, an N-type amorphous silicon, a first conductive layer, and a first electrode are provided. On the first surface located in the P-type region, a P-type amorphous silicon, a second conductive layer, and a second electrode are provided. The widths of the first electrode and the second electrode are the same everywhere along the thickness direction of the semiconductor substrate.

[0059] However, taking the first electrode as an example. In order to ensure that the contact region between the first electrode and the first conductive layer has a low contact recombination loss, the width of the first electrode needs to be set relatively narrow to reduce the contact area between the first electrode and the first conductive layer. In addition, in order to ensure that the first electrode has a low sheet resistance to reduce the current transmission loss, the cross-sectional area of the first electrode needs to be set relatively large. Therefore, the shape requirement of the first electrode is a narrow and high shape, and it is difficult to form the first electrode with this shape by using photolithography patterning technology or laser patterning technology.

[0060] To solve the above problems, the embodiments of the present application provide a solar cell, a photovoltaic module, and a method for manufacturing a solar cell, which can reduce the manufacturing difficulty of the first electrode.

[0061] The following will be combined with Figures 1 - 9 to describe the solar cell 100, the photovoltaic module, and the method for manufacturing the solar cell 100 provided by the embodiments of the present application.

[0062] The embodiments of the present application provide a solar cell 100, which may include a heterojunction solar cell (abbreviated as HJT), an Interdigitated BackContact (abbreviated as IBC), a tunnel oxide passivating contact (abbreviated as TOPCON), a Heterojunction Back Contact (abbreviated as HBC), a tunnel oxide passivating back contact (abbreviated as TBC), or a Heterojunction and Tunnel Oxide Passivated BackContact Solar Cell (abbreviated as HTBC), etc. The embodiments of the present application will be described by taking the heterojunction back contact cell as an example.

[0063] See Figure 1 and Figure 2, the solar cell 100 may have a first direction X, a second direction Y, and a third direction Z, and the first direction X, the second direction Y, and the third direction Z are all different from each other. The first direction X, the second direction Y, and the third direction Z may be perpendicular to each other pairwise. For example, the third direction Z may be the thickness direction of the solar cell 100, and the first direction X and the second direction Y may be any two different directions perpendicular to the thickness direction of the solar cell 100. The first direction X may be the length direction of the solar cell 100, and the second direction Y may be the width direction of the solar cell 100. The length, width, thickness, etc. in the embodiments of the present application are only for convenience of description and do not imply any limitation on the size. For example, the width may be greater than, equal to, or less than the length. The directions of the solar cell 100 and the film layers such as the semiconductor substrate 130 may be the same.

[0064] See Figure 1 , the solar cell 100 includes a semiconductor substrate 130, and the semiconductor substrate 130 may provide support for the subsequently formed film layers. The semiconductor substrate 130 may be used to receive incident light and generate photo-generated carriers.

[0065] Exemplarily, see Figure 1 , the semiconductor substrate 130 may have a first surface 131 and a second surface 132 oppositely disposed along the thickness direction of the semiconductor substrate 130 (i.e., the third direction Z), and at least one of the first surface 131 and the second surface 132 may be used to receive sunlight. In the embodiments of the present application, the case where the second surface 132 is used to receive sunlight is taken as an example for illustration, that is, the second surface 132 is close to the light-facing surface of the solar cell 100, and the first surface 131 is close to the backlight surface of the solar cell 100.

[0066] Exemplarily, the semiconductor substrate 130 may be a silicon substrate, and the material of the silicon substrate may include at least one of single-crystalline silicon and polycrystalline silicon. In the embodiments of the present application, single-crystalline silicon is taken as an example for illustration.

[0067] Exemplarily, the doping type of the semiconductor substrate 130 may be N-type doping, and the N-type doping may be achieved by doping N-type ions, and the N-type ions may include at least one of phosphorus, arsenic, and antimony. Alternatively, the doping type of the semiconductor substrate 130 is P-type doping, and the P-type doping may be achieved by doping P-type ions, and the P-type ions may include at least one of aluminum, boron, and gallium. In the embodiments of the present application, the case where the doping type of the semiconductor substrate 130 is N-type doping is taken as an example for illustration.

[0068] Exemplarily, the thickness range of the semiconductor substrate 130 may be 90 - 180 microns, for example, 110 microns. The resistivity range of the semiconductor substrate 130 may be 0.1 - 100 Ω·cm, for example, 3 Ω·cm.

[0069] The following describes the first imprinting layer 110, the second imprinting layer 120, the first electrode 141, and the second electrode 142 provided in the embodiments of the present application.

[0070] Referring to Figure 1 , the solar cell 100 includes a first imprinting layer 110. The first imprinting layer 110 may be disposed on the first surface 131. A first through hole 111 is provided on the first imprinting layer 110. The first through hole 111 penetrates the first imprinting layer 110 along the thickness direction of the semiconductor substrate 130. The first through hole 111 in the first imprinting layer 110 can be used to limit the shape of the first electrode 141 formed subsequently in the first through hole 111, so as to form a first electrode 141 adapted to the shape of the first through hole 111. The first through hole 111 includes a first sub-hole 1111 and a second sub-hole 1112 arranged in a direction away from the semiconductor substrate 130. The outer contour of the orthographic projection of the first sub-hole 1111 on the semiconductor substrate 130 is located within the outer contour of the orthographic projection of the second sub-hole 1112 on the semiconductor substrate 130.

[0071] Wherein, when the outer contour of the orthographic projection of the first sub-hole 1111 on the semiconductor substrate 130 is located within the outer contour of the orthographic projection of the second sub-hole 1112 on the semiconductor substrate 130, in a cross-section along the thickness direction perpendicular to the semiconductor substrate 130, the cross-sectional area of the first sub-hole 1111 is smaller than the cross-sectional area of the second sub-hole 1112.

[0072] Referring to Figure 1, the solar cell 100 includes a first electrode 141. The first electrode 141 can collect and transport carriers, thereby achieving the conversion of solar energy into electrical energy. The first electrode 141 can be disposed on the first surface 131. The first electrode 141 includes a first sub - part 1411 and a second sub - part 1412 arranged in a direction away from the semiconductor substrate 130. The outer contour of the positive projection of the first sub - part 1411 on the semiconductor substrate 130 is located within the outer contour of the positive projection of the second sub - part 1412 on the semiconductor substrate 130. The first sub - part 1411 is disposed in the first sub - hole 1111, and the second sub - part 1412 is disposed in the second sub - hole 1112. Thus, by providing the first imprint layer 110 and setting the first sub - hole 1111 and the second sub - hole 1112 in the first imprint layer 110, the first sub - part 1411 is disposed in the first sub - hole 1111 such that the shape of the first sub - part 1411 is adapted to the shape of the first sub - hole 1111, and the second sub - part 1412 is disposed in the second sub - hole 1112 such that the shape of the second sub - part 1412 is adapted to the shape of the second sub - hole 1112. The first imprint layer 110 can be formed by an imprinting method (e.g., nano - imprinting). The nano - imprinting method has the advantages of low difficulty, low cost, short construction period, high yield, high resolution, etc. By restricting the shape of the first electrode 141 through the first imprint layer 110, the patterning of the three - dimensional shape of the first electrode 141 can be achieved quickly and simply, so as to reduce the preparation difficulty of the first electrode 141. In a cross - section along the thickness direction perpendicular to the semiconductor substrate 130, the cross - sectional area of the first sub - part 1411 is smaller than the cross - sectional area of the second sub - part 1412. This makes the cross - sectional area of the first sub - part 1411 smaller, and the contact area between the first sub - part 1411 and the adjacent film layer smaller, thereby reducing the contact recombination loss between the first electrode 141 and the adjacent film layer (e.g., at least one of the first doped semiconductor layer 161, the first conductive layer 171, and the first seed layer). In addition, the larger cross - sectional area of the second sub - part 1412 is beneficial to reducing the line resistance of the first electrode 141 to reduce the current transmission loss. Thus, it is not necessary to make the first electrode 141 into a narrow and high shape, which is beneficial to reducing the thickness of the solar cell 100 and can also reduce the preparation difficulty of the first electrode 141. Secondly, the larger cross - sectional area of the second sub - part 1412 can increase the reflection of light irradiated from the light - receiving surface to the back - light surface, improving the conversion efficiency of the solar cell 100.

[0073] Exemplarily, the dimensions (i.e., lengths) of the first sub - part 1411 and the second sub - part 1412 along the second direction Y can be the same, and the dimension (i.e., width) of the first sub - part 1411 along the first direction X is smaller than the dimension of the second sub - part 1412 along the first direction X. Thus, the larger width of the second sub - part 1412 can increase the reflection of light irradiated from the light - receiving surface to the back - light surface, improving the conversion efficiency of the solar cell 100.

[0074] It should be noted that nanoimprint lithography (NIL) is a micro-nano processing technology that uses a template with a micro-nano structure pattern to transfer the pattern to the corresponding substrate to produce a micro-nano size pattern. The transfer medium is usually a very thin polymer film. The nanoimprint process mainly includes the following steps: 1. Preparation of imprint template, 2. Coating of imprint glue, 3. Imprint treatment of imprint glue, 4. Separation of imprint template and imprint glue, 5. Development treatment (i.e. removal of residual glue), 6. Cleaning and drying. A thermoplastic polymer coating (such as polymethyl methacrylate, polystyrene, polycarbonate, etc.) or a photosensitive polymer coating (such as acrylate-based polymer, epoxy resin photosensitive adhesive, etc.) or a thermosetting polymer coating (such as phenolic resin, polyimide, etc.) or a solvent-volatile polymer coating (such as polyvinyl alcohol PVA, polystyrene PS, etc.) or a two-component chemical cross-linking curing polymer coating (such as PDMS modified adhesive, fluorinated polymer, etc.) is pre-attached to silicon or other substrates as a substrate, and the template with nano-patterns is contacted with the substrate through the corresponding equipment and apparatus and accurately embossed and shaped. After certain conditions (such as time, pressure, temperature, light, etc.), the template is separated from the substrate, so that the pattern is replicated and the nano-structure pattern on the template surface is transferred to the polymer coating on the substrate surface. Compared with traditional photolithography, nanoimprinting can not only prepare two-dimensional planar structures, but also can emboss quasi-three-dimensional structures through template making, which provides greater freedom for performance regulation and device design. Nanoimprinting can not only produce high-resolution graphics with a resolution of less than 5nm, but also has a relatively simple process and low power consumption. The present application uses nanoimprinting technology as a graphic means in the first electrode 141 and the second electrode 142, which can obtain a three-dimensional "T"-shaped structure that cannot be obtained by photolithography, screen printing and laser direct writing at one time, which can greatly reduce the number of steps and shorten the process flow. Compared with using laser to graphic the first electrode 141 and / or the second electrode 142, it can reduce the thermal damage of the laser to the lower 151, 162 and 152, and improve the yield of the solar cell 100.

[0075] In some embodiments, the imprint template preparation may include, the imprint template surface treatment, first cleaning the imprint template surface to remove oxides, particles and other contaminants, usually using deionized water (DI water), ethanol (EtOH) and other solvents for cleaning, ultrasonic cleaning or plasma cleaning. Then, by applying an anti-stick coating (such as fluorinated self-assembled monolayer, diamond-like carbon film (DLC), fluorinated surfactant, trichlorosilane self-assembled film, polybenzoxazine anti-stick material) to reduce the demolding force and improve reusability. Preferably, trichlorosilane self-assembled film.

[0076] In some embodiments, see Figure 1, the solar cell 100 includes a first polar region 100a and a second polar region 100b with different polarities, and the first polar region 100a and the second polar region 100b may be arranged at intervals. Alternatively, the first polar region 100a and the second polar region 100b are arranged adjacent to each other.

[0077] In the embodiment of the present application, the case where the first polar region 100a and the second polar region 100b are arranged at intervals is taken as an example for illustration. Among them, the first polar region 100a and the second polar region 100b are arranged at intervals, and an isolation region 100c is formed between the first polar region 100a and the second polar region 100b.

[0078] Exemplarily, referring to Figure 2 , both the first polar region 100a and the second polar region 100b may be in a finger-like shape.

[0079] In some embodiments, referring to Figure 1 , both the first electrode 141 and the first imprinting layer 110 may be located in the first polar region 100a.

[0080] In some embodiments, referring to Figure 1 , the solar cell 100 may include a second electrode 142. The second electrode 142 may be disposed on the first surface 131. The second electrode 142 can collect and transport carriers, thereby realizing the conversion of solar energy into electrical energy. The second electrode 142 may be located in the second polar region 100b. The second electrode 142 includes a third sub-part 1423 and a fourth sub-part 1424 arranged along the direction away from the semiconductor substrate 130. The outer contour of the positive projection of the third sub-part 1423 on the semiconductor substrate 130 is located within the outer contour of the positive projection of the fourth sub-part 1424 on the semiconductor substrate 130. Thus, in a cross-section along the thickness direction perpendicular to the semiconductor substrate 130, the cross-sectional area of the third sub-part 1423 is smaller than the cross-sectional area of the fourth sub-part 1424, so that the cross-sectional area of the third sub-part 1423 is smaller, and the contact area between the third sub-part 1423 and the adjacent film layer is smaller, thereby reducing the contact recombination loss between the second electrode 142 and the adjacent film layer. In addition, the cross-sectional area of the fourth sub-part 1424 is larger, which is beneficial to reducing the line resistance of the second electrode 142 to reduce the current transmission loss. Therefore, it is not necessary to make the second electrode 142 into a narrow and high shape, which is beneficial to reducing the thickness of the solar cell 100 and can also reduce the preparation difficulty and cost of the second electrode 142.

[0081] Among them, the first through hole 111 and the second through hole 122 may be arranged at intervals, and the first electrode 141 and the second electrode 142 may be arranged at intervals, thereby preventing short circuit between the first electrode 141 and the second electrode 142.

[0082] In some embodiments, referring to Figure 1, the solar cell 100 further includes a second imprinting layer 120. The second imprinting layer 120 can be disposed on the first surface 131. The second imprinting layer 120 is located in the second polarity region 100b. A second through hole 122 is provided in the second imprinting layer 120. The second through hole 122 penetrates the second imprinting layer 120 along the thickness direction of the semiconductor substrate 130. The second through hole 122 includes a third sub-hole 1223 and a fourth sub-hole 1224 arranged in a direction away from the semiconductor substrate 130. The outer contour of the orthographic projection of the third sub-hole 1223 on the semiconductor substrate 130 is located within the outer contour of the orthographic projection of the fourth sub-hole 1224 on the semiconductor substrate 130. A third sub-part 1423 is disposed in the third sub-hole 1223, and a fourth sub-part 1424 is disposed in the fourth sub-hole 1224. In this way, by providing the second imprinting layer 120 and providing the third sub-hole 1223 and the fourth sub-hole 1224 in the second imprinting layer 120, and disposing the third sub-part 1423 in the third sub-hole 1223, the shape of the third sub-part 1423 is adapted to the shape of the third sub-hole 1223, and disposing the fourth sub-part 1424 in the fourth sub-hole 1224, the shape of the fourth sub-part 1424 is adapted to the shape of the fourth sub-hole 1224. The second imprinting layer 120 can be formed by nanoimprinting. The nanoimprinting method has the advantages of low difficulty, low cost, short construction period, high yield, high resolution, etc. By restricting the shape of the second electrode 142 through the second imprinting layer 120, the three-dimensional shaped patterned second electrode 142 can be realized quickly and simply, and the preparation difficulty and cost of the second electrode 142 can be reduced.

[0083] In summary, by restricting the shapes of the first electrode 141 and the second electrode 142 through the first imprinting layer 110 and the second imprinting layer 120, the three-dimensional shaped patterned first electrode 141 and second electrode 142 can be realized quickly and simply, that is, the first electrode 141 and the second electrode 142 are made to have a "T" - shaped structure with a narrow contact area and a large non - contact area. This structure can not only achieve good optical reflection and a low contact recombination area, but also achieve a lower line resistance and contact resistance, and can improve the conversion efficiency of the solar cell 100.

[0084] In some embodiments, referring to Figure 1 , there is a gap between the orthographic projection of the first imprinting layer 110 on the semiconductor substrate 130 and the orthographic projection of the second imprinting layer 120 on the semiconductor substrate 130. The gap is located in the isolation region 100c. In this way, by arranging the first imprinting layer 110 and the second imprinting layer 120 at intervals, it is beneficial to reduce the short - circuit risk between the first electrode 141 and the second electrode 142.

[0085] Exemplarily, the minimum dimension of the first sub - portion 1411 along the direction perpendicular to the thickness direction of the semiconductor substrate 130 (e.g., the width along the first direction X) ranges from 50 nm to 100 μm, so that the too - small dimension can be avoided, which is beneficial to reducing the difficulty of setting the first sub - portion 1411. In addition, the too - large dimension can also be avoided, which is beneficial to reducing the contact recombination loss between the first electrode 141 and the adjacent film layers.

[0086] For example, the minimum dimension of the first sub - portion 1411 along the direction perpendicular to the thickness direction of the semiconductor substrate 130 can be 50 nm, 500 nm, 5 μm, 10 μm, 15 μm, 25 μm, 35 μm, 45 μm, 90 μm or any value between 50 nm and 100 μm.

[0087] Exemplarily, the minimum dimension of the second sub - portion 1412 along the direction perpendicular to the thickness direction of the semiconductor substrate 130 (e.g., the width along the first direction X) ranges from 50 nm to 100 μm, so that the too - small dimension can be avoided, which is beneficial to reducing the wire resistance of the first electrode 141. In addition, the too - large dimension can also be avoided, which is beneficial to reducing the area occupied by the first electrode 141 and reducing the layout influence of the first electrode 141 on the second electrode 142.

[0088] For example, the minimum dimension of the second sub - portion 1412 along the direction perpendicular to the thickness direction of the semiconductor substrate 130 can be 50 nm, 500 nm, 5 μm, 10 μm, 15 μm, 25 μm, 35 μm, 45 μm, 90 μm or any value between 50 nm and 500 nm.

[0089] Exemplarily, the dimension of the first sub - portion 1411 along the thickness direction of the semiconductor substrate 130 (e.g., the thickness) ranges from 50 nm to 10 μm, so that the too - small dimension can be avoided, which is beneficial to reducing the wire resistance of the first electrode 141. In addition, the too - large dimension can also be avoided, which is beneficial to reducing the thickness of the solar cell 100 and shortening the preparation time of the first electrode 141.

[0090] For example, the dimension of the first sub - portion 1411 along the thickness direction of the semiconductor substrate 130 can be 50 nm, 500 nm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 10 μm or any value between 50 nm and 10 μm.

[0091] Exemplarily, the dimension of the second sub - portion 1412 along the thickness direction of the semiconductor substrate 130 (e.g., the thickness) ranges from 50 nm to 10 μm, so that the too - small dimension can be avoided, which is beneficial to reducing the wire resistance of the first electrode 141. In addition, the too - large dimension can also be avoided, which is beneficial to reducing the thickness of the solar cell 100 and shortening the preparation time of the first electrode 141.

[0092] For example, the dimension of the second sub - portion 1412 in the thickness direction of the semiconductor substrate 130 can be 50 nm, 500 nm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 10 μm, or any value between 50 nm and 10 μm.

[0093] Exemplarily, the range of the minimum dimension of the third sub - portion 1423 perpendicular to the thickness direction of the semiconductor substrate 130 (e.g., the width along the first direction X) is 50 nm - 100 μm, which is beneficial to reducing the setting difficulty of the third sub - portion 1423 and also beneficial to reducing the contact recombination loss between the second electrode 142 and the adjacent film layer.

[0094] For example, the minimum dimension of the third sub - portion 1423 perpendicular to the thickness direction of the semiconductor substrate 130 can be 50 nm, 500 nm, 5 μm, 10 μm, 15 μm, 25 μm, 35 μm, 45 μm, 90 μm, or any value between 50 nm and 100 μm.

[0095] Exemplarily, the range of the minimum dimension of the fourth sub - portion 1424 perpendicular to the thickness direction of the semiconductor substrate 130 (e.g., the width along the first direction X) is 50 nm - 100 μm, which is beneficial to reducing the wire resistance of the second electrode 142 and also beneficial to reducing the area occupied by the second electrode 142.

[0096] For example, the minimum dimension of the fourth sub - portion 1424 perpendicular to the thickness direction of the semiconductor substrate 130 can be 50 nm, 500 nm, 5 μm, 10 μm, 15 μm, 25 μm, 35 μm, 45 μm, 90 μm, or any value between 50 nm and 100 μm.

[0097] Exemplarily, the range of the dimension of the third sub - portion 1423 in the thickness direction of the semiconductor substrate 130 (e.g., the thickness) is 50 nm - 10 μm, which is beneficial to reducing the wire resistance of the second electrode 142 and also beneficial to reducing the thickness of the solar cell 100 and shortening the preparation time of the second electrode 142.

[0098] For example, the dimension of the third sub - portion 1423 in the thickness direction of the semiconductor substrate 130 can be 50 nm, 500 nm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 10 μm, or any value between 50 nm and 10 μm.

[0099] Exemplarily, the range of the dimension of the fourth sub - portion 1424 in the thickness direction of the semiconductor substrate 130 (e.g., the thickness) is 50 nm - 10 μm, which is beneficial to reducing the wire resistance of the second electrode 142 and also beneficial to reducing the thickness of the solar cell 100 and shortening the preparation time of the second electrode 142.

[0100] For example, the dimension of the fourth sub - part 1424 in the thickness direction of the semiconductor substrate 130 can be 50 nm, 500 nm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 10 μm, or any value between 50 nm and 10 μm.

[0101] In some embodiments, at least one of the first electrode 141 and the second electrode 142 can be formed by electroplating. For example, electroplating can include one of horizontal electroplating, vertical electroplating, and basket - type electroplating. For example, vertical electroplating is adopted. Specific electroplating processes, such as solution ratio and temperature control, electroplating time, current density, etc., are not limited in the embodiments of the present application.

[0102] The following describes the first conductive layer 171, the second conductive layer 172, the first seed layer, and the second seed layer provided by the embodiments of the present application.

[0103] In some embodiments, referring to Figure 1 , the solar cell 100 further includes a first conductive layer 171 and a first seed layer stacked in a direction away from the semiconductor substrate 130. Both the first conductive layer 171 and the first seed layer are located between the first imprint layer 110 and the semiconductor substrate 130, and the first seed layer is located between the first conductive layer 171 and the first imprint layer 110. The first conductive layer 171 can collect the current generated by the cell and transmit it to the first electrode 141. Thus, by providing a first seed layer between the first conductive layer 171 and the first electrode 141, the first seed layer contacts the first sub - part 1411 of the first electrode 141, and the first seed layer is beneficial to preventing metal ions of the first electrode 141 from diffusing into the first conductive layer 171, and can improve the bonding force between the first electrode 141 and the first conductive layer 171.

[0104] For example, the first seed layer can be formed by deposition, and the first electrode 141 can be formed by electroplating. The first seed layer is beneficial to accelerating the electroplating speed of the first electrode 141 and improving the electroplating efficiency.

[0105] In the embodiment with the first polarity region 100a provided, both the first conductive layer 171 and the first seed layer are located in the first polarity region 100a.

[0106] In some embodiments, referring to Figure 1, the solar cell 100 further includes a second conductive layer 172 and a second seed layer stacked in a direction away from the semiconductor substrate 130. Both the second conductive layer 172 and the second seed layer are located between the second imprint layer 120 and the semiconductor substrate 130, and the second seed layer is located between the second conductive layer 172 and the second imprint layer 120. The second conductive layer 172 can collect the current generated by the cell and transmit it to the second electrode 142. Thus, by providing a second seed layer between the second conductive layer 172 and the second electrode 142, the second seed layer contacts the third sub - portion 1423 of the second electrode 142, and the second seed layer helps prevent metal ions of the second electrode 142 from diffusing into the second conductive layer 172, and can improve the bonding force between the second electrode 142 and the second conductive layer 172.

[0107] For example, the second seed layer can be formed by a deposition method, and the second electrode 142 can be formed by an electroplating method. The second seed layer helps to accelerate the electroplating speed of the second electrode 142 and improve the electroplating efficiency.

[0108] In an embodiment provided with the second polar region 100b, both the second conductive layer 172 and the second seed layer are located in the second polar region 100b. Among them, the first conductive layer 171 and the second conductive layer 172 can be arranged at intervals, so as to prevent a short - circuit between the first conductive layer 171 and the second conductive layer 172. The first seed layer and the second seed layer can be arranged at intervals, so as to prevent a short - circuit between the first seed layer and the second seed layer.

[0109] Exemplarily, the material of at least one of the first conductive layer 171 and the second conductive layer 172 can include at least one of indium tin oxide, indium oxide, indium oxide doped with titanium, zinc oxide doped with aluminum, indium oxide doped with tungsten, for example, indium tin oxide.

[0110] Exemplarily, the thickness range of at least one of the first conductive layer 171 and the second conductive layer 172 is 20 - 200 nm, for example, the thickness is 100 nm.

[0111] Exemplarily, the material of at least one of the first electrode 141 and the second electrode 142 includes conductive metals such as silver, copper, tin, nickel, tantalum, etc.

[0112] The following describes the first doped semiconductor layer 161 and the second doped semiconductor layer 162 provided in the embodiments of the present application.

[0113] In some embodiments, referring to Figure 1 , the solar cell 100 includes a first doped semiconductor layer 161. The first doped semiconductor layer 161 is disposed on the first surface 131, and the first doped semiconductor layer 161 is located between the first conductive layer 171 and the semiconductor substrate 130. The first doped semiconductor layer 161 has a low resistance, can effectively reduce the current loss and increase the conductivity.

[0114] In an embodiment provided with the first polarity region 100a, the first doped semiconductor layer 161 may be located in the first polarity region 100a.

[0115] In some embodiments, referring to Figure 1 , the solar cell 100 includes a second doped semiconductor layer 162 disposed on the first surface 131, and the second doped semiconductor layer 162 is located between the second conductive layer 172 and the semiconductor substrate 130. The second doped semiconductor layer 162 has a lower resistance, which can effectively reduce current loss and increase conductivity.

[0116] In an embodiment provided with the second polarity region 100b, the second doped semiconductor layer 162 may be located in the second polarity region 100b.

[0117] Wherein, the first doped semiconductor layer 161 and the second doped semiconductor layer 162 may be spaced apart to prevent leakage between the first doped semiconductor layer 161 and the second doped semiconductor layer 162. For example, the first doped semiconductor layer 161 and the second doped semiconductor layer 162 may be separated by a first passivation layer 151 located in the isolation region 100c, and the first passivation layer 151 located in the isolation region 100c may extend between the first doped semiconductor layer 161 and the second doped semiconductor layer 162.

[0118] Exemplarily, the doping type of the second doped semiconductor layer 162 is opposite to that of the first doped semiconductor layer 161. The doping type of one of the first doped semiconductor layer 161 and the second doped semiconductor layer 162 may be N-type doping, and the doping type of the other may be P-type doping.

[0119] Exemplarily, the material of the first doped semiconductor layer 161 includes doped polysilicon, doped amorphous silicon or doped microcrystalline silicon.

[0120] Exemplarily, the material of the second doped semiconductor layer 162 includes doped polysilicon, doped amorphous silicon or doped microcrystalline silicon.

[0121] For example, the first doped semiconductor layer 161 is N-type doped amorphous silicon, and the second doped semiconductor layer 162 is P-type doped amorphous silicon.

[0122] Exemplarily, the thickness range of the first doped semiconductor layer 161 is 2 - 25 nm, and the doping concentration range is 1×10 15 -1×10 21 cm -3 , and the width (for example, the width along the first direction X) ranges from 20 - 800 microns. For example, the thickness is 20 nm and the doping concentration is 1×10 20 cm-3 , with a width of 50 microns.

[0123] Exemplarily, the thickness of the second doped semiconductor layer 162 ranges from 2 - 25 nm, and the doping concentration ranges from 1×10 15 -1×10 21 cm -3 , and the width (e.g., the width along the first direction X) ranges from 20 - 800 microns. For example, the thickness is 20 nm and the doping concentration is 5×10 19 cm -3 , with a width of 50 microns.

[0124] Exemplarily, the gap width between the first doped semiconductor layer 161 and the second doped semiconductor layer 162 (i.e., the dimension of the isolation region 100c along the direction from the first polar region 100a to the second polar region 100b) ranges from 10 - 100 microns, for example, 10 microns.

[0125] The following describes other film layers provided by the embodiments of the present application.

[0126] In some embodiments, referring to Figure 1 , the solar cell 100 includes a first passivation layer 151. The first passivation layer 151 is located on the first surface 131. The first passivation layer 151 can be located between the first doped semiconductor layer 161 and the semiconductor substrate 130. The first passivation layer 151 can improve the photoelectric conversion efficiency by reducing the surface recombination rate, and increase the open - circuit voltage and conversion efficiency of the solar cell 100.

[0127] In the embodiment where the first polar region 100a is provided, the first passivation layer 151 can be located in the first polar region 100a.

[0128] In some embodiments, the first passivation layer 151 can also be located between the second doped semiconductor layer 162 and the semiconductor substrate 130. In the embodiment where the second polar region 100b is provided, the first passivation layer 151 can be located in the second polar region 100b. In the embodiment where the isolation region 100c is provided, the first passivation layer 151 can be located in the isolation region 100c.

[0129] In other embodiments, the first passivation layer 151 can be provided in the first polar region 100a but not in the second polar region 100b, and the passivation layer between the second doped semiconductor layer 162 and the semiconductor substrate 130 can be made of a material different from that of the first passivation layer 151.

[0130] Exemplarily, the material of the first passivation layer 151 can include intrinsic amorphous silicon, tunneling ultra - thin silicon oxide, tunneling ultra - thin aluminum oxide, tunneling ultra - thin silicon nitride, etc.

[0131] Exemplarily, the thickness of the first passivation layer 151 may be in the range of 1-20 nm, for example, the thickness is 2 nm.

[0132] In some embodiments, the solar cell 100 includes a second passivation layer 152 , and the second passivation layer 152 is located on the second surface 132 .

[0133] Exemplarily, the thickness of the second passivation layer 152 may be in the range of 1-20 nm, for example, the thickness is 2 nm.

[0134] In some embodiments, the solar cell 100 includes a third passivation layer 153 , where the third passivation layer 153 is located on a side of the second passivation layer 152 facing away from the semiconductor substrate 130 .

[0135] The solar cell 100 may be provided with at least one of a second passivation layer 152 and a third passivation layer 153 .

[0136] For example, the thickness of the third passivation layer 153 is in the range of 2-25 nm, and the doping concentration is in the range of 1×10 15 -1×10 21 cm -3 For example, the thickness is 5nm and the doping concentration is 1×10 19 cm -3 .

[0137] Exemplarily, the material of at least one of the second passivation layer 152 and the third passivation layer 153 includes one or more of intrinsic amorphous silicon, doped microcrystalline silicon, doped amorphous silicon, tunneling oxide, doped polysilicon, silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride.

[0138] In some embodiments, see Figure 1 The solar cell 100 includes an anti-reflection layer 154 . The anti-reflection layer 154 is located on a side of the third passivation layer 153 facing away from the semiconductor substrate 130 .

[0139] Exemplarily, the thickness of the anti-reflection layer 154 is in the range of 40-80 nm, for example, 70 nm, and the refractive index is 2.0.

[0140] Exemplarily, the material of the anti-reflection layer 154 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium fluoride, and transparent conductive oxide. For example, the material of the anti-reflection layer 154 is silicon nitride.

[0141] The photovoltaic module provided in the embodiments of the present application is described below.

[0142] An embodiment of the present application further provides a photovoltaic module, which may include the solar cell 100 in the above embodiment. There may be at least one solar cell 100 in the photovoltaic module. In this embodiment of the present application, taking multiple solar cells 100 in the photovoltaic module as an example for illustration, multiple solar cells 100 together constitute a battery string layer.

[0143] In some embodiments, the photovoltaic module may include a first encapsulant and a second encapsulant located on both sides of the battery string layer. The first encapsulant and the second encapsulant encapsulate the battery string layer to protect the battery string layer. The first encapsulant and the second encapsulant may include an encapsulation adhesive layer and a cover plate. The encapsulation adhesive layer is located on the side of the cover plate facing the battery string layer. The cover plate can protect the battery string layer, and the encapsulation adhesive layer can be used to connect the cover plate and the battery string layer.

[0144] The following describes the preparation method of the solar cell 100 provided by the embodiment of the present application.

[0145] An embodiment of the present application provides a preparation method of a solar cell 100 for preparing the solar cell 100 in the above embodiment. Refer to Figure 9 and this preparation method includes:

[0146] S100: Provide a semiconductor substrate; the semiconductor substrate has a first surface and a second surface which are oppositely arranged.

[0147] Refer to Figure 3 , the semiconductor substrate 130 may have a first surface 131 and a second surface 132 which are oppositely arranged along the thickness direction of the semiconductor substrate 130. The semiconductor substrate 130 can provide support for the subsequently formed film layers.

[0148] Exemplarily, at least one of the first surface 131 and the second surface 132 of the semiconductor substrate 130 may be textured so that at least one of the first surface 131 and the second surface 132 forms a textured surface structure. For example, the second surface 132 may be textured.

[0149] Exemplarily, the textured surface structure may be a pyramid textured surface, an etched pit textured surface, a conical textured surface, an inverted pyramid textured surface, a columnar textured surface, a grass-like textured surface, a moth-eye textured surface, etc. The textured surface structure has a small reflectivity to incident light, so the absorption and utilization rate of incident light is relatively large, making the photoelectric conversion efficiency of the solar cell 100 relatively high.

[0150] S200: Form a first imprint layer on the first surface; the first imprint layer is provided with a first through hole. The first through hole penetrates the first imprint layer along the thickness direction of the semiconductor substrate 130. The first through hole includes a first sub-hole and a second sub-hole arranged in a direction away from the semiconductor substrate. The outer contour of the positive projection of the first sub-hole on the semiconductor substrate is located within the outer contour of the positive projection of the second sub-hole on the semiconductor substrate 130.

[0151] Referring to Figure 6 , after providing the semiconductor substrate 130, it may include forming a first imprint layer 110 on the first surface 131. A first through hole 111 is provided on the first imprint layer 110. The first through hole 111 penetrates the first imprint layer 110 along the thickness direction of the semiconductor substrate 130. The first through hole 111 includes a first sub-hole 1111 and a second sub-hole 1112 arranged in a direction away from the semiconductor substrate 130. The outer contour of the orthographic projection of the first sub-hole 1111 on the semiconductor substrate 130 is located within the outer contour of the orthographic projection of the second sub-hole 1112 on the semiconductor substrate 130. Thus, the first through hole 111 in the first imprint layer 110 can be used to limit the shape of the first electrode 141 formed subsequently in the first through hole 111, thereby forming a first electrode 141 adapted to the shape of the first through hole 111.

[0152] Exemplarily, referring to Figure 5 , the first imprint layer 110 can be formed by nanoimprinting. For example, nanoimprinting treatment is performed on the imprint resist using an imprint template to form the first imprint layer 110 on the first surface 131. It may include forming an imprint resist 101a on the first surface 131 and performing nanoimprinting treatment on the imprint resist 101a to form a first through hole 111 in the imprint resist 101a in the first polar region 100a. The imprint resist 101a corresponding to the first through hole 111 can be used to form the first imprint layer 110. Thus, the nanoimprinting method has advantages such as low difficulty, low cost, short construction period, high yield, and high resolution, which can reduce the preparation difficulty and cost of the first imprint layer 110.

[0153] Exemplarily, the nanoimprinting treatment of the imprint resist may include precisely aligning the imprint template with the semiconductor substrate coated with the imprint resist to ensure the correct position and orientation of the pattern, pressing the imprint template into the softened imprint resist to transfer the pattern onto the imprint resist, and simultaneously curing the imprint resist under a certain light intensity or temperature and pressure. Among them, curing the imprint resist can be carried out synchronously with the nanoimprinting treatment, or the imprint resist can be cured after the nanoimprinting treatment of the imprint resist and before separating the imprint template and the imprint resist.

[0154] Exemplarily, the curing methods of the imprint resist include thermal curing, UV curing, or solvent evaporation curing. Here, UV curing is preferably used.

[0155] In the embodiment using UV curing, the UV exposure intensity range is 5 - 1000 mW / cm2, preferably 300 mW / cm2 here, and the exposure curing time range is 1 - 300 s, preferably 60 s here.

[0156] Exemplarily, the imprinting speed ranges from 0.1 mm / s to 10 mm / s, and the contact pressure can be several tens to several hundreds of megapascals (for example, 50 - 300 MPa), which is specifically adjusted according to the geometric dimensions of the mold and the properties of the imprinting adhesive. Here, it is preferably 50000 Pa.

[0157] It should be noted that during the nanoimprinting process, since the pattern is formed by mechanical pressure extrusion, a relatively thin imprinting adhesive (i.e., residual adhesive) will remain between the imprinting template and the semiconductor substrate. The residual adhesive needs to be removed to expose the surface of the film layer that needs further processing. For example, the residual layer of the imprinting adhesive is removed by plasma etching or wet chemical treatment. Here, the method of plasma etching is preferably used.

[0158] Exemplarily, the etching process gas includes oxygen (O 2 ), or argon (Ar), and sometimes fluorinated gas (such as CF 4 ) is also used to enhance the removal effect. Here, a mixed gas of oxygen and argon is preferably used. The flow rate range of O 2 gas in the etching process gas is 20–100 sccm, preferably 60 sccm. The flow rate range of Ar gas in the etching process gas is 20–200 sccm, preferably 15 sccm. The working pressure range is 5–50 mTorr, here it is preferably 15 mToor. The radio frequency power range is 50 W–200 W, preferably 200 W. The substrate temperature range is 20 - 60 °C, here it is preferably 20 °C.

[0159] S300: Form a first electrode on the first surface; the first electrode includes a first sub - part and a second sub - part arranged in a direction away from the semiconductor substrate. The outer contour of the orthographic projection of the first sub - part on the semiconductor substrate is located within the outer contour of the orthographic projection of the second sub - part on the semiconductor substrate. The first sub - part is disposed in the first sub - hole, and the second sub - part is disposed in the second sub - hole.

[0160] See Figure 7 , after forming the first imprinting layer 110, it may include forming a first electrode 141 on the first surface 131. The first electrode 141 includes a first sub - part 1411 and a second sub - part 1412 arranged in a direction away from the semiconductor substrate 130. The outer contour of the orthographic projection of the first sub - part 1411 on the semiconductor substrate 130 is located within the outer contour of the orthographic projection of the second sub - part 1412 on the semiconductor substrate 130. The first sub - part 1411 is disposed in the first sub - hole 1111, and the second sub - part 1412 is disposed in the second sub - hole 1112. In this way, by providing the first imprinting layer 110 and providing the first through - hole 111 in the first imprinting layer 110 to limit the shape of the first electrode 141 through the first through - hole 111, it is beneficial to reduce the preparation difficulty and cost of the first electrode 141.

[0161] In some embodiments, see Figure 5and Figure 6 The solar cell 100 includes a first polar region 100a and a second polar region 100b with different polarities. A first imprinting layer 110 is formed on the first surface 131, which may include an imprinting adhesive 101a formed on the first surface 131 of the first polar region 100a and the second polar region 100b. The imprinting adhesive 101a is subjected to nanoimprinting treatment (for example, the imprinting adhesive is nanoimprinted using an imprinting template) to form a first through hole 111 in the imprinting adhesive 101a of the first polar region 100a and a second through hole 122 in the imprinting adhesive 101a of the second polar region 100b. Among them, the second through hole 122 includes a third sub-hole 1223 and a fourth sub-hole 1224 arranged in a direction away from the semiconductor substrate 130, and the outer contour of the orthographic projection of the third sub-hole 1223 on the semiconductor substrate 130 is located within the outer contour of the orthographic projection of the fourth sub-hole 1224 on the semiconductor substrate 130. The imprinting adhesive 101a located in the first polar region 100a can be used to form the first imprinting layer 110, and the imprinting adhesive 101a located in the second polar region 100b can be used to form the second imprinting layer 120. In this way, the nanoimprinting method has the advantages of low difficulty, low cost, short construction period, high yield, high resolution, etc., which can reduce the preparation difficulty of the first through hole 111 and the second through hole 122, and reduce the preparation difficulty and cost of the first imprinting layer 110 and the second imprinting layer 120.

[0162] After the imprinting adhesive is subjected to nanoimprinting treatment using an imprinting template, it may include separating the imprinting template and the imprinting adhesive. Under appropriate conditions, wait for the imprinting adhesive to cure and cool, and then separate the imprinting template from the cured imprinting adhesive to avoid damaging the formed pattern. For example, the separation speed of the imprinting template and the imprinting adhesive is 0.2 mm / s.

[0163] In some embodiments, referring to Figure 7 a first electrode 141 is formed on the first surface 131, which may include forming an electrode material layer 104a in the first through hole 111 and the second through hole 122. The electrode material layer 104a located in the first sub-hole 1111 forms a first sub-part 1411, the electrode material layer 104a located in the second sub-hole 1112 forms a second sub-part 1412, the electrode material layer 104a located in the third sub-hole 1223 forms a third sub-part 1423, and the electrode material layer 104a located in the fourth sub-hole 1224 forms a fourth sub-part 1424. Among them, the outer contour of the orthographic projection of the third sub-part 1423 on the semiconductor substrate 130 is located within the outer contour of the orthographic projection of the fourth sub-part 1424 on the semiconductor substrate 130, and the third sub-part 1423 and the fourth sub-part 1424 together form the second electrode 142. In this way, the shape of the first electrode 141 is restricted by the first through hole 111 of the first imprinting layer 110, and the shape of the second electrode 142 is restricted by the second through hole 122 of the second imprinting layer 120, which is beneficial to reducing the preparation difficulty and cost of the first electrode 141 and the second electrode 142.

[0164] Exemplarily, the electrode material layer 104a can be formed by electroplating. The material of the electrode material layer 104a can include metal materials such as Cu, Ni, Ag, Au, NiAl, Zn, Rh, Mg, etc. Due to the limitations of the first through hole 111 and the second through hole 122, the electroplating growth of the electrode material layer 104a is also restricted, and finally a "T"-shaped metal electrode adapted to the first through hole 111 and the second through hole 122 can be obtained.

[0165] Exemplarily, on the first surface 131, a nanoimprint template 200 with a three-dimensional structure is customized ( Figure 8 ) to perform nanoimprinting on the imprinting adhesive 101a, and then the residual adhesive is removed to form the first through hole 111 and the second through hole 122 in the imprinting adhesive 101a. The residual adhesive can be the residual imprinting adhesive 101a at one end of the first through hole 111 and the second through hole 122 facing the conductive material layer 107a.

[0166] Exemplarily, nanoimprinting can include photo-curing nanoimprinting, thermal-curing nanoimprinting, chemical-curing nanoimprinting, and mechanical-curing nanoimprinting.

[0167] Exemplarily, the material of the imprinting template 200 can include one of silicon, quartz glass, silicon, metal, polymer, alloy.

[0168] Exemplarily, the imprinting template 200 includes a first protrusion 210, a second protrusion 220, and a plate body 230 arranged in sequence. The first protrusion 210 and the second protrusion 220 together form a T-shaped structure. The size of the T-shaped structure can be determined according to the sizes of the first polar region 100a and the second polar region 100b. For example, the width of the first protrusion 210 (e.g., the width along the first direction X) can be 0.05 - 100 microns, and the thickness of the first protrusion 210 is 0.05 - 10 microns; the width of the second protrusion 220 (e.g., the width along the first direction X) is 0.05 - 100 microns, and the thickness of the second protrusion 220 is 0.05 - 10 microns. For example, the width of the first protrusion 210 is 5 microns, the thickness of the first protrusion 210 is 1 micron, the width of the second protrusion 220 is 40 microns, and the thickness of the second protrusion 220 is 5 microns.

[0169] See Figure 5 , in an embodiment where there is an isolation region 100c between the first polar region 100a and the second polar region 100b, forming the imprinting adhesive 101a on the first surface 131 of the first polar region 100a and the second polar region 100b can include forming the imprinting adhesive 101a on the first surface 131 of the first polar region 100a, the second polar region 100b, and the isolation region 100c. See Figure 1, after the first electrode 141 is formed on the first surface 131, it may include removing the imprinting glue 101a located in at least a partial area of the isolation region 100c, so that the first imprinting layer 110 and the second imprinting layer 120 are spaced apart, which is beneficial to reducing the short-circuit risk between the first electrode 141 and the second electrode 142. At this time, there is a gap between the positive projection of the first imprinting layer 110 on the semiconductor substrate 130 and the positive projection of the second imprinting layer 120 on the semiconductor substrate 130, and the gap is located in the isolation region 100c.

[0170] Exemplarily, the imprinting glue 101a can be prepared on the seed material layer of the first surface 131 by means of screen printing, spraying, spin coating, drop coating, scraping coating or printing (such as inkjet printing). The coating method can be selected according to the rheological properties and target film thickness of the imprinting glue, and spin coating is preferably used here.

[0171] In the embodiment of forming the imprinting glue 101a by spin coating, the rotation speed range of the spin coating process is 500 rpm - 8000 rpm, preferably 1000 rpm. The spin coating time range is 30 - 60 seconds, and 60 s is preferably used here.

[0172] In some embodiments, after the imprinting glue 101a is formed and before the imprinting glue 101a is subjected to nanoimprinting treatment, it may include soft baking the imprinting glue 101a to remove volatile substances in the imprinting glue 101a. Among them, the temperature range of the soft baking is 90 - 150 °C, preferably 110 °C here, and the soft baking time range is 30 - 60 seconds, preferably 30 s here.

[0173] Exemplarily, the thickness range of the imprinting glue 101a is 50 nm - 10 µm, which needs to be optimized according to the pattern depth and uniformity requirements.

[0174] Exemplarily, the material of the imprinting glue 101a can be a thermoplastic polymer coating (such as polymethyl methacrylate, polystyrene, polycarbonate, etc.) or a photosensitive polymer coating (such as acrylate-based polymer, epoxy resin-based photosensitive glue, etc.) or a thermosetting polymer coating (such as phenolic resin, polyimide, etc.) or a solvent volatile polymer coating (such as polyvinyl alcohol PVA, polystyrene PS, etc.) or a two-component chemical cross-linking and curing polymer coating (such as PDMS modified glue, fluorine-containing polymer, etc.). At least one of them, and epoxy resin-based photosensitive glue is preferably used here. The material of the imprinting glue 101a can be rapidly cured under ultraviolet or heating conditions.

[0175] Exemplarily, the thickness range of the imprinting glue 101a is 1 - 10 microns; for example, the thickness is 5 microns

[0176] In some embodiments, refer to Figure 3, after providing the semiconductor substrate 130 and before forming the first imprint layer 110 on the first surface 131, it may include forming a first passivation layer 151 on the first surface 131. The first passivation layer 151 may be located in the first polarity region 100a, the isolation region 100c, and the second polarity region 100b.

[0177] Exemplarily, the first passivation layer 151 may be formed by a deposition process.

[0178] Exemplarily, the deposition process may include an atomic layer deposition process (ALD for short), a physical vapor deposition process (PVD for short), a chemical vapor deposition process (CVD for short), or a reactive plasma deposition (RPD for short), etc. Other structural layers in the embodiments of the present disclosure may also be formed by deposition, which will not be elaborated herein.

[0179] In some embodiments, refer to Figure 3 , after forming the first passivation layer 151 on the first surface 131 and before forming the first imprint layer 110 on the first surface 131, it may include forming a first doped semiconductor layer 161 on the side of the first passivation layer 151 in the first polarity region 100a facing away from the semiconductor substrate 130, and forming a second doped semiconductor layer 162 on the side of the first passivation layer 151 in the second polarity region 100b facing away from the semiconductor substrate 130. For example, the first doped semiconductor layer 161 may be formed first and then the second doped semiconductor layer 162, or the second doped semiconductor layer 162 may be formed first and then the first doped semiconductor layer 161.

[0180] In some embodiments, refer to Figure 4 , after forming the first doped semiconductor layer 161 and the second doped semiconductor layer 162 and before forming the first imprint layer 110 on the first surface 131, it may include forming a conductive material layer 107a on the first surface 131. The conductive material layer 107a may be located in the first polarity region 100a, the isolation region 100c, and the second polarity region 100b. The conductive material layer 107a is located on the side of the first doped semiconductor layer 161 and the second doped semiconductor layer 162 facing away from the semiconductor substrate 130.

[0181] Exemplarily, the conductive material layer 107a may be formed on the first surface 131 by a deposition method (such as magnetron sputtering, active plasma substrate RPD, thermal evaporation, electron beam evaporation).

[0182] In some embodiments, after forming the conductive material layer 107a on the first surface 131 and before forming the first imprint layer 110 on the first surface 131, it may include forming a seed material layer on the side of the conductive material layer 107a facing away from the semiconductor substrate 130. The seed material layer may be located in the first polarity region 100a, the isolation region 100c, and the second polarity region 100b.

[0183] Exemplarily, the seed material layer may be formed on the first surface 131 by a deposition method (such as magnetron sputtering, reactive plasma deposition (RPD) on a substrate, thermal evaporation, electron beam evaporation).

[0184] Exemplarily, the material of the seed material layer includes at least one of metals such as Cu, Ni, Ag, Ti, and W. The thickness range of the seed material layer is 50 - 500 nm. For example, Cu may be used as the seed material layer with a thickness of 120 nm.

[0185] In some embodiments, referring to Figure 1 and Figure 7 , during the process of removing at least part of the imprinting glue 101a in the isolation region 100c, it may further include removing at least part of the conductive material layer 107a and the seed material layer in the isolation region 100c. The conductive material layer 107a in the first polarity region 100a forms the first conductive layer 171, and the conductive material layer 107a in the second polarity region 100b forms the second conductive layer 172. In this way, the first conductive layer 171 and the second conductive layer 172 can be separated to prevent short - circuit between the first conductive layer 171 and the second conductive layer 172. Additionally, the seed material layer in the first polarity region 100a forms the first seed layer, and the seed material layer in the second polarity region 100b forms the second seed layer. In this way, the first seed layer and the second seed layer can be separated to prevent short - circuit between the first seed layer and the second seed layer.

[0186] Exemplarily, in the isolation region 100c, at least part of the imprinting glue 101a, the conductive material layer 107a, and the seed material layer may be removed by laser direct writing etching, wet etching, or dry etching to break the imprinting glue 101a, the conductive material layer 107a, and the seed material layer. For example, in the implementation mode of laser etching, the laser pulse time may be one of picosecond laser and femtosecond laser, and the laser wavelength range is one of ultraviolet and green light. For example, the laser may be an ultraviolet femtosecond laser. The beam profile of the laser spot is one of Gaussian light and flat - top light, such as flat - top light. The spot size of the laser is 3 - 10 microns, for example, the spot size is 5 microns.

[0187] In some embodiments, referring to Figure 3, The method for preparing the solar cell 100 may further include sequentially forming a second passivation layer 152, a third passivation layer 153, and an antireflection layer 154 on the second surface 132.

[0188] It should be noted that in the nanoimprinting technology, residual glue is a common and challenging problem. Especially in the imprinting process of high resolution and complex structures, the control of the residual glue thickness directly affects the clarity, functionality, and repeatability of the final pattern. Excessive residual glue will cause pattern deformation, defects, or incomplete transfer. Especially for the production of solar cells, the lower the residual glue thickness, the lower the processing cost. At the same time, the back surface of the solar cell is usually polished with an alkaline solution and has a certain roughness, and it is relatively easy to cause uneven filling in some areas during the imprinting process. For the traditional imprinting process, the present application combines ultrasonic technology with nanoimprinting to optimize and reduce the residual glue thickness of nanoimprinting through the mechanical vibration of ultrasonic waves. The high-frequency mechanical vibration generated by ultrasonic waves (usually in the range of 20 - 100 kHz) can generate tiny pressure fluctuations on liquid or solid thin film materials. These microwave vibrations can help break the adhesion of the part of the imprinting glue in contact with the imprinting template on the surface of the imprinting glue, thereby reducing the residue of the imprinting glue when the imprinting template is demolded. During the nanoimprinting process, when ultrasonic vibration is applied, it can prompt the molecules inside the imprinting glue to rearrange, making it form a more uniform and dense thin film during the curing process after being imprinted by the imprinting template. Ultrasonic waves promote the fluidity of the imprinting glue, making the glue layer evenly distributed on the surface of the semiconductor substrate, thereby reducing uneven or overly thick imprinting glue.

[0189] In some embodiments, after the imprinting glue is formed on the first surface of the first polar region and the second polar region, before the nanoimprinting treatment of the imprinting glue, it may include performing a first ultrasonic treatment on the imprinting glue. In this way, a preliminary homogenization treatment of the imprinting glue is performed using an ultrasonic vibration device. After the first ultrasonic treatment, the imprinting template is directly imprinted onto the imprinting glue. Due to the early intervention of the ultrasonic wave action, the uniformity and adhesion of the imprinting glue are optimized, and the imprinting glue can complete a more delicate pattern transfer at a lower pressure.

[0190] Exemplarily, the ultrasonic frequency range of the first ultrasonic treatment is 20 - 100 kHz. The ultrasonic power range of the first ultrasonic treatment is 5 - 30 W / cm². The time range of the first ultrasonic treatment is 30 - 60 seconds.

[0191] In some embodiments, separating the imprint template and the imprint resist may include separating the imprint template and the imprint resist and simultaneously performing a second ultrasonic treatment on the cured imprint resist and the imprint template. In this way, during the process of separating the imprint template and the imprint resist, ultrasonic vibration can continue to be applied through the second ultrasonic treatment. The effect of the ultrasonic wave can reduce the adhesion between the imprint template and the imprint resist, promote the smooth demolding of the imprint resist, accelerate the demolding process, and at the same time reduce the thickness of the residual glue. Among them, Figure 10 and Figure 11 show a T-shaped structure formed on the imprint resist after the imprint template is separated from the imprint resist.

[0192] Exemplarily, the ultrasonic vibration frequency range of the second ultrasonic treatment is 20 - 50 kHz. The time range of the second ultrasonic treatment is 10 - 30 seconds.

[0193] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0194] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate having a first surface and a second surface arranged opposite to each other; A first embossing layer, disposed on the first surface; A first electrode, disposed on the first surface; The first electrode comprises a first sub-portion and a second sub-portion arranged in a direction away from the semiconductor substrate, wherein an outer contour of an orthographic projection of the first sub-portion on the semiconductor substrate is located within an outer contour of an orthographic projection of the second sub-portion on the semiconductor substrate; Among them, a first through hole is provided on the first imprinted layer, and the first through hole penetrates the first imprinted layer along the thickness direction of the semiconductor substrate. The first through hole includes a first sub-hole and a second sub-hole arranged in a direction away from the semiconductor substrate. The outer contour of the orthographic projection of the first sub-hole on the semiconductor substrate is located within the outer contour of the orthographic projection of the second sub-hole on the semiconductor substrate. The first sub-portion is arranged in the first sub-hole, and the second sub-portion is arranged in the second sub-hole.

2. The solar cell according to claim 1, characterized in that The solar cell comprises a first polarity region and a second polarity region with different polarities, and the first electrode and the first imprinted layer are both located in the first polarity region; The solar cell includes a second electrode arranged on the first surface, and the second electrode is located in the second polarity zone; the second electrode includes a third sub-section and a fourth sub-section arranged in a direction away from the semiconductor substrate, and the orthographic projection outer contour of the third sub-section on the semiconductor substrate is located within the orthographic projection outer contour of the fourth sub-section on the semiconductor substrate.

3. The solar cell according to claim 2, characterized in that: The solar cell further comprises a second imprinted layer disposed on the first surface, wherein the second imprinted layer is located in the second polarity region; A second through hole is provided on the second imprinted layer, and the second through hole penetrates the second imprinted layer along the thickness direction of the semiconductor substrate. The second through hole includes a third sub-hole and a fourth sub-hole arranged in a direction away from the semiconductor substrate, and the orthographic projection outer contour of the third sub-hole on the semiconductor substrate is located within the orthographic projection outer contour of the fourth sub-hole on the semiconductor substrate; the third sub-portion is arranged in the third sub-hole, and the fourth sub-portion is arranged in the fourth sub-hole.

4. The solar cell according to claim 3, characterized in that: An isolation region is provided between the first polarity region and the second polarity region; A gap is provided between an orthographic projection of the first imprinted layer on the semiconductor substrate and an orthographic projection of the second imprinted layer on the semiconductor substrate, and the gap is located in the isolation region.

5. The solar cell according to claim 3 or 4, characterized in that: The minimum dimension of the first sub-portion along a direction perpendicular to the thickness of the semiconductor substrate ranges from 50 nm to 100 μm; and / or, The minimum dimension of the second sub-portion along a direction perpendicular to the thickness of the semiconductor substrate ranges from 50 nm to 100 μm; and / or, The size of the first sub-portion along the thickness direction of the semiconductor substrate ranges from 50 nm to 10 μm; and / or, The size of the second sub-portion along the thickness direction of the semiconductor substrate ranges from 50 nm to 10 μm; The minimum dimension of the third sub-portion along a direction perpendicular to the thickness of the semiconductor substrate ranges from 50 nm to 100 μm; and / or, The minimum dimension of the fourth sub-portion along a direction perpendicular to the thickness of the semiconductor substrate ranges from 550 nm to 100 μm; and / or, The size of the third sub-portion along the thickness direction of the semiconductor substrate ranges from 50 nm to 10 μm; and / or, The size of the fourth sub-portion along the thickness direction of the semiconductor substrate ranges from 50 nm to 10 μm; The solar cell comprises a first conductive layer and a first seed layer stacked in a direction away from the semiconductor substrate, wherein the first conductive layer and the first seed layer are both located in the first polarity region and between the first imprinted layer and the semiconductor substrate; and / or, The solar cell includes a second conductive layer and a second seed layer stacked in a direction away from the semiconductor substrate. The second conductive layer and the second seed layer are both located in the second polarity region and between the second imprinted layer and the semiconductor substrate.

6. A photovoltaic module, characterized in that: A solar cell comprising any one of claims 1 to 5.

7. A method for preparing a solar cell, characterized in that: include: Providing a semiconductor substrate; the semiconductor substrate has a first surface and a second surface arranged opposite to each other; forming a first embossed layer on the first surface; A first through hole is provided on the first imprinting layer, the first through hole penetrates the first imprinting layer along the thickness direction of the semiconductor substrate, the first through hole comprises a first sub-hole and a second sub-hole arranged in a direction away from the semiconductor substrate, and an orthographic projection outer contour of the first sub-hole on the semiconductor substrate is located within an orthographic projection outer contour of the second sub-hole on the semiconductor substrate; forming a first electrode on the first surface; The first electrode includes a first sub-portion and a second sub-portion arranged in a direction away from the semiconductor substrate, wherein an outer contour of an orthographic projection of the first sub-portion on the semiconductor substrate is located within an outer contour of an orthographic projection of the second sub-portion on the semiconductor substrate; the first sub-portion is arranged in the first sub-hole, and the second sub-portion is arranged in the second sub-hole.

8. The method for preparing a solar cell according to claim 7, characterized in that: The solar cell comprises a first polarity region and a second polarity region having different polarities; The forming of the first embossing layer on the first surface comprises: forming an embossed adhesive on the first surface of the first polarity region and the second polarity region; The imprint glue is subjected to nanoimprint processing by using an imprint template to form a first through hole in the imprint glue in the first polarity region, and a second through hole in the imprint glue in the second polarity region; the second through hole comprises a third sub-hole and a fourth sub-hole arranged in a direction away from the semiconductor substrate, and an orthographic projection outer contour of the third sub-hole on the semiconductor substrate is located within an orthographic projection outer contour of the fourth sub-hole on the semiconductor substrate; the imprint glue located in the first polarity region forms the first imprint layer, and the imprint glue located in the second polarity region forms the second imprint layer; The imprint template and the imprint glue are separated.

9. The method for preparing a solar cell according to claim 8, characterized in that: The forming of the first electrode on the first surface comprises: An electrode material layer is formed in the first through hole and the second through hole; the electrode material layer located in the first sub-hole forms a first sub-portion, the electrode material layer located in the second sub-hole forms a second sub-portion, the electrode material layer located in the third sub-hole forms a third sub-portion, and the electrode material layer located in the fourth sub-hole forms a fourth sub-portion; the outer contour of the orthographic projection of the third sub-portion on the semiconductor substrate is located within the outer contour of the orthographic projection of the fourth sub-portion on the semiconductor substrate, and the third sub-portion and the fourth sub-portion together form a second electrode.

10. The method for preparing a solar cell according to claim 9, characterized in that: An isolation region is provided between the first polarity region and the second polarity region; The forming of the embossed adhesive on the first surface of the first polarity region and the second polarity region comprises: forming the embossed adhesive on the first polarity region, the second polarity region and the first surface of the isolation region; After forming the first electrode on the first surface, the method comprises: removing at least part of the imprint glue located in the isolation region; a gap is provided between the orthographic projection of the first imprint layer on the semiconductor substrate and the orthographic projection of the second imprint layer on the semiconductor substrate, and the gap is located in the isolation region; and / or, After forming the embossed adhesive on the first surface of the first polar region and the second polar region, before performing nanoimprinting treatment on the embossed adhesive using an imprint template, the method includes: performing a first ultrasonic treatment on the embossed adhesive; and / or, The nanoimprinting treatment of the imprint adhesive by using the imprint template includes: nanoimprinting the imprint adhesive and simultaneously curing the imprint adhesive; or, after the nanoimprinting treatment of the imprint adhesive by using the imprint template, before the separation of the imprint template and the imprint adhesive includes: curing the imprint adhesive; The separating the imprint template and the imprint glue comprises: separating the imprint template and the imprint glue, and simultaneously performing a second ultrasonic treatment on the solidified imprint glue and the imprint template.

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