Crystalline silicon solar cell with tunneling oxide layer structure and preparation method of crystalline silicon solar cell

Abstract

The invention relates to the technical field of solar cells, in particular to a crystalline silicon solar cell with a tunneling oxide layer structure and a preparation method thereof, and the crystalline silicon solar cell comprises a suede structure, a boron diffusion layer, an aluminum oxide layer and an anti-reflection film which are sequentially stacked on the front side; the tunneling oxide layer, the phosphorus-doped polycrystalline silicon layer and the anti-reflection film are sequentially stacked on the back surface; a complete tunneling oxide layer and a complete phosphorus-doped polycrystalline silicon layer are reserved in a back metallization region, and a non-metallization region is etched to form a tower footing structure; according to the invention, by optimizing the structural design of the back tunneling oxide layer and the phosphorus-doped polycrystalline silicon layer and combining laser and wet processing processes, the contradiction between the thickness of the polycrystalline silicon layer and parasitic absorption and the balance problem between the area of a graphical region and a fill factor in the prior art are effectively solved, so that the conversion efficiency of the cell is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a crystalline silicon solar cell with a tunneling oxide layer structure and a preparation method thereof. Background Art

[0002] Crystalline silicon solar cells are the mainstream products in the current photovoltaic market, and the improvement of their conversion efficiency has always been the focus of research. In recent years, polycrystalline silicon passivation contact technology (poly-Si passivation contact technology) has become one of the key technologies to improve the efficiency of crystalline silicon solar cells due to its excellent passivation effect and carrier transport characteristics. This technology introduces a tunneling silicon oxide layer and a doped polysilicon layer on the back of the cell to form a passivation contact structure, which effectively reduces carrier recombination and improves the open circuit voltage (Voc) and fill factor (FF) of the cell.

[0003] However, the existing polysilicon passivation contact technology still faces some technical bottlenecks in practical applications. First, in order to ensure good contact with the back metallization paste, the thickness of the doped polysilicon film usually needs to be more than 90nm, or even higher. Too thick polysilicon film will cause parasitic absorption of long-wave light, thereby reducing the long-wave response and bifaciality of the battery, restricting the further improvement of the battery conversion efficiency. Secondly, although the parasitic absorption problem can be significantly improved by thinning the polysilicon layer, when the polysilicon layer is thinned to a certain thickness, the back slurry will penetrate the polysilicon layer during the sintering process, affecting the integrity of the tunneling oxide layer, resulting in a decrease in the passivation performance of the battery.

[0004] In order to solve the above problems, laser and wet processing are usually used in the prior art to remove polysilicon in non-metallized areas to reduce parasitic absorption. However, there is a contradiction in this method: the area of ​​the patterned area is proportional to the current gain, but an overly large patterned area will increase the lateral transmission path of the carriers and lengthen the carrier diffusion path, thereby reducing the fill factor (FF), and ultimately affecting the overall efficiency of the battery. Therefore, how to remove as much polysilicon as possible from the non-metallic area while ensuring the passivation and contact performance of the back metal area, reduce the parasitic absorption of long-wave light, and keep the FF unchanged, has become a technical problem that needs to be solved urgently by those skilled in the art.

[0005] In the prior art, an excellent passivation effect is achieved by tunneling a silicon oxide layer and a doped polysilicon layer. The passivation mechanism mainly comes from three aspects: the chemical passivation of the silicon oxide interface, the field passivation of doped polysilicon, and the mismatch between the valence bands of polysilicon and silicon that blocks the transmission of holes. However, in practical applications, there is still a contradiction between the thickness of the polysilicon layer and parasitic absorption, as well as a balance between the area of ​​the patterned region and FF.

[0006] In summary, the parasitic absorption problem caused by the overly thick polysilicon layer in the prior art, as well as the impact on the passivation performance after thinning the polysilicon layer, limit the further improvement of the conversion efficiency of crystalline silicon solar cells. Therefore, there is an urgent need for a crystalline silicon solar cell with a tunneling oxide layer structure that can effectively reduce the polysilicon in the non-metal region, reduce parasitic absorption, and maintain a high fill factor while ensuring the passivation and contact performance of the back metal region, thereby maximizing the cell efficiency. Summary of the Invention

[0007] To solve the above problems, the present invention provides a crystalline silicon solar cell with a tunneling oxide layer structure and a preparation method thereof.

[0008] In the first aspect, the present invention provides a crystalline silicon solar cell with a tunneling oxide layer structure, including the following steps:

[0009] S1. Select an N-type monocrystalline silicon wafer as the substrate, and perform single-sided texturing treatment on the front surface of the silicon substrate to form a textured surface;

[0010] S2. Perform front boron diffusion on the front surface of the silicon substrate to form a front boron diffusion layer;

[0011] S3. Etch and remove the borosilicate glass layer on the back surface of the silicon substrate, and perform alkaline polishing on the back surface;

[0012] S4. Deposit a back tunneling oxide layer on the back surface of the silicon substrate;

[0013] S5. Perform phosphorus doping on the back tunneling oxide layer to form a phosphorus-doped polysilicon layer;

[0014] S6. Use a laser to locally process the non-metallized area on the back surface of the silicon substrate, and retain the phosphorus-doped polysilicon layer and the back tunneling oxide layer;

[0015] S7. Use chain pickling to remove the phosphorus-silicate glass layer deposited on the front and side surfaces of the silicon wafer and expose the deposited polysilicon layer;

[0016] S8. Use trough alkaline cleaning to remove the deposited polysilicon layer, etch the remaining phosphorus-doped polysilicon layer and tunneling oxide layer in the non-metallized area on the back surface, and back-etch the N-type silicon substrate to form a tower base;

[0017] S9. Use atomic vapor deposition to prepare aluminum oxide on the front surface of the silicon wafer to form a front aluminum oxide layer;

[0018] S10. Use plasma-enhanced chemical vapor deposition to form a tunneling oxide layer / phosphorus-doped polysilicon layer on the back surface of the silicon substrate;

[0019] S11. Deposit antireflection films on the front and back surfaces of the silicon wafer respectively, and form metal electrodes in the preset electrode areas;

[0020] S12. Anneal the tunneling oxide layer / phosphorus-doped polysilicon layer, and make the metal electrode contact with the silicon wafer to obtain a crystalline silicon solar cell.

[0021] Preferably, in the step S5, the thickness of the phosphorus-doped polysilicon layer is 90 - 150 nm.

[0022] Preferably, in the step S5, the sheet resistance of the back phosphorus-doped polysilicon layer is 50 - 200 Ω / □, and the sheet resistance of the front boron diffusion layer is 80 - 150 Ω / □.

[0023] Preferably, in the step S6, the wavelength of the laser is 355 - 1064 nm, the energy density is 0.5 - 3 J / cm 2 , and the scanning speed is 1 - 10 m / s.

[0024] Preferably, in the step S8, the etching depth of the N-type silicon substrate is 0 - 5 μm, and the tower base depth is 8 - 30 μm.

[0025] Preferably, in the step S8, the trough-type alkali washing uses a sodium hydroxide solution with a concentration of 0.5 - 5%, the temperature is 40 - 80 °C, and the treatment time is 30 - 300 s.

[0026] Preferably, in the step S10, the thickness of the tunneling oxide layer / phosphorus-doped polysilicon layer is 10 - 15 nm.

[0027] Preferably, in the step S10, the doping concentration of the phosphorus-doped polysilicon layer is 1*10 19 -1*10 21 cm -3 .

[0028] Preferably, in the step S11, the antireflection film includes at least one of a silicon nitride layer and a silicon oxide layer, and the thickness is 70 - 120 nm.

[0029] In the second aspect, the present invention provides a crystalline silicon solar cell with a tunneling oxide layer structure, which is obtained by using the preparation method of the crystalline silicon solar cell with the tunneling oxide layer structure as described in the first aspect.

[0030] In the present invention, a crystalline silicon solar cell with a tunneling oxide layer structure includes:

[0031] A textured structure, a boron diffusion layer, an alumina layer, and an antireflection film stacked in sequence on the front side;

[0032] A tunneling oxide layer, a phosphorus-doped polysilicon layer, and an antireflection film stacked in sequence on the back side;

[0033] The back metallization region retains the complete tunneling oxide layer and the phosphorus-doped polysilicon layer. The non-metallized region is etched to form a tower base structure, and the thickness of the silicon substrate is reduced by 0 - 5 μm.

[0034] The metal electrode is a silver electrode or a copper electrode. The electrode width is 10 - 50 μm, and the height is 5 - 20 μm.

[0035] The conversion efficiency of the solar cell is ≥24.5%, and the open-circuit voltage is ≥720 mV.

[0036] In a second aspect, the present invention provides a UV solar cell, which is prepared by using the preparation process of the silicon wafer with an alumina thin film as described in the first aspect.

[0037] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0038] 2. By optimizing the structural design of the back tunneling oxide layer and the phosphorus-doped polysilicon layer, and combining the laser and wet treatment processes, the present invention effectively solves the contradiction between the thickness of the polysilicon layer and parasitic absorption in the prior art, as well as the balance problem between the area of the patterned region and the fill factor, thereby significantly improving the conversion efficiency of the battery.

[0039] 3. By controlling the thickness range of the phosphorus-doped polysilicon layer and combining the laser and wet treatment to remove the polysilicon layer in the non-metallized region, the present invention significantly reduces the parasitic absorption of the back polysilicon layer to long-wavelength light, improves the long-wavelength response and bifaciality of the battery, thereby enhancing the overall photoelectric conversion efficiency of the battery.

[0040] 4. The combined structure of the back tunneling oxide layer and the phosphorus-doped polysilicon layer of the present invention provides excellent passivation effects, effectively reducing carrier recombination. By controlling the thickness and phosphorus doping concentration of the tunneling oxide layer and the phosphorus-doped polysilicon layer, good contact performance and passivation performance of the back metallization region are ensured, thereby significantly increasing the open-circuit voltage of the battery.

[0041] 5. The present invention adopts the laser local treatment technology and the trough alkaline cleaning process to accurately remove the polysilicon layer in the non-metallized region, reducing the lateral transport path of carriers and avoiding the reduction of FF. At the same time, by optimizing the area of the patterned region, parasitic absorption is reduced while maintaining a high fill factor.

[0042] 6. The front alumina layer prepared by atomic vapor deposition and the back tunneling oxide layer / phosphorus-doped polysilicon layer formed by plasma-enhanced chemical vapor deposition of the present invention further enhance the passivation effect and carrier transport characteristics of the battery, and the introduction of the antireflection film effectively reduces the surface reflectivity and improves the light absorption efficiency. Description of the Drawings

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0044] Figure 1 It is a process flow chart of a preparation method for a crystalline silicon solar cell with a tunneling oxide layer structure. Detailed implementation manners

[0045] The following will clearly and completely describe the technical solutions of the present invention in combination with specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0046] Embodiment 1

[0047] This embodiment provides a preparation method for a crystalline silicon solar cell with a tunneling oxide layer structure, including the following steps:

[0048] S1. Select an N-type monocrystalline silicon wafer (with a thickness of 170 μm) as the substrate, and perform single-sided texturing on the front side through an acidic solution to form a pyramid texture surface (with a height of 1.2 μm);

[0049] S2. Put the textured silicon wafer into a diffusion furnace, introduce boron tribromide, and perform front-side boron diffusion at a temperature of 900 °C to form a 0.5-μm front-side boron diffusion layer, with the sheet resistance controlled at 100 Ω / □;

[0050] S3. Take out the silicon wafer, use a hydrofluoric acid solution to etch and remove the boron-silicate glass layer on the back side, and then perform alkaline polishing on the back side in a 5% potassium hydroxide solution at 50 °C to obtain a smooth surface to remove the surface damage layer;

[0051] S4. Put the silicon wafer into a CVD device, introduce oxygen and silane at a temperature of 850 °C, and deposit a back-side tunneling oxide layer on the back side of the silicon wafer, with the thickness controlled at 10 nm;

[0052] S5. On the back-side tunneling oxide layer, introduce phosphine and silane through a PECVD device at a temperature of 400 °C to form a phosphorus-doped polysilicon layer with a thickness of 150 nm and a sheet resistance of 80 Ω / □;

[0053] S6. Use a wavelength of 532 nm and an energy density of 1.8 J / cm 2, a laser with a scanning speed of 5 m / s is used to locally process the non-metallized area on the back of the silicon wafer, and the phosphorus-doped polysilicon layer and the back tunneling oxide layer are retained;

[0054] S7. Place the silicon wafer into a chain pickling equipment, and use pickling solution (HF:HNO 3 =1:3) to remove the phosphorus-silicate glass layer deposited on the front and side surfaces of the silicon wafer, and expose the deposited polysilicon layer.

[0055] S8. Place the silicon wafer into a tank-type alkali cleaning equipment, and use a sodium hydroxide solution with a concentration of 3% to process it at a temperature of 60 °C for 200 s to remove the deposited polysilicon layer, etch the remaining phosphorus-doped polysilicon layer and the tunneling oxide layer in the non-metallized area on the back, and back-etch the N-type silicon substrate to form a tower base structure. The etching depth of the N-type silicon substrate is 3 μm, and the tower base depth is 15 μm;

[0056] S9. Use atomic vapor deposition method to prepare an alumina layer on the front of the silicon wafer, with a thickness of 70 - 120 nm;

[0057] S10. Form a tunneling oxide layer / phosphorus-doped polysilicon layer on the back of the silicon substrate through a PECVD equipment, with a thickness of 10 nm, and the doping concentration of the phosphorus-doped polysilicon layer is 1*10 20 cm -3 ;

[0058] S11. Deposit an antireflection film on the front and back of the silicon wafer respectively. The antireflection film includes at least one of a silicon nitride layer and a silicon oxide layer, with a thickness of 80 nm; form a metal electrode in the preset electrode area. The metal electrode is a silver electrode or a copper electrode, with an electrode width of 30 μm and a height of 12 μm;

[0059] S12. Place the prepared cell into an annealing furnace and perform annealing treatment in a nitrogen atmosphere. The annealing temperature is 450 °C and the time is 30 min. The tunneling oxide layer / phosphorus-doped polysilicon layer is in good contact with the silicon wafer, and a crystalline silicon solar cell is obtained.

[0060] This embodiment also provides a crystalline silicon solar cell with a tunneling oxide layer structure. The conversion efficiency of the crystalline silicon solar cell with a tunneling oxide layer structure is 25.1%, the open-circuit voltage is 735 mV, and the fill factor is 82.3%.

[0061] Embodiment 2

[0062] Compared with Embodiment 1, in steps S5 and S10, the thickness of the phosphorus-doped polysilicon layer is 90 nm, the doping concentration of the phosphorus-doped polysilicon layer is 1*10 21 cm -3 , and the sheet resistance of the phosphorus-doped polysilicon layer is 50 Ω / □; in step S8, the alkali cleaning time is shortened to 100 s, the tower base depth is 8 μm, and the rest is the same as Embodiment 1.

[0063] Comparative Example 1

[0064] Compared with Example 1, steps S4 and S10 are omitted, and a phosphorus-doped polysilicon layer is deposited on the back; in step 8, only the phosphorus-doped layer is etched, and no tower base structure is formed, and the rest is the same as Example 1.

[0065] Comparative Example 2

[0066] Compared with Example 1, in step S6, a 1090 nm laser, an energy density of 4 J / cm 2 , and a scanning speed of 12 m / s are used, and the rest is the same as Example 1.

[0067] Comparative Example 3

[0068] Compared with Example 1, in step S8, full back etching is used, the tunneling oxide layer and the polysilicon layer are cancelled, and there is no selective etching, and the rest is the same as Example 1.

[0069] Comparative Example 4

[0070] Compared with Example 1, the thickness of the phosphorus-doped polysilicon layer is 200 nm, and a sodium hydroxide solution with a concentration of 8% is used for trough alkaline cleaning.

[0071] The conversion efficiency, open circuit voltage, fill factor, quasi-steady state photoconductivity test, and reflectivity test (based on the GB / T6495 standard) are carried out on Example 2 and Comparative Examples 1-4;

[0072] Test conditions:

[0073] Light source: AM1.5G spectrum, light intensity 1000 W / m 2 , temperature 25°C ± 1°C

[0074] Test equipment: IV tester (Keysight B2900A) combined with a solar simulator (AAA-level uniformity)

[0075] Calibration: Use a standard cell (NREL certified) to calibrate the system error

[0076] The test results are shown in Table 1

[0077] Table 1

[0078]

[0079] The test results show that:

[0080] Compared Example 1 with Example 1

[0081] The back surface recombination rate of Comparative Example 1 (without tunneling oxide layer) is as high as 85 cm / s, resulting in a 11.2% decrease in conversion efficiency, indicating that the tunneling oxide layer significantly inhibits carrier recombination and is the core structure for improving open-circuit voltage and fill factor.

[0082] When comparing Example 1 with Example 2

[0083] The sheet resistance of Example 2 is reduced to 50 Ω / □, but the recombination rate increases to 18 cm / s, indicating that an overly thin polysilicon layer may not be able to fully passivate defects, and a high doping concentration may introduce lattice distortion.

[0084] When comparing Example 1 with Comparative Example 2

[0085] The reflectivity of Comparative Example 2 drops to 91%, and the recombination rate increases to 42 cm / s, indicating that the penetration depth of long-wavelength laser is insufficient, resulting in uneven local treatment and damage to the tunneling oxide layer / polysilicon interface.

[0086] When comparing Example 1 with Comparative Example 3

[0087] The reflectivity of Comparative Example 3 (full back etching without tunneling layer) drops suddenly to 82%, and the recombination rate soars to 110 cm / s, indicating that the tower base structure and selective etching are crucial for light trapping and passivation effects.

[0088] When comparing Example 1 with Comparative Example 4

[0089] The recombination rate of Comparative Example 4 increases to 63 cm / s, and the reflectivity drops to 89%, indicating that an overly thick polysilicon layer may increase parasitic absorption, and high-concentration alkali washing leads to excessive etching of the silicon substrate.

[0090] In summary,

[0091] The use of SiO 2 / Poly-Si stack to achieve carrier selective transport, with a recombination rate < 20 cm / s, and the Al 2 O 3 / SiN x passivation system controls the front surface recombination rate below 15 cm / s, laser micro-nano processing improves the back reflectivity to 95%, the light utilization rate is increased by 7%, and the optimized ranges of the phosphorus layer thickness, laser energy density, and alkali solution concentration ensure the balance of yield and efficiency.

[0092] The above further describes the present invention with the aid of specific embodiments. However, it should be understood that this specific description should not be construed as limiting the essence and scope of the present invention. Various modifications made by those of ordinary skill in the art to the above embodiments after reading this specification all fall within the scope protected by the present invention.

Claims

1. A method for preparing a crystalline silicon solar cell with a tunneling oxide layer structure, characterized in that: The following steps are involved: S1, select an N-type single crystal silicon wafer as a substrate, perform a single-sided texturing treatment on the front side of the silicon substrate to form a velvet surface; S2, performing front boron diffusion on the front side of the silicon substrate to form a front boron diffusion layer; S3, etching the back side of the silicon substrate to remove the borosilicate glass layer, and performing alkali polishing on the back side; S4, depositing a back tunneling oxide layer on the back side of the silicon substrate; S5, performing phosphorus doping on the back tunnel oxide layer to form a phosphorus doped polysilicon layer; S6, using laser to locally process the non-metallized area on the back side of the silicon substrate, retaining the phosphorus-doped polysilicon layer and the back side tunneling oxide layer; S7, using chain pickling to remove the phosphorus-silicon glass layer on the front and side surfaces of the silicon wafer, and exposing the polysilicon layer; S8, using a tank-type alkali wash to remove the plated polysilicon layer, etching the phosphorus-doped polysilicon layer and the tunnel oxide layer remaining in the non-metallized area on the back, and etching back the N-type silicon substrate to form a tower base; S9, preparing aluminum oxide on the front side of the silicon wafer by using an atomic vapor deposition method to form a front aluminum oxide layer; S10, forming a tunneling oxide layer / phosphorus-doped polysilicon layer on the back side of the silicon substrate by plasma enhanced chemical vapor deposition; S11, depositing anti-reflection films on the front and back sides of the silicon wafer, respectively, and forming metal electrodes in a preset electrode region; S12, annealing the tunneling oxide layer / phosphorus-doped polysilicon layer, contacting the metal electrode with the silicon wafer, and manufacturing a crystalline silicon solar cell.

2. The method for preparing a crystalline silicon solar cell with a tunneling oxide layer structure according to claim 1, characterized in that: In the step S5, the thickness of the phosphorus-doped polysilicon layer is 90-150 nm.

3. The method for preparing a crystalline silicon solar cell with a tunneling oxide layer structure according to claim 1, characterized in that: In the step S5, the square resistance of the back phosphorus-doped polysilicon layer is 50-200Ω / □, and the square resistance of the front boron diffusion layer is 80-150Ω / □.

4. The method for preparing a crystalline silicon solar cell with a tunneling oxide layer structure according to claim 1, characterized in that: In step S6, the wavelength of the laser is 355-1064nm, and the energy density is 0.5-3J / cm 2 , scanning speed is 1-10m / s.

5. The method for preparing a crystalline silicon solar cell with a tunneling oxide layer structure according to claim 1, characterized in that: In the step S8, the etching depth of the N-type silicon substrate is 0-5 μm, and the depth of the tower base is 8-30 μm.

6. The method for preparing a crystalline silicon solar cell with a tunneling oxide layer structure according to claim 1, characterized in that: In step S8, the tank-type alkali washing uses a sodium hydroxide solution with a concentration of 0.5-5%, a temperature of 40-80° C., and a treatment time of 30-300 seconds.

7. The method for preparing a crystalline silicon solar cell with a tunneling oxide layer structure according to claim 1, characterized in that: In the step S10, the thickness of the tunneling oxide layer / phosphorus-doped polysilicon layer is 10-15 nm.

8. The method for preparing a crystalline silicon solar cell with a tunneling oxide layer structure according to claim 1, characterized in that: In step S10, the doping concentration of the phosphorus-doped polysilicon layer is 1*10 19 -1*10 21 cm -3 .

9. The method for preparing a crystalline silicon solar cell with a tunneling oxide layer structure according to claim 1, characterized in that: In the step S11, the anti-reflection film includes at least one of a silicon nitride layer and a silicon oxide layer, and has a thickness of 70-120 nm.

10. A crystalline silicon solar cell with a tunneling oxide layer structure, characterized in that: The invention is prepared by the method for preparing a crystalline silicon solar cell with a tunneling oxide layer structure as described in any one of claims 1 to 9.

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