Battery piece preparation method and battery piece

Abstract

The embodiment of the invention provides a preparation method of a battery piece and the battery piece, and the preparation method of the battery piece comprises the following steps: depositing a first passivation layer on the back surface of a silicon substrate, and removing the first passivation layer in a first region and a second region of the silicon substrate through laser, and sequentially depositing a tunneling oxide layer and a polycrystalline silicon layer on the back surfaces of the silicon substrate and the first passivation layer. According to the method, after the first passivation layer is deposited on the back face of the silicon substrate, the first passivation layer in the first area and the first passivation layer in the second area of the silicon substrate are independently removed through the laser, and the first passivation layer which is not removed through the laser can cover the isolation area of the silicon substrate; the first passivation layer on the isolation region can play an isolation role in advance to isolate the first region and the second region, and the phenomenon of local electric leakage caused by fusion of the doped polycrystalline silicon layers of the first region and the second region is avoided, so that the safety of the battery piece in the preparation and subsequent use processes can be improved.

Description

Technical Field

[0001] This application relates to the technical field of photovoltaic cells, and specifically relates to a method for preparing a cell and a cell. Background Art

[0002] TBC cells can combine the tunneling oxide layer technology of TOPCon cells and the advantages of the back-side arranged electrodes of IBC cells. The passivation effect and open-circuit voltage are significantly improved, and economy can be achieved while realizing higher cell conversion efficiency. There is a risk of short circuit between the P region and the N region of TBC cells. Therefore, an isolation region needs to be set between the P region and the N region. In the process of preparing TBC cells, it is usually to deposit and dope a polysilicon layer first, and then process the isolation region by laser grooving and alkaline etching. However, during the doping process of the polysilicon layer, the P-type region and the N-type region are prone to fusion, resulting in leakage. Summary of the Invention

[0003] In view of this, this application provides a method for preparing a cell and a cell, which is conducive to solving the technical problem of easy leakage of cells in the prior art.

[0004] In a first aspect, an embodiment of this application provides a method for preparing a cell. The method for preparing the cell includes: Preparing a silicon substrate, where the silicon substrate includes a first region, a second region, and an isolation region for separating the first region and the second region; Depositing a first passivation layer on the back surface of the silicon substrate; Laser removing the first passivation layer on the first region and the second region of the silicon substrate; Sequentially depositing a tunneling oxide layer and a polysilicon layer on the back surface of the silicon substrate and the first passivation layer; Performing a doping treatment on the polysilicon layer to convert the polysilicon layer into a doped polysilicon layer, and the doped polysilicon layer in the first region has the opposite polarity to the doped polysilicon layer in the second region; Sequentially removing the polysilicon layer, the tunneling oxide layer, and the first passivation layer in the isolation region.

[0005] In this embodiment, after depositing a first passivation layer on the back surface of the silicon substrate, the first passivation layer in the first region and the second region of the silicon substrate is separately removed by laser. The first passivation layer that is not removed by laser can cover the isolation region of the silicon substrate. When subsequent steps of depositing and doping a polysilicon layer are carried out, the first passivation layer on the isolation region can play a pre - isolation role, isolating the first region and the second region, and avoiding the mutual influence and fusion between the doped polysilicon layers formed in the first region and the second region in subsequent steps, which may lead to local leakage. Thus, the safety during the preparation and subsequent use of the battery cell can be improved. Compared with the prior art method of first depositing and doping a polysilicon layer and then laser - grooving, the battery cell preparation method provided by the embodiment of the present application first sets the first passivation layer to separate the first region and the second region, avoiding the mutual influence between the first region and the second region. While significantly improving the preparation and use safety of the battery cell, it also has the advantages of simple operation and easy implementation.

[0006] In a specific embodiment, the step of depositing the first passivation layer on the back surface of the silicon substrate specifically includes: Depositing a silicon nitride layer on the back surface of the silicon substrate.

[0007] In a specific embodiment, in the step of sequentially depositing a tunneling oxide layer and a polysilicon layer on the back surfaces of the silicon substrate and the first passivation layer, the battery cell preparation method further includes: Making the sum of the thicknesses of the tunneling oxide layer and the polysilicon layer less than the thickness of the first passivation layer.

[0008] In a specific embodiment, the battery cell preparation method satisfies at least one of the following conditions: the thickness L1 of the silicon nitride layer is 150 nm - 220 nm, the thickness L2 of the tunneling oxide layer is 1 - 2 nm, and the thickness L3 of the polysilicon layer is 100 - 200 nm.

[0009] In a specific embodiment, when the polysilicon layer is doped to be converted into a doped polysilicon layer, the battery cell preparation method further includes: Printing a first paste on the polysilicon layer in the first region, and simultaneously printing a second paste on the polysilicon layer in the second region. Doping at a preset temperature to convert the polysilicon layers in the first region and the second region into the doped polysilicon layer, and generating a doped oxide layer on the doped polysilicon layer and the polysilicon layer in the isolation region.

[0010] In a specific embodiment, before sequentially removing the polysilicon layer, the tunneling oxide layer, and the first passivation layer in the isolation region, the battery cell preparation method further includes: The doped polysilicon layer in the first region is subjected to laser doping, and the laser doping frequency is 300 - 400 KHz, and the energy is 1.5 - 2.5 J / cm².

[0011] In a specific embodiment, after the step of laser doping the doped polysilicon layer in the first region, the method for manufacturing the cell specifically includes: Laser-remove the doped oxide layer formed on the isolation region; Alkaline-wash to remove the polysilicon layer in the isolation region; Acid-wash to remove the tunneling oxide layer and the first passivation layer in the isolation region, and the doped oxide layers in the first region and the second region.

[0012] In a specific embodiment, in the step of sequentially depositing a tunneling oxide layer and a polysilicon layer on the back surface of the silicon substrate and the first passivation layer, the method for manufacturing the cell further includes: A wrap-around polysilicon layer is formed on the front surface of the silicon substrate; When doping the polysilicon layer to convert the polysilicon layer into a doped polysilicon layer, the method for manufacturing the cell further includes: The doped oxide layer is formed on the wrap-around polysilicon layer; When sequentially removing the polysilicon layer, the tunneling oxide layer and the first passivation layer in the isolation region, the method for manufacturing the cell further includes: Chain acid-wash to remove the doped oxide layer on the wrap-around polysilicon layer, and alkaline-wash to remove the wrap-around polysilicon layer, so as to form a textured surface on the front surface of the silicon substrate.

[0013] In a specific embodiment, after sequentially removing the polysilicon layer, the tunneling oxide layer and the first passivation layer in the isolation region, the method for manufacturing the cell further includes: Deposit a second passivation layer on the front surface of the silicon substrate, the back surface of the silicon substrate and the doped polysilicon layer; Screen-print electrodes at the first region and the second region.

[0014] In a second aspect, an embodiment of the present application provides a cell, which is manufactured by using the method for manufacturing the cell described above. Among them, the cell includes a silicon substrate, the silicon substrate has a second region, a first region, and an isolation region separating the first region and the second region, and the isolation region is a polished surface on the back surface of the silicon substrate.

[0015] In this embodiment, the solar cell prepared by the above method for preparing a solar cell can avoid local leakage of the solar cell, improve safety, and at the same time make the isolation region on the back of the silicon substrate a polished surface, which can improve the internal reflection of long-wavelength light by the solar cell, thereby improving the utilization rate of long-wavelength light by the solar cell. At the same time, making the isolation region on the back of the silicon substrate a polished surface can increase the uniformity when depositing a passivation film on the subsequent isolation region, thereby improving the passivation effect of the solar cell and further improving the working efficiency of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 It is a schematic structural diagram of the solar cell after depositing the first passivation layer in the method for preparing a solar cell provided by the present application; Figure 2 For Figure 1 It is a schematic structural diagram of the solar cell in after removing the first passivation layer in the first region and the second region; Figure 3 For Figure 2 It is a schematic structural diagram of the solar cell in after sequentially depositing a tunneling oxide layer and a polysilicon layer; Figure 4 For Figure 3 It is a schematic structural diagram of the solar cell in after doping process; Figure 5 For Figure 4 It is a schematic structural diagram of the solar cell in after laser removing the doped oxide layer in the isolation region; Figure 6 For Figure 5 It is a schematic structural diagram of the solar cell in after chain pickling; Figure 7 For Figure 6 It is a schematic structural diagram of the solar cell in after alkali cleaning; Figure 8 For Figure 7 It is a schematic structural diagram of the solar cell in after pickling; Figure 9 It is a schematic structural diagram of the solar cell provided by the embodiment of the present application in a specific embodiment.

[0018] Reference Signs: 1 - Solar cell; 11 - Silicon substrate; 111 - First region; 112 - Second region; 113 - Isolation region; 12 - First passivation layer; 13 - Tunneling oxide layer; 14 - Polysilicon layer; 15 - Doped polysilicon layer; 16 - Doped oxide layer; 17 - Bypass polysilicon layer; 18 - Second passivation layer; 19 - Electrode. Detailed implementation manners

[0019] For a better understanding of the technical solutions of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0020] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0021] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0022] It should be understood that the term " / and" used herein is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A / and B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the front and rear associated objects.

[0023] The TBC cell can combine the tunneling oxide layer technology of the TOPCon cell and the advantages of the back-arranged electrodes of the IBC cell. The passivation effect and the open-circuit voltage are significantly improved, and it can be economical while achieving a higher cell conversion efficiency. The TBC cell has a preset P-type region and N-type region. Since there is a risk of short circuit between the P-type region and the N-type region, an isolation region needs to be set between the P-type region and the N-type region. During the preparation process of the TBC cell, usually, a tunneling oxide layer and a polysilicon layer are sequentially deposited on the back of the silicon substrate, and then doped polysilicon layers are respectively prepared in the P-type region and the N-type region. After laser grooving and alkaline etching, an isolation region for isolating the P-type region and the N-type region is formed. However, during the doping process, the doped polysilicon layers in the P-type region and the N-type region are likely to affect each other and fuse, and in the subsequent laser grooving and alkaline etching steps, the fused part cannot be completely removed, which easily leads to a leakage phenomenon.

[0024] To solve the above technical problems, as Figures 1 to 8 shown, an embodiment of the present application provides a method for preparing a solar cell 1, and the method for preparing the solar cell 1 may include but is not limited to the following steps: S11: Prepare a silicon substrate 11, where the silicon substrate 11 includes a first region 111, a second region 112, and an isolation region 113 for separating the first region 111 and the second region 112; S12: Deposit a first passivation layer 12 on the back surface of the silicon substrate 11; S13: Laser-remove the first passivation layer 12 in the first region 111 and the second region 112 of the silicon substrate 11; S14: Sequentially deposit a tunneling oxide layer 13 and a polysilicon layer 14 on the back surface of the silicon substrate 11 and the first passivation layer 12; S15: Perform doping treatment on the polysilicon layer 14 to convert the polysilicon layer 14 into a doped polysilicon layer 15, and the doped polysilicon layer 15 in the first region 111 has the opposite polarity to the doped polysilicon layer 15 in the second region; S16: Sequentially remove the polysilicon layer 14, the tunneling oxide layer 13, and the first passivation layer 12 in the isolation region 113.

[0025] In this embodiment, after depositing the first passivation layer 12 on the back surface of the silicon substrate 11, the first passivation layer 12 in the first region 111 and the second region 112 of the silicon substrate 11 is separately removed by laser. The first passivation layer 12 that is not removed by laser can cover the isolation region 113 of the silicon substrate 11. When subsequent steps of depositing and doping the polysilicon layer 14 are carried out, the first passivation layer 12 on the isolation region 113 can play a pre-isolation role to isolate the first region 111 and the second region 112, avoiding mutual influence and fusion between the doped polysilicon layers 15 formed in the first region 111 and the second region 112 during subsequent steps, resulting in local leakage phenomenon, thereby improving the safety during the preparation and subsequent use of the solar cell 1.

[0026] In this embodiment, compared with the method in the related art of first forming a doped polysilicon layer and then laser-grooving and etching with alkali solution to form an isolation groove, the method for preparing the solar cell 1 provided by the embodiment of the present application first sets the first passivation layer 12 to isolate the first region 111 and the second region 112, avoiding mutual influence between the doped polysilicon layers 15 formed in the first region 111 and the second region 112. While significantly improving the safety during the preparation and use of the solar cell 1, it also has the advantages of simple operation and easy implementation.

[0027] Among them, the first region 111 and the second region 112 in the embodiments of the present application are two regions with opposite polarities. For example, the first region 111 can be a P-type region, the second region 112 can be an N-type region, or the first region 111 can be an N-type region, and the second region 112 can be a P-type region. The specific setting forms of the first region 111 and the second region 112 in the embodiments of the present application are not limited.

[0028] The embodiments of the present application also provide a battery cell 1, as Figure 8 and Figure 9 shown. The battery cell 1 is made by the preparation method of the above battery cell 1. The battery cell 1 may include a silicon substrate 11, and the silicon substrate 11 has a first region 111, a second region 112, and an isolation region 113 separating the first region 111 and the second region 112. The isolation region 113 is a polished surface on the back of the silicon substrate 11.

[0029] In this embodiment, for the battery cell 1 prepared by the preparation method of the above battery cell 1, while avoiding the phenomenon of local leakage of the battery cell 1 and improving safety, the isolation region 113 is a polished surface on the back of the silicon substrate 11, which can improve the internal reflection effect of long-wavelength light in this region, thereby improving the utilization rate of long-wavelength light by the battery cell 1. At the same time, making the isolation region 113 a polished surface on the back of the silicon substrate 11 can improve the uniformity when depositing a passivation film on the isolation region 113 on the back of the subsequent silicon substrate 11, thereby improving the overall passivation effect of the battery cell 1, and further improving the working efficiency of the battery cell 1.

[0030] In a specific embodiment, as Figure 1 and Figure 2 shown, the above step S12 may specifically include: S121: Deposit a silicon nitride layer on the back of the silicon substrate 11.

[0031] In this embodiment, the first passivation layer 12 is a silicon nitride layer, and the silicon nitride layer has good physical and chemical properties. Silicon nitride has good hardness, is not easy to deform, and is wear-resistant. At the same time, silicon nitride also has good corrosion resistance. By the preparation method of the above battery cell, before forming the doped polysilicon layer, a first passivation layer 12 made of silicon nitride is formed on the isolation region 113, which can isolate the first region 111 and the second region 112, and has a good isolation effect, avoiding the mutual influence of the doped polysilicon layers in the two regions in the subsequent steps, resulting in a leakage phenomenon, thereby ensuring the normal preparation of the battery cell.

[0032] In a specific embodiment, as Figure 2 and Figure 3 shown, the above step S14 may specifically include: S141: Make the sum of the thicknesses of the tunneling oxide layer 13 and the polysilicon layer 14 less than the thickness of the first passivation layer 12.

[0033] In this embodiment, after retaining the first passivation layer 12 at the isolation region 113, the first passivation layer 12 provides an isolation effect between the first region and the second region, such that the sum of the thicknesses of the tunneling oxide layer 13 and the polysilicon layer 14 deposited on the back surface of the silicon substrate 11 in the first region and the second region is less than the thickness of the first passivation layer 12, preventing the polysilicon layer 14 on either side of any first passivation layer 12 from having a partial structure that crosses the first passivation layer 12. Therefore, making the sum of the thicknesses of the tunneling oxide layer 13 and the polysilicon layer 14 in the first region 111 and the second region 112 less than the thickness of the first passivation layer 12 enables the first passivation layer 12 in the isolation region 113 to completely separate the first region 111 and the second region 112, further enhancing the isolation effect of the first passivation layer 12 in the isolation region 113 on the first region 111 and the second region 112.

[0034] In the above embodiment, as Figure 2 and Figure 3 shown, the method for preparing the solar cell can satisfy at least one of the following conditions: the thickness L1 of the silicon nitride layer (the first passivation layer 12) is 150 nm - 220 nm, the thickness L2 of the tunneling oxide layer 13 is 1 nm - 2 nm, and the thickness L3 of the polysilicon layer 14 is 100 nm - 200 nm.

[0035] In this embodiment, during the preparation process of the solar cell, making the thicknesses of the silicon nitride layer (the first passivation layer 12), the tunneling oxide layer 13, and the polysilicon layer 14 satisfy the above conditions enables the silicon nitride layer (the first passivation layer 12) in the isolation region 113 to completely separate the tunneling oxide layer 13 and the polysilicon layer 14 in the first region 111 and the second region 112, enhancing the isolation effect of the isolation region 113 during the preparation process of the solar cell and preventing the subsequently formed doped polysilicon layers in the first region 111 and the second region 112 from interfering with each other, resulting in a leakage phenomenon.

[0036] In a specific embodiment, as Figure 2 and Figure 4 shown, the above step S15 may specifically include: S151: Print a first paste on the polysilicon layer 14 in the first region 111, and simultaneously print a second paste on the polysilicon layer 14 in the second region 112. Dope at a preset temperature to convert the polysilicon layers 14 in the first region 111 and the second region 112 into doped polysilicon layers 15, and form a doped oxide layer 16 on the doped polysilicon layers 15 and the polysilicon layer 14 in the isolation region 113.

[0037] In this embodiment, by providing a first passivation layer 12 on the isolation region 113 and making the sum of the thicknesses of the tunneling oxide layer 13 and the polysilicon layer 14 in the first region 111 and the second region 112 less than the thickness of the first passivation layer 12 in the isolation region 113, the polysilicon layers in the first region and the second region can be completely separated. Therefore, during the doping process, the first paste can be printed on the polysilicon layer 14 in the first region 111 while the second paste is printed on the polysilicon layer 14 in the second region 112. Compared with the related art in which the second paste needs to be printed first to prepare a boron-doped polysilicon layer, and then a slot is opened to print the first paste to prepare a phosphorus-doped polysilicon layer, the method for manufacturing a solar cell provided in this embodiment of the present application can simultaneously prepare the doped polysilicon layers 15 in the first region 111 and the second region 112. While ensuring the safety of the solar cell manufacturing process, it can also simplify the process flow, thereby improving the efficiency of solar cell manufacturing.

[0038] Among them, in this embodiment of the present application, screen printing or transfer printing can be used to simultaneously print the first paste in the second region 112 and the second paste in the first region 111. Additionally, the preset temperature can be 850°C - 950°C.

[0039] In the above embodiment, when the first region 111 is a P-type region and the second region 112 is an N-type region, the first paste can be a boron paste and the second paste can be a phosphorus paste. When the first region 111 is an N-type region and the second region 112 is a P-type region, the first paste can be a phosphorus paste and the second paste can be a boron paste. In other embodiments, the first paste and the second paste can also be other materials, and the present application does not limit the specific materials of the first paste and the second paste.

[0040] The following describes by taking the first region 111 as a P-type region, the second region 112 as an N-type region, the first paste as a boron paste, and the second paste as a phosphorus paste as an example.

[0041] In a specific embodiment, as Figures 5 to 8 shown, before sequentially removing the polysilicon layer 14, the tunneling oxide layer 13, and the first passivation layer 12 in the isolation region 113, step S15 may further include the following specific steps: S152: Perform laser doping on the doped polysilicon layer 15 in the first region 111, with a laser doping frequency of 300 - 400 KHz and an energy of 1.5 - 2.5 J / cm².

[0042] In this embodiment, in step 151, the first region 111 and the second region 112 are doped simultaneously at a preset temperature, and the preset temperature is 850°C - 950°C. However, the boron doping in the first region 111 needs to be carried out at 1000°C - 1050°C to form a higher concentration required for the cell. Therefore, the first region 111 also needs to be subjected to secondary laser doping, and the laser doping frequency is 300 - 400 KHz, and the energy is 1.5 - 2.5 J / cm², so as to further increase the boron doping concentration in the first region 111 to meet the usage requirements of the cell.

[0043] In a specific embodiment, as Figures 5 to 8 shown, after the step of laser doping the doped polysilicon layer 15 in the first region 111, the method for preparing the cell may further include the following steps: S153: Laser-remove the doped oxide layer 16 formed on the isolation region 113; S161: Alkaline-wash to remove the polysilicon layer 14 in the isolation region 113; S162: Acid-wash to remove the tunneling oxide layer 13 and the first passivation layer 12 in the isolation region 113, and the doped oxide layers 16 in the first region 111 and the second region 112.

[0044] In this embodiment, since a doped oxide layer 16 will be formed on the doped polysilicon layer 15 and the polysilicon layer 14 during the doping process, in step S153, it is necessary to use laser treatment to remove the doped oxide layer 16 formed on the isolation region 113, and retain the doped oxide layers 16 in the first region 111 and the second region 112. In step S161, the polysilicon layer 14 in the isolation region 113 is removed by alkaline-washing. Since the doped oxide layers 16 are retained in the first region 111 and the second region 112, during the alkaline-washing process, the doped polysilicon layers 15 in the first region 111 and the second region 112 are not affected by the alkaline-washing. In step 162, the tunneling oxide layer 13 and the first passivation layer 12 in the isolation region 113, and the doped oxide layers 16 in the first region 111 and the second region 112 are removed by acid-washing, so as to obtain a cell with a first region 111, a second region 112, and an isolation region 113. At the same time, during the alkaline-washing process, since the isolation region 113 is covered with a tunneling oxide layer 13 and a first passivation layer 12 on the back of the silicon substrate 11 and is not affected by the alkaline-washing, it can be retained as a polished surface after the subsequent acid-washing removal step.

[0045] In a specific embodiment, as Figures 3 to 8 shown, the above step S141 may further specifically include: S1411: Deposit a circumferential polysilicon layer 17 on the front surface of the silicon substrate 11; The above step S151 may further specifically include: S1511: Deposit a doped oxide layer 16 on the polycrystalline silicon layer 17 coated around. The above step S161 may further specifically include: S1611: Remove the doped oxide layer 16 on the polycrystalline silicon layer 17 coated around by chain pickling, and remove the polycrystalline silicon layer 17 coated around by alkali cleaning to form a textured surface on the front of the silicon substrate 11.

[0046] In this embodiment, when depositing the tunneling oxide layer 13 and the polycrystalline silicon layer 14 on the back of the silicon substrate 11, a polycrystalline silicon layer 17 coated around will also be formed on the front of the silicon substrate 11, and when doping treatment is performed, a doped oxide layer 16 will be formed on the polycrystalline silicon layer 17 coated around. Therefore, before alkali cleaning the silicon substrate 11, chain pickling is first performed to remove the doped oxide layer 16 on the front of the silicon substrate, and it has no influence on other positions of the silicon substrate 11. Then, the silicon substrate 11 is alkali-cleaned to remove the polycrystalline silicon layer 14 in the isolation region 113 and the polycrystalline silicon layer 17 coated around on the front of the silicon substrate 11, and a textured surface is formed on the front of the silicon substrate 11. Since at this time the isolation region 113 is covered with a doped oxide layer 16 on the back of the silicon substrate 11, the isolation region 113 is not affected by the alkali cleaning on the back of the silicon substrate 11 during alkali cleaning, so a textured surface is not formed, enabling the isolation region 113 to retain a polished surface after the subsequent pickling to remove the doped oxide layer 16, improving the internal reflection effect of this region on long-wavelength light, and further improving the utilization rate of long-wavelength light by the solar cell.

[0047] In a specific embodiment, as Figure 8 and Figure 9 shown, the method for preparing the solar cell 1 may further include: S17: Deposit a second passivation layer 18 on the front of the silicon substrate 11, the back of the silicon substrate 11, and the doped polycrystalline silicon layer 15; S18: Screen-print electrodes 19 on the first region 111 and the second region 112.

[0048] In this embodiment, by making the isolation region 113 be a polished surface on the back of the silicon substrate 11, when depositing the second passivation layer 18, the uniformity of the second passivation layer 18 in this region can be improved, thereby improving the passivation effect of the second passivation layer 18, and further improving the working efficiency of the solar cell 1.

[0049] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a battery cell, characterized in that: The method for preparing the battery cell (1) comprises: Preparing a silicon substrate (11), the silicon substrate (11) comprising a first region (111), a second region (112), and an isolation region (113) for isolating the first region (111) from the second region (112); Depositing a first passivation layer (12) on the back side of the silicon substrate (11); Using a laser to remove the first passivation layer (12) in the first region (111) and the second region (112) of the silicon substrate (11); Depositing a tunneling oxide layer (13) and a polysilicon layer (14) in sequence on the backside of the silicon substrate (11) and the first passivation layer (12); Performing a doping treatment on the polysilicon layer (14) so ​​that the polysilicon layer (14) is converted into a doped polysilicon layer (15), wherein the doped polysilicon layer (15) in the first region (111) and the doped polysilicon layer (15) in the second region (112) have opposite polarities; The polysilicon layer (14), the tunneling oxide layer (13) and the first passivation layer (12) of the isolation region (113) are removed in sequence.

2. The method for preparing a battery cell according to claim 1, characterized in that: The step of depositing a first passivation layer (12) on the back side of the silicon substrate (11) specifically comprises: A silicon nitride layer is deposited on the back side of the silicon substrate (11).

3. The method for preparing a battery cell according to claim 2, characterized in that: In the step of sequentially depositing a tunneling oxide layer (13) and a polysilicon layer (14) on the back side of the silicon substrate (11) and the first passivation layer (12), the method for preparing the cell (1) further comprises: The sum of the thicknesses of the tunnel oxide layer (13) and the polysilicon layer (14) is smaller than the thickness of the first passivation layer (12).

4. The method for preparing a battery cell according to claim 3, characterized in that: The method for preparing the cell (1) satisfies at least one of the following conditions: the thickness L1 of the silicon nitride layer is 150nm-220nm, the thickness L2 of the tunneling oxide layer (13) is 1-2nm, and the thickness L3 of the polysilicon layer (14) is 100-200nm.

5. The method for preparing a battery cell according to claim 1, characterized in that: When the polycrystalline silicon layer (14) is subjected to a doping treatment so as to convert the polycrystalline silicon layer (14) into a doped polycrystalline silicon layer (15), the method for preparing the cell (1) further comprises: A first paste is printed on the polysilicon layer (14) of the first region (111), and a second paste is printed on the polysilicon layer (14) of the second region (112), and the polysilicon layers (14) of the first region (111) and the second region (112) are doped at a preset temperature so that the polysilicon layers (14) are converted into the doped polysilicon layers (15), and a doped oxide layer (16) is generated on the doped polysilicon layer (15) and the polysilicon layer (14) of the isolation region (113).

6. The method for preparing a battery cell according to claim 5, characterized in that: Before sequentially removing the polysilicon layer (14), the tunneling oxide layer (13) and the first passivation layer (12) of the isolation region (113), the method for preparing the cell (1) further comprises: The doped polysilicon layer (15) in the first region (111) is laser doped, with the laser doping frequency being 300-400 kHz and the energy being 1.5-2.5 J / cm².

7. The method for preparing a battery cell according to claim 6, characterized in that: After the step of laser doping the doped polysilicon layer (15) in the first region (111), the method for preparing the cell (1) specifically comprises: Using a laser to remove the doped oxide layer (16) generated on the isolation region (113); Alkaline washing to remove the polysilicon layer (14) in the isolation region (113); The tunneling oxide layer (13) and the first passivation layer (12) of the isolation region (113), and the doped oxide layer (16) of the first region (111) and the second region (112) are removed by pickling.

8. The method for preparing a battery cell according to claim 7, characterized in that: In the step of sequentially depositing a tunneling oxide layer (13) and a polysilicon layer (14) on the back side of the silicon substrate (11) and the first passivation layer (12), the method for preparing the cell (1) further comprises: A polysilicon layer (17) is formed on the front surface of the silicon substrate (11); When the polysilicon layer (14) is subjected to a doping treatment so as to convert the polysilicon layer (14) into a doped polysilicon layer (15), the method for preparing the cell (1) further comprises: The doped oxide layer (16) is formed on the wrap-around polysilicon layer (17); When the polysilicon layer (14), the tunneling oxide layer (13) and the first passivation layer (12) of the isolation region (113) are removed in sequence, the method for preparing the cell (1) further comprises: The doped oxide layer (16) on the coated polysilicon layer (17) is removed by chain pickling, and the coated polysilicon layer (17) is removed by alkali washing, so that a velvet surface is formed on the front side of the silicon substrate (11).

9. The method for preparing a battery cell according to claim 1, characterized in that: After sequentially removing the polysilicon layer (14), the tunneling oxide layer (13) and the first passivation layer (12) of the isolation region (113), the method for preparing the cell (1) further comprises: Depositing a second passivation layer on the front side of the silicon substrate (111), the back side of the silicon substrate (111) and the doped polysilicon layer (15); Electrodes are screen-printed at the first region (111) and the second region (112).

10. A battery cell, characterized in that: The battery cell (1) is prepared by the method for preparing the battery cell (1) described in claims 1 to 9; The cell (1) comprises a silicon substrate (11), the silicon substrate (11) having a second region (112), a first region (111), and an isolation region (113) separating the first region (111) and the second region (112), wherein the isolation region (113) is a polished surface on the back side of the silicon substrate (11).

Images