Preparation process of front laminated passivation film for crystalline silicon cell

Abstract

The invention relates to a solar crystalline silicon cell, and particularly discloses a preparation process of a front laminated passivation film for a crystalline silicon cell, which comprises the following steps of: S1, pretreating two sides of an N-type substrate silicon wafer to form textured surfaces on the two sides of the silicon wafer; s2, forming a P-type doping layer on the front surface of the silicon wafer; s3, carrying out alkali polishing on the back surface; s4, doping a polycrystalline silicon layer on the back surface; s5, high-temperature annealing; s6, carrying out PSG etching and removing the mask layer from the front surface; s7, preparing an aluminum oxide laminated layer on the front surface of the P-type doping layer, wherein the aluminum oxide laminated layer is prepared into aluminum oxide with different thicknesses; and S8, preparing a front anti-reflection laminated layer on the front surface of the aluminum oxide laminated layer, and respectively supporting a first SiO2 layer, a first SiNx layer, a second SiNx layer and a first SiONx layer with certain thicknesses. A second SiONx layer and a Mask protection layer; and S9, Ag electrode printing, sintering and LECO. The method has the beneficial effects that the field passivation effect of the front passivation layer is enhanced on the basis of the passivation effect of the original front passivation layer, and the efficiency of the cell is improved by reducing the recombination loss caused by surface defects of the silicon wafer.

Description

Technical Field

[0001] The invention relates to the technical field of solar crystalline silicon cells, in particular to a preparation process of a front laminated passivation film for a crystalline silicon cell. Background Art

[0002] Reducing production costs and improving photoelectric conversion efficiency are the eternal goals of solar cell production.

[0003] In order to reduce the loss of battery efficiency, a variety of new crystalline silicon battery structures have been developed. For example, OPCON batteries use silicon oxide films with tunneling effects and doped polysilicon films to passivate the back surface of n-type silicon batteries and the metal electrode contact area, significantly improving the open circuit voltage of the battery; compared with PERC batteries and HJT batteries, TOPCON batteries have a higher theoretical efficiency limit - 28.7% (the theoretical efficiency of converting electricity during battery charging and discharging), and its industrial efficiency is around 24% (the efficiency of charging and discharging batteries after actual production), which shows that there is still room for improvement; in addition, the manufacturing cost of TOPCON batteries is also rapidly declining, so the competitive advantage of batteries with this concept is becoming more and more obvious.

[0004] Currently, some companies on the market, such as Yingli, use TOPCON battery technology: conducting research on industrial process solutions, preparing high-quality back-surface tunneling passivation contact layers, and developing emitter stacked composite passivation layer technology and low-surface composite doping technology, which further improves the efficiency of TOPCON type batteries.

[0005] It should be noted that there are many factors that affect the conversion efficiency of solar cells, and the recombination loss in electrical loss is one of them. One of the main factors that affect the efficiency of existing N-type TOPCON cell technology is the recombination loss in electrical loss. The current means to solve this problem is to reduce the recombination loss of the cell through the passivation effect of silicon nitride film; however, the problem that still exists is that the passivation effect of silicon nitride is not able to completely and effectively reduce the recombination loss of the cell, and there is still some recombination loss that reduces the efficiency of the cell.

[0006] Therefore, our company takes reducing electrical composite loss as the research direction, and uses the structure of the laminated passivation film to explore the principle and process of improving the efficiency of N-type TOPCON cells. At present, a method for making a front laminated passivation film has been developed and is now protected. Summary of the invention

[0007] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a preparation process for the front-side laminated passivation film of a crystalline silicon cell, which solves the problem that the composite loss of the cell cannot be completely and effectively reduced when the passivation effect of silicon nitride is used to solve the composite electrical loss in the current N-type TOPCON cell.

[0008] The object of the present invention is achieved by the following technical solution: A process for preparing a front laminated passivation film for a crystalline silicon cell comprises the following steps: S1. Pretreatment: pretreatment is performed on both sides of the N-type substrate silicon wafer, that is, alkali is used to treat the N-type substrate silicon wafer so that both sides form a velvet surface; S2, P-type doping layer: Boron chloride is introduced to the front of the N-type base silicon wafer, and the boron chloride is decomposed at high temperature and reacted with silicon to generate elemental boron. The boron layer attached to the front of the silicon wafer is a P-type doping layer; the generated elemental boron diffuses into the silicon wafer, forming a PN junction between the P-type doping layer and the N-type base silicon wafer; S3, back side alkali polishing: the back side of the N-type substrate silicon wafer is alkali washed again, and the back side after alkali washing is polished; S4, back-doped polysilicon layer: preparing a tunneling oxide layer and an N-type polysilicon Poly layer on the back of the N-type base silicon wafer, thereby forming a back-doped polysilicon layer; S5, high temperature annealing: using a high temperature tubular annealing furnace to activate doping atoms and improve the crystallization rate; S6, PSG etching + front mask layer removal: Use hydrofluoric acid to process the back side - that is, PSG etching; Use hydrofluoric acid to further process the crystalline silicon cell after PSG etching to remove the front side wrap and mask layer, that is, front mask layer removal processing; S7, preparing an aluminum oxide stack on the front side of the P-type doped layer, reacting in a high temperature environment of 300-320° C., and obtaining an aluminum oxide stack with a thickness of 4-6 nm; First aluminum oxide layer: first introduce trimethylaluminum as aluminum precursor, react at high temperature for a period of time, then purge with nitrogen, and then introduce H 2 O vapor is used as an oxidizing precursor. After a period of reaction at high temperature, nitrogen is purged. In this process, trimethylaluminum and H 2 The ratio of O steam was 1:1.2; the temperature, amount of introduction and reaction time were kept constant, and the reaction time was controlled by “introducing trimethylaluminum-purging after reaction-introducing H 2 O steam-reaction post-purge" as a cycle, multiple cycles are performed, and after a total of 10 cycles, the first aluminum oxide layer grows on the front side of the N-type substrate silicon wafer; Second alumina layer: trimethylaluminum is introduced, and nitrogen is purged after a period of reaction at high temperature, and then H 2O vapor, react at high temperature for a period of time and then purge with nitrogen; after a total of 12 cycles, a second aluminum oxide layer grows on the front side of the first aluminum oxide layer; The third alumina layer: trimethylaluminum is introduced, and nitrogen is purged after a period of reaction at high temperature, and then H is introduced. 2 O vapor, react at high temperature for a period of time and then purge with nitrogen; after a total of 14 cycles, a third aluminum oxide layer grows on the front side of the second aluminum oxide layer; S8. Prepare a front anti-reflection laminate on the front side of the aluminum oxide laminate, and perform an ionization reaction under a high temperature environment at a high temperature of 400-540°C and an electric field with a power of 8000-9000W. The thickness of the prepared front anti-reflection laminate is (1+8+22+10+19+7)-(2.5+15+35+20+25+10) nm; Silane and laughing gas are introduced, and ionization reaction occurs under high temperature to form the first SiO2 layer; Silane and ammonia are introduced to form an ionization reaction at high temperature to form the first SiNx layer; Silane and ammonia are introduced, and ionization reaction is carried out under high temperature environment to form the second SiNx layer; Silane, ammonia and laughing gas are introduced, and ionization reaction is carried out under high temperature environment to form the first SiONx layer; Silane, ammonia and laughing gas are introduced, and ionization reaction is carried out under high temperature environment to form the second SiONx layer; Silane and laughing gas are introduced, and ionization reaction occurs under high temperature environment, eventually forming a mask protective layer; S9, Ag electrode printing, sintering, LECO.

[0009] Furthermore, in the above S7, when preparing the first aluminum oxide layer, the second aluminum oxide layer, and the third aluminum oxide layer: they are all in a high temperature environment of 300-320°C, and the process of "introducing trimethylaluminum-purging after reaction-introducing H 2 O steam-purge after reaction" cycle. In one cycle: the amount of trimethylaluminum introduced is 18-20sccm, the reaction time of trimethylaluminum is 7s, and the purge time after the reaction of trimethylaluminum is 10-14s; the amount of H introduced is 18-20sccm, the reaction time of trimethylaluminum is 7s, and the purge time after the reaction of trimethylaluminum is 10-14s; 2 O steam is 1.2 times 18-20sccm, H 2 The reaction time of O steam is 7s, and that of H 2 The purge time after the O steam reaction is 10-14s.

[0010] Furthermore, the thickness of the aluminum oxide stack obtained in S7 is 4.9 nm, wherein the thickness of the first aluminum oxide layer is 1.5 nm, the thickness of the second aluminum oxide layer is 1.6 nm, and the thickness of the third aluminum oxide layer is 1.8 nm.

[0011] Furthermore, in said S5, when preparing the front anti-reflection laminate: When preparing the first SiO2 layer, 500-2000 sccm silane and 1000-3000 sccm nitrous oxide are introduced, and the ionization reaction is carried out for 10-25 seconds under high temperature environment, and the thickness obtained is 1-2.5nm. When preparing the first SiNx layer, 1000-5000 sccm silane and 8000-12000 sccm ammonia are introduced, and the ionization reaction is carried out for 80-150 seconds under high temperature environment; the thickness obtained is 8-15nm. When preparing the second SiNx layer, 1000-5000 sccm silane and 8000-14000 sccm ammonia are introduced, and the ionization reaction is carried out for 220-350 seconds under high temperature environment; the thickness obtained is 22-35nm. When preparing the first SiONx layer, 1000-5000sccm silane, 8000-14000sccm ammonia, and 800-2000sccm nitrous oxide are introduced, and the ionization reaction is 100-200s under high temperature environment; the thickness obtained is 10-20nm. When preparing the second SiONx layer, 1000-5000sccm silane, 8000-14000sccm ammonia, and 800-2000sccm nitrous oxide are introduced, and the ionization reaction is 190-250s under high temperature environment; the thickness obtained is 19-25nm. When preparing the Mask protective layer, 1000-2000sccm silane and 7000-9000sccm nitrous oxide are introduced, and the ionization reaction is 70-100s under high temperature environment; the thickness obtained is 7-10nm.

[0012] Furthermore, in the crystalline silicon cell, the thickness of the N-type base silicon wafer is 120-140 um, and the thickness of the P-type doping layer is 0.8-1.2 um.

[0013] Furthermore, the crystalline silicon cell includes an N-type base silicon wafer, which has a P-type doping layer, an aluminum oxide stack, and a front anti-reflection stack in sequence on the front side of the N-type base silicon wafer, and a tunneling oxide layer, an N-type polysilicon Poly layer, and a passivation film stack in sequence on the back side of the N-type base silicon wafer.

[0014] Furthermore, when preparing the passivation film stack, the temperature is 400-540°C and the electric field is 8000-17000W. When preparing the back passivation film stack, the temperature is 400-540°C and the electric field is 8000-17000W. After silane and ammonia are introduced, the back passivation film stack is obtained under the action of the high temperature electric field.

[0015] The present invention has the following advantages: In this scheme, "aluminum oxide stacking + SiO2-SiNx-SiONx" is used to form a passivation film layer on the front surface of the battery as a reflector; compared with the existing single-layer aluminum oxide + SiNx passivation layer, it has a better passivation effect, and the multi-layer aluminum oxide has a higher passivation quality than the single-layer AlOx film. SiO2, SiNx and SiONx all have the function of fixing positive charges. The stacked SiO2-SiNx-SiONx has a stronger ability to fix positive charges and forms a better field passivation effect. After annealing, the original hydrogen passivation of the SiNx passivation layer can be maintained; therefore, the present invention can enhance its field passivation effect based on the passivation effect of the original front passivation layer, thereby reducing the composite loss caused by surface defects of the silicon wafer to increase the efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the structure of a crystalline silicon cell; Figure 2 is a schematic diagram of the structure of an aluminum oxide laminate; Figure 3 Schematic diagram of the structure of the front anti-reflection stack. DETAILED DESCRIPTION

[0017] The present invention is further described below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0018] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] The present invention provides a process for preparing a front laminated passivation film for a crystalline silicon cell, comprising the following steps: S1. Pretreatment: Pretreatment is performed on both sides of the N-type substrate silicon wafer, that is, alkali is used to treat the N-type substrate silicon wafer so that the two sides of the N-type substrate silicon wafer form a velvet surface.

[0020] S2, P-type doped layer: Boron chloride is introduced into the front side of the N-type base silicon wafer, and the boron chloride is decomposed at high temperature and reacted with silicon to generate elemental boron. The boron layer attached to the front side of the silicon wafer is the P-type doped layer. The generated elemental boron diffuses into the interior of the silicon wafer, forming a PN junction between the P-type doped layer and the N-type base silicon wafer.

[0021] S3, back side alkaline polishing: a chain cleaning machine is used, in which a sodium hydroxide solution is added, and the back side treated in step S2 is alkaline-washed with the sodium hydroxide solution, and then the back side after alkaline washing is polished.

[0022] S4, back-doped polysilicon layer: Then PECVD equipment (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition is a thin film preparation technology that uses radio frequency electric field to plasmatize the reaction gas in a vacuum environment and chemically deposits it on the substrate) is used to generate a tunneling oxide layer and an N-type polysilicon Poly layer on the back side after S3 treatment (the two together become the back-doped polysilicon layer).

[0023] S5. High temperature annealing: Use a high temperature tubular annealing furnace to activate doping atoms and improve the crystallization rate.

[0024] S6, PSG etching + front mask removal; PSG etching: a chain cleaning machine is filled with hydrofluoric acid, and a protective liquid layer is provided on the surface of the hydrofluoric acid; the crystalline silicon treated in step S5 is placed in the chain cleaning machine, the hydrofluoric acid is allowed to contact the doped polysilicon layer on the back side, and the P-type doped layer on the front side of the N-type substrate silicon wafer is located in the protective liquid layer; Removing the mask layer from the front: It should be noted that after the S2 treatment, there is a mask layer on the upper surface of the P-type doped layer, and during the step S4 treatment, a portion of the doped polysilicon will expand around the upper surface of the mask layer; therefore, in the tank cleaning machine, hydrofluoric acid is added, and all the silicon cells after the PSG treatment are placed in the hydrofluoric acid, so that the mask layer and the corresponding extension can be removed.

[0025] S7, preparing an aluminum oxide stack on the front side of the P-type doped layer, the thickness of the aluminum oxide stack being 4-6 nm; Specifically, the ALD equipment is used to: Nitrogen purge: At 300-320℃, increase N 2 Purge in the range of 5000-50000sccm to fully remove the air in the furnace tube; First aluminum oxide layer: At 300-320°C, alternately fill with aluminum precursor (trimethyl aluminum) and oxidation precursor (H 2 O), each ALD cycle is set as follows: aluminum precursor flow rate 18-20 sccm → reaction 7s → nitrogen purge 10-14s → oxidation precursor 1.2×(18-20) sccm → reaction 7s → nitrogen purge 10-14s. After 10 ALD cycles, a layer of aluminum oxide grows on the front side of the silicon wafer. For example, the thickness of the aluminum oxide layer is preferably about 1.5 nm. Second aluminum oxide layer: At 300-320°C, alternately fill with aluminum precursor (trimethylaluminum) and oxidation precursor (H 2O), each ALD cycle is set as follows: aluminum precursor flow rate 18-20 sccm → reaction 7s → nitrogen purge 10-14s → oxidation precursor 1.2×(18-20) sccm → reaction 7s → nitrogen purge 10-14s. After 12 ALD cycles, another layer of aluminum oxide is grown on the above aluminum oxide layer. For example, the thickness of the aluminum oxide layer is preferably about 1.6 nm. At 300-320°C, the aluminum precursor (trimethylaluminum) and the oxidation precursor (H 2 O), each ALD cycle is set as: aluminum precursor flow 18-20sccm→reaction 7s→nitrogen purge 10-14s→oxidation precursor 1.2×(18-20)sccm→reaction 7s→nitrogen purge 10-14s. After 14 ALD cycles, another layer of aluminum oxide is grown on the above aluminum oxide layer. For example, the thickness of the aluminum oxide layer is preferably about 1.8nm.

[0026] It should be noted that ALD equipment refers to atomic layer deposition (ALD) equipment, which is an advanced chemical vapor deposition technology device used to prepare thin film materials. ALD equipment is a high-precision, large-scale, uniform thin film material preparation technology, which has important applications in the fields of electronic device nanotechnology, especially in the chemical vapor deposition process, it can prepare thin films of uniform thickness. ALD equipment can be used to produce semiconductor chips, thin-film batteries, microelectronic devices, optoelectronic devices, etc., and is widely used in advanced electronics, optoelectronics and nanotechnology fields. The core of the ALD equipment is a reaction chamber that can control the composition, thickness and quality of the material. It uses colloidal synthesis, chemical vapor deposition, physical vapor deposition and other methods, and uses solids, gases or liquids in the reaction chamber to alternately perform different monolayer chemical reactions in a circulation system to form a monolayer of molecules on the surface, which is gradually deposited to the required thickness, thus becoming a complete, uniform and dense thin film material. During the deposition process, the material is controlled to be generated layer by layer, so that the film is uniform, dense and has a precise thickness.

[0027] S7. Prepare a front anti-reflection laminate on the front side of the aluminum oxide laminate.

[0028] Specifically, use PECVD equipment from JEC or Red Sun to prepare the front anti-reflection stack: Nitrogen purge: At 400-540℃, increase N 2 Purge in the range of 5000-50000ccm to fully remove the air in the furnace tube; When preparing the first SiO2 layer, 500-2000 sccm silane and 1000-3000 sccm nitrous oxide are introduced, and the ionization reaction is carried out for 10-25 seconds under a high temperature environment; the obtained thickness is 1-2.5nm; When preparing the first SiNx layer, 1000-5000sccm silane and 8000-12000sccm ammonia are introduced, and the ionization reaction is carried out for 80-150s under high temperature environment; the obtained thickness is 8-15nm; When preparing the second SiNx layer, 1000-5000sccm silane and 8000-14000sccm ammonia are introduced, and the ionization reaction is carried out for 220-350s under high temperature environment; the obtained thickness is 22-35nm; When preparing the first SiONx layer, 1000-5000sccm silane, 8000-14000sccm ammonia, and 800-2000sccm nitrous oxide are introduced, and the ionization reaction is carried out for 100-200s under high temperature environment; the obtained thickness is 10-20nm; When preparing the second SiONx layer, 1000-5000sccm silane, 8000-14000sccm ammonia, and 800-2000sccm nitrous oxide are introduced, and the ionization reaction is carried out for 190-250s under high temperature environment; the obtained thickness is 19-25nm; When preparing the mask protective layer, 1000-2000sccm silane and 7000-9000sccm nitrous oxide are introduced, and the ionization reaction takes 70-100s under high temperature environment; the obtained thickness is 7-10nm.

[0029] S8, Ag electrode printing, sintering, LECO.

[0030] It should be noted that, see Figure 1 In a crystalline silicon cell, an N-type base silicon wafer (a) is included, and a P-type doping layer (b), an aluminum oxide stack (c), and a front anti-reflection stack (d) are sequentially provided on the front side of the N-type base silicon wafer (a), and a front groove line (e) is also provided on the front side; a tunneling oxide layer (f), an N-type polycrystalline silicon Poly layer (g), and a passivation film stack (h) are sequentially provided on the back side of the N-type base silicon wafer (a), and a back groove line (j) is also provided on the back side; wherein the thickness of the aluminum oxide stack is 4-6nm (preferably 4.9nm), and the thickness of the front anti-reflection stack is (1+8+22+10+19+7)-(2.5+15+35+20+25+10)nm. Figure 2 , the alumina stack is a stack of alumina deposits of different thicknesses. Figure 3 The front anti-reflection stack is formed by stacking a first SiO2 layer, a first SiNx layer, a second SiNx layer, a first SiONx layer, and a second SiONx layer of different thicknesses through precipitation.

[0031] Furthermore, in the crystalline silicon cell, the thickness of the N-type base silicon wafer is 120-140 um, and the thickness of the P-type doping layer is 0.8-1.2 um.

[0032] Exemplarily, the preparation parameters are illustrated below.

[0033] Example 1 The crystalline silicon cell is prepared by adopting the above-mentioned preparation process for the front laminated passivation film of the crystalline silicon cell; wherein S1, S2, S3, S4, S5, S6, and S9 are all prepared in the above-mentioned manner; When preparing the aluminum oxide stack on the front side in S7, the temperature is maintained in the range of 300-320°C: 5000sccm of nitrogen is introduced for purging; 18sccm of trimethylaluminum is introduced; 1.2×18sccm of H 2 O vapor, when trimethylaluminum or H 2 After the O vapor reaction, nitrogen was purged for 10 s with a nitrogen purge volume of 5000 sccm; When preparing the front anti-reflection stack in S8, maintaining the temperature in the range of 400-540°C and under the electric field of 14000W power: 500 sccm of silane and 1000 sccm of nitrous oxide were introduced, and ionization was carried out at high temperature for 10 seconds to form the first layer of SiO 2 layer; 1000 sccm silane and 8000 sccm ammonia were introduced and ionized at high temperature for 80 seconds to form the first SiNx layer; 1000 sccm silane and 8000 sccm ammonia are introduced and ionized at high temperature for 220 seconds to form a second SiNx layer; 1000 sccm silane, 8000 sccm ammonia, and 800 sccm nitrous oxide were introduced, and ionized at high temperature for 100 s to form the first SiONx layer; 1000 sccm silane, 8000 sccm ammonia, and 800 sccm nitrous oxide were introduced, and ionization was performed at high temperature for 190 s to form a second SiONx layer; 1000sccm silane and 7000sccm nitrous oxide were introduced, and ionization was performed at high temperature for 70s to form a mask protective layer; In S8, a nitrogen purge of 5000 sccm was used after each layer was deposited.

[0034] Example 2 The crystalline silicon cell is prepared by adopting the above-mentioned preparation process for the front laminated passivation film of the crystalline silicon cell; wherein S1, S2, S3, S4, S5, S6, and S9 are all prepared in the above-mentioned manner; When preparing the aluminum oxide stack on the front side in S7, the temperature is maintained in the range of 300-320°C: 5000sccm of nitrogen is introduced for purging; 18sccm of trimethylaluminum is introduced; 1.2×18sccm of H 2 O vapor, when trimethylaluminum or H 2After the O vapor reaction, nitrogen was purged for 10 s with a nitrogen purge volume of 5000 sccm; When preparing the front anti-reflection stack in S8, maintaining the temperature in the range of 400-540°C and under the electric field of 14000W power: 1000sccm of silane and 2000sccm of nitrous oxide were introduced, and ionization was carried out at high temperature for 20s to form the first layer of SiO 2 layer; 3000 sccm silane and 10000 sccm ammonia were introduced and ionized at high temperature for 120 s to form the first SiNx layer; 3000 sccm silane and 10000 sccm ammonia are introduced and ionized at high temperature for 300 s to form a second SiNx layer; 3000 sccm silane, 10000 sccm ammonia, and 1500 sccm nitrous oxide were introduced, and ionization was performed at high temperature for 180 seconds to form the first SiONx layer; 3000 sccm silane, 10000 sccm ammonia, and 1500 sccm nitrous oxide were introduced, and ionization was performed at high temperature for 220 s to form a second SiONx layer; 1500sccm silane and 8000sccm nitrous oxide were introduced, and ionized at high temperature for 90s to form a mask protective layer; In S8, a nitrogen purge of 3000 sccm was used after each layer was deposited.

[0035] Example 3 The crystalline silicon cell is prepared by adopting the above-mentioned preparation process for the front laminated passivation film of the crystalline silicon cell; wherein S1, S2, S3, S4, S5, S6, and S9 are all prepared in the above-mentioned manner; When preparing the front aluminum oxide stack in S7, the temperature is maintained in the range of 300-320°C: 50000sccm of nitrogen is introduced for purging; 20sccm of trimethylaluminum is introduced; 1.2×20sccm of H 2 O vapor, when trimethylaluminum or H 2 After the O vapor reaction, nitrogen was purged for 10 seconds with a nitrogen purge volume of 50,000 sccm; When preparing the front anti-reflection stack in S8, maintaining the temperature in the range of 400-540°C and under the electric field of 15000W power: 2000sccm of silane and 3000sccm of nitrous oxide were introduced, and ionization was carried out at high temperature for 25s to form the first layer of SiO 2 layer; 5000 sccm silane and 12000 sccm ammonia were introduced and ionized at high temperature for 150 s to form the first SiNx layer; 5000 sccm silane and 14000 sccm ammonia are introduced and ionized at high temperature for 350 seconds to form a second SiNx layer; 5000 sccm silane, 14000 sccm ammonia, and 2000 sccm nitrous oxide were introduced, and ionized at high temperature for 200 s to form the first SiONx layer; 5000 sccm silane, 14000 sccm ammonia, and 2000 sccm nitrous oxide were introduced, and ionization was performed at high temperature for 250 s to form a second SiONx layer; 2000sccm silane and 9000sccm nitrous oxide were introduced, and ionized for 100s at high temperature to form a mask protective layer; In S8, a nitrogen purge of 50,000 sccm was used after each layer was deposited.

[0036] Experimental example The thickness of the front laminated passivation film of the crystalline silicon solar cells obtained in the above-mentioned Example 1, Example 2 and Example 3 was tested, as shown in Table 1.

[0037] The above-mentioned Example 1, Example 2, and Example 3 are now used as experimental examples, and Comparative Examples 1, Comparative Example 2, and Comparative Example 3 are used as references to perform composite losses in electrical losses. The parameters of Comparative Examples 1, Comparative Example 2, and Comparative Example 3 are shown in Table 2, and the performance comparison test data are shown in Table 3.

[0038] Table 2 Parameters of Comparative Example 1, Comparative Example 2, and Comparative Example 3 Table 3 Composite loss table of electrical loss of embodiments and comparative examples It should be noted that, in Table 3: Eta is the photoelectric conversion efficiency, Uoc is the open circuit voltage, Isc is the short circuit current, FF is the fill factor, Rser is the series resistance, Rshunt is the parallel resistance, and Irev2 is the leakage current.

[0039] It can be seen from Table 3 that in terms of Eta light spot conversion efficiency, the values ​​of Examples 1 to 3 are greater than those of Comparative Examples 1 to 3; in terms of Uoc open circuit voltage, the values ​​of Examples 1 to 3 are greater than those of Comparative Examples 1 to 3. This shows that the battery of this solution is superior to the traditional battery.

[0040] It should be noted that the parameters that best reflect electrical loss are Isc and FF. As can be seen from Table 3, the Isc of Examples 1 to 3 is greater than that of Comparative Examples 1 to 3, and the FF of Examples 1 to 3 is greater than that of Comparative Examples 1 to 3. Therefore, the experimental process of this scheme can effectively improve the passivation effect, reduce the composite loss in electrical loss, and improve the current transmission of the battery.

[0041] The above embodiments only express preferred implementation modes, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention.

Claims

1. A process for preparing a front laminated passivation film for a crystalline silicon cell, characterized in that: The following steps are involved: S1. Pretreatment: pretreatment is performed on both sides of the N-type substrate silicon wafer, that is, alkali is used to treat the N-type substrate silicon wafer so that both sides form a velvet surface; S2, P-type doping layer: Boron chloride is introduced to the front of the N-type base silicon wafer, and the boron chloride is decomposed at high temperature and reacted with silicon to generate elemental boron. The boron layer attached to the front of the silicon wafer is a P-type doping layer; the generated elemental boron diffuses into the silicon wafer, forming a PN junction between the P-type doping layer and the N-type base silicon wafer; S3, back side alkali polishing: the back side of the N-type substrate silicon wafer is alkali washed again, and the back side after alkali washing is polished; S4, back-doped polysilicon layer: preparing a tunneling oxide layer and an N-type polysilicon Poly layer on the back of the N-type base silicon wafer, thereby forming a back-doped polysilicon layer; S5, high temperature annealing: using a high temperature tubular annealing furnace to activate the doping atoms; S6, PSG etching + front mask layer removal: Use hydrofluoric acid to process the back side - that is, PSG etching; Use hydrofluoric acid to further process the crystalline silicon cell after PSG etching to remove the front side wrap and mask layer, that is, front mask layer removal processing; S7, preparing an aluminum oxide stack on the front side of the P-type doped layer, reacting in a high temperature environment of 300-320° C., and obtaining an aluminum oxide stack with a thickness of 4-6 nm; First aluminum oxide layer: firstly introduce trimethyl aluminum as an aluminum precursor, react at high temperature for a period of time, then purge with nitrogen, then introduce H2O vapor as an oxidation precursor, react at high temperature for a period of time, then purge with nitrogen, wherein the ratio of trimethyl aluminum to H2O vapor is 1:1.2; keep the temperature, introduction amount, and reaction time unchanged, take "introducing trimethyl aluminum-purging after reaction-introducing H2O vapor-purging after reaction" as one cycle, and perform multiple cycles. After a total of 10 cycles, the first aluminum oxide layer is grown on the front side of the N-type substrate silicon wafer; Second aluminum oxide layer: introduce trimethyl aluminum, react at high temperature for a period of time, then purge with nitrogen, introduce H2O vapor, react at high temperature for a period of time, then purge with nitrogen; after a total of 12 cycles, a second aluminum oxide layer grows on the front side of the first aluminum oxide layer; The third aluminum oxide layer: trimethyl aluminum is introduced, reacted at high temperature for a period of time, and then purged with nitrogen, and then H2O vapor is introduced, reacted at high temperature for a period of time, and then purged with nitrogen; after a total of 14 cycles, a third aluminum oxide layer grows on the front side of the second aluminum oxide layer; S8, preparing a front anti-reflection laminate on the front side of the aluminum oxide laminate, performing an ionization reaction under a high temperature environment at a high temperature of 400-540° C. and an electric field of 8000-17000 W, and the thickness of the prepared front anti-reflection laminate is (1+8+22+10+19+7)-(2.5+15+35+20+25+10) nm; Silane and laughing gas are introduced, and ionization reaction occurs under high temperature to form the first SiO2 layer; Silane and ammonia are introduced to form an ionization reaction at high temperature to form the first SiNx layer; Silane and ammonia are introduced, and ionization reaction is carried out under high temperature environment to form the second SiNx layer; Silane, ammonia and laughing gas are introduced, and ionization reaction is carried out under high temperature environment to form the first SiONx layer; Silane, ammonia and laughing gas are introduced, and ionization reaction is carried out under high temperature environment to form the second SiONx layer; Silane and laughing gas are introduced, and ionization reaction occurs under high temperature environment, eventually forming a mask protective layer; S9, Ag electrode printing, sintering, LECO.

2. The process for preparing the front laminated passivation film for a crystalline silicon cell according to claim 1, characterized in that: In the above S7, when preparing the first aluminum oxide layer, the second aluminum oxide layer, and the third aluminum oxide layer: they are all in a high temperature environment of 300-320°C, and a cycle of "introducing trimethylaluminum-purging after reaction-introducing H2O steam-purging after reaction" is performed; In one cycle: the amount of trimethylaluminum introduced is 18-20 sccm, the reaction time of trimethylaluminum is 7s, and the purge time after the reaction of trimethylaluminum is 10-14s; the amount of H2O steam introduced is 1.2 times 18-20 sccm, the reaction time of H2O steam is 7s, and the purge time after the reaction of H2O steam is 10-14s.

3. The process for preparing the front laminated passivation film for a crystalline silicon cell according to claim 2, characterized in that: The thickness of the aluminum oxide stack obtained in S7 is 4.9 nm, wherein the thickness of the first aluminum oxide layer is 1.5 nm, the thickness of the second aluminum oxide layer is 1.6 nm, and the thickness of the third aluminum oxide layer is 1.8 nm.

4. The process for preparing the front laminated passivation film for a crystalline silicon cell according to claim 3, characterized in that: In the above S8, when preparing the front anti-reflection laminate: When preparing the first SiO2 layer, 500-2000sccm silane and 1000-3000sccm nitrous oxide are introduced, and the ionization reaction is carried out for 10-25s under high temperature environment; the obtained thickness is 1-2.5nm; When preparing the first SiNx layer, 1000-5000sccm silane and 8000-12000sccm ammonia are introduced, and the ionization reaction is carried out for 80-150s under high temperature environment; the obtained thickness is 8-15nm; When preparing the second SiNx layer, 1000-5000sccm silane and 8000-14000sccm ammonia are introduced, and the ionization reaction is carried out for 220-350s under high temperature environment; the obtained thickness is 22-35nm; When preparing the first SiONx layer, 1000-5000sccm silane, 8000-14000sccm ammonia, and 800-2000sccm nitrous oxide are introduced, and the ionization reaction is carried out for 100-200s under high temperature environment; the obtained thickness is 10-20nm; When preparing the second SiONx layer, 1000-5000sccm silane, 8000-14000sccm ammonia, and 800-2000sccm nitrous oxide are introduced, and the ionization reaction is carried out for 190-250s under high temperature environment; the obtained thickness is 19-25nm; When preparing the mask protective layer, 1000-2000sccm silane and 7000-9000sccm nitrous oxide are introduced, and the ionization reaction takes 70-100s under high temperature environment; the obtained thickness is 7-10nm.

5. The process for preparing the front laminated passivation film for a crystalline silicon cell according to claim 4, characterized in that: In the crystalline silicon cell, the thickness of the N-type base silicon wafer is 120-140 um, and the thickness of the P-type doping layer is 0.8-1.2 um.

6. The process for preparing the front laminated passivation film for a crystalline silicon cell according to claim 5, characterized in that: The crystalline silicon cell comprises an N-type base silicon wafer, on the front side of which a P-type doping layer, an aluminum oxide stack, and a front anti-reflection stack are sequentially provided, and on the back side of which a tunneling oxide layer, an N-type polysilicon Poly layer, and a back passivation film stack are sequentially provided.

7. The process for preparing the front laminated passivation film for a crystalline silicon cell according to claim 6, characterized in that: When preparing the back passivation film stack, silane and ammonia are introduced at a high temperature of 400-540°C and an electric field with a power of 8000-17000W to obtain the back passivation film stack under the action of the high temperature electric field.

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