Laminated cell and preparation method thereof

Abstract

The invention discloses a laminated battery, which comprises a bottom battery and a top battery, the bottom battery comprises a silicon substrate with a front surface and a back surface which are opposite to each other, the front surface comprises a first region, a second region, a first groove and a second groove, and the first region, the second region and the first groove respectively comprise a tunneling layer and an N-poly layer; the first region further comprises a conductive layer which is arranged above the N-poly layer; the back surface comprises a third region and a fourth region, the third region and the fourth region comprise passivation layers, and the third region further comprises a tunneling layer and a P-poly layer between the passivation layers and the silicon substrate. According to the invention, the large-size crystal silicon bottom cell is cut into a plurality of small-size bottom cells, so that the small-size bottom cells can be matched with the current small-size perovskite top cell; passivation contact of an emitter is realized by adopting P-poly for the crystalline silicon bottom cell, a relatively high passivation effect is provided, and parasitic absorption is further reduced by thinning an N-poly layer on the front surface of the crystalline silicon bottom cell.

Description

Technical Field

[0001] The present disclosure relates to the field of solar cell manufacturing, and particularly to a tandem cell and a method for preparing the same. Background Art

[0002] Tandem Solar Cells is a battery technology designed to improve solar conversion efficiency. Such a battery usually consists of two or more photovoltaic layers that absorb different wavelength spectra and are stacked together in series. Each photovoltaic layer is optimized to absorb a specific range of the solar spectrum, so that the entire solar spectrum can be utilized more effectively, thereby improving the overall energy conversion efficiency.

[0003] The bottom cell of the tandem cell is usually prepared using pure silver paste or silver-aluminum paste, but there are the following problems in its actual preparation process: If pure silver paste is used, there are few electrons in the emitter, and it is difficult to reduce silver ions, and good Schottky contact cannot be achieved; If silver-aluminum paste is used, aluminum spikes can achieve good conductivity between the metal and the silicon substrate. On the other hand, the existence of aluminum spikes makes the recombination more serious, affecting the Voc of the battery. Therefore, the current industry adopts the leco process, which can prepare the emitter with pure silver paste and, through the bias voltage of the leco process, make enough electrons gather at the Schottky contact of the emitter to achieve the reduction of silver ions and achieve good Schottky contact. At the same time, the heat of the laser also helps the pure silver paste to achieve good Schottky contact.

[0004] However, for perovskite-silicon tandem cells, there is only one grid line in the bottom cell structure. Since the bias voltage of the leco process requires the grid lines on both the front and back sides to be conductive, the perovskite-silicon tandem cell cannot perform the LECO process. Therefore, only the printed paste silver-aluminum paste before the LECO technology can be used, but as mentioned above, this method has a higher recombination rate. Currently, the size of crystalline silicon cells is usually 182*182mm or 210mm large size, and the size of existing perovskite cells is usually small, usually 1*1cm, and the two cannot be matched. If a larger size perovskite cell is used, its stability and energy conversion efficiency will be reduced.

[0005] Therefore, how to reduce the recombination of the emitter and improve the Schottky contact of the emitter in the tandem cell, thereby improving the efficiency of the tandem cell, and adjusting the size of the silicon cell to match the perovskite cell to improve stability and energy conversion efficiency is an urgent problem to be solved. Summary of the Invention

[0006] The present disclosure aims to provide a tandem cell and a method for preparing the same, solve the difficulty that the bottom cell of the tandem cell is difficult to perform the LECO process, provide a higher battery conversion efficiency, and solve the problem that it is difficult to match with the currently smaller perovskite cells.

[0007] To solve the above technical problems, the technical solution adopted in the present disclosure is as follows:

[0008] A stacked battery, comprising a bottom battery and a top battery,

[0009] wherein, the bottom battery includes a silicon substrate, and the silicon substrate includes opposite front and back surfaces;

[0010] The front surface includes a first region, a second region, a first groove and a second groove. Among them, the first region, the second region and the first groove respectively include a tunneling layer and an N-poly layer (N-type doped polysilicon layer). The first groove separates the first region and the second region, and the second groove is located on the periphery of the second region;

[0011] Wherein the first region further includes a conductive layer disposed above the N-poly layer,

[0012] The top battery is stacked above the first region, the second region and the first groove;

[0013] The back surface includes a third region and a fourth region. Among them, the third region corresponds to the first region, and the region outside the third region is the fourth region.

[0014] The third region and the fourth region include a passivation layer. Among them, the third region further includes a tunneling layer and a P-poly layer (P-type doped polysilicon layer) between the passivation layer and the silicon substrate.

[0015] Preferably, the conductive layer is a TCO film layer, which is electrically connected to the top battery.

[0016] Preferably, the passivation layer is a stack of alumina and silicon nitride.

[0017] Preferably, the fourth region further includes a textured structure, and the third region further includes a polishing layer.

[0018] Preferably, the main function of the first groove is to mark the position. When depositing the conductive layer on the first region, it is used to identify the first region. First, the first groove is opened on the silicon substrate, and then the tunneling layer and the N-poly layer are deposited. Therefore, the first region, the groove and the second region all include the tunneling layer and the N-poly layer; the first groove or the second groove penetrates into the silicon substrate by 2-5 microns, and the width of the first groove or the second groove is 30-50 microns.

[0019] Preferably, the thickness of the N-poly layer is less than 100 nm.

[0020] In the above text, the reserved second region can, on the one hand, avoid secondary passivation of the edge of the cut crystalline silicon bottom battery, and on the other hand, facilitate the clamping of the top battery by the top battery fixture to avoid contamination of the top battery.

[0021] Preferably, a first groove provided between the first region and the second region forms an isolation region between the first region and the second region, thereby avoiding side contact between the top cell and the bottom cell and causing leakage. The top cell is prepared on the front surface of the silicon substrate, and only the first groove is an effective region. From top to bottom in the first groove are a top cell, a TCO film layer, an N-poly layer, a tunneling layer, a silicon substrate, a tunneling layer, a P-poly layer, an AlOx layer, and a SiNx layer.

[0022] Preferably, the preparation method of the bottom cell includes the following steps:

[0023] Step S1, primary polishing: The silicon substrate is polished on both sides.

[0024] Step S2, P1 laser: A plurality of the first grooves and second grooves are formed on the silicon substrate by a P1 laser. There is a certain distance between adjacent second grooves, and the region formed between adjacent second grooves is an ineffective region; the first groove is used to mark the boundary of the first region, corresponding to the edge of the first region, and the second groove is used to mark the boundary of the cutting region, corresponding to the edge of the second region; the depth of the first groove or the second groove is 2-5 microns, and the width is 30-50 microns.

[0025] Step S3, P-poly preparation: Single insertion is adopted to prepare a P-poly layer and borosilicate glass on both sides of the silicon substrate.

[0026] Step S4, P2 laser: The P2 laser is used to pattern the back surface of the crystalline silicon bottom cell prepared in step S3.

[0027] Step S5, front surface borosilicate glass removal: The crystalline silicon bottom cell prepared in step S4 is passed through a chain acid pickling machine to remove the borosilicate glass on the front surface of the crystalline silicon bottom cell.

[0028] Step S6, P2 cleaning: The P-poly layer without borosilicate glass protection on the crystalline silicon bottom cell is removed by P2 cleaning.

[0029] Step S7, N-poly preparation: Single insertion is adopted to prepare phosphosilicate glass and an N-poly layer with a thickness of less than 100 nm on both sides of the crystalline silicon bottom cell.

[0030] Step S8, back surface P3 laser PSG removal: The phosphosilicate glass on the back surface of the crystalline silicon bottom cell is removed.

[0031] Step S9, P3 cleaning: The N-poly layer on the back surface of the crystalline silicon bottom cell is removed, and at the same time, the borosilicate glass and phosphosilicate glass on both sides are removed. A textured structure is formed on the silicon substrate in the fourth region by trough alkaline texturing.

[0032] Step S10, ALD: Deposit aluminum oxide on both sides of the crystalline silicon bottom cell to form an AlOx layer; the aluminum oxide deposited on the front side of the crystalline silicon bottom cell serves as a sacrificial layer for passivation;

[0033] Step S11, coating: Deposit SiNx on the back side of the crystalline silicon bottom cell to form a SiNx layer;

[0034] Step S12, cleaning: Remove the aluminum oxide on the N-poly layer with hydrochloric acid;

[0035] Step S13, printing: Print a back grid on the P-poly layer to form the positive electrode of the bottom cell, and obtain a crystalline silicon cell;

[0036] Step S14, cutting: Cut the crystalline silicon cell prepared in Step S12 along the second groove to make a plurality of the bottom cells.

[0037] Preferably, in Step S4, the borosilicate glass in the fourth region is modified by laser to facilitate the removal of the borosilicate glass and P-poly in this region by wet method in Step S6.

[0038] This application also claims to protect a preparation method of a stacked cell, including the following steps:

[0039] Step S15, deposit the conductive layer in the first region,

[0040] Step S16, prepare the top cell on the front side of the bottom cell.

[0041] Preferably, before Step S15, it also includes removing the N-poly layer in the second region to further reduce the parasitic absorption on the front side of the bottom cell.

[0042] Preferably, in Step S3, replace the single insertion with a double insertion, and only prepare the P-poly layer on the back side of the crystalline silicon bottom cell.

[0043] Preferably, the method for preparing the N-poly layer with a thickness of less than 100 nm (preferably less than 40 nm) in Step S6 includes at least one of reducing the deposition time or adopting a thinning process.

[0044] Preferably, the size of the bottom cell is larger than the size of the effective area of the top cell, and the size of the effective area is preferably 10*10 mm.

[0045] Preferably, the size of the bottom cell includes 20*20 mm to 40*40 mm, and more preferably 25*25 mm.

[0046] Preferably, in Step S3, the patterning on the back side of the cell includes retaining the borosilicate glass in the first region and removing the borosilicate glass in the second region;

[0047] Either retain the borosilicate glass in the first region and the second region, and operate a laser to remove the borosilicate glass in the first groove between the first region and the second region;

[0048] Or only remove the borosilicate glass in the first groove between the first region and the second region, and retain the borosilicate glass in other regions.

[0049] Preferably, in step S2, before preparing the P-poly, a tunneling layer also needs to be prepared on both sides of the crystalline silicon bottom cell.

[0050] Due to the application of the above technical solutions, the beneficial effects of the present disclosure compared with the prior art are as follows:

[0051] (1) By cutting a relatively large-sized crystalline silicon bottom cell into several small-sized bottom cells, this application can solve the problem of being difficult to match with the currently smaller-sized perovskite top cell, ensuring that the stability and energy conversion efficiency of the perovskite top cell are not affected;

[0052] (2) Through the thinning of the N-poly layer on the front side of the crystalline silicon bottom cell, this application further reduces parasitic absorption. The thinner polysilicon layer reduces the absorption of incident light, enabling more photons to reach the base silicon of the cell, thereby generating more photo-generated carriers, further increasing the short-circuit current, and improving the overall efficiency and photoelectric conversion efficiency of the cell.

[0053] (3) By designing the P-poly structure to improve the crystalline silicon bottom cell of the perovskite / crystalline silicon tandem cell, this application realizes the passivated contact of the emitter by adopting P-poly for the crystalline silicon bottom cell, solves the problem that it is difficult to perform the LECO process on the crystalline silicon bottom cell of the perovskite / crystalline silicon tandem cell, and at the same time provides a high passivation effect, which can reduce its recombination with the paste and can also achieve good Schottky contact through the heavily doped P-poly. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0055] Figure 1 It is a schematic structural diagram of a tandem cell in Embodiment 1 of the present disclosure; among them, 1(a) is a schematic structural diagram of the back side of the uncut tandem cell; 1(b) is a schematic structural diagram of the back side of the cut tandem cell;

[0056] Figure 2 It is a schematic structural diagram of the front side of the cut tandem cell in Embodiment 2 of the present disclosure;

[0057] Figure 3 This is a schematic diagram of the preparation process of the crystalline silicon bottom cell in a stacked cell in Embodiment 3 of the present disclosure.

[0058] Explanation of the reference numerals:

[0059] 1 - Bottom cell; 2 - Top cell; 3 - Silicon substrate; 4 - First region; 5 - Second region; 6 - First groove; 7 - Second groove; 8 - Third region; 9 - Fourth region; 10 - Invalid region; 11 - TCO film layer; 12 - N-poly layer. Detailed implementation manners

[0060] In order to enable those skilled in the art to better understand the solution of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0061] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to describe the embodiments of the present disclosure here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0062] In the present disclosure, the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal", etc. is based on the orientation or positional relationship shown in the accompanying drawings. These terms are mainly used to better describe the present disclosure and its embodiments, and are not used to limit that the indicated devices, elements or components must have a specific orientation or be constructed and operated in a specific orientation.

[0063] Moreover, in addition to being able to represent the orientation or positional relationship, some of the above terms may also be used to represent other meanings. For example, the term "upper" may also be used to represent a certain attachment relationship or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in the present disclosure can be understood according to specific circumstances.

[0064] It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0065] Embodiment 1

[0066] Please refer to Figure 1 and Figure 2 , a stacked battery, including a bottom battery 1 and a top battery 2,

[0067] wherein, the bottom battery includes a silicon substrate 3, and the silicon substrate includes opposite front and back surfaces; wherein, exemplarily, the silicon substrate is an N-type single-crystalline silicon substrate, and the N-type doping is doping with VA group elements such as phosphorus, arsenic or antimony, having a high carrier mobility (>1400 cm 2 / Vs) and a low bulk resistivity (0.001 - 10 Ω·cm).

[0068] The front surface includes a first region 4, a second region 5, a first groove 6 and a second groove 7, wherein the first region, the second region and the first groove respectively include a tunneling layer and an N-poly layer 12, the first groove separates the first region and the second region, and the second groove is located outside the second region;

[0069] wherein the first region further includes a conductive layer disposed above the N-poly layer,

[0070] The top battery is stacked above the first region, the second region and the first groove;

[0071] The back surface includes a third region 8 and a fourth region 9, wherein the third region corresponds to the first region, and the region outside the third region is the fourth region,

[0072] The third region and the fourth region include a passivation layer, and the third region further includes a tunneling layer and a P-poly layer between the passivation layer and the silicon substrate.

[0073] Preferably, the top battery is a perovskite battery, and the perovskite battery is a p-i-n type inverted perovskite battery layer. Among them, the p-i-n type inverted perovskite battery layer is composed of three parts. The bottom layer is a hole transport layer for collecting and transporting holes; the middle is an intrinsic (i) perovskite light-absorbing layer that can absorb photons to generate electron-hole pairs; the top is an electron transport layer responsible for collecting and transporting electrons.

[0074] Preferably, the tunneling layer on the front side of the crystalline silicon bottom cell is composed of an ultra-thin silicon oxide layer between the silicon substrate and the N-poly layer. The ultra-thin oxide layer allows majority electrons to tunnel into the polysilicon layer while blocking the recombination of minority holes, thereby improving the open-circuit voltage and short-circuit current of the cell.

[0075] Preferably, the tunneling layer on the back side of the crystalline silicon bottom cell is composed of an ultra-thin silicon oxide layer between the silicon substrate and the P-poly layer. The ultra-thin oxide layer allows majority electrons to tunnel into the polysilicon layer while blocking the recombination of minority holes, thereby improving the open-circuit voltage and short-circuit current of the cell.

[0076] Preferably, the conductive layer is the TCO film layer 11.

[0077] Preferably, the passivation layer is a stack of alumina and silicon nitride.

[0078] Preferably, the fourth region further includes a textured structure, and the third region further includes a polishing layer.

[0079] Preferably, the first groove or the second groove penetrates into the silicon substrate by 2 - 5 microns, and the width of the first groove or the second groove is 30 - 50 microns.

[0080] Preferably, the thickness of the N-poly layer is less than 100 nm, preferably less than 40 nm, for example, any value between 0 - 40 nm. In this embodiment, preparing a thinner N-poly layer can reduce the parasitic absorption of N-poly. The thinner polysilicon layer reduces the absorption of incident light, enabling more photons to reach the base silicon of the cell, thereby generating more photo-generated carriers, and further increasing the short-circuit current (Isc). At the same time, the ultra-thin polysilicon layer can improve the contact performance of the cell, reduce the contact resistance (Rs), thereby reducing the loss during the power transmission process, improving the overall efficiency of the cell. Reducing parasitic absorption and optimizing the contact resistance contribute to improving the fill factor (FF) of the cell, further enhancing the photoelectric conversion efficiency of the cell. In addition, the thinner polysilicon layer can reduce the recombination current density (J0) while maintaining good passivation performance, thereby reducing the carrier recombination rate and further increasing the open-circuit voltage (Voc) of the cell.

[0081] In the above text, the reserved second region can, on the one hand, avoid secondary passivation of the edges of the cut crystalline silicon bottom cells, and on the other hand, facilitate the clamping of the top cell by the top cell fixture, avoiding contamination of the top cell.

[0082] Preferably, a first groove is provided between the first region and the second region, so that the first region and the second region form an isolation region, thereby avoiding side contact between the top cell and the bottom cell, which may cause leakage. The top cell is fabricated on the front surface of the silicon substrate, and only the first groove is the effective region. From top to bottom in the first groove are the top cell, the TCO film layer, the N-poly layer, the tunneling layer, the silicon substrate, the tunneling layer, the P-poly layer, the AlOx layer, and the SiNx layer.

[0083] Example 2

[0084] This embodiment is based on the above Embodiment 1, and the same parts as those in the above Embodiment 1 will not be described in detail.

[0085] As Figure 3 shown, this embodiment relates to a method for fabricating the bottom cell, including the following steps:

[0086] Step S1, primary polishing: Double-sided polish the silicon substrate.

[0087] Step S2, P1 laser: Form a plurality of the first grooves and second grooves on the silicon substrate. There is a certain distance between adjacent second grooves, and the area formed between adjacent second grooves is the ineffective region 10. The first groove is used to mark the boundary of the first region, corresponding to the edge of the first region, and the second groove is used to mark the boundary of the cutting region, corresponding to the edge of the second region. The depth of the first groove or the second groove is 2 - 5 microns, and the width is 30 - 50 microns.

[0088] Step S3, P-poly preparation: Adopt single insertion to fabricate the P-poly layer and borosilicate glass on both sides of the silicon substrate.

[0089] Step S4, P2 laser: Use the P2 laser to perform backside patterning on the crystalline silicon bottom cell prepared in Step S3.

[0090] Step S5, front-side removal of borosilicate glass: Pass the crystalline silicon bottom cell prepared in Step S4 through a chain acid pickling machine to remove the borosilicate glass on the front side of the crystalline silicon bottom cell.

[0091] Step S6, P2 cleaning: Remove the P-poly layer on the crystalline silicon bottom cell that is not protected by borosilicate glass through P2 cleaning.

[0092] Step S7, N-poly preparation: Adopt single insertion to fabricate phosphosilicate glass and an N-poly layer with a thickness less than 40 nm on both sides of the crystalline silicon bottom cell.

[0093] Step S8, backside P3 laser removal of PSG: Remove the phosphosilicate glass on the back side of the crystalline silicon bottom cell.

[0094] Step S9, P3 cleaning: Remove the N-poly layer on the back of the crystalline silicon bottom cell, and at the same time remove the borosilicate glass and phosphosilicate glass on both sides. A textured structure is formed on the silicon substrate in the fourth region by means of trough alkaline texturing;

[0095] Step S10, ALD: Deposit aluminum oxide on both sides of the crystalline silicon bottom cell to form an AlOx layer; The aluminum oxide deposited on the front of the crystalline silicon bottom cell is used as a sacrificial layer for passivation;

[0096] Step S11, coating: Deposit SiNx on the back of the crystalline silicon bottom cell to form a SiNx layer;

[0097] Step S12, cleaning: Remove the aluminum oxide on the N-poly layer with hydrochloric acid;

[0098] Step S13, printing: Print a back grid on the P-poly layer to form the positive electrode of the bottom cell, and obtain a crystalline silicon cell;

[0099] Step S14, cutting: Cut the crystalline silicon cell prepared in Step S12 along the second groove to make a plurality of the bottom cells.

[0100] Preferably, in Step S3, replace the single insertion with a double insertion, and prepare the P-poly layer only on the back of the crystalline silicon bottom cell.

[0101] Preferably, in Step S4, laser modify the borosilicate glass in the fourth region to facilitate the removal of the borosilicate glass and P-poly in this region by wet method in Step S6.

[0102] Preferably, the method for preparing the N-poly layer with a thickness less than 100 nm in Step S6 includes at least one of reducing the deposition time or adopting a thinning process.

[0103] Preferably, the size of the bottom cell is larger than the size of the effective area of the top cell, and the size of the effective area is preferably 10*10 mm.

[0104] Preferably, the size of the bottom cell includes 20*20 mm to 40*40 mm, and more preferably 25*25 mm.

[0105] Preferably, in Step S3, the patterning on the back of the cell includes retaining the borosilicate glass in the first region and removing the borosilicate glass in the second region.

[0106] Preferably, in Step S2, before preparing the P-poly, it is also necessary to prepare a tunneling layer on both sides of the crystalline silicon bottom cell.

[0107] Example 3

[0108] This example is based on the above Example 2, and the same parts as the above Example 1 will not be elaborated.

[0109] In this embodiment, in step S3 of the preparation method of the crystalline silicon bottom cell in the stacked cell, the patterning of the back surface of the cell includes retaining the borosilicate glass in the first region and the second region, removing the borosilicate glass in the third region, and operating a laser to remove the borosilicate glass in the fourth region between the first region and the second region;

[0110] Or only remove the borosilicate glass in the fourth region between the first region and the second region, and retain the borosilicate glass in other regions.

[0111] Example 4

[0112] This embodiment is based on the above-mentioned embodiment 2, and the same parts as the above-mentioned embodiment 1 will not be repeated.

[0113] This embodiment relates to a preparation method of a stacked cell including the bottom cell described in Embodiment 2, and includes the following steps:

[0114] Step S15, depositing the conductive layer in the first region,

[0115] Step S16, preparing the top cell on the front surface of the bottom cell.

[0116] Preferably, before the step S15, it further includes removing the N-poly layer in the second region to further reduce the parasitic absorption on the front surface of the bottom cell.

[0117] In one embodiment, the perovskite cell layer is a p-i-n type inverted perovskite cell layer. Exemplarily, its preparation process may include the preparation of a hole transport layer (HTL): placing a crystalline silicon cell in a vacuum coating equipment and depositing a layer of p-type semiconductor material, such as nickel oxide (NiO), as the hole transport layer on the surface of the crystalline silicon cell by physical vapor deposition methods, such as thermal evaporation or sputtering, and precisely controlling the deposition rate and thickness; the preparation of the perovskite light-absorbing layer: using the solution spin-coating method to drop the perovskite precursor solution on the crystalline silicon cell with the deposited hole transport layer, and forming a uniform perovskite thin film by controlling the spin-coating speed, time, and solution concentration, and then annealing at a certain temperature to make the precursor fully react to form a high-quality perovskite light-absorbing layer; the preparation of the electron transport layer (ETL): preparing the electron transport layer on the perovskite layer by solution spin-coating or atomic layer deposition method. First, prepare a C60 thin film by evaporation method, and then deposit tin oxide (SnO) by atomic layer deposition technology, and control the process parameters to ensure the uniformity and performance of the thin film; the preparation of the electrode: depositing a metal electrode, such as evaporating gold (Au) or silver (Ag), etc. as the top electrode on the electron transport layer by thermal evaporation and other methods, and then performing encapsulation treatment, using encapsulation materials such as glass cover plates and encapsulation adhesives to seal the battery to prevent damage to the battery caused by moisture and oxygen, etc. It can be understood that other materials and other process flows can also be used for the preparation of the perovskite cell layer, and the present application does not make any restrictions.

[0118] Finally, it should be noted that the above are only the preferred embodiments of the present disclosure and are not used to limit the present disclosure. Although the present disclosure has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A laminated battery, characterized in that: Including bottom battery and top battery, Wherein, the bottom cell comprises a silicon substrate, and the silicon substrate comprises a front side and a back side opposite to each other; The front surface includes a first area, a second area, a first groove and a second groove, wherein the first area, the second area and the first groove respectively include a tunneling layer and an N-poly layer, the first groove separates the first area and the second area, and the second groove is located at the periphery of the second area; The first region further includes a conductive layer disposed above the N-poly layer, The top battery is stacked above the first region, the second region and the first groove; The back side includes a third area and a fourth area, wherein the third area corresponds to the first area, and the area outside the third area is the fourth area. The third region and the fourth region include a passivation layer, wherein the third region further includes a tunneling layer and a P-poly layer between the passivation layer and the silicon substrate.

2. A laminated battery as claimed in claim 1, characterized in that: The conductive layer is a TCO film layer.

3. A laminated battery as claimed in claim 1, characterized in that: The passivation layer is a stack of aluminum oxide and silicon nitride.

4. A laminated battery as claimed in claim 1, characterized in that: The fourth region further includes a suede structure, and the third region further includes a polishing layer.

5. A laminated battery as claimed in claim 1, characterized in that: The first groove is 2-5 microns deep into the silicon substrate, and the width of the first groove is 30-50 microns.

6. A laminated battery as claimed in claim 1, characterized in that: The thickness of the N-poly layer is less than 40 nm.

7. A laminated battery as claimed in claim 1, characterized in that: The preparation method of the bottom battery comprises the following steps: Step S1, primary polishing: double-sided polishing of the silicon substrate; Step S2, using a P1 laser to form a plurality of the first grooves and the second grooves on the silicon substrate, with a certain distance between adjacent second grooves, and the area between adjacent second grooves being an invalid area; Step S3, P-poly preparation: adopt single insertion to prepare P-poly layer and borosilicate glass on both sides of the silicon substrate; Step S4, P2 laser: using P2 laser to pattern the back side of the crystalline silicon bottom cell prepared in step S3; Step S5, removing borosilicate glass from the front: passing the crystalline silicon bottom battery prepared in step S4 through a chain pickling machine to remove the borosilicate glass on the front of the crystalline silicon bottom battery; Step S6, P2 cleaning: P2 cleaning is used to remove the P-poly layer on the crystalline silicon bottom cell that is not protected by borosilicate glass; Step S7, N-poly preparation: adopt single insertion to prepare phosphorus silicon glass and N-poly layer with thickness less than 40nm on both sides of the crystalline silicon bottom cell; Step S8, laser removal of PSG on the back P3: removing the phosphorus silicon glass on the back of the crystalline silicon bottom cell; Step S9, P3 cleaning: remove the N-poly layer on the back of the crystalline silicon bottom cell, and remove the borosilicate glass and phosphorus silicon glass on both sides, and form a velvet structure on the silicon substrate in the fourth area by tank alkali texturing; Step S10, ALD: depositing aluminum oxide on both sides of the crystalline silicon bottom cell to form an AlOx layer; the aluminum oxide deposited on the front side of the crystalline silicon bottom cell is used as a sacrificial layer for passivation; Step S11, coating: depositing SiNx on the back side of the crystalline silicon bottom cell to form a SiNx layer; Step S12, cleaning: using hydrochloric acid to remove the aluminum oxide on the N-poly layer; Step S13, printing: printing a back grid on the P-poly layer to form the positive electrode of the bottom battery, thereby obtaining a crystalline silicon battery; Step S14, cutting: cutting the crystalline silicon cell prepared in step S12 along the second groove to produce a plurality of bottom cells.

8. A laminated battery as claimed in claim 7, characterized in that: In step S3, the single insertion is replaced by the double insertion, and the P-poly layer is prepared only on the back side of the crystalline silicon bottom cell.

9. A laminated battery as claimed in claim 7, characterized in that: The method of preparing the N-poly layer with a thickness less than 100 nm in step S6 includes at least one of reducing the deposition time or adopting a thinning process.

10. A method for preparing a laminated battery, characterized in that: The method for preparing the laminated battery according to any one of claims 1 to 9 comprises the following steps: Step S15, depositing the conductive layer in the first region, Step S16, preparing the top cell on the front side of the bottom cell.

11. The method for preparing a laminated battery according to claim 10, characterized in that: Before step S15, the method further includes removing the N-poly layer in the second region.

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