Semiconductor device

Abstract

The invention discloses a semiconductor device. A capacitor contact plug is arranged on a substrate; a lower electrode is arranged on the capacitor contact plug; a supporting structure is arranged on the outer side wall of the lower electrode, the supporting structure comprises a top supporting structure for supporting the upper area of the lower electrode, the top supporting structure at least comprises a first supporting layer and a second supporting layer, and the lower surface of the first supporting layer is arranged to be in contact with the upper surface of the second supporting layer; the contact interface of the first supporting layer and the second supporting layer is lower than the top of the lower electrode, and the upper surface of the first supporting layer is higher than the top of the lower electrode; and a capacitor dielectric layer covering the lower electrode and the supporting structure and an upper electrode covering the capacitor dielectric layer are formed. The extension height of the lower electrode in the vertical direction is met, the electric leakage rate is reduced, the supporting structure at the position needing to be reserved is prevented from being damaged in the patterning process of the top supporting structure, and the stability of the lower electrode and the performance of the semiconductor device can be improved.

Description

[0001] This application is a divisional application of Chinese Patent CN202010788768.5 with the application date of August 7, 2020 and the title of "A Capacitor Structure, a Semiconductor Device and a Method for Preparing a Capacitor Structure". Technical Field

[0002] This application relates to the field of semiconductor technology, and particularly to a semiconductor device. Background Art

[0003] As a semiconductor storage device, capacitors are continuously miniaturized with the progress of manufacturing processes and requirements in the prior art. To ensure the storage capacity of capacitors on the basis of miniaturization, it is usually necessary to extend the electrode in the direction perpendicular to the substrate, such as setting a columnar lower electrode. However, setting a lower electrode extended in the vertical direction is likely to cause the lower electrode to tilt or bend. Therefore, a support structure needs to be provided outside the lower electrode to prevent the lower electrode from deforming.

[0004] In the prior art, carbon-containing materials are usually used as the support layer of the lower electrode. However, the carbon-containing support layer will react during the subsequent deposition of the high-order dielectric layer, causing carbon pollution and resulting in a high leakage rate of the capacitor. When using non-carbon-containing materials as the support layer of the lower electrode, the etching solution has a relatively high etching rate for the non-carbon-containing support layer. Therefore, during the patterning process of the top support structure of the lower electrode, the structure of the support layer will be damaged, affecting the structural stability of the capacitor and resulting in poor performance of the semiconductor storage device. Summary of the Invention

[0005] The technical problem to be solved by this application is: how to improve the structural stability of the capacitor structure and the performance of the semiconductor device.

[0006] To solve the above technical problem, this application provides a semiconductor device.

[0007] In the first aspect of this application, a semiconductor device is provided, which includes:

[0008] A substrate;

[0009] A capacitor contact plug located on the substrate;

[0010] A lower electrode located on the capacitor contact plug;

[0011] A support structure, the support structure being located on the outer sidewall of the lower electrode. Among them, the support structure includes a top support structure that supports the upper region of the lower electrode. The top support structure at least includes a first support layer and a second support layer made of a material different from that of the first support layer. The lower surface of the first support layer is in contact with the upper surface of the second support layer, and the contact interface between the first support layer and the second support layer is lower than the top of the lower electrode, and the upper surface of the first support layer is higher than the top of the lower electrode;

[0012] A capacitive dielectric layer, the capacitive dielectric layer covering the lower electrode and the support structure; and

[0013] An upper electrode, the upper electrode covering the capacitive dielectric layer.

[0014] On the other hand, the present application provides a semiconductor device, which includes:

[0015] A substrate;

[0016] A capacitive contact plug, located on the substrate;

[0017] A lower electrode, located on the capacitive contact plug;

[0018] A support structure, the support structure being located on the outer sidewall of the lower electrode. Among them, the support structure includes a top support structure that supports the upper region of the lower electrode. The top support structure at least includes a first support layer and a second support layer made of a material different from that of the first support layer. The lower surface of the first support layer is in contact with the upper surface of the second support layer;

[0019] A capacitive dielectric layer, the capacitive dielectric layer covering the lower electrode and the support structure. Among them, the sidewall of the first support layer is simultaneously in contact with the outer sidewall of the lower electrode and the capacitive dielectric layer; and

[0020] An upper electrode, the upper electrode covering the capacitive dielectric layer.

[0021] Optionally, the thickness of the second support layer is 3 to 7 times the thickness of the first support layer.

[0022] Optionally, the first support layer includes: silicon carbonitride, silicon carbon oxide, or silicon carbon oxynitride; the second support layer includes: silicon oxide, silicon nitride, or silicon oxynitride.

[0023] Optionally, the top support structure further includes a third support layer made of a material different from that of the second support layer. The upper surface of the third support layer is in contact with the upper surface of the second support layer.

[0024] Optionally, the thickness of the third support layer is less than the thicknesses of the first support layer and the second support layer.

[0025] Optionally, the support structure further includes an intermediate support structure for supporting the intermediate region of the lower electrode, wherein the intermediate support structure includes at least a fourth support layer.

[0026] Optionally, the fourth support layer includes: silicon oxide, silicon nitride, or silicon oxynitride.

[0027] Optionally, the substrate includes a cell array region and a peripheral circuit region. A cell array transistor is disposed in the cell array region, and a peripheral circuit transistor is disposed in the peripheral circuit region. Dielectric layers are disposed between the substrate and the lower electrode and between the substrate and the upper electrode. The capacitive contact plug is located in the dielectric layer for electrically connecting the lower electrode and the substrate.

[0028] Compared with the prior art, one or more embodiments of the above solutions may have the following advantages or beneficial effects:

[0029] In the semiconductor device provided by the present application, a support structure is disposed on the outer sidewall of the lower electrode. The support structure includes a top support structure for supporting the upper region of the lower electrode. The top support structure includes at least a first support layer and a second support layer made of a material different from that of the first support layer. The lower surface of the first support layer is configured to contact the upper surface of the second support layer, and the contact interface between the first support layer and the second support layer is lower than the top of the lower electrode, and the upper surface of the first support layer is higher than the top of the lower electrode. Then, a capacitive dielectric layer covering the lower electrode and the support structure and an upper electrode covering the capacitive dielectric layer are formed. By applying the capacitive structure and the semiconductor device provided by the present application, the leakage rate can be reduced while satisfying the height of the lower electrode extending in the vertical direction. In addition, by providing the first support layer and the second support layer made of different materials and forming the contact surface between the first support layer and the second support layer lower than the top of the lower electrode, it is possible to avoid damage to the support structure at the position to be reserved during the patterning process of the top support structure of the lower electrode, and the stability of the lower electrode can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The scope of the present disclosure can be better understood by reading the following detailed description of the exemplary embodiments in conjunction with the accompanying drawings. The accompanying drawings included are:

[0031] Figure 1 Showing a cross-sectional structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0032] Figure 2 Showing a cross-sectional structural schematic diagram of a capacitive structure provided by an embodiment of the present application;

[0033] Figure 3Shows a schematic cross-sectional structure diagram of another capacitor structure provided by an embodiment of the present application;

[0034] Figure 4 Shows a schematic cross-sectional structure diagram of another capacitor structure provided by an embodiment of the present application;

[0035] Figure 5 Shows a schematic cross-sectional structure diagram of an intermediate support structure provided by an embodiment of the present application;

[0036] Figures 6 to 12 Shows schematic cross-sectional structure diagrams corresponding to each step of a method for fabricating a capacitor structure provided by an embodiment of the present application. Detailed implementation manners

[0037] To make the objectives, technical solutions, and advantages of the present application clearer, the following will describe in detail the implementation methods of the present application in conjunction with the accompanying drawings and embodiments, so as to fully understand how the present application uses technical means to solve technical problems and achieve the implementation process of technical effects and implement accordingly.

[0038] It should be noted that unless otherwise defined, the technical terms or scientific terms used in the present application should have the ordinary meanings understood by those of ordinary skill in the field to which the present application belongs. The "first", "second", and similar terms used in the present application do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. The terms such as "upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0039] In the prior art, carbon-containing materials are usually used as the support layer of the lower electrode of the capacitor. However, the carbon-containing support layer will react with ozone during the subsequent deposition of the high-order dielectric layer, causing carbon pollution and resulting in a high leakage rate of the capacitor. When a carbon-free material is used as the support layer of the lower electrode, the etching solution has a relatively high etching rate for the carbon-free support layer. Therefore, during the patterning process of the top support structure of the lower electrode, the structure of the support layer will be damaged, affecting the structural stability of the capacitor.

[0040] In view of this, the present application provides a capacitor structure, a semiconductor device, and a method for manufacturing a capacitor structure. By providing a support structure on the outer sidewall of the lower electrode of the columnar structure, wherein the support structure includes a top support structure for supporting the upper region of the lower electrode, the top support structure at least includes a first support layer and a second support layer made of a material different from that of the first support layer. The lower surface of the first support layer is arranged to contact the upper surface of the second support layer, and the contact interface between the first support layer and the second support layer is lower than the top of the lower electrode, and the upper surface of the first support layer is higher than the top of the lower electrode; a capacitor dielectric layer covering the lower electrode and the support structure and an upper electrode covering the capacitor dielectric layer are then formed. Applying the capacitor structure and the semiconductor device provided by the present application can reduce the leakage rate while satisfying the height of the lower electrode extending in the vertical direction. In addition, by providing the first support layer and the second support layer with different materials and forming the contact surface between the first support layer and the second support layer lower than the top of the lower electrode, it is possible to avoid damage to the support structure at the position to be reserved during the patterning process of the top support structure of the lower electrode, and effectively improve the stability of the lower electrode.

[0041] Embodiment 1

[0042] See Figure 2 as shown Figure 2 The cross-sectional structural schematic diagram of a capacitor structure provided by an embodiment of the present application is shown, which includes:

[0043] Lower electrode 11, the lower electrode 11 has a columnar structure;

[0044] Support structure 12, the support structure 12 is located on the outer sidewall of the lower electrode 11. Among them, the support structure 12 includes a top support structure for supporting the upper region of the lower electrode 11. The top support structure at least includes a first support layer 121 and a second support layer 122 made of a material different from that of the first support layer 121. The lower surface of the first support layer 121 contacts the upper surface of the second support layer 122, and the contact interface between the first support layer 121 and the second support layer 122 is lower than the top of the lower electrode 11, and the upper surface of the first support layer 121 is higher than the top of the lower electrode 11;

[0045] Capacitor dielectric layer 13, the capacitor dielectric layer 13 covers the lower electrode 11 and the support structure 12; and

[0046] Upper electrode 14, the upper electrode 14 covers the capacitor dielectric layer 13.

[0047] In the embodiments of the present application, the capacitive structure may be disposed on a substrate. The lower electrode 11 may be a columnar structure. Specifically, the lower electrode 11 may be formed by a bottom surface and sidewalls extending in a direction perpendicular to the substrate. By extending in a direction perpendicular to the substrate, the surface area of the lower electrode 11 can be increased, thereby effectively improving the storage capacity of the capacitive structure. It should be noted that the sidewalls of the lower electrode 11 may be set perpendicular to the substrate surface or may be set to have a certain inclination angle in a direction perpendicular to the substrate surface. In the embodiments of the present application, the lower electrode with sidewalls extending in a direction perpendicular to the substrate is taken as an example for description.

[0048] As an example, the lower electrode 11 may be formed of at least one material selected from metals, metal nitrides, and metal silicides. As a specific example, titanium nitride may be used as the lower electrode 11.

[0049] The support structure 12 may include a top support structure that supports the upper region of the lower electrode 11. The top support structure can prevent the top of the lower electrode 11 from bending. In the embodiments of the present application, the top support structure at least includes a first support layer 121 and a second support layer 122 made of a material different from that of the first support layer 121. Figure 1 exemplarily shows that the top support structure only includes one layer of the first support layer 121 and one layer of the second support layer 122. In the following embodiments, the description will also be based on Figure 1 the top support structure shown. Among them, the first support layer 121 may be selected from materials with a low etching rate, and the second support layer may be selected from materials without carbon. As an example, the first support layer 121 may include silicon carbonitride, silicon oxycarbide, or silicon carbonitride oxide, and the second support layer 122 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0050] In addition, in order not to affect the structural stability of the capacitor structure, the lower surface of the first support layer 121 is in contact with the upper surface of the second support layer 122, and the contact interface between the first support layer 121 and the second support layer 122 is lower than the top of the lower electrode 11, and the upper surface of the first support layer 121 is higher than the top of the lower electrode 11. With such a setting, on the one hand, while meeting the height of the lower electrode extending in the vertical direction, it is possible to reduce the carbon pollution caused by the reaction between the carbon-containing support structure and ozone when the support structure 12 is exposed to the ozone environment during the subsequent deposition process of the capacitor dielectric layer 13, thereby effectively improving the problem of high leakage rate of the capacitor structure caused by carbon pollution; on the other hand, by setting the lower surface of the first support layer 121 to be in contact with the upper surface of the second support layer 122 and making the contact interface lower than the top surface of the lower electrode 11, and the upper surface of the first support layer 121 higher than the top of the lower electrode 11, the first support layer 121 plays a role in protecting the second support layer 122, so as to prevent the second support layer 122 from being severely deformed due to its relatively weak etching rate when etching the grooves of the lower electrode 11 or the dielectric layer between adjacent lower electrodes 11, which seriously affects the structural stability of the capacitor structure.

[0051] As an optional example, in order to improve the stability of the capacitor structure and at the same time improve the performance of the capacitor structure, the thickness of the second support layer 122 can be set to 3 to 7 times the thickness of the first support layer 121.

[0052] The capacitor dielectric layer 13 can include at least one of an oxide, a nitride, or a high-order dielectric material, and a conductive material can be deposited on the capacitor dielectric layer 13 as the upper electrode 14. It should be noted that the upper electrode 14 can be set to conformally cover the capacitor dielectric layer 13 and fill the region between adjacent lower electrodes 11 provided with the support structure 12, wherein the upper electrode 14 is isolated from the lower electrode 11 and the support structure 12 by the capacitor dielectric layer 13. For details, please refer to Figure 2 shown.

[0053] The above is a capacitance structure provided by an embodiment of the present application. By setting the top support structure on the outer sidewall of the lower electrode 11 to include a first support layer 121 and a second support layer 122 made of a material different from that of the first support layer 121, the lower surface of the first support layer 121 is in contact with the upper surface of the second support layer 122, and the contact interface between the first support layer 121 and the second support layer 122 is lower than the top of the lower electrode 11, and the upper surface of the first support layer 121 is higher than the top of the lower electrode 11. On the one hand, while meeting the height of the lower electrode extending in the vertical direction, it effectively improves the problem of high leakage rate of the capacitance structure caused by carbon pollution; on the other hand, the first support layer 121 plays a role in protecting the second support layer 122, avoiding the second support layer 122 being easily etched due to its relatively weak etching resistance, resulting in serious deformation of the support structure, and can effectively improve the structural stability of the capacitance structure.

[0054] Based on the capacitance structure provided in the first embodiment, the support structure 12 for supporting the outer sidewall of the lower electrode 11 may further include an intermediate support structure located in the middle region of the lower electrode 11 in addition to the top support structure located at the top of the lower electrode 11. Please refer to the second embodiment for details.

[0055] Embodiment Two

[0056] Refer to Figure 3 as shown in Figure 3 FIG. shows a schematic cross-sectional structure diagram of another capacitance structure provided by an embodiment of the present application. Compared with the capacitance structure provided in the first embodiment of the present application, the top support structure further includes a third support layer 123 made of a material different from that of the second support layer 122, and the upper surface of the third support layer 123 is in contact with the upper surface of the second support layer 122. In addition, the support structure may further include an intermediate support structure for supporting the middle region of the lower electrode 11, and the intermediate support structure at least includes a fourth support layer 124.

[0057] For the sake of brevity, the similarities between the capacitance structure provided in the second embodiment and the capacitance structure provided in the first embodiment will not be elaborated below. The following will mainly describe the differences between the second embodiment and the first embodiment.

[0058] In the embodiment of the present invention, the third support layer 123 may include: silicon carbonitride, silicon oxycarbide or silicon carbonitride oxide. Among them, the thickness of the third support layer 123 is less than the thicknesses of the first support layer 121 and the second support layer 122. The third support layer 123 can protect the second support layer 122, avoiding the second support layer 122 being etched when etching the dielectric structure between adjacent lower electrodes 11, thereby effectively improving the stability of the top support layer and effectively improving the problem of high leakage rate of the capacitance structure caused by carbon pollution.

[0059] In addition, the intermediate support structure includes at least a fourth support layer 124. As an example, the intermediate support structure is provided to include only one layer of the fourth support layer 124. Herein, the fourth support layer 124 may include silicon oxide, silicon nitride, or silicon oxynitride. By providing the intermediate support structure, the overall stability of the capacitor structure is improved.

[0060] The above is another capacitor structure provided in the second embodiment of the present application. Based on the capacitor structure provided in the first embodiment, a third support layer 123 is further provided in the top support structure. In addition, a support structure is further provided with an intermediate support structure for supporting the middle region of the lower electrode 11. Herein, the third support layer 123 is different from the second support layer 122 in material, and the thickness of the third support layer 123 is less than the thicknesses of the first support layer 121 and the second support layer 122. In addition, the intermediate support structure includes at least a fourth support layer 124, which can strengthen the support for the capacitor structure, improve the stability of the capacitor structure, and effectively improve the problem of high leakage rate of the capacitor structure caused by carbon pollution.

[0061] Embodiment Three

[0062] See Figure 4 as shown in Figure 4 which shows a schematic cross-sectional structure diagram of another capacitor structure provided in the embodiment of the present application. Compared with the capacitor structure provided in the first embodiment of the present application, the support structure 12 may further include an intermediate support structure for supporting the middle region of the lower electrode 11. For the sake of brevity, the same parts of the capacitor structure provided in the third embodiment and the capacitor structure provided in the first embodiment will not be described again. The following will mainly describe the differences between the third embodiment and the first embodiment.

[0063] In the third embodiment of the present application, the intermediate support structure includes at least a fourth support layer 124 and a fifth support layer 125 different from the fourth support layer 124 in material. The upper surface of the fourth support layer 124 is in contact with the lower surface of the fifth support layer 125.

[0064] As an example, see Figure 4As shown, the intermediate support structure includes a fourth support layer 124 and a fifth support layer 125 made of a material different from that of the fourth support layer 124. The upper surface of the fourth support layer 124 contacts the lower surface of the fifth support layer 125. Among them, the fourth support layer 124 may include: silicon carbonitride, silicon oxycarbide, or silicon carbonitride oxide; the fifth support layer 125 may include: silicon oxide, silicon nitride, or silicon oxynitride. It should be noted that the fourth support layer 124 (the fifth support layer 125) in the intermediate support structure may be made of the same material as the second support layer 122 (the first support layer 121) in the top support structure, or the fourth support layer 124 (the fifth support layer 125) in the intermediate support structure may be made of a material different from that of the second support layer 122 (the first support layer 121) in the top support structure, which will not be specifically limited in the embodiments of the present application.

[0065] By setting the intermediate support structure to be composed of the fourth support layer 124 and the fifth support layer 125 made of different materials, the middle area of the lower electrode 11 can be supported to enhance the stability of the lower electrode 11. At the same time, by setting the fourth support layer 124 to be made of a carbon-free material, the problem of high leakage rate of the capacitive dielectric layer 13 caused by carbon pollution during the subsequent deposition process can be reduced. In addition, the lower surface of the fifth support layer 125 contacts the upper surface of the fourth support layer 124, and the fifth support layer 125 can play a role in protecting the fourth support layer 124 located below it, preventing the fourth support layer 124 from being etched prematurely due to its relatively weak etching resistance, which affects the structure of the intermediate support structure and further affects the stability of the support.

[0066] As an optional example, in order to effectively avoid the problem of high leakage rate caused by carbon pollution, the thickness of the fifth support layer 125 can be set to be less than the thickness of the fourth support layer 124 to improve the performance of the capacitor.

[0067] As another example, refer to Figure 5 shown in Figure 5 FIG. shows a schematic cross-sectional structure diagram of the intermediate support structure provided by the embodiment of the present application. The intermediate support structure may further include a stacked structure formed by alternating stacking of the fourth support layer 124 and the fifth support layer 125. Among them, the thickness of the stacked structure formed by alternating stacking of the fourth support layer 124 and the fifth support layer 125 can be set according to the height of the lower electrode 11 to ensure the stability of the lower electrode.

[0068] In the stacked structure formed by alternating stacking of the fourth support layer 124 and the fifth support layer 125, the thickness of the fifth support layer 125 can be set to be less than the thickness of the fourth support layer 124. The fifth support layer 125 may include silicon carbonitride, silicon oxycarbide, or silicon carbonitride oxide, and the fourth support layer 124 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0069] It should be noted that in the stacked structure formed by alternately stacking the fourth support layer 124 and the fifth support layer 125, each fourth support layer 124 (fifth support layer 125) can be made of the same material or different materials. In addition, the thickness of each fourth support layer 124 (fifth support layer 125) can be set to the same thickness or different thicknesses, which will not be specifically limited in the embodiments of the present application.

[0070] The above is another capacitor structure provided by the third embodiment of the present application. By further providing an intermediate support structure for supporting the middle region of the lower electrode 11 on the basis of the capacitor structure provided by the first embodiment, wherein the intermediate support structure at least includes a fourth support layer 124 and a fifth support layer 125 made of a material different from that of the fourth support layer 124. The lower surface of the fifth support layer 125 is in contact with the upper surface of the fourth support layer 124, and by setting the thickness of the fifth support layer 125 to be less than that of the fourth support layer 124, the supporting effect on the capacitor structure can be enhanced, the stability of the capacitor structure can be improved, and the problem of relatively high leakage rate of the capacitor structure caused by carbon pollution can be effectively improved. In addition, the fifth support layer 125 can protect the fourth support layer 124 and prevent the deformation of the intermediate support structure caused by the relatively weak etching resistance of the fourth support layer 124. Thus, the stability and performance of the capacitor structure are improved as a whole by setting the intermediate support layer.

[0071] Another aspect of the present application further provides a semiconductor device provided with the capacitor structure as described in the third embodiment above. For details, please refer to the fourth embodiment.

[0072] Embodiment Four

[0073] It should be noted that the fourth embodiment can be set based on any one of the above-mentioned first to third embodiments. For the sake of brevity, in this embodiment, the description will be given based on the third embodiment as an example.

[0074] Refer to Figure 1 as shown in Figure 1 which shows a cross-sectional structure schematic diagram of a semiconductor device provided by the embodiment of the present application, and it includes:

[0075] a substrate 10; and

[0076] a capacitor structure as described in the third embodiment above, and the capacitor structure is disposed above the substrate 10.

[0077] As an example, the substrate 10 includes a cell array region and a peripheral circuit region. A cell array region transistor 15 is disposed in the cell array region, a peripheral circuit transistor 16 is disposed in the peripheral circuit region, a dielectric layer 17 is disposed between the substrate 10 and the capacitor structure, and a capacitor contact plug 18 for realizing electrical connection between the capacitor structure and the substrate 10 is disposed in the substrate 10.

[0078] Among them, the base 10 can be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator), a GOI (Germanium On Insulator), etc. In other embodiments, the base can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, etc., and can also be a stacked structure, such as Si / SiGe, etc., and can also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc.

[0079] The dielectric layer 17 can include borophosphosilicate glass, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, and carbon-containing low-k dielectrics, etc.

[0080] In the embodiments of the present application, a cell array region transistor 15 and a peripheral circuit transistor 16 are also exemplarily provided. Among them, the cell array region transistor 15 includes a source electrode 151 and a drain electrode 152 disposed in the base 10, and a gate structure 153 located in the dielectric layer 17 and disposed between the source electrode 151 and the drain electrode 152. Among them, as an example, the gate structure 153 can be set to include a semiconductor layer 1531 located above the base 10, a barrier layer 1532 located on the semiconductor layer 1531, a metal layer 1533 located on the barrier layer 1532, and a mask layer 1534 located on the metal layer 1533. In addition, sidewalls can also be included on both sides of the gate structure to prevent the metal layer 1533 in the gate structure from being exposed.

[0081] Among them, the cell array region transistor 15 can be set as an N-type or P-type transistor, and will not be specifically limited in the embodiments of the present application.

[0082] The semiconductor layer 1531 can be a semiconductor layer doped with N-type ions or P-type ions. For example, it can be a polysilicon layer doped with N-type ions. It should be noted that an insulating layer is also disposed between the semiconductor layer 1531 and the base 10, which is not shown in the figure.

[0083] The barrier layer 1532 can be a metal silicide layer. For example, tungsten silicide. The metal layer 1533 can include tungsten, and the mask layer 1534 can include insulating materials such as silicon nitride or silicon oxynitride.

[0084] The peripheral circuit transistor 16 can be set to have the same structure as the cell array region transistor 15. The peripheral circuit transistor 16 may include a source electrode 161 and a drain electrode 162 disposed in the substrate 10, and a gate structure 163 located in the dielectric layer 17 and disposed between the source electrode 161 and the drain electrode 162. As an example, the gate structure 163 may be set to include a semiconductor layer 1631 above the substrate 10, a barrier layer 1632 on the semiconductor layer 1631, a metal layer 1633 on the barrier layer 1632, and a mask layer 1634 on the metal layer 1633.

[0085] Among them, the peripheral circuit transistor 16 may include an N-type or P-type transistor, which will not be specifically limited in the embodiments of the present application.

[0086] The semiconductor layer 1631 may be a semiconductor layer doped with N-type ions or P-type ions. For example, it may be a polysilicon layer doped with N-type ions. It should be noted that an insulating layer is also provided between the semiconductor layer 1631 and the substrate 10, which is not shown in the figure.

[0087] The barrier layer 1632 may be a metal silicide layer. For example, tungsten silicide. The metal layer 1633 may include tungsten, and the mask layer 1634 may include insulating materials such as silicon nitride or silicon oxynitride.

[0088] It should be noted that the peripheral circuit transistor 16 may be set to have the same material as the cell array region transistor 15, or may be set to have a different material from the cell array region transistor 15, which will not be specifically limited in the embodiments of the present application.

[0089] The capacitor contact plug 18 may be filled with a conductive material such as doped polysilicon or metal silicide to electrically connect the capacitor structure to the substrate 10. As a specific example, the capacitor contact plug 18 may be set to contact the active region 1051 of the cell array region transistor 15.

[0090] The above is a semiconductor device provided by the embodiments of the present application, which includes a substrate 10 and a capacitor structure as described in Embodiment 3 above. By simultaneously providing a top support structure and an intermediate support structure in the capacitor structure, the semiconductor device in this embodiment can have the same beneficial effects as those in Embodiment 2, and overall improve the working performance of the semiconductor device.

[0091] In another aspect of the present application, a method for preparing a capacitor structure is also provided. For details, please refer to Embodiment 5.

[0092] Embodiment 5

[0093] See Figures 6 to 12 as shown Figures 6 to 12The cross-sectional structure diagrams corresponding to the steps of the method for preparing a capacitive structure provided by the embodiments of the present application are shown.

[0094] Referring to Figure 6 As shown, a stacked structure is formed on the substrate 10. Among them, the stacked structure includes a dielectric structure 19, a second support layer 122, and a first support layer 121 that are sequentially formed on the substrate 10. The materials of the first support layer 121 and the second support layer 122 are different.

[0095] Forming a stacked structure on the substrate 10 can specifically be to sequentially deposit a dielectric structure 19, a first support layer 121, and a second support layer 122 on the substrate 10 by using a chemical vapor deposition process or a physical vapor deposition process.

[0096] In the embodiments of the present application, the dielectric structure 19 may include at least one of silicon nitride, boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), and plasma enhanced (PE)-tetraethyl orthosilicate (TEOS).

[0097] As an example, the first support layer 121 may include silicon carbonitride, silicon oxycarbide, or silicon carbonitride oxide, and the second support layer 122 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0098] Referring to Figure 7 As shown, the stacked structure is etched until the upper surface of the substrate 10 is exposed to stop, so as to form a plurality of trenches in the stacked structure.

[0099] This step can specifically be to select a suitable etching process to etch the stacked structure to form a plurality of trenches exposing the upper surface of the substrate 10 in the stacked structure. As an example, the etching process can select a dry etching process or a wet etching process.

[0100] Referring to Figure 8 As shown, a conductive layer 20 covering at least the sidewalls and the bottom of the trenches is conformally deposited.

[0101] In the embodiments of the present application, a deposition process with a better step coverage effect can be used to deposit the conductive layer 20. As an example, an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process can be used to conformally deposit a conductive layer 20 covering at least the sidewalls and the bottom of the trenches. Among them, in some embodiments, in addition to covering the sidewalls and the bottom of the trenches, the conductive layer 20 can also cover the upper surface of the first support layer 121.

[0102] The conductive layer 20 may include a metal or a metal nitride. As a specific example, the conductive layer 20 may be titanium nitride.

[0103] Referring to Figure 9As shown, the conductive layer 20 is etched back to form the lower electrode 11, and the top of the lower electrode 11 is higher than the contact interface between the first support layer 121 and the second support layer 122 and lower than the upper surface of the first support layer 121.

[0104] This step can specifically be that the conductive layer 20 is etched back by using a dry etching process to form the lower electrode 11.

[0105] See Figure 10 As shown, the dielectric structure 19 between adjacent lower electrodes is etched.

[0106] In the embodiment of the present application, the dielectric structure 19 can be etched by using a dry etching process or a wet etching process.

[0107] See Figure 11 As shown, the capacitive dielectric layer 13 is deposited, and the capacitive dielectric layer 13 conformally covers the upper surfaces of the lower electrode 11 and the first support layer 121.

[0108] See Figure 12 As shown, an upper electrode 14 is formed on the capacitive dielectric layer 13, and a capacitive structure can be obtained.

[0109] In the embodiment of the present application, the capacitive dielectric layer 13 and the upper electrode 14 can be respectively deposited by using the same deposition process as that for depositing the conductive layer 20. The upper electrode 14 can not only conformally cover the capacitive dielectric layer 13 but also fill the region between adjacent lower electrodes 11 provided with the support structure 12. It should be noted that the capacitive dielectric layer 13 can also be formed on the lower surface of the second support layer 122, and the upper electrode 14 is isolated from the lower electrode 11 and the support structure 12 through the capacitive dielectric layer 13. Among them, the capacitive dielectric layer 13 can include at least one of an oxide, a nitride or a high-order dielectric material, and the upper electrode 14 can be formed of a metal material or a metal nitride, etc.

[0110] The above is a method for preparing a capacitor structure provided by an embodiment of the present application. A stacked structure including a dielectric structure 19, a second support layer 122, and a first support layer 121 made of a material different from that of the second support layer 122 is sequentially formed on a substrate 10. The stacked structure is etched to etch out a plurality of grooves exposing the upper surface of the substrate 10, and then a conductive layer 20 covering at least the side walls and the bottom of the grooves is conformally deposited. By back-etching the conductive layer 20, a lower electrode 11 is formed with a top higher than the contact interface between the first support layer 121 and the second support layer 122 and lower than the upper surface of the first support layer 121. Then, the dielectric structure 19 between adjacent lower electrodes 11 is etched away. Finally, a capacitor dielectric layer 13 covering the upper surfaces of the lower electrode 11 and the first support layer 121 is deposited, and an upper electrode 14 covering the capacitor dielectric layer 13 is formed to form a capacitor structure. On the one hand, while meeting the height of the lower electrode 11 extending in the vertical direction, this method effectively improves the problem of high leakage rate of the capacitor structure caused by carbon pollution. On the other hand, the first support layer 121 plays a protective role for the second support layer 122, avoiding the second support layer 122 being easily etched due to its relatively weak etching resistance, resulting in serious deformation of the support structure, and can effectively improve the structural stability of the capacitor structure.

[0111] Although the embodiments disclosed in the present application are as above, the content described above is only an embodiment adopted for the convenience of understanding the present application and is not intended to limit the present application. Any person skilled in the art within the technical field to which the present application pertains may make any modifications and changes in the form of implementation and details without departing from the spirit and scope disclosed in the present application. However, the protection scope of the present application shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized in that, comprising: a substrate; a capacitive contact plug located on the substrate; a lower electrode located on the capacitive contact plug; a support structure, the support structure being located on the outer sidewall of the lower electrode, wherein the support structure includes a top support structure that supports an upper region of the lower electrode, the top support structure at least includes a first support layer and a second support layer having a different material from the first support layer, a lower surface of the first support layer contacts an upper surface of the second support layer, and a contact interface between the first support layer and the second support layer is lower than a top of the lower electrode, and an upper surface of the first support layer is higher than the top of the lower electrode; a capacitive dielectric layer covering the lower electrode and the support structure; and an upper electrode covering the capacitive dielectric layer.

2. The semiconductor device according to claim 1, characterized in that, a thickness of the second support layer is 3 to 7 times a thickness of the first support layer.

3. The semiconductor device according to claim 1, characterized in that, the first support layer includes: silicon carbonitride, silicon oxycarbide or silicon carbonitride oxide; the second support layer includes: silicon oxide, silicon nitride or silicon oxynitride.

4. The semiconductor device according to claim 1, characterized in that, the top support structure further includes a third support layer having a different material from the second support layer, an upper surface of the third support layer contacts the upper surface of the second support layer.

5. The semiconductor device according to claim 4, characterized in that, a thickness of the third support layer is less than thicknesses of the first support layer and the second support layer.

6. The semiconductor device according to claim 1, characterized in that, the support structure further includes an intermediate support structure that supports an intermediate region of the lower electrode, wherein the intermediate support structure at least includes a fourth support layer.

7. The semiconductor device according to claim 6, characterized in that, the fourth support layer includes: silicon oxide, silicon nitride or silicon oxynitride.

8. The semiconductor device according to claim 1, characterized in that, the substrate includes a cell array region and a peripheral circuit region, cell array region transistors are provided in the cell array region, and peripheral circuit transistors are provided in the peripheral circuit region; a dielectric layer is provided between the substrate and the lower electrode and between the substrate and the upper electrode, and the capacitive contact plug is located in the dielectric layer for electrically connecting the lower electrode and the substrate.

9. A semiconductor device, characterized in that, comprising: a substrate; a capacitive contact plug located on the substrate; a lower electrode located on the capacitive contact plug; a support structure, the support structure being located on the outer sidewall of the lower electrode, wherein the support structure includes a top support structure that supports an upper region of the lower electrode, the top support structure at least includes a first support layer and a second support layer having a different material from the first support layer, a lower surface of the first support layer contacts an upper surface of the second support layer; A capacitive dielectric layer that covers the lower electrode and the support structure, wherein a sidewall of the first support layer is in contact with the outer sidewall of the lower electrode and the capacitive dielectric layer at the same time; and An upper electrode that covers the capacitive dielectric layer.

10. The semiconductor device according to claim 9, wherein, the thickness of the second support layer is 3 to 7 times the thickness of the first support layer.

11. The semiconductor device according to claim 9, wherein, the first support layer includes: silicon carbonitride, silicon carbon oxide, or silicon carbonitride oxide; the second support layer includes: silicon oxide, silicon nitride, or silicon oxynitride.

12. The semiconductor device according to claim 9, wherein, the top support structure further includes a third support layer different from the second support layer in material, and an upper surface of the third support layer is in contact with an upper surface of the second support layer.

13. The semiconductor device according to claim 12, wherein, the thickness of the third support layer is less than the thicknesses of the first support layer and the second support layer.

14. The semiconductor device according to claim 9, wherein, the support structure further includes an intermediate support structure that supports an intermediate region of the lower electrode, and the intermediate support structure includes at least a fourth support layer.

15. The semiconductor device according to claim 14, wherein, the fourth support layer includes: silicon oxide, silicon nitride, or silicon oxynitride.

16. The semiconductor device according to claim 9, wherein, the substrate includes a cell array region and a peripheral circuit region. A cell array region transistor is provided in the cell array region, and a peripheral circuit transistor is provided in the peripheral circuit region; a dielectric layer is provided between the substrate and the lower electrode and between the substrate and the upper electrode, and the capacitive contact plug is located in the dielectric layer to electrically connect the lower electrode and the substrate.

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