Controller for voltage converter

Abstract

A controller integrated circuit (410) for controlling a voltage converter (400). The controller IC (410) includes a transistor control driver terminal (416) and a power terminal (418). The driver (427) has a driver input, a driver output, and a driver supply voltage input. The driver output is coupled to the transistor control driver terminal (416), and the driver supply voltage input is coupled to the power terminal (418). The logic has a first logic output and a second logic output. The first transistor (Q42) has a first control input, a first current terminal, and a second current terminal. The first logic output is coupled to the first control input, and the first current terminal is coupled to the power terminal. A second transistor (Q43) has a second control input, a third current terminal and a fourth current terminal. The second logic output is coupled to the second control input, and the third current terminal is coupled to the transistor control driver terminal (416).

Description

BACKGROUND OF THE INVENTION

[0001] An electric vehicle (EV) includes a battery pack that generates a relatively high direct current (DC) voltage. The battery packs of some EVs generate a DC voltage of 400V. EV battery packs are trending towards even higher voltages (e.g., 800V). The use of the battery pack voltage will drive a traction inverter that, in some cases, generates a three-phase time-varying voltage (e.g., sinusoidal voltage and current) to a three-phase motor. The traction inverter causes the motor to rotate. The motor is coupled to one or two axles of the EV. The rotation of the motor causes the axles to rotate, which in turn causes the wheels of the EV to rotate.

[0002] At least some EVs have a "tow mode". To safely tow an EV, the EV is placed in tow mode, which may disconnect the battery pack. However, when towing an EV, at least two of the wheels rotate because the EV is being pulled by a tow truck. The rotating wheels cause the motor to rotate, and the motor then acts as a generator. The motor generates a voltage on the main high-voltage bus. The voltage generated by the motor can be much smaller than the voltage of the EV's battery pack. In one example, the voltage generated by the motor is in the range of, for example, 40V to 60V, while the voltage of the battery pack can be 400V, 800V, etc.

[0003] A DC-to-DC voltage converter is included in the EV to convert the relatively high battery pack voltage to a much smaller voltage (e.g., 12V to 20V) to power control electronics (e.g., the main electronic control unit of the EV) within the EV. One class of voltage converter used in at least some EVs is a flyback voltage converter that converts a DC input voltage to a smaller DC output voltage. If the EV is in tow mode and the voltage generated by the motor powers the main electronic control unit of the EV, the electronic control unit can configure the traction inverter into a safe mode (e.g., short each of the three phases of the motor) to prevent the motor from generating a higher voltage further.

[0004] Therefore, the DC input voltage of the flyback voltage converter should have a wide range from, for example, 40V to 800V. The flyback converter should also include circuitry for quickly generating a relatively low bias voltage (compared to the 800V battery pack voltage) to power the controller of the flyback converter. Regardless of how wide the range of the input voltage is, the bias voltage generation capability of such a flyback converter should quickly generate the bias voltage. SUMMARY OF THE INVENTION

[0005] A controller integrated circuit for controlling a voltage converter. The controller IC includes a transistor control driver terminal and a power terminal. The driver has a driver input, a driver output, and a driver supply voltage input. The driver output is coupled to the transistor control driver terminal, and the driver supply voltage input is coupled to the power terminal. Logic has a first logic output and a second logic output. A first transistor has a first control input, a first current terminal, and a second current terminal. The first logic output is coupled to the first control input, and the first current terminal is coupled to the power terminal. A second transistor has a second control input, a third current terminal, and a fourth current terminal. The second logic output is coupled to the second control input, and the third current terminal is coupled to the transistor control driver terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of a DC-to-DC converter in one example.

[0007] Figure 2 is a schematic diagram showing how to turn on Figure 1 the main power transistor of the converter in one example.

[0008] Figure 3 is a schematic diagram showing how to turn off Figure 1 the main power transistor of the converter in one example.

[0009] Figure 4 is a schematic diagram of a DC-to-DC converter in another example.

[0010] Figure 5 is a block diagram of a system of a DC-to-DC converter in which Figure 4 can be used. DETAILED DESCRIPTION

[0011] The same reference numerals or other reference indicators are used in the drawings to denote (functionally and / or structurally) identical or similar features.

[0012] Figure 1It is a schematic diagram of a DC-DC voltage converter 100. The voltage converter 100 is a flyback converter in this example, which converts a DC input voltage VIN into a DC output voltage VOUT. In one example, the magnitude of VOUT is less than the magnitude of VIN. Among other components, the flyback converter 100 includes a controller 110, a transformer T1, a transistor Q1, and a feedback circuit 132. The transistor Q1 is an n-channel field effect transistor (NFET), but the transistor Q1 can be implemented as any one of a variety of other types of transistors. The controller 110 controls the on and off states of the transistor Q1. The feedback circuit 132 includes an optocoupler 135. The feedback circuit is coupled to the output terminals 151, 152 of the converter 100 and thus receives the output voltage VOUT. A scaled version of VOUT is transmitted through the optocoupler to pin 114 of the controller 110 to provide a signal indicating the magnitude of VOUT. The controller 110 controls the timing of the on and off states of the transistor Q1 to maintain VOUT at a regulated level (e.g., a target level with an output voltage ripple).

[0013] The controller 110 also includes pins 115 - 118. The VDD pin 118 receives an operating voltage Vdd to power the controller 110. The pin 117 is a ground pin. The pin 116 is coupled to the source of the transistor Q1 and to the anode of a diode (e.g., a Zener diode) D1. A parallel combination of a resistor R2 and a diode D2 is coupled between the pin 115 and the gate of the transistor Q1. A series connection of a resistor R1 and a C1 is coupled between VIN and ground. The transformer includes a primary winding 121, an auxiliary winding 122, and a secondary winding 123.

[0014] The input voltage VIN may be too large to be connected to the VDD pin 118 of the controller. For example, VIN can be 400V, 800V, etc., and the maximum allowable value for the VDD pin of the controller can be 12V, 15V, etc. The controller 110 implements a startup process to cause the voltage on the VDD pin 118 to increase from 0V to a suitable operating voltage to power the controller 110. The controller 110 includes an internal switch SW1 (e.g., a transistor), which is coupled between the source of the transistor Q1 and ground through the pin 116. During the startup process, the logic inside the controller turns off (switches off) the switch SW1. With the switch SW1 off, the current flowing through the primary winding 121 passes through the transistor Q1 and the diode D1 to charge the capacitor Cvdd. The voltage across the capacitor Cvdd is coupled to the VDD pin 118 of the controller 110. When the capacitor Cvdd is charged, its voltage increases above the minimum operating voltage of the controller, and the under-voltage lockout (UVLO) function inside the controller changes the logic state of the internal UVLO signal to release the controller from its reset state. At this time, the voltage pin 115 is set to a fixed voltage level (e.g., set by an internal reverse-biased Zener diode not shown).

[0015] The fixed voltage level on the pin 115 is coupled to the gate of the transistor Q1 through the resistor R2. In this configuration, the gate of the transistor Q1 is coupled to a fixed voltage. After the controller 110 is released from its reset state, the switch SW1 is immediately used to turn on and off the transistor Q1.

[0016] Figure 2 and 3 illustrate the behavior of the converter when the switch SW1 is on ( Figure 2 ) and when the switch SW1 is off ( Figure 3 ). Figure 2 and 3 illustrate the fixed voltage 204 (resistor R2 not shown) provided to the gate of the transistor Q1. The switch SW1 is implemented as an NFET Q2 in this example. The controller 110 generates (through the driver 206) a pulse-width modulation (PWM) control signal that reaches the gate of the transistor Q2. When the PWM control signal is logic high, the transistor Q2 is on. When the PWM control signal is logic low, the transistor Q2 is off.

[0017] Referring to Figure 2 , when the transistor Q2 is on, the source of the transistor Q1 is pulled down to approximately ground potential. With the gate voltage of the transistor Q1 at a fixed level, the gate-to-source voltage (Vgs) of the transistor Q1 exceeds its threshold voltage, and the transistor Q1 is on. The current I1 flows through the primary winding 121 and the transistors Q1 and Q2 to ground.

[0018] The transistor Q2 has Figure 3 the parasitic capacitance Cds shown. When the transistor Q2 is turned off, the current I1 continues to flow through the transistor Q1, and the parasitic capacitance Cds is charged. Node A is the connection between the source of the transistor Q1 and the drain of the transistor Q2. When the capacitance Cds is charged, the voltage at node A increases. Eventually, the voltage at node A becomes large enough such that the Vgs of the transistor Q1 is less than its threshold voltage. When this occurs, the transistor Q1 is turned off.

[0019] The rate at which the voltage at node A increases is proportional to the magnitude of the current I1, which can be quite large. The rate of change of the node A voltage is thus also large. The large rate of change of the node A voltage between the primary winding 121 (and inductor) and the capacitance Cds causes ringing at node A. The ringing voltage at node A can be large enough to damage the transistors Q1 and / or Q2 and cause electromagnetic interference (EMI) to circuits other than the voltage converter 100. Certain features can be added to the converter to attempt to mitigate the ringing. For example, a ferrite bead can be coupled to the gate of the transistor Q1. In another example, a capacitor can be coupled between pins 116 and 117 (ground). In yet another example, a resistor can be added between the gate of the transistor Q1 and the anode of the diode D2. In some cases, these mitigation techniques do not work. The embodiments described below can solve this problem.

[0020] Figure 4 is a schematic diagram of an example flyback DC-to-DC converter 400 that includes a controller 410, a diode D41, a capacitor C41, a resistor R41, a transistor Q41, and a transformer. The transformer includes a primary winding 421 and an auxiliary winding 422 (the secondary winding of the transformer and the circuits connected thereto are not shown for convenience). The controller has pins 415, 416, 417, and 418. Pin 417 is coupled to ground. Pin 418 receives the operating voltage VDD. In this example, the transistor Q41 is an NFET, and its source is coupled to pin 415 of the controller 410. The gate of the transistor Q41 is coupled to pin 416 of the controller (which can be referred to as the transistor control driver pin). The diode D41 is serially coupled between the auxiliary winding 422 and ground to the capacitor C41, where the connection between the cathode of the diode D41 and the capacitor C41 is coupled to pin 418 of the controller 410. The drain of the transistor Q41 is coupled to one terminal of the primary winding 421, and VIN is coupled to the other terminal of the primary winding. The resistor R41 is coupled between VIN and the gate of the transistor Q41.

[0021] In one example, the controller 410 is fabricated as an IC, and the diodes D41, capacitors C41, resistors R41, transistors Q41, and transformers are external to the controller 410. The example controller 410 includes inverters 411 and 412, AND gates 413 and 414, comparator 407, diodes D42, D43, and D44, transistors Q42, Q43, Q44, and Q45, and resistor R42. The comparator 407 and inverter 412 are logic 405 that at least partially controls the on and off states of transistors Q42 and Q43. The controller 410 may include additional components, such as a PWM generator 403 that generates a PWM signal 409. In Figure 4 the example, the transistors Q42 - Q45 are NFETs. The combination of the AND gates 413 and 414, inverter 411, transistors Q44 and Q45, and diode D42 forms a driver 427 to control the voltage on the gate of transistor Q41. The PWM signal 409 is coupled to the inputs of the AND gate 413 and the input of the inverter 411. The comparator 407 has a positive input and a negative input. The positive input is coupled to VDD, and a reference voltage VREF is coupled to the negative input. VREF may be generated by a bandgap reference circuit and represents the voltage as the minimum acceptable level of VDD for the correct operation of the controller 410. When VDD initially rises, the output signal (UVLO bar) is logic low while VDD is less than VREF. After VDD reaches VREF, instantly transitions from logic low to logic high. Other types of logic may be used to implement the under - voltage lock - out function.

[0022] The output of the comparator 407 is coupled to the inputs of the AND gates 413 and 414 and the inverter 412. The output of the AND gate 413 is coupled to the gate of transistor Q45. The output of the AND gate 414 is coupled to the gate of transistor Q44. The output of the inverter 412 is coupled to the gate of transistor Q43. The anode of diode D42 is coupled to pin 418 and thus coupled to capacitor C41. The cathode of diode D42 is coupled to the drain of transistor Q45. The source of transistor Q45 is coupled to the drain of transistor Q44 and pin 416. The source of transistor Q44 is coupled to pin 417 (ground). The sources of transistors Q42 and Q43 are also coupled to pin 417 (ground).

[0023] Diode D43 is implemented as a Zener diode. The anode of diode D43 is coupled to the drain of transistor Q43. The cathode of diode D43 is coupled to pin 416 and thus to the source of transistor Q45 and the drain of transistor Q44. Resistor R42 and diode D44 are coupled in series between pin 418 and the drain of transistor Q42, where the cathode of diode D44 is coupled to resistor R42. The anode of diode D42 is coupled to the drain of transistor Q42 and via pin 415 to the source of transistor Q41.

[0024] During startup, VDD is less than VREF, and comparator 407 responds by forcing to go logic low, which ensures that transistor Q42 is turned off. When is logic low, the output signal from inverter 412 is logic high, which in turn turns on transistor Q43. When transistor Q43 is on, current flows through resistor R41, diode D43, and transistor Q43 to ground. The Zener diode D43 helps to clamp the gate voltage of transistor Q41 to a safe level. The voltage on the gate of transistor Q41 rises, eventually turning on transistor Q41. When transistor Q41 is on, current I41 flows through primary winding 421, transistor Q41, diode D44, and resistor R42 to charge capacitor C41. The voltage on capacitor C41 is VDD. Charging capacitor C41 causes the voltage VDD to rise.

[0025] When VDD exceeds VREF, comparator 407 forces its output signal to go logic high, which causes transistor Q42 to turn on and (through inverter 412) causes transistor Q43 to turn off. Transistor Q42 remains on during normal operation (after startup), and transistor Q42 is not used to turn on and off the external transistor Q41.

[0026] During normal operation (when VDD is greater than VREF) with transistor Q42 on, the source of transistor Q41 is pulled low to approximately ground. Instead of using transistor Q42 to cause transistor Q41 to turn on and off (as in the case of using switch SW1 and the corresponding transistor Q2 in Figure 1 to turn on and off transistor Q1), in Figure 2 transistor Q41 is turned on and off by changing its gate voltage. When VDD is greater than VREF and thus one input to AND gates 413 and 414 is logic high, Figure 4 in The signal is logic high. The PWM signal 409 is provided to the input of the AND gate 413, and the logical inversion of the PWM signal is provided to the input of the AND gate 414. Accordingly, the transistor Q45 turns on in response to the PWM signal being logic high (and the transistor Q44 turns off). The transistor Q44 turns on in response to the PWM signal being logic low (and the transistor Q45 turns off). When the transistor Q45 turns on, the gate of the transistor Q41 is pulled up towards VDD, thereby turning on the transistor Q41. When both the transistors Q41 and Q42 are on (Q42 remains on during the operation after the full startup of the converter), the current I42 flows from the primary winding 421 and through the transistors Q41 and Q42 to the ground. When the transistor Q44 turns on, the gate of the transistor Q41 is pulled down towards the ground, thereby turning off the transistor Q41.

[0027] Since the transistor Q42 does not turn off to turn off the transistor Q41, ringing (or much less) does not occur on the source and gate of the transistor Q41. Accordingly, the risk of damage to the transistors Q41 and Q42 is less. Further, the voltage converter 400 generates less EMI than the voltage converter 100.

[0028] Figure 5 A block diagram of a system 500 showing the use of the voltage converter 400. The system 500 represents the electronics within an electric vehicle (EV). The system 500 includes a battery pack 510, a microcontroller unit (MCU) 520, a system basis chip (SBC) 526, and a traction inverter 530. The battery pack 510 may include a plurality of battery cells, and the total voltage of the battery pack may be a generally high voltage, such as 400V, 800V, etc. The higher voltage (HV) power bus 511 couples the battery pack 510 to the input of the voltage converter 400. The voltage converter 400 converts the higher voltage of the battery pack 510 into a lower voltage on the lower voltage (LV) power bus 512. The output voltage from the voltage converter 400 may be a voltage that is generally lower than the output voltage of the battery pack 510. For example, the output voltage from the voltage converter 400 may be 12V, 15V, 20V, etc. The LV power bus 512 is coupled to the power input of the SBC 526 (via a diode). The SBC 526 generates one or more output voltages based on the voltage from the LV power bus 512. At least one of the output voltages is VCC, which is coupled to the power input of the MCU 520 and is the operating voltage for the MCU.

[0029] The MCU 520 generates a control signal 521 that is provided to the driver 523. The driver 523 processes the control signal 521 to turn on and off individual transistors of the traction inverter 530. The traction inverter 530 has three phases 531, 532, and 533. Each phase includes a high-side transistor coupled to a low-side transistor, as shown. The phases 531 - 533 of the traction inverter 530 drive the three-phase motor M1. The motor M1 is operable to rotate the axle and thus rotate the wheels of the EV.

[0030] The voltage converter 400 is capable of starting and generating an output voltage over a wide range of input voltages. This wide input voltage range is particularly useful in the case where the EV is towed as described above. During towing, at least two of the wheels rotate, which causes the motor M1 to rotate and operate as a generator. As a generator, the motor generates a voltage that can be imposed on the HV power bus 511 through the traction inverter 530. The voltage generated by the motor during towing is generally less than the voltage of the battery pack. In one example, the voltage imposed on the HV power bus 511 at the input to the voltage converter 400 during towing can be 40V - 60V, which is generally less than the battery pack voltage (e.g., 400V, 800V, etc.). The output voltage generated by the voltage converter 400 onto the LV power bus 512 causes the MCU 520 to power on. Once powered on, the MCU 520 turns on all three low-side transistors of the three phases 531 - 532, thereby preventing the motor M1 from continuing to generate voltage onto the HV bus 511. The input voltage VCC to the MCU 520 also decreases, thereby turning off the MCU. This process repeats, where each power cycle of the MCU includes shorting the motor to ground through the three low-side transistors of the traction inverter 530.

[0031] In this description, the term "coupled" can encompass a connection, communication, or signal path that enables a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, if an intermediate component C does not change the functional relationship between device A and device B, then device A is coupled to device B through the intermediate component C such that device B is controlled by device A via the control signal generated by device A.

[0032] Additionally, in this description, the recitation "based on" means "at least partially based on". Thus, if X is based on Y, then X can depend on Y and any number of other factors.

[0033] A device “configured to” perform a task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by the manufacturer to perform the function, and / or may be configured (or reconfigured) by the user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0034] As used herein, the terms “terminal,” “node,” “interconnection,” “lead,” and “pin” may be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to denote an interconnection between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components, or the ends thereof.

[0035] A circuit or device described herein as including certain components may in fact be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may in fact include only semiconductor elements (e.g., semiconductor die and / or integrated circuit (IC) packages) within a single physical device, and may be adapted to be coupled to at least some of the passive elements and / or sources, e.g., by a end user and / or a third party, at the time of manufacture or after manufacture to form the described structure.

[0036] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may alternatively be used with little or no change to the remaining circuitry. For example, field effect transistors (“FETs”) (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs - e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used instead of or in combination with the devices described herein. The transistors may be depletion-mode devices, drain-extension devices, enhancement-mode devices, natural transistors, or other types of device-structure transistors. Additionally, the device may be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0037] As used herein, an FET being “on” means that there is a conductive channel in the FET and a drain current can flow through the FET. An FET being “off” as used herein means that there is no conductive channel, and thus no drain current flows through the FET. However, an “off” FET may have a current flowing through the body diode of the transistor.

[0038] Reference may be made in this text to the control input of a transistor and its current terminals. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0039] The circuits described herein may be reconfigured to include additional or different components to provide at least partially a functionality similar to that available prior to the component replacement. Unless otherwise specified, a component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0040] Although some of the elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features described as external to the integrated circuit may be included in the integrated circuit, and / or some of the features described as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / above a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0041] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this description. In this specification, unless otherwise specified, "about", "substantially", or "generally" before a parameter means within + / - 10% of the stated parameter.

[0042] Modifications may be made to the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A voltage converter, which comprises: a first transistor having a first control input, a first current terminal, and a second current terminal; a driver having a driver input and a driver output, the driver output being coupled to the first control input; a capacitor coupled to the second current terminal; a second transistor having a second control input, a third current terminal, and a fourth current terminal, the third current terminal being coupled to the second current terminal, and the fourth current terminal being coupled to a ground terminal; and logic coupled to the second control input and configured to turn off the second transistor during a startup process and turn on the second transistor after the startup process.

2. The voltage converter according to claim 1, wherein the driver comprises: a first AND gate having a first AND gate input, a second AND gate input, and a first AND gate output, the driver input being coupled to the first AND gate input, and the logic being coupled to the second AND gate input; a second AND gate having a third AND gate input, a fourth AND gate input, and a second AND gate output, the driver input being coupled to the third AND gate input, and the logic being coupled to the fourth AND gate input; a third transistor having a third control input and a fifth current terminal and a sixth current terminal, the first AND gate output being coupled to the third control input; and a fourth transistor having a fourth control input and a seventh current terminal and an eighth current terminal, the second AND gate output being coupled to the fourth control input, and the sixth current terminal being coupled to the seventh current terminal and the first control input.

3. The voltage converter according to claim 1, further comprising a transformer coupled to the first current terminal.

4. The voltage converter according to claim 1, wherein the voltage converter is a flyback voltage converter.

5. The voltage converter according to claim 1, wherein the logic comprises a comparator.

6. The voltage converter according to claim 5, wherein the comparator has a first comparator input configured to receive a supply voltage, and the comparator has a second comparator input configured to receive a reference voltage.

7. The voltage converter according to claim 6, wherein the comparator has a comparator output, and the logic comprises an inverter having an inverter input coupled to the comparator output and an inverter output coupled to the second control input.

8. A controller integrated circuit (IC) for controlling a voltage converter, the controller IC comprises: a transistor control driver terminal; a power terminal; a driver having a driver input, a driver output, and a driver supply voltage input, the driver output being coupled to the transistor control driver terminal, and the driver supply voltage input being coupled to the power terminal; logic having a first logic output and a second logic output; A first transistor having a first control input, a first current terminal, and a second current terminal, the first logic output being coupled to the first control input, and the first current terminal being coupled to the power terminal; and A second transistor having a second control input, a third current terminal, and a fourth current terminal, the second logic output being coupled to the second control input, the third current terminal being coupled to the transistor control driver terminal.

9. The controller IC according to claim 8, wherein the driver comprises: A first AND gate having a first AND gate input, a second AND gate input, and a first AND gate output, the logic being coupled to the second AND gate input; A second AND gate having a third AND gate input, a fourth AND gate input, and a second AND gate output, the logic being coupled to the fourth AND gate input; A third transistor having a third control input and a fifth current terminal and a sixth current terminal, the first AND gate output being coupled to the third control input; and A fourth transistor having a fourth control input and a seventh current terminal and an eighth current terminal, the second AND gate output being coupled to the fourth control input, and the sixth current terminal being coupled to the seventh current terminal and the transistor driver control terminal.

10. The controller IC according to claim 8, wherein the controller IC is configured to control a flyback voltage converter.

11. The controller IC according to claim 8, wherein the logic comprises a comparator.

12. The controller IC according to claim 11, wherein the comparator has a first comparator input configured to receive a supply voltage, and the comparator has a second comparator input configured to receive a reference voltage.

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