Oxidation enhanced doping

Abstract

Embodiments of the present technology include semiconductor processing methods. The method may include providing a silicon-containing precursor and a dopant precursor to a processing region of a semiconductor processing chamber. The substrate may be disposed within a semiconductor processing chamber. A silicon-containing material may be formed on a substrate. The method may include contacting a silicon-containing material with a silicon-containing precursor and a dopant precursor. The method may include forming a doped silicon-containing material on a silicon-containing material. The method may include oxidizing a substrate. The oxidation may form an oxidized doped silicon-containing material. The method may include etching an oxidized doped silicon-containing material.

Description

Technical Field

[0001] This application claims the benefit and priority of U.S. Patent Application No. 17 / 973,927, titled "OXIDATION ENHANCED DOPING", filed on October 26, 2022, the entirety of which is incorporated herein by reference.

[0002] This technology relates to deposition and removal processes and chambers. More particularly, this technology relates to systems and methods for enhancing the doping of silicon materials through oxidation. Background Art

[0003] Integrated circuits may be fabricated through processes that produce intricately patterned material layers on a substrate surface. Producing patterned materials on a substrate requires controlled methods for forming and removing materials. Material properties may affect the operation of the device and may also affect the way in which films are removed relative to each other. Deposition processes produce films with certain properties. To provide suitable properties, many of the films formed require additional processing to adjust or enhance the material properties of the film.

[0004] Accordingly, there is a need for improved systems and methods that can be used to produce high-quality devices and structures. This technology can address these and other needs. Summary of the Invention

[0005] Embodiments of this technology include semiconductor processing methods. The method may include: providing a silicon precursor and a dopant precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the semiconductor processing chamber. A silicon-containing material may be formed on the substrate. The method may include: contacting the silicon-containing material with the silicon precursor and the dopant precursor. The method may include: forming a doped silicon-containing material on the silicon-containing material. The method may include: oxidizing the substrate. The oxidation may form an oxidized doped silicon-containing material. The method may include: etching the oxidized doped silicon-containing material.

[0006] In some embodiments, the pressure within the semiconductor processing chamber may be maintained at less than or about 760 Torr. The temperature within the semiconductor processing chamber may be maintained at less than or about 1200 °C. The silicon precursor may be or may include: silane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), tetrasilane (Si 4 H 10 ), dichlorosilane (SiH 2 Cl 2 ) or trichlorosilane (SiHCl 3)). The dopant precursor may include phosphorus. The dopant precursor contains boron. The method may include: providing an etchant precursor along with a silicon precursor and a dopant precursor. The etchant precursor may be or may include an oxygen-containing precursor or a chlorine-containing precursor. Oxidizing the substrate may include: contacting the substrate with an oxygen-containing precursor or treating the substrate with a laser. Oxidizing the substrate may increase the doping depth in the silicon-containing material to greater than or about 10 nm. The method may include: removing a defective silicon-containing material formed on a silicon nitride material to be formed on the substrate.

[0007] Some embodiments of the present technology may cover semiconductor processing methods. The method may include: providing a silicon precursor and a dopant precursor to a processing region of a semiconductor processing chamber. A silicon-containing material may be deposited on a substrate disposed in the semiconductor processing chamber. The silicon-containing material may be a silicon channel of a 3D DRAM structure. The method may include: contacting the silicon-containing material with the silicon precursor and the dopant precursor. The method may include: forming a doped silicon-containing material on the silicon-containing material. The method may include: oxidizing the substrate. Oxidation may form an oxidized doped silicon-containing material.

[0008] In some embodiments, the doped silicon-containing material may be formed by chemical vapor deposition. The dopant precursor may be or may include: phosphine (PH 3 ), arsine (AsH 3 ), nitrogen (N 2 ), ammonia (NH 3 ), germane (GeH 4 ), borane (BH 3 ), diborane (B 2 H 6 ), trimethylgallium (Ga(CH 3 ) 3 ), aluminum chloride (AlCl 3 ), trimethylaluminum (C 6 H1 5 Al) or methylsilane (CH 3 SiH 3 ). The 3D DRAM structure further includes silicon- and germanium-containing materials deposited above and below the silicon-containing material, and silicon- and nitrogen-containing materials extending from the silicon- and germanium-containing materials. The silicon channel may extend between respective portions of the silicon- and nitrogen-containing materials. The silicon channel may be characterized by: a depth greater than or about 300 nm and a width greater than or about 5 nm. The method may include: removing the oxidized doped silicon-containing material from the silicon-containing material. The method may include: removing silicon by-products from the silicon- and nitrogen-containing materials.

[0009] Some embodiments of the present technology may encompass semiconductor structures. The structure may include a silicon-containing substrate. The structure may include: a silicon and germanium material extending into a recess formed in the silicon-containing substrate. The structure may include: a silicon and nitrogen material extending from the silicon and germanium material. The silicon and nitrogen material may define a channel. The structure may include: a doped silicon material extending from the silicon-containing substrate within the channel.

[0010] In some embodiments, a dopant from the doped silicon material may be used to dope the silicon-containing substrate to a doping depth greater than or about 10 nm. The doped silicon material may be formed through chemical vapor deposition.

[0011] Such a technology may provide many benefits relative to conventional processing methods. For example, an oxidation process after depositing the doped silicon material may drive the dopant further into the underlying material. This increased doping depth may reduce the resistivity and ohmic contact between the silicon channel and the metal silicide. In addition, the oxidation process may oxidize byproduct materials formed on other materials of the structure. The subsequent removal or etching of the oxidized material may also remove the byproduct materials formed during the deposition of the doped silicon material. These and other embodiments, as well as their advantages and features, are described in more detail in conjunction with the following description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A further understanding of the nature and advantages of the disclosed technology can be realized by referring to the remainder of the specification and the drawings.

[0013] Figure 1 A top plan view showing an exemplary processing system according to some embodiments of the present technology.

[0014] Figure 2 A schematic cross-sectional view showing an exemplary plasma system according to some embodiments of the present technology.

[0015] Figure 3 An operation showing an exemplary method of semiconductor processing according to some embodiments of the present technology.

[0016] Figures 4A to 4D A cross-sectional view showing a semiconductor structure according to some embodiments of the present technology.

[0017] The drawings include several diagrams as schematic illustrations. It should be understood that the drawings are for illustrative purposes and should not be considered to be to scale unless specifically stated. In addition, as schematic illustrations, the drawings are provided to assist in understanding and may not include all aspects or information compared to a real-world representation, and may include exaggerated materials for illustrative purposes.

[0018] In the drawings, similar components and / or features may have the same reference numerals. Further, each of the same type of components may be distinguished by adding a letter after the reference numeral (the letter differentiating among the similar components). If only the first reference numeral is used in the specification, the description applies to any one of the similar components having the same first reference numeral, regardless of the letter. Detailed Description

[0019] As the dimensions of 3D DRAM structures increase, the aspect ratios of the silicon channels and other structures increase, sometimes dramatically. During 3D DRAM processing, when other materials, such as silicon nitride and silicon oxide, form high aspect ratio features with a silicon material, such as a substrate, a silicon channel is formed, thereby forming the bottom end of the feature. In subsequent processing, source and drain regions are formed by doping the underlying silicon-containing material. Subsequent processing may form contacts over the source and drain regions.

[0020] Conventional doping of the underlying silicon-containing material may be accomplished by epitaxial growth of doped silicon. Depending on whether a source or a drain is to be formed, the underlying silicon may be doped to be p-type silicon or n-type silicon. Conventional doping involves epitaxially depositing doped silicon over the underlying silicon-containing material. A portion of the dopant in the silicon may enter the underlying silicon-containing material, thereby doping the underlying silicon-containing material. However, as the dimensions of the structures increase and the demand for high-quality structures increases, these conventional techniques may not provide sufficient doping depth or concentration. In addition, the conventional techniques deposit byproduct materials elsewhere on the structure, which may impede subsequent processing, require intermediate processing to remove the byproduct materials, or reduce the final device functionality.

[0021] The present technique overcomes these problems by performing an oxidation process after depositing the doped silicon. Due to the bonding between the doped silicon and the oxidized silicon material, oxidation can drive additional dopants into the underlying silicon-containing material. In addition to the increased doping depth, oxidation can drive an increased amount of dopants into the underlying silicon-containing material and can thereby increase the dopant concentration. The increased doping depth and increased dopant concentration can result in low resistivity and ohmic contact with the silicon channel and contacts, such as metal silicides. In addition, oxidation may oxidize the byproduct materials deposited elsewhere on the structure. A subsequent etch operation to remove the oxidation material adjacent to the doped silicon can also remove the oxidized byproduct materials.

[0022] Although the remainder of the disclosure will routinely utilize the disclosed techniques to denote specific deposition and etch processes, it will be readily understood that the systems and methods are equally applicable to other deposition and etch chambers, and processes that may occur within such chambers. Accordingly, the techniques should not be considered so limited as to be used solely with these specific deposition processes or chambers. Before discussing additional details of embodiments in accordance with the present techniques, the present disclosure will discuss one possible system and chamber that can be used to perform deposition processes in accordance with embodiments of the present techniques.

[0023] Figure 1 FIG. 4 shows a top plan view of one embodiment of a processing system 100 for deposition, etch, bake, and cure chambers in accordance with an embodiment. In the figure, a pair of front-opening unified wafer cassettes 102 supply substrates of various sizes, which are received by a robotic arm 104 and placed within a low-pressure holding zone 106, and then the substrates are placed into one of substrate processing chambers 108a-108f, which are positioned in series sections 109a-109c. A second robotic arm 110 can be used to transport substrate wafers from the holding zone 106 to and from the substrate processing chambers 108a-108f. Each substrate processing chamber 108a-108f can be configured to perform several substrate processing operations, including the formation of stacks of semiconductor materials as described herein, as well as plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and other substrate processes (including annealing, ashing, etc.).

[0024] The substrate processing chambers 108a-108f can include one or more system components for depositing, annealing, curing, and / or etching a hard mask layer on a substrate. In one configuration, two pairs of processing chambers (e.g., 108c-108d and 108e-108f) can be used to deposit a hard mask layer on a substrate, and a third pair of processing chambers (e.g., 108a-108b) can be used to etch the deposited hard mask (i.e., hard mask opening operation). In another configuration, all three pairs of chambers (e.g., 108a-108f) can be configured to deposit and etch a hard mask layer on a substrate. Any one or more of the processes described can be performed in chambers separate from the manufacturing system as shown in different embodiments. It will be understood that additional configurations of system 100 for hard mask layer deposition, etch, bake, and cure chambers are envisioned.

[0025] Figure 2Shows a schematic cross-sectional view of an exemplary plasma system 200 in accordance with some embodiments of the present technology. The plasma system 200 may illustrate a pair of processing chambers 108, which may be mounted in one or more of the above-described tandem segments 109, and may include a lid stack component in accordance with an embodiment of the present technology, and as may be further explained below. The plasma system 200 generally may include a chamber body 202 having sidewalls 212, a bottom wall 216, and an inner sidewall 201 that define a pair of processing regions 220A and 220B. Each of the processing regions 220A to 220B may be configured similarly, and each of the processing regions 220A to 220B may include the same components.

[0026] For example, the processing region 220B (whose components may also be included in the processing region 220A) may include a pedestal 228, which is disposed in the processing region via a channel 222 formed in the bottom wall 216 of the plasma system 200. The pedestal 228 may provide a heater adapted to support a substrate 229 on an exposed surface (such as a body portion) of the pedestal. The pedestal 228 may include a heating element 232, such as a resistive heating element, which may heat and control the substrate temperature at a desired process temperature. The pedestal 228 may also be heated by a remote heating element, such as a lamp assembly or any other heating device.

[0027] The body of the pedestal 228 may be coupled to a shaft 226 by a flange 233. The shaft 226 may electrically couple the pedestal 228 to a power outlet or power box 203. The power box 203 may include a drive system that controls the raising and movement of the pedestal 228 within the processing region 220B. The shaft 226 may also include a power interface to provide power to the pedestal 228. The power box 203 may also include interfaces for power and temperature indicators, such as a thermocouple interface. The shaft 226 may include a base assembly 238 adapted to removably couple to the power box 203. A circumferential ring 235 is shown above the power box 203. In some embodiments, the circumferential ring 235 may be a shoulder adapted to serve as a mechanical stop, or a platform configured to provide a mechanical interface between the base assembly 238 and the upper surface of the power box 203.

[0028] A rod 230 may be included that passes through a channel 224 formed in the bottom wall 216 of the processing region 220B, and the rod 230 may be utilized to position a substrate lift pin 261 that passes through the body of the pedestal 228. The substrate lift pin 261 may selectively separate the substrate 229 from the pedestal to facilitate the exchange of the substrate 229 with a robot that is used to transfer the substrate 229 into and out of the processing region 220B via a substrate transfer port 260.

[0029] The chamber lid 204 may be coupled to the top portion of the chamber body 202. The lid 204 may house one or more precursor delivery systems 208 coupled to the lid 204. The precursor delivery system 208 may include a precursor inlet channel 240 that may deliver reactants and cleaning precursors to the processing region 220B via a dual-channel showerhead 218. The dual-channel showerhead 218 may include an annular baseplate 248 having a baffle 244 disposed in the middle of the panel 246. A radio frequency (“RF”) source 265 may be coupled to the dual-channel showerhead 218, and the RF source 265 may power the dual-channel showerhead 218 to facilitate generating a plasma region between the panel 246 of the dual-channel showerhead 218 and the pedestal 228. The dual-channel showerhead 218 and / or the panel 246 may include one or more openings to allow precursors to flow from the precursor delivery system 208 to the processing regions 220A and / or 220B. In some embodiments, the openings may include at least one of straight-shaped openings and conical openings. In some embodiments, the RF source may be coupled to other parts of the chamber body 202, such as the pedestal 228, to facilitate plasma generation. A dielectric insulator 258 may be disposed between the lid 204 and the dual-channel showerhead 218 to prevent conduction of RF power to the lid 204. A shadow ring 206 may be disposed on the periphery of the pedestal 228, and the shadow ring 206 engages with the pedestal 228.

[0030] Optional cooling channels 247 may be formed in the annular baseplate 248 of the precursor delivery system 208 to cool the annular baseplate 248 during operation. A heat transfer fluid such as water, ethylene glycol, gas, etc. may be circulated through the cooling channels 247 so that the baseplate 248 can be maintained at a predetermined temperature. A liner assembly 227 may be disposed in the processing region 220B adjacent to the sidewalls 201, 212 of the chamber body 202 to prevent the sidewalls 201, 212 from being exposed to the processing environment within the processing region 220B. The liner assembly 227 may include a circumferential pumping chamber 225 that may be coupled to a pumping system 264 configured to discharge gases and by-products from the processing region 220B and control the pressure within the processing region 220B. A plurality of discharge ports 231 may be formed in the liner assembly 227. The discharge ports 231 may be configured to allow gases to flow from the processing region 220B to the circumferential pumping chamber 225 in a manner that enhances processing within the system 200.

[0031] As mentioned above, the present technology may form a doped silicon-containing material that, after oxidation, can drive dopants into the underlying material. Turning to Figure 3, which shows exemplary operations in method 300 for forming a semiconductor structure according to an embodiment of the present technology. Method 300 may include one or more operations before the start of the method, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed before the described operations. For example, the method may start after depositing several layers, such as for generating a 3D DRAM structure. However, as explained above, it can be understood that the drawings only show one exemplary process in which the processes according to the embodiments of the present technology can be employed, and this specification is not intended to limit the technology only to this process. Some or all of these operations may be performed in a chamber or system as described above, or some or all of these operations may be performed in different chambers on the same system tool, which may include a chamber in which the operations of method 300 can be performed.

[0032] As shown, method 300 may include several optional operations, which may or may not be specifically associated with some embodiments of the method according to the present technology. For example, many operations are described to provide a wider range of structure formation, but these operations are not critical to the technology, or may be performed by alternative methods to be further discussed below. Method 300 may describe Figures 4A to 4D the operations schematically illustrated in, and will be described in connection with the operations of method 300 Figures 4A to 4D the illustration of. It should be understood that Figures 4A to 4D only a partial schematic is shown, and the substrate may contain any number of structural segments having the aspects shown in the figure, as well as alternative structural aspects that may still benefit from the operations of the present technology.

[0033] Method 300 may or may not involve optional operations to develop the semiconductor structure for a specific manufacturing operation. It should be understood that method 300 may be performed on any number of semiconductor structures or substrates 405, such as Figure 4A shown in, including an exemplary structure on which oxidation-enhanced doping can be formed. As Figure 4A shown in, substrate 405 may have several material layers deposited to cover the substrate. Substrate 405 may be any number of materials, such as a base wafer or substrate made of silicon or silicon-containing materials, germanium, other substrate materials, and one or more materials that can be formed during semiconductor processing to cover the substrate.

[0034] Structure 400 may show a partial view of a stack of alternating material layers, which may be used for 3D DRAM memory formation in some embodiments. As Figure 4AAs shown, structure 400 may include a material extending into a recess formed in substrate 405. The material may be a silicon-germanium-containing material 410. A silicon-nitrogen-containing material 415 may extend from the silicon-germanium-containing material 410 and may define a silicon channel in the structure, such as a silicon channel in a 3D DRAM structure. That is, the silicon channel may extend between respective portions of the silicon-nitrogen-containing material 415. The silicon channel may be characterized by a depth greater than or about 300 nm, such as greater than or about 400 nm, greater than or about 500 nm, greater than or about 600 nm, greater than or about 700 nm or greater. The silicon channel may be characterized by a width or critical dimension greater than or about 5 nm, such as greater than or about 25 nm, greater than or about 50 nm, greater than or about 75 nm, greater than or about 100 nm or greater.

[0035] In operation 305, method 300 may include: providing a silicon precursor and a dopant precursor to a processing region of a semiconductor processing chamber, such as a processing region of a chamber in plasma system 200. When the deposition precursors flow into the chamber, the substrate 405 and layers discussed above may be present in the substrate processing region of the semiconductor processing chamber. The silicon precursor that may be used in operation 305 may be or may include any number of silicon precursors. For example, any silicon precursor used for depositing a silicon-containing material, such as a doped silicon-containing material, may be used. As a non-limiting example, in embodiments of the present technology, the silicon precursor may be or may include: silane (SiH 4 )), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), tetrasilane (Si 4 H 10 ), dichlorosilane (SiH 2 Cl 2 ) or trichlorosilane (SiHCl 3 ). The flow rate of the silicon precursor may be greater than or about 50 sccm, greater than or about 100 sccm, greater than or about 250 sccm, greater than or about 500 sccm, greater than or about 1000 sccm, greater than or about 2500 sccm, greater than or about 5000 sccm, greater than or about 10000 sccm or greater.

[0036] The dopant precursor that may be used in operation 305 may be or may include any number of dopant precursors. For example, any dopant precursor used for depositing a doped silicon-containing material may be used. As a non-limiting example, in embodiments of the present technology, the dopant precursor may include phosphorus or boron, such as for forming a doped source region or drain region. For example, the dopant precursor may be or may include: phosphine (PH 3 ), arsine (AsH3 ), nitrogen (N 2 ), ammonia (NH 3 ), germane (GeH 4 ), borane (BH 3 ), diborane (B 2 H 6 ), trimethylgallium (Ga(CH 3 )) 3 ), aluminum chloride (AlCl 3 ), trimethylaluminum (C 6 H1 5 Al) or methylsilane (CH 3 SiH 3 ). The flow rate of the dopant precursor can be greater than or about 50 sccm, greater than or about 100 sccm, greater than or about 250 sccm, greater than or about 500 sccm, greater than or about 1000 sccm, greater than or about 2500 sccm, greater than or about 5000 sccm, greater than or about 10000 sccm or greater. The flow rate of the dopant precursor can depend on the target doping concentration, as well as other process conditions such as temperature and pressure. However, compared to conventional epitaxial growth processes, a lower dopant precursor flow rate may be required due to the effects of subsequent oxidation described herein.

[0037] In optional operation 310, method 300 can include: providing an etchant precursor in conjunction with the silicon-containing precursor and the dopant precursor. The etchant precursor can maintain selective deposition of the material. As discussed previously, structure 400 includes multiple materials, and providing the etchant precursor can reduce and / or remove materials that are undesirably deposited on other materials in structure 400. By way of non-limiting example, any etchant precursor for reducing and / or removing materials from silicon- and nitrogen-containing material 415 can be provided in conjunction with the silicon-containing precursor and the dopant precursor. By way of non-limiting example, in embodiments of the present technology, the etchant precursor can include an oxygen-containing precursor or a chlorine-containing precursor. By way of example, the etchant precursor can be or can include molecular oxygen (O 2 ), hydrogen chloride (HCl) or diatomic chlorine (Cl 2 ). However, in some embodiments, to maintain an oxygen-free semiconductor processing chamber, the etchant precursor can exclude oxygen-containing precursors. As discussed herein, by maintaining an oxygen-free semiconductor processing chamber, the silicon-containing material to be deposited can be oxygen-free, which can increase the drive of the dopant into the underlying material.

[0038] A carrier gas can be combined with the silicon-containing precursor and / or the dopant precursor flowing into the substrate processing region of the substrate processing chamber. In embodiments, the carrier gas can be helium, argon, molecular nitrogen (N 2 ), and molecular hydrogen (H 2) and one or more of other carrier gases. The carrier gas may be beneficial to the mechanical properties of the film. In addition, the carrier gas may also make it easier to impinge the plasma.

[0039] Once the silicon-containing precursor and the dopant precursor are provided to the processing region, method 300 may include: forming a plasma of the silicon-containing precursor and the dopant precursor within the processing region. The plasma of the silicon-containing precursor and the dopant precursor can be generated at any plasma power suitable for depositing the doped silicon-containing material. Generating the plasma of the silicon-containing precursor and the dopant precursor can increase the deposition rate and promote the interaction between the precursors, thereby increasing the boron concentration or phosphorus in the deposited material.

[0040] In operation 315, method 300 may include: bringing the substrate 405 (which may be a silicon-containing material) into contact with the silicon-containing precursor and the dopant precursor. As Figure 4B shown, in operation 320, method 300 may include: forming a doped silicon-containing material 420. The doped silicon-containing material 420 may be formed on the silicon-containing material of the substrate 405. The doped silicon-containing material can be formed by chemical vapor deposition (CVD), and chemical vapor deposition (CVD) may include atomic layer epitaxy (ALE). Chemical vapor deposition includes the use of many techniques, such as plasma-assisted CVD (PACVD), plasma-enhanced CVD (PECVD), atomic layer CVD (ALCVD), organometallic or metalorganic CVD (OMCVD or MOCVD), laser-assisted CVD (LA-CVD), ultraviolet CVD (UV-CVD), hot-wire CVD (HWCVD), reduced pressure CVD (RP-CVD), and ultra-high vacuum CVD (UHV-CVD).

[0041] The thickness of the doped silicon-containing material 420 can affect the doping depth of the dopant into the underlying material (such as the carbon-containing material of the substrate 405). When the thickness of the doped silicon-containing material 420 is larger, the dopant can be driven further into the underlying material to a greater doping depth and / or the dopant concentration in the underlying material can be increased. In an embodiment, the thickness of the doped silicon-containing material 420 can be greater than or about 5 nm, such as greater than or about 10 nm, greater than or about 15 nm, greater than or about 20 nm, greater than or about 25 nm, greater than or about 30 nm, greater than or about 35 nm, greater than or about 40 nm, greater than or about 45 nm, greater than or about 50 nm or greater. Although larger thicknesses are envisioned, thicknesses less than or about 50 nm or less than or about 25 nm may be sufficient.

[0042] While forming the doped silicon-containing material 420, by-product material 425 may be deposited on other materials (such as silicon- and nitrogen-containing material 415) in structure 400. As discussed previously, an etchant precursor may be provided along with the silicon precursor and the dopant precursor, but some deposition of materials may still occur on the surrounding materials. The by-product material 425 or defective material may include polycrystalline silicon-containing material or amorphous silicon-containing material.

[0043] The deposition temperature of the material may affect the deposition on the exposed material. Thus, in some embodiments, forming the doped silicon-containing material may be performed at a temperature less than or about 1200 °C, and the process may be performed at temperatures of less than or about 1100 °C, less than or about 1000 °C, less than or about 900 °C, less than or about 800 °C, less than or about 700 °C, less than or about 600 °C, less than or about 500 °C, less than or about 400 °C, less than or about 300 °C, less than or about 200 °C, or less.

[0044] The deposition pressure may also affect the deposition on the exposed material. For example, a higher pressure may enhance the directionality of the silicon precursor and the dopant precursor. Thus, in some embodiments, forming the carbon-containing material may include specific materials delivered at a pressure less than or about 760 Torr, and may be less than or about 700 Torr, less than or about 600 Torr, less than or about 500 Torr, less than or about 400 Torr, less than or about 300 Torr, less than or about 200 Torr, less than or about 100 Torr, less than or about 50 Torr, less than or about 10 Torr, less than or about 5 Torr, less than or about 1 Torr, less than or about 500 mTorr, less than or about 250 mTorr, less than or about 100 mTorr, less than or about 1 mTorr, less than or about 0.1 mTorr, or less. At high pressures (such as pressures greater than 760 Torr), the selectivity may decrease. At lower pressures (such as pressures below 0.1 mTorr), the doping concentration may decrease. Thus, the pressure may be maintained between about 0.1 mTorr and about 760 Torr, or any other range encompassing these values.

[0045] As Figure 4CAs shown, at operation 325, method 300 may include: oxidizing substrate 405. In an embodiment, method 300 may include: transferring substrate 405 from a first chamber to a second chamber before oxidizing substrate 405. However, it is contemplated that substrate 405 may be maintained in one chamber for both deposition and oxidation. During the oxidation process at operation 325, a silicon-containing precursor and / or a dopant precursor may continue to be provided. Continuously providing a silicon-containing precursor and / or a dopant precursor may allow a silicon- and oxygen-containing material 430 to be formed over the previously deposited doped silicon-containing material 420. Alternatively, if a silicon-containing precursor is not provided, a silicon- and oxygen-containing material 430 may be formed by interacting with the underlying doped silicon-containing material 420. Oxidizing structure 400 (including substrate 405) may drive a dopant material (such as phosphorus or boron) into the material below the doped silicon-containing material 420 (such as the silicon-containing material of substrate 405). Forming the silicon- and oxygen-containing material 430 may result in bonding with the doped silicon-containing material 420. This bond may be a Si—O bond, which may have a lower activation energy than the bond between silicon and the dopant. The lower activation energy may allow the dopant (such as phosphorus or boron) to be released and driven into the underlying material. While oxidizing substrate 405, by-product material 425 may also be oxidized to form oxidized by-product material 435.

[0046] Oxidizing substrate 405 at operation 325 may include: contacting substrate 405 with an oxygen-containing precursor, or laser treating substrate 405. In an embodiment where oxidizing substrate 405 includes contacting substrate 405 with an oxygen-containing precursor, the oxygen-containing precursor may be any oxygen-containing precursor operable to form an oxidation material. For example, the oxygen-containing precursor may be vapor or water (H 2 O), molecular oxygen (O 2 ) or any other oxygen-containing precursor used in semiconductor processing. The oxygen-containing precursor (which may or may not be provided together with the silicon-containing precursor) may form a silicon- and oxygen-containing material 430 over the doped silicon-containing material 420. In an embodiment where oxidizing substrate 405 includes laser treating substrate 405, ultraviolet (UV) pulse laser excitation in an oxygen environment may form a silicon- and oxygen-containing material 430 over the doped silicon-containing material 420. Whether contacting substrate 405 with an oxygen-containing precursor or laser treating substrate 405 may form a silicon- and oxygen-containing material 430 over the doped silicon-containing material 420. As discussed previously, the formation and bonding of the silicon- and oxygen-containing material 430 over the doped silicon-containing material 420 may drive the dopant into the underlying material.

[0047] Similar to the doped silicon-containing material 420, the thickness of the silicon- and oxygen-containing material 430 can affect the doping depth of dopants into the underlying material, such as the carbon-containing material of the substrate 405. When the thickness of the silicon- and oxygen-containing material 430 is relatively large, the dopants can be driven further into the underlying material to achieve a greater doping depth and / or the dopant concentration in the underlying material can be increased. In an embodiment, the thickness of the silicon- and oxygen-containing material 430 can be greater than or about 10 nm, such as greater than or about 20 nm, greater than or about 30 nm, greater than or about 40 nm, greater than or about 50 nm, greater than or about 60 nm, greater than or about 70 nm, greater than or about 80 nm, greater than or about 90 nm, greater than or about 100 nm or greater. Although greater thicknesses are contemplated, a thickness less than or about 50 nm or 20 nm may be sufficient. In an embodiment, the thickness of the silicon- and oxygen-containing material 430 can be at least twice the thickness of the doped silicon-containing material 420, which can allow the silicon- and oxygen-containing material 430 and the resulting bond to drive the dopant material into the underlying material.

[0048] The oxidation temperature of the material can affect the incorporation of dopants on the underlying material, such as the substrate 405. Thus, in some embodiments, the substrate 405 can be oxidized at a temperature greater than or about 500 °C, and the oxidation process can be carried out at the following temperatures: greater than or about 550 °C, greater than or about 600 °C, greater than or about 650 °C, greater than or about 700 °C, greater than or about 750 °C, greater than or about 800 °C, greater than or about 850 °C, greater than or about 900 °C, greater than or about 950 °C, greater than or about 1000 °C or greater. In an embodiment, the substrate 405 can be oxidized at a temperature between about 650 °C and about 750 °C. At higher oxidation temperatures, it may be easier to oxidize the structure 400 and form the silicon- and oxygen-containing material 430. However, the thermal budget may limit the temperature at which the oxidation process can be carried out. Thus, in some embodiments, the substrate 405 can be oxidized at a temperature greater than or about 1000 °C, and the oxidation process can be carried out at the following temperatures: greater than or about 950 °C, greater than or about 900 °C, greater than or about 850 °C, greater than or about 800 °C, greater than or about 750 °C, greater than or about 700 °C, greater than or about 650 °C, greater than or about 600 °C, greater than or about 550 °C, greater than or about 500 °C or less. However, lower oxidation temperatures may slow down the formation of the silicon- and oxygen-containing material 430, which can also limit the driving of dopants into the underlying material.

[0049] Oxidation pressure can also affect dopant incorporation into underlying materials such as substrate 405. The oxidation pressure can be maintained at greater than or about 1 Torr, and can be maintained at greater than or about 5 Torr, greater than or about 10 Torr, greater than or about 50 Torr, greater than or about 100 Torr, greater than or about 200 Torr, greater than or about 300 Torr, greater than or about 400 Torr, greater than or about 500 Torr, greater than or about 600 Torr, greater than or about 700 Torr, greater than or about 760 Torr or greater. At higher pressures (which may indicate a higher oxidant flow rate), the oxidation rate can be increased. The increased oxidation rate can drive dopants further into the underlying material, thereby increasing the doping depth and / or concentration.

[0050] The oxidation at operation 325 can continue for a time period sufficient to form the silicon- and oxygen-containing material to a desired thickness. In an embodiment, the oxidation can continue for greater than or about 1 minute, such as greater than or about 5 minutes, greater than or about 10 minutes, greater than or about 15 minutes, greater than or about 20 minutes, greater than or about 25 minutes, greater than or about 30 minutes, greater than or about 35 minutes, greater than or about 40 minutes, greater than or about 45 minutes, greater than or about 50 minutes, greater than 55 minutes, greater than 60 minutes or longer. However, at longer durations, the increased oxidation duration may highly oxidize substrate 405 or damage structure 400 due to the thermal budget. Thus, in some embodiments, the oxidation can continue for less than or about 30 minutes, such as less than or about 25 minutes, less than or about 20 minutes, less than or about 15 minutes, less than or about 10 minutes or shorter.

[0051] After the oxidation process, the doping depth in the silicon-containing material of substrate 405 can be greater than or about 10 nm, and can be greater than or about 15 nm, greater than or about 20 nm, greater than or about 25 nm, greater than or about 30 nm, greater than or about 35 nm, greater than or about 40 nm, greater than or about 45 nm, greater than or about 50 nm, greater than 55 nm, greater than 60 nm, greater than 65 nm, greater than 70 nm, greater than 75 nm, greater than 80 nm or greater. Compared to conventional techniques that do not perform a post-deposition oxidation step, the doping depth and concentration provided in this embodiment can be significantly increased. In conventional techniques, the doping depth can be limited to less than 10 nm or less. This increased doping depth and concentration can result in a low resistivity and an ohmic contact with the silicon channel and subsequently formed metal silicide (such as the contacts in a 3D DRAM structure).

[0052] As Figure 4DAs shown, at operation 330, method 300 may include: etching a silicon- and oxygen-containing material 430. In an embodiment, method 300 may include: before etching, transferring substrate 405 from a first chamber to a second chamber. However, it is contemplated that substrate 405 may be maintained in one chamber for both oxidation and etching. The etching operation may include any wet etching or dry etching process. For example, a wet etching process using a fluorine-containing precursor (such as diluted hydrofluoric acid (DHF)) may be performed to etch and remove the oxidized doped silicon-containing material 420. The underlying doped silicon-containing material 420 may act as an etch stop and may remain after operation 330. In an embodiment, a dry etching operation may be performed using a fluorine-containing precursor (such as difluoromethane (CH 2 F 2 2) or any other fluorine-containing precursor). The fluorine-containing precursor used in the dry etching operation may include a fluorocarbon having a high carbon-to-fluorine ratio (such as greater than 1:2) to maximize the etch selectivity between the silicon- and oxygen-containing material 430 and other materials in structure 400 (such as the silicon- and nitrogen-containing material 415). While etching the oxidized doped silicon-containing material 420, oxidized byproduct material 435 may also be removed. For example, the carbon-to-fluorine ratio may maintain an etch selectivity of SiO 2 2:SiN x at greater than 5:1 or greater than 10:1.

[0053] Compared to conventional techniques, this embodiment can successfully drive the dopant further into the underlying material. During the deposition of the doped material to be driven into the underlying material, conventional techniques also produce unwanted byproduct materials on other materials. In addition to driving the dopant further into the underlying material via the oxidation step, this embodiment can also oxidize the unwanted byproduct materials. During subsequent etching or removal operations, this oxidized unwanted byproduct material can also be removed, resulting in a cleaner and more desirable structure.

[0054] In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of the various embodiments of the present technology. However, it will be apparent to one of ordinary skill in the art that some of these details may not be required or that certain embodiments may be practiced with additional details.

[0055] After several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Additionally, to avoid unnecessarily obscuring the present technology, several well-known processes and elements have not been described. Therefore, the foregoing description should not be considered as limiting the scope of the present technology.

[0056] Where a range of values is provided, it is to be understood that each intermediate value, to the smallest fraction of the lower limit unit, between the upper and lower limits of that range is also specifically disclosed, unless the context clearly dictates otherwise. Any stated value or unstated intermediate value in a stated range is included in any narrower range formed by any other stated value or intermediate value in that stated range. The upper and lower limits of those smaller ranges may independently be included in or excluded from the range, and each range where either, neither, or both of the limits are included in the smaller range is also covered within the technology, subject to any specifically excluded limits in the stated range. Where the stated range includes one or both of such limits, ranges excluding either or both of the included limits are also included.

[0057] As used herein and in the appended claims, unless expressly specified otherwise herein, the singular forms "a", "an", and "the" include plural references. Thus, for example, reference to "a material" includes a plurality of such materials, and reference to "the precursor" includes reference to one or more precursors known to those of ordinary skill in the art and their equivalents, and so forth.

[0058] Furthermore, when the words "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including" are used in this specification and in the claims below, it is intended to specify the presence of the stated feature, integer, component, or operation, but these words do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. A semiconductor processing method, the method comprises: providing a silicon-containing precursor and a dopant precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed in the semiconductor processing chamber, and wherein a silicon-containing material is formed on the substrate; contacting the silicon-containing material with the silicon-containing precursor and the dopant precursor; forming a doped silicon-containing material on the silicon-containing material; oxidizing the substrate, wherein the oxidation forms an oxidized doped silicon-containing material; and etching the oxidized doped silicon-containing material.

2. The semiconductor processing method according to claim 1, wherein the pressure in the semiconductor processing chamber is maintained at less than or about 760 Torr.

3. The semiconductor processing method according to claim 1, wherein the temperature in the semiconductor processing chamber is maintained at less than or about 1200 °C.

4. The semiconductor processing method according to claim 1, wherein the silicon-containing precursor comprises silane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), tetrasilane (Si 4 H 10 ), dichlorosilane (SiH 2 Cl 2 ), or trichlorosilane (SiHCl 3 ).

5. The semiconductor processing method according to claim 1, wherein the dopant precursor comprises phosphorus.

6. The semiconductor processing method according to claim 1, wherein the dopant precursor comprises boron.

7. The semiconductor processing method according to claim 1, the method further comprises: providing an etchant precursor along with the silicon-containing precursor and the dopant precursor, wherein the etchant precursor comprises an oxygen-containing precursor or a chlorine-containing precursor.

8. The semiconductor processing method according to claim 1, wherein oxidizing the substrate comprises contacting the substrate with an oxygen-containing precursor or treating the substrate with a laser.

9. The semiconductor processing method according to claim 1, wherein oxidizing the substrate increases the doping depth in the silicon-containing material to greater than or about 10 nm.

10. The semiconductor processing method according to claim 1, the method further comprises: removing a defective silicon-containing material formed on a silicon nitride material formed on the substrate.

11. A semiconductor processing method, the method comprises: providing a silicon-containing precursor and a dopant precursor to a processing region of a semiconductor processing chamber, wherein a silicon-containing material is deposited on a substrate disposed in the semiconductor processing chamber, and wherein the silicon-containing material comprises a silicon channel of a 3D DRAM structure; contacting the silicon-containing material with the silicon-containing precursor and the dopant precursor; forming a doped silicon-containing material on the silicon-containing material; and oxidizing the substrate, wherein the oxidation forms an oxidized doped silicon-containing material.

12. The semiconductor processing method according to claim 11, wherein the doped silicon-containing material is formed by chemical vapor deposition.

13. The semiconductor processing method as claimed in claim 11, wherein the dopant precursor includes phosphine (PH 3 ), arsine (AsH 3 ), nitrogen (N 2 ), ammonia (NH 3 ), germane (GeH 4 ), borane (BH 3 ), diborane (B 2 H 6 ), trimethylgallium (Ga(CH 3 ) 3 ), aluminum chloride (AlCl 3 ), trimethylaluminum (C 6 H1 5 Al) or methylsilane (CH 3 SiH 3 ).

14. The semiconductor processing method according to claim 11, wherein the 3D DRAM structure further comprises: a silicon- and germanium-containing material, the silicon- and germanium-containing material being deposited above and below the silicon-containing material; and a silicon- and nitrogen-containing material, the silicon- and nitrogen-containing material extending from the silicon- and germanium-containing material.

15. The semiconductor processing method according to claim 14, wherein: the silicon channel extends between respective portions of the silicon- and nitrogen-containing material; and the silicon channel is characterized by a depth greater than or about 300 nm and a width greater than or about 5 nm.

16. The semiconductor processing method as claimed in claim 11, the method further comprises: removing the oxidized doped silicon-containing material from the silicon-containing material.

17. The semiconductor processing method as claimed in claim 14, the method further comprises: removing silicon-containing by-products from the silicon- and nitrogen-containing material.

18. A semiconductor structure, the semiconductor structure comprising: a silicon-containing substrate; a silicon- and germanium-containing material, the silicon- and germanium-containing material extending into a recess formed in the silicon-containing substrate; a silicon- and nitrogen-containing material, the silicon- and nitrogen-containing material extending from the silicon- and germanium-containing material, wherein the silicon- and nitrogen-containing material defines a channel; and a doped silicon-containing material, the doped silicon-containing material extending from the silicon-containing substrate within the channel.

19. The semiconductor structure as claimed in claim 18, wherein the silicon-containing substrate is doped with a dopant from the doped silicon-containing material to a doping depth greater than or about 10 nm.

20. The semiconductor structure as claimed in claim 18, wherein the doped silicon-containing material is formed by chemical vapor deposition.

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