Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes an insulating layer; and an electrode portion disposed in the insulating layer, wherein the electrode portion includes a first electrode; a second electrode disposed on the first electrode; and a first via electrode and a second via electrode disposed between the first electrode and the second electrode, the first via electrode being connected to the first electrode and the second electrode, and a length of the second via electrode in a vertical direction being smaller than a length of the first via electrode in the vertical direction.

Description

Technical Field

[0001] Embodiments relate to a circuit board, and more particularly, to a circuit board having improved adhesion between an insulating layer and an electrode part, and a semiconductor package including the same. Background Art

[0002] As the performance of electrical / electronic products advances, technologies for arranging a greater number of semiconductor devices on a semiconductor package substrate of limited size are being proposed and studied. However, since general semiconductor packages are based on mounting a single semiconductor device, there are limitations in achieving desired performance.

[0003] Therefore, a semiconductor package for mounting a plurality of semiconductor devices using a plurality of circuit boards has recently been provided. The semiconductor package has a structure in which a plurality of semiconductor devices are connected to each other in a horizontal direction and / or a vertical direction on a circuit board. Therefore, the semiconductor package has the advantages of effectively utilizing the mounting area of ​​the semiconductor device and transmitting a high-speed signal through a short signal transmission path between the semiconductor devices.

[0004] Due to these advantages, the semiconductor package as described above is widely used in mobile devices and the like.

[0005] In addition, as the number of semiconductor devices and / or the size of each semiconductor device increases according to the trend of high integration, or as the functional parts of semiconductor devices are divided, semiconductor packaging applied to products providing the Internet of Things (IoT), autonomous vehicles, and high-performance servers will expand the concept to semiconductor chiplets.

[0006] Therefore, mutual communication between semiconductor devices and / or semiconductor chiplets has become important, and thus there is a trend to provide an interposer between a circuit board of a semiconductor package and the semiconductor device.

[0007] The interposer may be used as a redistribution layer that gradually increases the width or depth of a circuit pattern from a semiconductor device to a semiconductor package to facilitate mutual communication between semiconductor devices and / or semiconductor chiplets, or to interconnect a semiconductor device and a semiconductor package substrate, thereby smoothly transmitting electrical signals between the semiconductor device and the semiconductor package substrate, which has a relatively large circuit pattern compared to the circuit pattern of the semiconductor device.

[0008] The interposer may have an area greater than the total area of ​​a plurality of semiconductor devices and / or semiconductor chips (chiplets) so as to mount the plurality of semiconductor devices and / or semiconductor chips (chiplets) as a whole, or may be provided only in a portion for interconnection between semiconductor devices and / or semiconductor chips (chiplets). That is, the area of ​​the interposer may increase as the number of semiconductor devices and / or semiconductor chips (chiplets) increases, or the area of ​​the interposer may not increase. However, as the number of semiconductor devices and / or semiconductor chips (chiplets) increases, the area of ​​the circuit board of the semiconductor package tends to increase.

[0009] Therefore, as the area of ​​the semiconductor package increases, the area of ​​the electrode portion also increases. At this time, when the area of ​​the electrode portion increases, the problem of insufficient discharge of gas generated from the insulating layer in contact with the electrode portion may occur. In addition, when the gas is not discharged, the surface of the electrode portion may swell due to the gas, and as a result, the problem of peeling of the electrode portion from the insulating layer may occur.

[0010] Meanwhile, in order to solve these problems, the electrode portion of the conventional technology may be provided with a through hole corresponding to the gas outlet for exhausting gas. However, when the through hole is provided in the electrode portion, the area of ​​the electrode portion is reduced due to the through hole, and there is a problem that the rigidity of the semiconductor package is reduced due to the reduced area of ​​the electrode portion. In addition, when the rigidity is reduced, the problem of the semiconductor package being bent significantly in a specific direction may occur. In addition, the electrode portion of the semiconductor package may include an impedance matching portion that performs an impedance matching function, etc. At this time, the impedance matching portion and / or the electrode portion adjacent to the impedance matching unit vertically or horizontally may not be provided with a through hole corresponding to the gas outlet. For example, if the impedance matching portion and / or the electrode portion adjacent to the impedance matching portion is provided with a through hole, the impedance matching characteristics may be changed due to the through hole, and therefore, the electrical characteristics of the semiconductor package may be deteriorated. Summary of the invention

[0011]

Technical issues

[0012] Embodiments provide a circuit board having a novel structure and a semiconductor package including the same.

[0013] In addition, embodiments provide a circuit board having improved adhesion between an insulating layer and an electrode part, and a semiconductor package including the same.

[0014] The technical problems to be solved by the proposed implementation are not limited to the above-mentioned technical problems, and those skilled in the art in the field to which the proposed implementation is related can clearly understand other technical problems not mentioned from the following description.

[0015]

Technical solution

[0016] According to an embodiment, a circuit board includes an insulating layer; and an electrode portion arranged in the insulating layer, wherein the electrode portion includes a first electrode; a second electrode arranged on the first electrode; and a first via electrode and a second via electrode arranged between the first electrode and the second electrode, wherein the first via electrode is connected to the first electrode and the second electrode, and the length of the second via electrode in the vertical direction is less than the length of the first via electrode in the vertical direction.

[0017] In addition, the second via electrode is connected to the second electrode.

[0018] In addition, the second via electrode is spaced apart from the first via electrode in a horizontal direction.

[0019] In addition, the second via electrode extends from the second electrode toward the first electrode.

[0020] In addition, an upper surface of the second via electrode is located on the same plane as an upper surface of the first via electrode, and a lower surface of the second via electrode is positioned higher than a lower surface of the first via electrode.

[0021] In addition, the length of the second via electrode in the vertical direction satisfies the range of 30% to 70% of the length of the first via electrode in the vertical direction.

[0022] In addition, a width of the second via electrode in the horizontal direction is smaller than a width of the first via electrode in the horizontal direction.

[0023] In addition, the second via electrode has a slope in which a width thereof in a horizontal direction gradually changes as the second via electrode moves away from the second electrode.

[0024] In addition, the first via electrode has a slope in which a width thereof in a horizontal direction gradually changes from the second electrode toward the first electrode.

[0025] In addition, the slope of the second via electrode is the same as the slope of the first via electrode.

[0026] In addition, the first via electrode includes a first portion and a second portion, the first portion overlaps with the second via electrode in the insulating layer along a horizontal direction, and the second portion does not overlap with the second via electrode along the horizontal direction.

[0027] Meanwhile, the semiconductor package according to the embodiment includes a circuit board and a connection portion disposed on the second electrode on the circuit board.

[0028] In addition, the second via electrode extends from the second electrode and is disposed in the insulating layer, and the second electrode further includes a bonding portion extending outside the insulating layer and not overlapping the insulating layer in a horizontal direction, and the connecting portion is disposed on the bonding portion.

[0029] In addition, the bonding portion extends from the second electrode in a direction opposite to a direction in which the second via electrode extends.

[0030] In addition, the semiconductor package includes an interposer disposed on the connection portion, and the interposer includes at least one of an active interposer and a passive interposer.

[0031] Furthermore, the semiconductor package further includes a semiconductor device provided on the connection portion.

[0032]

Beneficial Effects

[0033] The circuit board of the embodiment may include an insulating layer; and an electrode portion disposed in the insulating layer. In addition, the electrode portion may include a first electrode; a second electrode disposed on the first electrode; and a first via electrode connecting the first electrode and the second electrode in a vertical direction. In addition, the electrode portion may include a second via electrode extending in a vertical direction, and the length of the second via electrode in the vertical direction may be less than the length of the first via electrode in the vertical direction. The second via electrode may extend from the second electrode in the vertical direction, and is therefore used to improve the adhesion between the insulating layer and the electrode portion. For example, the second via electrode may be used as an anchor point to firmly fix the electrode portion to the insulating layer. Therefore, the embodiment can improve the adhesion between the insulating layer and the electrode portion. Therefore, the embodiment can solve the physical reliability problem of the electrode portion peeling off from the insulating layer.

[0034] At this time, the insulating layer may generate gas during the curing process. In addition, if the gas is not completely removed to the outside of the insulating layer, the problem of the electrode portion protruding from the insulating layer due to the gas may occur. In order to solve this problem, a through hole for gas discharge can be formed in the electrode portion. However, if the through hole is provided in the electrode portion, the electrical characteristics (e.g., impedance characteristics) of the electrode portion may change, and thus electrical reliability problems may occur. In addition, if the through hole is provided in the electrode portion, the area of ​​the electrode portion may reduce the area of ​​the through hole, and the rigidity of the circuit board and the semiconductor package may be reduced accordingly. Therefore, there may be a problem that the circuit board and the semiconductor package are greatly bent in a specific direction.

[0035] In contrast, the embodiment provides a second via electrode in the electrode portion, thereby maintaining the rigidity of the circuit board and the semiconductor package without changing the electrical characteristics of the electrode portion, while improving the adhesion between the electrode portion and the insulating layer. Therefore, the embodiment can improve the overall product reliability of the circuit board and the semiconductor package.

[0036] In addition, as the number of input terminals and output terminals of semiconductor devices increases, the width and / or spacing of the terminals of semiconductor devices and / or semiconductor small chips become narrower. Therefore, the width and / or spacing of the electrodes set in the circuit board also become smaller. In addition, as the width and / or spacing of the electrodes become smaller, the contact area between the electrode portion and the insulating layer decreases, which may cause mechanical reliability problems in which the electrode portion is easily peeled off from the insulating layer. In addition, in order to minimize the width and / or spacing of the electrodes, the insulating layer may include a photosensitive material. The photosensitive material may be, for example, a PID (Photo Imageable Dielectric). The insulating layer with a photosensitive material can be used to form electrodes using a photolithography process, so that the width and / or spacing of the electrodes can be refined. At this time, the photosensitive material has the characteristic of lower adhesion to the electrode compared to the thermosetting material. Therefore, when the width and / or spacing of the electrode becomes thinner, or when the insulating layer includes a photosensitive material, the embodiment can solve the mechanical reliability problem of the electrode peeling off from the insulating layer by using a protrusion set in the electrode portion, thereby improving the overall product reliability of the circuit board and the semiconductor package.

[0037] In addition, the rigidity of the insulating layer provided with the photosensitive material may be lower than the rigidity of the thermosetting material provided with the reinforcing member. Therefore, the circuit board provided with the photosensitive material has the problem of being greatly bent in a specific direction. At this time, the embodiment can improve the rigidity of the circuit board by using a protrusion provided in the electrode, thereby preventing the circuit board and the semiconductor package from being greatly bent in a specific direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment.

[0039] Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0040] Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0041] Figure 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0042] Figure 1eis a cross-sectional view showing a semiconductor package according to a fifth embodiment.

[0043] Figure 1f is a cross-sectional view showing a semiconductor package according to a sixth embodiment.

[0044] Figure 1g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0045] Figure 2a is a cross-sectional view showing a circuit board according to the first embodiment.

[0046] Figure 2b is a cross-sectional view showing a circuit board according to a second embodiment.

[0047] Figure 3 is a diagram for explaining a problem of a circuit board according to the related art.

[0048] Figure 4 is a cross-sectional view showing an arrangement structure of an electrode portion according to the first embodiment.

[0049] Figure 5 is a cross-sectional view showing an arrangement structure of an electrode portion according to a second embodiment.

[0050] Figure 6 is a cross-sectional view showing an arrangement structure of an electrode portion according to a third embodiment.

[0051] Figure 7 is a cross-sectional view showing an arrangement structure of an electrode portion according to a fourth embodiment.

[0052] Figure 8a is a plan view for explaining an arrangement structure of an electrode portion according to an embodiment.

[0053] Figure 8b is a cross-sectional view for explaining an arrangement structure of an electrode portion according to an embodiment.

[0054] Fig. 9 is a cross-sectional view showing an arrangement structure of an electrode portion according to a fourth embodiment. DETAILED DESCRIPTION

[0055] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein the same reference numerals are used to represent the same or similar elements, and redundant descriptions thereof will be omitted. The suffixes "module" and "part" of the components used in the following description are given or mixed only in consideration of ease of preparing the specification, and there is no meaning or function to distinguish one from another. In addition, in the following description of the embodiments of the present invention, when it is determined that the purport of the embodiments disclosed herein may be difficult to understand, the detailed description of the related art will be omitted. In addition, the accompanying drawings are included to provide a further understanding of the present invention, and the accompanying drawings are incorporated into and constitute a part of this specification, and it should be understood that the present invention is intended to cover all modifications, equivalents or alternatives that fall within the spirit and scope of the present invention.

[0056] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by these terms. These terms are only used to distinguish one component from another.

[0057] When a component is referred to as being "connected" or "in contact with" another component, it may be directly connected or joined to the other component, but it should be understood that other components may exist between them, and when a component is referred to as being "directly connected" or "directly in contact with" another component, it should be understood that other components may not exist between them.

[0058] A singular expression includes a plural expression unless the context clearly implies otherwise.

[0059] In the present application, terms such as "include" or "have" are used to specify the presence of features, numbers, steps, operations, components, parts or a combination thereof described in the specification, however, it should be understood that these terms do not exclude the presence or addition of one or more other features, numbers, steps, operations, components, parts or a combination thereof.

[0060] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0061] -Electronic Devices-

[0062] Before describing the embodiment, an electronic device to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be connected to the semiconductor package of the embodiment. Various semiconductor devices can be mounted on the semiconductor package.

[0063] Semiconductor devices may include active devices and / or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs) in which hundreds to millions of devices are integrated into one semiconductor device. Semiconductor devices may be logic chips, memory chips, and the like. Logic chips may be central processing units (CPUs), graphics processing units (GPUs), and the like. For example, a logic chip may be an application processor (AP) chip including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application specific IC (ASIC), and the like, or a chipset including a specific combination of those listed so far.

[0064] The memory chip may be a stacked memory such as HBM. The memory chip may also include a memory chip such as a volatile memory (eg, DRAM), a nonvolatile memory (eg, ROM), or a flash memory.

[0065] On the other hand, a product group of a semiconductor package to which an embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package) and SIP (System In Package), but is not limited thereto.

[0066] In addition, the electronic device may be a smart phone, a personal digital assistant, a digital camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game, a smart watch, a car, etc. However, the embodiment is not limited thereto, and may be any other electronic device that processes data in addition to these.

[0067] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package of the embodiment may have various package structures including a circuit board to be described later.

[0068] In addition, the circuit board in one embodiment may be the first circuit board described below.

[0069] In addition, the circuit board in another embodiment may be the second circuit board described below.

[0070] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment, Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment, Figure 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment, Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment, Figure 1f is a cross-sectional view showing a semiconductor package according to a sixth embodiment, Figure 1g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0071] refer to Figure 1a , the semiconductor package according to the first embodiment may include a first circuit board 1100 , a second circuit board 1200 , and a semiconductor device 1300 .

[0072] The first circuit board 1100 may represent a package substrate.

[0073] For example, the first circuit board 1100 may provide a space to which at least one external circuit board is coupled. The external circuit board may refer to the second circuit board 1200 coupled to the first circuit board 1100. In addition, the external circuit board may refer to a main board included in the electronic device coupled to the lower portion of the first circuit board 1100.

[0074] In addition, although not shown in the drawings, the first circuit board 1100 may provide a space in which at least one semiconductor device is mounted.

[0075] The first circuit board 1100 may include at least one insulating layer, and an electrode portion disposed on the at least one insulating layer.

[0076] The second circuit board 1200 may be disposed on the first circuit board 1100 .

[0077] The second circuit board 1200 may be an interposer. For example, the second circuit board 1200 may provide a space in which at least one semiconductor device is mounted. The second circuit board 1200 may be connected to at least one semiconductor device 1300. For example, the second circuit board 1200 may provide a space in which a first semiconductor device 1310 and a second semiconductor device 1320 are mounted. The second circuit board 1200 may electrically connect the first semiconductor device 1310 and the second semiconductor device 1320 while electrically connecting the first semiconductor device 1310 and the second semiconductor device 1320 and the first circuit board 1100. That is, the second circuit board 1200 may perform a horizontal connection function between a plurality of semiconductor devices and a vertical connection function between a semiconductor device and a package substrate.

[0078] Figure 1aIt is shown that the first semiconductor device 1310 and the second semiconductor device 1320 are disposed on the second circuit board 1200, but is not limited thereto. For example, one semiconductor device may be disposed on the second circuit board 1200, or alternatively, three or more semiconductor devices may be disposed.

[0079] The second circuit board 1200 may be disposed between the at least one semiconductor device 1300 and the first circuit board 1100 .

[0080] In one embodiment, the second circuit board 1200 may be an active interposer used as a semiconductor device. When the second circuit board 1200 is used as a semiconductor device, the semiconductor package of the embodiment may have a structure vertically stacked on the first circuit board 1100, and may have the functions of multiple logic chips. Having the function of a logic chip may mean that it may have the functions of an active device and a passive device. In the case of an active device, the characteristics of current and voltage may not be linear like a passive device, and in the case of an active interposer, it may have the function of an active device. In addition, the active interposer may perform the function of the corresponding logic chip while performing the signal transmission function between the second logic chip disposed thereon and the first circuit board 1100.

[0081] According to another embodiment, the second circuit board 1200 may be a passive interposer. For example, the second circuit board 1200 may be used as a signal relay between the semiconductor device 1300 and the first circuit board 1100, and may have a passive device function such as a resistor, a capacitor, or an inductor. For example, due to 5G, the Internet of Things (IOT), the improvement of image quality, and the improvement of communication speed, the number of terminals of the semiconductor device 1300 is gradually increasing. That is, the number of terminals provided in the semiconductor device 1300 is increased, thereby reducing the width of the terminal or the interval between the plurality of terminals. In this case, the first circuit board 1100 may be connected to the main board of the electronic device. There is a problem that in order to make the electrodes provided on the first circuit board 1100 have a width and interval respectively connected to the semiconductor device 1300 and the main board, the thickness of the first circuit board 1100 increases or the layer structure of the first circuit board 1100 becomes complicated. Therefore, in the first embodiment, the second circuit board 1200 may be provided on the first circuit board 1100 and the semiconductor device 1300. In addition, the second circuit board 1200 may include electrodes having a fine width and interval corresponding to the terminals of the semiconductor device 1300.

[0082] The semiconductor device 1300 may be an application processor (AP) chip including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application specific IC (ASIC), etc., or a chipset including a specific combination of those listed so far. The memory chip may be a stacked memory such as HBM. The memory chip may also include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc.

[0083] Meanwhile, the semiconductor package of the first embodiment may include a connection portion.

[0084] For example, the semiconductor package may include a first connection portion 1410 disposed between the first circuit board 1100 and the second circuit board 1200. The first connection portion 1410 may electrically connect the second circuit board 1200 to the first circuit board 1100 while coupling them.

[0085] For example, the semiconductor package may include a second connection portion 1420 disposed between the second circuit board 1200 and the semiconductor device 1300. The second connection portion 1420 may electrically connect the semiconductor device 1300 to the second circuit board 1200 while coupling them.

[0086] The semiconductor package may include a third connection portion 1430 disposed on a lower surface of the first circuit board 1100. The third connection portion 1430 may electrically connect the first circuit board 1100 to the main board while coupling them.

[0087] At this time, the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 can be electrically connected between multiple components by using at least one bonding method of wire bonding, solder bonding, and direct metal bonding. That is, since the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 have the function of electrically connecting multiple components, when direct metal bonding is used, the connection portion of the semiconductor package can be understood as an electrical connection portion, rather than solder or wire.

[0088] The wire bonding method may refer to electrically connecting multiple components using a conductive wire such as gold (Au). In addition, the solder bonding method may electrically connect multiple components using a material containing at least one of Sn, Ag, and Cu. In addition, the metal-to-metal direct bonding method may refer to recrystallization by applying heat and pressure between multiple components in the absence of solder, wire, conductive adhesive, etc., and may refer to direct bonding between multiple components. In addition, the metal-to-metal direct bonding method may refer to a bonding method through the second connection portion 1420. In this case, the second connection portion 1420 may represent a metal layer formed between multiple components by recrystallization.

[0089] Specifically, the first connection part 1410, the second connection part 1420, and the third connection part 1430 may couple the plurality of components to each other by a thermal compression (TC) bonding method. Thermocompression bonding may refer to a method of directly coupling the plurality of components by applying heat and pressure to the first connection part 1410, the second connection part 1420, and the third connection part 1430.

[0090] At this time, at least one of the first circuit board 1100 and the second circuit board 1200 may be provided with a protrusion protruding outwardly away from the insulating layer of the corresponding circuit board on which the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 are provided. The protrusion may protrude outwardly from the first circuit board 1100 or the second circuit board 1200.

[0091] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode in the electrode of the second circuit board 1200, on which a second connection portion 1420 for coupling with the semiconductor device 1300 is provided. That is, as the pitch of the terminals of the semiconductor device 1300 becomes finer, a short circuit may occur between a plurality of second connection portions 1420 respectively connected to a plurality of terminals of the semiconductor device 1300 by a conductive adhesive such as solder. Therefore, in an embodiment, thermocompression bonding may be performed to reduce the volume of the second connection portion 1420, and in addition, in order to ensure diffusion prevention and alignment to prevent an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the circuit board, the protrusion may be included in an electrode of the second circuit board 1200 on which the second connection portion 1420 is provided.

[0092] At the same time, reference Figure 1b, the semiconductor package of the second embodiment may be different from the semiconductor package of the first embodiment in that the connecting member 1210 is disposed on the second circuit board 1200. The connecting member 1210 may be referred to as a bridging substrate. For example, the connecting member 1210 may include a redistribution layer. The connecting member 1210 may perform the function of electrically connecting a plurality of semiconductor devices horizontally to each other. For example, since the area of ​​the semiconductor device is generally too large, the connecting member 1210 may include a redistribution layer. Since the semiconductor package and the semiconductor device differ greatly in terms of the width or spacing of the circuit pattern, the circuit pattern is required to play a buffering role in terms of electrical connection. The buffering role may mean having a size between the width or spacing of the circuit pattern of the semiconductor package and the width or spacing of the circuit pattern of the semiconductor device, and the redistribution layer may include the function of performing a buffering role.

[0093] In one implementation, the connection member 1210 may be a silicon bridge. That is, the connection member 1210 may include a silicon substrate and a redistribution layer disposed on the silicon substrate.

[0094] In another embodiment, the connection member 1210 may be an organic bridge. For example, the connection member 1210 may include an organic material. For example, the connection member 1210 may include an organic substrate including an organic material instead of a silicon substrate.

[0095] The connection member 1210 may be embedded in the second circuit board 1200, but is not limited thereto. For example, the connection member 1210 may be provided on the second circuit board 1200 to have a protruding structure.

[0096] In addition, the second circuit board 1200 may include a cavity, and the connection member 1210 may be disposed in the cavity of the second circuit board 1200 .

[0097] The connection member 1210 may horizontally connect a plurality of semiconductor devices disposed on the second circuit board 1200 .

[0098] refer to Figure 1c , the semiconductor package according to the third embodiment may include a second circuit board 1200 and a semiconductor device 1300. In this case, the semiconductor package of the third embodiment may have a structure in which the first circuit board 1100 is removed, compared with the semiconductor package of the second embodiment.

[0099] That is, the second circuit board 1200 of the third embodiment may be used as a package substrate while performing the interposer function.

[0100] The first connection portion 1410 disposed on the lower surface of the second circuit board 1200 may couple the second circuit board 1200 to a main board of the electronic device.

[0101] refer to Figure 1d , the semiconductor package according to the fourth embodiment may include a first circuit board 1100 and a semiconductor device 1300 .

[0102] In this case, the semiconductor package of the fourth embodiment may have a structure in which the second circuit board 1200 is omitted, compared with the semiconductor package of the second embodiment.

[0103] That is, the first circuit board 1100 of the fourth embodiment can be used as a packaging substrate, while also performing the function of connecting the semiconductor device 1300 and the main board. To this end, the first circuit board 1100 may include a connecting member 1110 for connecting a plurality of semiconductor devices. The connecting member 1110 may be a silicon bridge or an organic material bridge connecting a plurality of semiconductor devices.

[0104] refer to Figure 1e Compared with the semiconductor package of the fourth embodiment, the semiconductor package of the fifth embodiment may further include a third semiconductor device 1330 .

[0105] To this end, the fourth connection portion 1440 may be disposed on the lower surface of the first circuit board 1100 .

[0106] In addition, the third semiconductor device 1330 may be disposed on the fourth connection portion 1400. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor devices are mounted on the upper and lower sides, respectively.

[0107] In this case, the third semiconductor device 1330 may have a configuration in which Figure 1c The structure on the lower surface of the second circuit board 1200 in the semiconductor package.

[0108] refer to Figure 1f , the semiconductor package according to the sixth embodiment may include a first circuit board 1100. A first semiconductor device 1310 may be provided on the first circuit board 1100. To this end, a first connection portion 1410 may be provided between the first circuit board 1100 and the first semiconductor device 1310.

[0109] In addition, the first circuit board 1100 may include a conductive coupling portion 1450. The conductive coupling portion 1450 may further protrude from the first circuit board 1100 toward the second semiconductor device 1320. The conductive coupling portion 1450 may be referred to as a bump, or alternatively, may also be referred to as a column. The conductive coupling portion 1450 may be configured to have a protruding structure on an electrode disposed on the uppermost side of the first circuit board 1100.

[0110] The second semiconductor device 1320 may be disposed on the conductive coupling portion 1450. In this case, the second semiconductor device 1320 may be connected to the first circuit board 1100 through the conductive coupling portion 1450. In addition, the second connection portion 1420 may be disposed on the first semiconductor device 1310 and the second semiconductor device 1320.

[0111] Therefore, the second semiconductor device 1320 may be electrically connected to the first semiconductor device 1310 through the second connection portion 1420 .

[0112] That is, the second semiconductor device 1320 may be connected to the first circuit board 1100 through the conductive coupling portion 1450 , and may also be connected to the first semiconductor device 1310 through the second connection portion 1420 .

[0113] In this case, the second semiconductor device 1320 may receive a power signal and / or electric power through the conductive coupling portion 1450. In addition, the second semiconductor device 1320 may transmit and receive communication signals to and from the first semiconductor device 1310 through the second connection portion 1420.

[0114] The semiconductor package according to the sixth embodiment may provide a power signal and / or electric power to the second semiconductor device 1320 through the conductive coupling portion 1450 , thereby providing sufficient power to drive the second semiconductor device 1320 or enabling smooth control of power operation.

[0115] Therefore, the embodiment can improve the driving characteristics of the second semiconductor device 1320. That is, the embodiment can solve the problem of insufficient power provided to the second semiconductor device 1320. In addition, in the embodiment, at least one of the power signal, the electric power, and the communication signal of the second semiconductor device 1320 can be provided through different paths passing through the conductive coupling portion 1450 and the second connection portion 1420. Thus, the embodiment can solve the problem that the communication signal is lost due to the power signal. For example, the embodiment can minimize the mutual interference between the communication signal and the power signal.

[0116] Meanwhile, the second semiconductor device 1320 in the sixth embodiment may have a POP (Package On Package) structure in which a plurality of package substrates are stacked, and may be provided on the first circuit board 1100. For example, the second semiconductor device 1320 may be a memory package including a memory chip. In addition, the memory package may be coupled to the conductive coupling portion 1450. In this case, the memory package may not be connected to the first semiconductor device 1310.

[0117] refer to Figure 1g, the semiconductor package according to the seventh embodiment may include a first circuit board 1100 , a first connection portion 1410 , a second connection portion 1420 , a semiconductor device 1300 , and a third connection portion 1430 .

[0118] In this case, the semiconductor package of the seventh embodiment may be different from the semiconductor package of the fourth embodiment in that the first circuit board 1100 includes a plurality of substrate layers, while the connection member 1110 is omitted.

[0119] The first circuit board 1100 may include a plurality of circuit board layers. For example, the first circuit board 1100 may include a first circuit board layer 1100A corresponding to the package substrate and a second circuit board layer 1100B corresponding to the connection member.

[0120] In other words, the semiconductor package of the seventh embodiment may include a first circuit board layer 1100A and a second circuit board layer 1100B, wherein Figure 1a The first circuit board (package substrate 1100) and the second circuit board (interposer 1200) disclosed in the seventh embodiment are formed integrally. The material of the insulating layer of the second circuit board layer 1100B may be different from the material of the insulating layer of the first substrate layer 1100A. For example, the material of the insulating layer of the second circuit board layer 1100B may include a photocurable material. For example, the second circuit board layer 1100B may be a photoimageable dielectric (PID). In addition, since the second circuit board layer 1100B includes a photocurable material, the electrode can be miniaturized. Therefore, in the seventh embodiment, the second circuit board layer 1100B can be formed by sequentially stacking insulating layers of photocurable material on the first circuit board layer 1100A and forming miniaturized electrodes on the insulating layers of photocurable material. Therefore, the second circuit board layer 1100B may include a redistribution layer function including microelectrodes, and may include a function of horizontally connecting a plurality of semiconductor devices 1310 and 1320.

[0121] Before describing the circuit board of the embodiment, the circuit board described below may represent any one of the circuit boards included in the previous semiconductor package. For example, the circuit board described below may represent any one of the first circuit board 1100 and the second circuit board 1200 included in the semiconductor package of the first to seventh embodiments.

[0122] Figure 2a is a cross-sectional view showing a circuit board according to a first embodiment, Figure 2b is a cross-sectional view showing a circuit board according to a second embodiment, Figure 3 is a diagram for explaining a problem of a circuit board according to the prior art, Figure 4 is a cross-sectional view showing an arrangement structure of an electrode portion according to a first embodiment, Figure 5is a cross-sectional view showing an arrangement structure of an electrode portion according to a second embodiment, Figure 6 is a cross-sectional view showing an arrangement structure of an electrode portion according to a third embodiment, Figure 7 is a cross-sectional view showing an arrangement structure of an electrode portion according to a fourth embodiment, Figure 8a is a plan view for explaining an arrangement structure of an electrode portion according to an embodiment, Figure 8b is a cross-sectional view for explaining an arrangement structure of an electrode portion according to an embodiment, Fig. 9 is a cross-sectional view showing an arrangement structure of an electrode portion according to a fourth embodiment.

[0123] In the following, reference will be made to Figures 2a to 9 A circuit board according to an embodiment is described in detail.

[0124] refer to Figure 2a The circuit board 100 according to the first embodiment may include an insulating layer 110 , a first resist layer 116 , a second resist layer 117 , an electrode portion 120 , and an insulating member 140 . The electrode portion 120 may include a second via electrode 130 .

[0125] In addition, refer to Figure 2b The circuit board 100 according to the second embodiment may include an insulating layer 110 , a first resist layer 116 , a second resist layer 117 , an electrode portion 120 , and an insulating member 140 . The electrode portion 120 may include a second via electrode 130 and a bonding portion 125 .

[0126] Specifically, the difference can be determined by whether the joint portion 125 is included. Figure 2a and Figure 2b . The second via electrode 130 and the bonding portion 125 are components of the electrode portion 120, and may be distinguished by a direction and / or function of protruding from one electrode constituting the electrode portion 120. For example, the second via electrode 130 may be a portion of the electrode located within the insulating layer 110. In addition, the bonding portion 125 may be a portion of the electrode that is not located within the insulating layer 110. For example, the bonding portion 125 may be located outside the insulating layer 110. For example, the second via electrode 130 may be a component located within the insulating layer 110, and the bonding portion 125 may be a component located outside the insulating layer 110. Hereinafter, reference will be made to Figure 2b A circuit board of an embodiment is described.

[0127] The second via electrode 130 and the bonding portion 125 are components of the electrode portion 120 and may be distinguished according to directions in which they protrude from electrodes constituting the electrode portion 120 and / or their functions.

[0128] The insulating layer 110 of the circuit board 100 may have a layer structure of at least one layer. Preferably, the insulating layer 110 of the circuit board 100 may have a structure in which a plurality of layers are laminated. The laminated structure may be distinguished by the electrode portion 120, and may be distinguished by the width difference of the first electrode 121, the second electrode 122, and the first via electrode 123 of the electrode portion 120.

[0129] That is, the width of each of the first electrode 121 and the second electrode 122 of the electrode portion 120 may be greater than the width of the first via electrode 123, and the laminated structure may be distinguished by this. Through the above-mentioned laminated structure, the circuit board 100 of the embodiment can effectively electrically connect at least one semiconductor device and / or the second circuit board to the main board.

[0130] at this time, Figure 2a and 2b The insulating layer 110 of the circuit board 100 is shown as having a five-layer structure, but is not limited thereto. For example, the insulating layer 110 of the circuit board 100 may have four or fewer layers, or may have six or more layers. In addition, when the plurality of insulating layers 110 of the circuit board 100 include the same insulating material, it may be difficult to distinguish the interfaces between the plurality of insulating layers. In this case, the laminated structure may be distinguished by the first electrode 121, the second electrode 122, and the first via electrode 123 of the electrode portion 120.

[0131] Meanwhile, in the case where the insulating layer 110 of the circuit board 100 has a multi-layer structure, the plurality of first insulating layers of the circuit board 100 may include the same insulating material, but is not limited thereto. For example, at least one of the plurality of first insulating layers of the circuit board 100 may include an insulating material different from the insulating material of another first insulating layer.

[0132] The insulating layer 110 of the circuit board 100 may be rigid or flexible. For example, the insulating layer 110 of the circuit board 100 may include glass or plastic. For example, the insulating layer 110 of the circuit board 100 may include chemically strengthened / semi-strengthened glass, such as soda lime glass or aluminosilicate glass. For example, the insulating layer 110 of the circuit board 100 may include strengthened or flexible plastic, such as polyimide (PI), polyethyleneterephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer 110 of the circuit board 100 may include sapphire. For example, the insulating layer 110 of the circuit board 100 may include an optically isotropic film. For example, the insulating layer 110 of the circuit board 100 may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer 110 of the circuit board 100 may be formed of a material including an inorganic filler and an insulating resin. For example, the insulating layer 110 of the circuit board 100 may have a structure in which an inorganic filler of silicon dioxide or aluminum oxide is provided in a thermosetting resin or a thermoplastic resin.

[0133] The insulating layer 110 may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

[0134] In one embodiment, the insulating layer may include a first layer corresponding to a core layer including a reinforcing member. Here, the core layer may be an insulating layer including a reinforcing member and having a thickness of more than 100 μm in its vertical direction. In addition, the insulating layer may include a plurality of second layers respectively disposed on the upper and lower parts of the core layer and not including the reinforcing member. In this case, the circuit board 100 may be a core substrate. The reinforcing member may also be referred to as reinforcing fiber or glass fiber.

[0135] The reinforcing member may refer to a glass fiber material extending in the horizontal direction of the insulating layer, and may have a different meaning from the inorganic fillers spaced apart from each other. That is, the reinforcing member of the first layer may have a different length or width in the horizontal direction from the filler of the second layer. For example, the glass fiber may extend to have a width greater than the width of the first layer. Here, the meaning of having a width greater than the width of the first layer may mean that the glass fiber may be arranged in a shape that is bent in the horizontal direction. In addition, even if the second layer includes a filler, the effect of preventing problems such as bending is not as great as that of the glass fiber of the first layer, so the reinforcing member is described separately from the filler of the second layer.

[0136] In another embodiment, the insulating layer 110 of the circuit board 100 may be a coreless substrate that does not include a core. For example, the insulating layer 110 of the circuit board 100 may include an organic material that does not include a reinforcing member, which has excellent processability, can make the circuit board 100 thinner, and can miniaturize the electrode portion 120 of the circuit board 100. For example, the insulating layer 110 of the circuit board 100 can use ABF (Ajinomoto Build-up Film) (a product issued by Ajinomoto Co., Ltd.) as an example, and the insulating layer 110 of the circuit board 100 can use FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. For example, the insulating layer 110 may include a plurality of layers composed of ABF.

[0137] At this time, if the insulating layer 110 of the circuit board 100 is composed only of ABF that does not include a reinforcing member, the warpage characteristics of the circuit board 100 may be deteriorated. Therefore, if the insulating layer 110 of the circuit board 100 is composed of ABF (Ajinomoto buildup film), at least one of the ABFs constituting the plurality of insulating layers of the circuit board 100 may include a reinforcing member that can improve the warpage characteristics.

[0138] For example, the insulating layer 110 of the circuit board 100 may include a first layer composed of a first ABF including a resin and a filler. In addition, the insulating layer 110 of the circuit board 100 may include a layer composed of a second ABF further including adding a reinforcing member to the first ABF. At this time, the reinforcing member included in the second ABF may include a GCP (Glass Core Primer) material, but is not limited thereto.

[0139] In addition, the insulating layer 110 may be provided with a PID that is conducive to miniaturizing the width and / or spacing of the electrodes. The PID may form electrodes on the insulating layer 110 using an exposure and development process, thereby minimizing the width and / or spacing of the electrodes. When the insulating layer 110 is provided with a PID, a mechanical reliability problem in which the adhesion between the insulating layer 110 and the electrodes is reduced may occur. However, the embodiment improves the adhesion between the insulating layer and the electrodes by using a protrusion provided on the electrodes described below, thereby improving electrical reliability and / or mechanical reliability.

[0140] The layer of the insulating layer 110 of the circuit board 100 that does not include the reinforcement member may have a thickness in the range of 10 μm to 40 μm. Preferably, the layer of the insulating layer 110 of the circuit board 100 that does not include the reinforcement member may satisfy the thickness in the range of 15 μm to 35 μm. More preferably, the layer of the insulating layer 110 of the circuit board 100 that does not include the reinforcement member may satisfy the thickness in the range of 18 μm to 32 μm. If the thickness of the layer of the insulating layer 110 of the circuit board 100 that does not include the reinforcement member is less than 10 μm, the warpage characteristics of the circuit board 100 may be deteriorated. In addition, if the thickness of the layer of the insulating layer 110 of the circuit board 100 that does not include the reinforcement member is less than 10 μm, the electrode portion 120 of the circuit board 100 cannot be stably protected, and thus the electrical reliability may be reduced. In addition, if the thickness of the layer of the insulating layer 110 of the circuit board 100 that does not include the reinforcement member exceeds 40 μm, the total thickness of the circuit board 100 increases, and thus, the thickness of the semiconductor package may increase. In addition, if the thickness of the layer of the insulating layer 110 of the circuit board 100 excluding the reinforcement member exceeds 40 μm, it may be difficult to minimize the electrode portion 120 of the circuit board 100 .

[0141] The thickness may correspond to the vertical distance between the electrode parts arranged on different layers. That is, the thickness may represent the length in the direction from the upper surface to the lower surface or from the lower surface to the upper surface of the circuit board 100, and may represent the length in the vertical direction. Here, the upper surface may represent the highest position in the vertical direction in each component, and the lower surface may represent the lowest position in the vertical direction in each component. In addition, the positions of the upper surface and the lower surface may be referred to oppositely to each other.

[0142] Meanwhile, the semiconductor package of the embodiment may include a first resist layer 116 disposed on the upper surface of the circuit board 100. In addition, the semiconductor package may include a second resist layer 117 disposed on the lower surface of the circuit board 100. The first resist layer 116 and the second resist layer 117 may represent an "insulating layer" other than the insulating layer 110 of the circuit board 100. In this case, the insulating layer 110 may be referred to as a "first insulating layer", the first resist layer 116 may be referred to as a "second insulating layer", and the second resist layer 117 may be referred to as a "third insulating layer". Therefore, the insulating layer of the circuit board 100 may include not only the insulating layer 110 but also the first resist layer 116 and the second resist layer 117.

[0143] At this time, the upper surface of the circuit board 100 may refer to the upper surface of the insulating layer 110, and more specifically, the upper surface of the circuit board 100 may refer to the upper surface of the first insulating layer disposed at the uppermost side among the plurality of first insulating layers. The lower surface of the circuit board 100 may refer to the lower surface of the insulating layer 110, and more specifically, the lower surface of the circuit board 100 may refer to the lower surface of the first insulating layer disposed at the lowest side among the plurality of first insulating layers.

[0144] The first resist layer 116 and the second resist layer 117 may have a function of protecting the upper surface and the lower surface of the circuit board 100. Therefore, the first resist layer 116 and the second resist layer 117 may be functionally referred to as a first protective layer and a second protective layer, respectively.

[0145] The first resist layer 116 and the second resist layer 117 may be solder resist layers including organic polymer materials. For example, the first resist layer 116 and the second resist layer 117 may include epoxy acrylate series resins. In detail, the resist layer 116 and the second resist layer 117 may include resins, curing agents, photoinitiators, pigments, solvents, fillers, additives, acrylic monomers, etc. However, the embodiment is not limited thereto, and the resist layer 116 and the second resist layer 117 may be any one of a photosensitive solder resist layer, a cover layer, and a polymer material.

[0146] For example, when the bonding portion 125 and the semiconductor device are bonded by solder, the solder and the solder resist layer do not have good wettability to each other, and therefore, the solder can prevent the problem of electrical short circuit between two adjacent bonding portions in the plurality of bonding portions 125. At this time, the bonding portion 125 can be configured as an electrode connected to a terminal or an interposer of the semiconductor device through a connecting portion such as solder. In addition, the bonding portion 125 can represent a different configuration from the second via electrode 130 described below.

[0147] The thickness of each of the first resist layer 116 and the second resist layer 117 may be 1 μm to 20 μm. The thickness of each of the first resist layer 116 and the second resist layer 117 may be 1 μm to 15 μm. For example, the thickness of each of the first resist layer 116 and the second resist layer 117 may be 5 μm to 20 μm. In this case, the thickness of the first resist layer 116 may represent the vertical distance from the upper surface of the electrode portion 120 disposed on the uppermost side to the upper surface of the first resist layer 116. In addition, the thickness of the second resist layer 117 may represent the vertical distance from the lower surface of the electrode portion disposed on the lowermost side to the lower surface of the second resist layer 117.

[0148] If the thickness of each of the first resist layer 116 and the second resist layer 117 exceeds 20 μm, it may be difficult to thin the semiconductor package due to an increase in the thickness of the semiconductor package, or stress applied to an insulating layer disposed between the first resist layer 116 and the second resist layer 117 may increase. If the thickness of each of the first resist layer 116 and the second resist layer 117 is less than 1 μm, it may be difficult to stably protect the electrode portion 120 included in the circuit board 100, and thus electrical reliability or physical reliability may be deteriorated.

[0149] The circuit board 100 may include an electrode portion 120. The electrode portion 120 may be disposed on the insulating layer 110 of the circuit board 100. For example, the electrode portion 120 may be disposed in the insulating layer of the circuit board 100. At this time, being disposed in the insulating layer may mean that the electrode portion 120 is disposed in the insulating layer including the insulating layer 110, the first resist layer 116, and the second resist layer 117.

[0150] The electrode part 120 may include a plurality of electrodes according to positions or functions.

[0151] For example, the electrode portion 120 may include a first electrode 121 and a second electrode 122 disposed on the first electrode 121. In addition, the electrode portion 120 may include a first via electrode 123 connecting the first electrode 121 and the second electrode 122 in a vertical direction of the circuit board 100. That is, the first via electrode 123 may be disposed between the first electrode 121 and the second electrode 122, and thus, the first electrode 121 and the second electrode 122 may be electrically connected.

[0152] At this time, when the insulating layer 110 of the circuit board 100 has a five-layer structure, the first via electrode 123 of the electrode part 120 may have a five-layer structure in the vertical direction. In addition, the first electrode 121 or the second electrode 122 may be provided between the first via electrodes 123 of the five layers.

[0153] At this time, at least one of the first electrode 121 and the second electrode 122 of the electrode portion 120 may have an ETS (Embedded Trace Substrate) structure. For example, the first electrode 121 of the electrode portion 120 disposed at the uppermost side of the circuit board 100 may have an ETS structure. For example, the first electrode 121 of the electrode portion 120 disposed at the uppermost side of the circuit board 100 may be disposed in a recess provided at the upper surface of the uppermost insulating layer 110. The ETS structure may also be referred to as an embedded structure. Compared with an electrode portion having a general protruding structure, the ETS structure is conducive to miniaturization. Therefore, the embodiment is able to form an electrode corresponding to the size and spacing of a terminal disposed in a semiconductor device. Thus, the embodiment can improve circuit integration. In addition, the embodiment can minimize the transmission distance of a signal transmitted through a semiconductor device, thereby minimizing signal transmission loss.

[0154] At this time, the first electrode 121 and the second electrode 122 of the electrode portion 120 may be referred to oppositely to each other. For example, according to the position of the first via electrode 123 used as a reference, the first electrode 121 of the electrode portion 120 may be referred to as the second electrode 122. In addition, according to the position of the first via electrode 123 used as a reference, the second electrode 122 of the electrode portion 120 may be referred to as the first electrode 121.

[0155] For example, the first via electrode 123 may include a 3-1 electrode disposed in a first layer of the insulating layer 110 , a 3-2 electrode disposed in a second layer on the first layer, and a 3-3 electrode disposed in a third layer on the second layer.

[0156] At this time, the electrode provided between the 3-1 electrode and the 3-2 electrode may be a “second electrode” based on the 3-1 electrode, and may be a “first electrode” based on the 3-2 electrode.

[0157] In addition, the electrode provided between the 3-2 electrode and the 3-3 electrode may be a “second electrode” based on the 3-2 electrode, and may be a “first electrode” based on the 3-3 electrode.

[0158] The first electrode 121 and the second electrode 122 may perform a function of transmitting a signal in a horizontal direction on the insulating layer 110. In addition, the first via electrode 123 is connected to the first electrode 121 and the second electrode 122, and may perform a function of transmitting a signal in a vertical direction between the first electrode 121 and the second electrode 122. The first via electrode 123 may also be referred to as a through electrode or a via.

[0159] Meanwhile, the electrode portion 120 may include a second via electrode 130. Preferably, the second electrode 122 of the electrode portion 120 may include the second via electrode 130. At this time, although the second via electrode 130 is described as a configuration included in the second electrode 122, the embodiment is not limited thereto. That is, as described above, the second electrode 122 may be the first electrode 121 according to the first via electrode 123 used as a reference. Therefore, the second via electrode 130 may be a configuration provided in the first electrode 121.

[0160] Hereinafter, for convenience of explanation, a configuration in which the second via electrode 130 is the second electrode 122 of the electrode part 120 will be described.

[0161] The second via electrode 130 may extend in a vertical direction from the second electrode 122 of the electrode portion 120. The second via electrode 130 may be disposed between the first electrode 121 and the second electrode 122. The second via electrode 130 may be disposed between the first electrode 121 and the second electrode 122 and spaced apart from the first via electrode 123 in a horizontal direction.

[0162] The first via electrode 123 may extend in a vertical direction from the second electrode 122. At this time, the length of the second via electrode 130 in the vertical direction may be different from the length of the first via electrode 123 in the vertical direction.

[0163] That is, the first via electrode 123 may be used to electrically connect the first electrode 121 and the second electrode 122 .

[0164] Therefore, the first via electrode 123 may be connected to the first electrode 121 and the second electrode 122. The first via electrode 123 may electrically connect the first electrode 121 and the second electrode 122. In contrast, the second via electrode 123 may not electrically connect the first electrode 121 and the second electrode 122. For example, the second via electrode 123 may be connected to one of the first electrode 121 and the second electrode 122, and may not be connected to the other electrode.

[0165] Therefore, the length of the first via electrode 123 in the vertical direction may correspond to the distance between the first electrode 121 and the second electrode 122 in the vertical direction.

[0166] In contrast, the second via electrode 130 may serve to improve adhesion between the second electrode 122 and the insulating layer 110 .

[0167] That is, the second via electrode 130 increases the contact area between the insulating layer 110 and the electrode portion 120, thereby solving the problem of the electrode portion 120 peeling off from the insulating layer 110. In addition, the second via electrode 130 can prevent the circuit board 100 from being greatly bent in a specific direction.

[0168] Specifically, as the number of input terminals and output terminals of semiconductor devices increases, the width and / or spacing of the terminals of semiconductor devices and / or semiconductor small chips become narrower. Therefore, the width and / or spacing of the electrodes set on the circuit board also become smaller. In addition, as the width and / or spacing of the electrodes become smaller, the contact area between the electrode portion 120 and the insulating layer 110 decreases, which may cause the mechanical reliability problem of the electrode portion 120 being easily peeled off from the insulating layer 110. In addition, in order to minimize the width and / or spacing of the electrodes, the insulating layer may include a photosensitive material. The photosensitive material may be, for example, a PID (photosensitive imageable dielectric). The insulating layer with the photosensitive material may be formed into an electrode using a photolithography process, so it may be beneficial to refine the width and / or spacing of the electrode. At this time, the photosensitive material has the characteristic of lower adhesion to the electrode compared to the thermosetting material. Therefore, when the width and / or spacing of the electrode is refined or the insulating layer includes a photosensitive material, the embodiment can solve the mechanical reliability problem of the electrode peeling off from the insulating layer, thereby improving the overall product reliability of the circuit board and the semiconductor package.

[0169] In addition, the rigidity of the insulating layer provided with the photosensitive material may be lower than the rigidity of the thermosetting material provided with the reinforcing member. Therefore, the circuit board provided with the photosensitive material has the problem of being greatly bent in a specific direction. In this case, the embodiment can improve the rigidity of the circuit board by using a protrusion provided in the electrode, thereby preventing the circuit board and the semiconductor package from being greatly bent in a specific direction.

[0170] In addition, the second via electrode 130 can solve the problem that the electrode portion 120 is peeled off from the insulating layer 110 due to the gas generated in the insulating layer 110. For example, in order to briefly explain the manufacturing process of the circuit board 100, the insulating layer 110 may be provided in a semi-cured state. Then, the electrode portion 120 may be disposed on the insulating layer 110 having the semi-cured state. Then, a process of completely curing the insulating layer 110 may be performed after the electrode portion 120 is disposed.

[0171] At this time, when the process of completely curing the insulating layer 110 is performed, gas may be generated from the insulating layer 110. At this time, the generated gas must be discharged from the insulating layer 110 to the outside of the circuit board 100. At this time, the electrode part 120 is provided on the insulating layer 110. Therefore, the gas generated from the insulating layer 110 may not be discharged to the outside of the circuit board 100 through the electrode part 120, and may remain in the insulating layer 110.

[0172] Therefore, the electrode part 120 of the embodiment may include the second via electrode 130. In addition, the second via electrode 130 increases the adhesion between the electrode part 120 and the insulating layer 110, thereby preventing the electrode part 120 from being peeled off from the insulating layer 110 due to the generated gas.

[0173] For example, if the second via electrode 130 is not provided in the electrode portion 120 , a problem may occur in which the electrode portion 120 rises above the insulating layer 110 due to gas generated from the insulating layer 110 .

[0174] For example, refer to Figure 3 , the electrode portion of the circuit board of the comparative example may not be provided with a second via electrode. In addition, due to the various reasons described above, the electrode portion of the comparative example may not be provided with a through hole for gas discharge. Therefore, the circuit board of the comparative example may have a problem that the gas generated from the insulating layer 10 is not discharged to the upper side of the electrode portion 20. Therefore, the circuit board of the comparative example may have a problem that the electrode portion 20 is raised due to the gas. For example, the electrode portion 20 of the comparative example may include a convex area (A) that bulges upward from the insulating layer 10. The electrode portion 120 may not contact the insulating layer 10 in the convex area (A). Therefore, the circuit board of the comparative example may have a physical reliability problem in which the adhesion between the electrode portion 20 and the insulating layer 10 is reduced due to the convex area (A), and therefore the electrode portion 20 may be separated from the insulating layer 10.

[0175] On the contrary, the embodiment may have a second via electrode 130 disposed on the second electrode 122 of the electrode portion 120. In addition, the second via electrode 130 may have a function of improving the adhesion between the electrode portion 120 and the insulating layer 110. For example, the second via electrode 130 may have an anchoring function of firmly fixing the electrode portion 120 to the insulating layer 110. Therefore, the embodiment may improve the adhesion between the plurality of insulating layers and the adhesion between the insulating layer and the electrode portion. Thus, the embodiment may improve the physical reliability of the circuit board.

[0176] Meanwhile, the second via electrode 130 may be disposed in a region of the second electrode 122 that should not be connected to the first electrode 121 .

[0177] However, the second via electrode 130 may be disposed in a region of the second electrode 122 electrically connected to the first electrode 121, and thus may connect the first electrode 121 and the second electrode 122. However, when the second via electrode 130 connects the first electrode 121 and the second electrode 122, the function and structure of the second via electrode may correspond to the function and structure of the first via electrode 123.

[0178] That is, the first via electrode 123 may extend from the second electrode 122 in the vertical direction together with the second via electrode 130. In addition to the function of electrically connecting the first electrode 121 and the second electrode 122, the first via electrode 123 may also have the function of improving the adhesion between the insulating layer 110 and the electrode portion 120. Therefore, the first via electrode 123 may be arranged in the entire region of the insulating layer 110 instead of the second via electrode 130. However, the electrode portion 120 includes an area where the first electrode 121 and the second electrode 122 should not be electrically connected to each other, and the first via electrode 123 may not be arranged in the area. In addition, if only the first via electrode 123 is included without using the second via electrode 130, there is a problem of increased time, cost and material for plating the first via electrode 123. In addition, as the number of the first via electrode 123 increases, the flatness of the second electrode 122 plated together with the first via electrode 123 may deteriorate. For example, the second electrode 122 may be plated together with the first via electrode 123. At this time, when the number of first via electrodes 123 increases, a step may exist between a region of the second electrode 122 vertically overlapping with the first via electrodes 123 and a region not vertically overlapping with the first via electrodes 123. In addition, the step may serve as a factor that reduces physical and electrical reliability of the circuit board.

[0179] Therefore, the embodiment provides at least one second via electrode 130 on the electrode part 120 .

[0180] In addition, the second electrode 122 should not be electrically connected to the first electrode 121 through the second via electrode 130. At this time, when the length of the second via electrode 130 of the second electrode 122 in the vertical direction is the same as the length of the first via electrode 123 in the vertical direction, the second via electrode 130 is electrically connected to the first electrode 121 overlapped in the vertical direction. Therefore, the length of the second via electrode 130 in the vertical direction may be less than the length of the first via electrode 123 in the vertical direction. At this time, the length of the first via electrode 123 in the vertical direction according to the arrangement structure of the first electrode 121 and the second electrode 122 will be described. That is, the positions and structures of the first electrode 121, the second electrode 122, the first via electrode 123 and the second via electrode 130 of the electrode portion 120 may vary based on a specific insulating layer in the insulating layer 110 of the circuit board 100.

[0181] That is, reference Figure 4, the first electrode 121 may be embedded in the insulating layer 110. For example, the first electrode 121 may be provided in a recess (not shown) provided at the lower surface of the insulating layer 110. In addition, the second electrode 122 may be provided on the insulating layer 110. For example, the second electrode 122 may protrude on the upper surface of the insulating layer 110. Meanwhile, the first via electrode 123 may be provided in the insulating layer 110. The first via electrode 123 may be provided between the first electrode 121 and the second electrode 122. The first via electrode 123 may extend from the first electrode 121 to the second electrode 122 in the vertical direction. In addition, the first via electrode 123 may extend from the second electrode 122 to the first electrode 121 in the vertical direction. At this time, the length of the first via electrode 123 in the vertical direction may be less than the length of the insulating layer 110 in the vertical direction. For example, the length of the first via electrode 123 in the vertical direction may correspond to the distance from the upper surface of the first electrode 121 to the lower surface of the second electrode 122 in the vertical direction. In addition, the second via electrode 130 may extend from the second electrode 122 toward the first electrode 121 in the vertical direction. At this time, the length of the second via electrode 130 in the vertical direction may be different from the length of the first via electrode 123 in the vertical direction. Preferably, the length of the second via electrode 130 in the vertical direction may be less than the length of the first via electrode 123 in the vertical direction. For example, the lower surface of the second via electrode 130 may be positioned higher than the lower surface of the first via electrode 123. In addition, the upper surface of the second via electrode 130 may be located on the same plane as the upper surface of the first via electrode 123.

[0182] In addition, refer to Figure 5 , the first electrode 121 may be located below the insulating layer 110. For example, the first electrode 121 may protrude below the lower surface of the insulating layer 110. The second electrode 122 may be embedded in the insulating layer 110. For example, the second electrode 122 may be located in a recess (not shown) provided at the upper surface of the insulating layer 110. Meanwhile, the first via electrode 123 may be located in the insulating layer 110. The first via electrode 123 may be disposed between the first electrode 121 and the second electrode 122. The first via electrode 123 may extend from the first electrode 121 to the second electrode 122 in a vertical direction. In addition, the first via electrode 123 may extend from the second electrode 122 to the first electrode 121 in a vertical direction.

[0183] In addition, refer to Figure 6, the first electrode 121 may be embedded in the insulating layer 110. For example, the first electrode 121 may be disposed in a recess (not shown) provided at the lower surface of the insulating layer 110. The second electrode 122 may be embedded in the insulating layer 110. For example, the second electrode 122 may be disposed in a recess (not shown) provided at the upper surface of the insulating layer 110. Meanwhile, the first via electrode 123 may be disposed in the insulating layer 110. The first via electrode 123 may be disposed between the first electrode 121 and the second electrode 122. The first via electrode 123 may extend from the first electrode 121 to the second electrode 122 in a vertical direction. In addition, the first via electrode 123 may extend from the second electrode 122 to the first electrode 121 in a vertical direction.

[0184] In addition, reference Figure 7 , the first electrode 121 may be disposed below the insulating layer 110. For example, the first electrode 121 may protrude below the lower surface of the insulating layer 110. In addition, the second electrode 122 may be disposed on the insulating layer 110. For example, the second electrode 122 may protrude above the upper surface of the insulating layer 110. Meanwhile, the first via electrode 123 may be disposed in the insulating layer 110. The first via electrode 123 may be disposed between the first electrode 121 and the second electrode 122. The first via electrode 123 may extend from the first electrode 121 to the second electrode 122 in a vertical direction. In addition, the first via electrode 123 may extend from the second electrode 122 to the first electrode 121 in a vertical direction.

[0185] At the same time, reference Figure 8a and 8b , the length T1 of the first via electrode 123 in the vertical direction of the embodiment may correspond to the distance between the first electrode 121 and the second electrode 122 in the vertical direction. Figure 4 In the case of , the length T1 of the first via electrode 123 in the vertical direction may correspond to a value obtained by subtracting the thickness of the first electrode 121 from the thickness of one insulating layer. Figure 5 In the case of , the length T1 of the first via electrode 123 in the vertical direction may correspond to a value obtained by subtracting the thickness of the second electrode 122 from the thickness of one insulating layer. Figure 6 In the case of , the length T1 of the first via electrode 123 in the vertical direction may correspond to a value obtained by subtracting the thickness of the first electrode 121 and the thickness of the second electrode 122 from the thickness of one insulating layer. Figure 7 In this case, the length T1 of the first via electrode 123 in the vertical direction may correspond to the thickness of one insulating layer.

[0186] The length T2 of the second via electrode 130 in the vertical direction may be different from the length T1 of the first via electrode 123 in the vertical direction. Preferably, the length T2 of the second via electrode 130 in the vertical direction may be less than the length T1 of the first via electrode 123 in the vertical direction. For example, the length T2 of the second via electrode 130 in the vertical direction may satisfy the range of 30% to 70% of the length T1 of the first via electrode 123 in the vertical direction. Preferably, the length T2 of the second via electrode 130 in the vertical direction may satisfy the range of 35% to 65% of the length T1 of the first via electrode 123 in the vertical direction. More preferably, the length T2 of the second via electrode 130 in the vertical direction may satisfy the range of 40% to 60% of the length T1 of the first via electrode 123 in the vertical direction.

[0187] If the length T2 of the second via electrode 130 in the vertical direction is less than 30% of the length T1 of the first via electrode 123 in the vertical direction, the effect of increasing the adhesion between the insulating layer 110 and the electrode portion 120 achieved by the second via electrode 130 may be insufficient. As a result, a physical reliability problem of the electrode portion 120 peeling off from the insulating layer 110 may occur. If the length T2 of the second via electrode 130 in the vertical direction exceeds 70% of the length T1 of the first via electrode 123 in the vertical direction, the second via electrode 130 and the first electrode 121 may be electrically connected due to a process error, which may cause a circuit short circuit problem. If the length T2 of the second via electrode 130 in the vertical direction exceeds 70% of the length T1 of the first via electrode 123 in the vertical direction, the time, materials and costs for forming the second via electrode 130 may be wasted. If the length T2 of the second via electrode 130 in the vertical direction exceeds 70% of the length T1 of the first via electrode 123 in the vertical direction, the flatness of the second electrode 122 may deteriorate.

[0188] Meanwhile, the width of the second via electrode 130 may be different from the width of the first via electrode 123. Preferably, the width of the second via electrode 130 may be smaller than the width of the first via electrode 123.

[0189] For example, the second via electrode 130 may have a slope 130S in which the width thereof gradually decreases from a region adjacent to the second electrode 122 toward the first electrode 121 .

[0190] In addition, the first via electrode 123 may have a slope 123S in which the width thereof gradually decreases from a region adjacent to the second electrode 122 toward the first electrode 121 .

[0191] At this time, the slope 130S of the second via electrode 130 may correspond to the slope 123S of the first via electrode 123 .

[0192] For example, the second via electrode 130 may be formed by filling a recess provided in the insulating layer 110. In addition, the first via electrode 123 may be formed by filling a through hole passing through the insulating layer 110. At this time, the recess filled by the second via electrode 130 may be formed in the same process or the same equipment as the through hole filled by the first via electrode 123. For example, when forming the through hole, the recess may be formed together with the through hole. For example, the recess may be formed using an equipment for forming a through hole. Therefore, the slope 123S of the first via electrode 123 may correspond to the slope 130S of the second via electrode 130.

[0193] In addition, the width of the area having the maximum width in the entire area of ​​the second via electrode 130 may be smaller than the width of the area having the maximum width in the entire area of ​​the first via electrode 123. Thus, embodiments may increase adhesion between the electrode portion 120 and the insulating layer 110 through the second via electrode 130 without changing electrical characteristics of the second electrode 122.

[0194] At the same time, reference Fig. 9 Although the insulating layer 110 is composed of a plurality of layers, it may be difficult to distinguish interfaces between the layers.

[0195] Therefore, a plurality of electrode parts may be provided in the insulating layer 110 without distinguishing an interface.

[0196] For example, the first electrode portion 120 a and the second electrode portion 120 b may be disposed in the insulating layer 110 in a vertical direction.

[0197] The second electrode portion 120 b may be disposed on the first electrode portion 120 a within the insulating layer 110 .

[0198] In addition, the first electrode portion 120 a may include a first electrode 121 a , a second electrode 122 a , a first via electrode 123 a , and a second via electrode 130 a , respectively.

[0199] In addition, the second electrode portion 120 b may include a first electrode 121 b , a second electrode 122 b , a first via electrode 123 b , and a second via electrode 130 b , respectively.

[0200] Therefore, the first electrode, the second electrode, the first via electrode, and the second via electrode of the electrode part may all be disposed within the insulating layer.

[0201] Meanwhile, the electrode portion 120 may include a bonding portion 125. The bonding portion 125 may protrude on the circuit board 100 in a direction away from the circuit board 100. The bonding portion 125 may be disposed at the second electrode 122 disposed at the uppermost side in the electrode portion 120. However, the embodiment is not limited thereto. The bonding portion 125 may also be disposed below the first electrode 121 disposed at the lowermost side in the electrode portion 120.

[0202] Therefore, the second electrode 122 of the electrode part 120 disposed at the uppermost side of the circuit board 100 may be provided with the second via electrode 130 extending in the vertical direction toward the inside of the insulating layer 110 and the bonding part 125 extending in the vertical direction toward the outside of the insulating layer 110 .

[0203] The bonding portion 125 may be referred to as a bump. The bonding portion 125 may also be referred to as a post. The bonding portion 125 may be referred to as a pillar. The semiconductor device may be disposed on the electrode portion 120 of the circuit board 100. On the contrary, the interposer coupled to the semiconductor device may be coupled to the electrode portion 120 of the circuit board 100. At this time, as the pitch of the terminal of the semiconductor device or the electrode of the interposer becomes thinner, a short circuit problem of the conductive connection portion disposed on a plurality of terminals or electrodes may occur. Therefore, in order to reduce the volume of the conductive connection portion disposed on each of the plurality of terminals or electrodes, the electrode portion 120 may include a protrusion 125. In addition, when a thermocompression bonding is used to apply heat and pressure to the conductive connection portion disposed between the circuit board 100 and the semiconductor device or the interposer to bond them, the bonding portion 125 may have a function of improving the alignment between the electrode portion 120 and the terminal of the semiconductor device or the electrode of the interposer. In addition, the bonding portion 125 may also have a function of preventing the diffusion of the conductive connection portion.

[0204] The electrode portion 120 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the electrode portion 120 of the circuit board 100 may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. Preferably, the electrode portion 120 of the circuit board 100 may be formed of copper (Cu) having high conductivity and relatively low price.

[0205] Each of the first electrode 121 and the second electrode 122 of the electrode portion 120 may have a thickness in the range of 7 μm to 20 μm. For example, each of the first electrode 121 and the second electrode 122 of the electrode portion 120 may have a thickness in the range of 9 μm to 17 μm. Each of the first electrode 121 and the second electrode 122 of the electrode portion 120 may have a thickness in the range of 10 μm to 13 μm. If the thickness of each of the first electrode 121 and the second electrode 122 of the electrode portion 120 is less than 7 μm, the resistance of the electrode portion 120 may increase, and the allowable current of the transmittable signal may decrease. In addition, if the thickness of each of the first electrode 121 and the second electrode 122 of the electrode portion 120 exceeds 20 μm, it may be difficult to miniaturize the electrode portion 120 and thin the circuit board 100.

[0206] Meanwhile, if the electrode portion 120 includes the bonding portion 125, the width of the bonding portion 125 may have a range of 40 μm to 70 μm. If the width of the bonding portion 125 is less than 40 μm, a problem of collapse may occur during thermal compression bonding due to the small width of the bonding portion 125. In addition, if the width of the bonding portion 125 is greater than 70 μm, there may be a problem that it is difficult to correspond to a fine pitch of an electrode of a terminal or an interposer of a semiconductor device.

[0207] Meanwhile, the first via electrode 123 of the electrode part 120 may be formed by filling the inside of the via hole provided in the insulating layer 110 with a conductive material. The via hole may be formed by any one of mechanical, laser, and chemical processing methods. When the via hole is formed by mechanical processing, methods such as milling, drilling, and routing may be used. In addition, when the via hole is formed by laser processing, UV or CO 2 may be used. 2 Laser method. In addition, when the via hole is formed by chemical processing, chemicals containing aminosilane, ketone, etc. may be used. In addition, the via hole corresponding to the first via electrode 123 may be formed together with the concave portion corresponding to the second via electrode 130, but is not limited thereto.

[0208] Meanwhile, when the through holes and the recesses are formed, the insides of the through holes and the recesses may be filled with a conductive material to form the first via electrode 123 and the second via electrode 130 of the circuit board 100 .

[0209] Meanwhile, when the insulating layer 110 includes a core layer, the insulating member 140 may be disposed in the core layer. The insulating member 140 may be disposed to fill a portion of a through hole that penetrates the core layer. The insulating member 140 may also be referred to as a hole plugging member. The insulating member 140 may include an insulating material disposed in the through hole of the core layer. For example, the insulating member 140 may include a paste of an insulating ink material. For example, the insulating member 140 may include plugging ink. However, embodiments are not limited thereto. For example, the insulating member 140 may include a conductive material. Specifically, the insulating member 140 may include a conductive paste containing a conductive metal powder.

[0210] On the other hand, when the circuit board having the above-mentioned features of the present invention is used for IT equipment or household appliances (such as smart phones, server computers, TVs, etc.), functions such as signal transmission or power supply can be stably performed. For example, when the circuit board having the features of the present invention performs a semiconductor packaging function, the circuit board can be used to safely protect the semiconductor chip from external moisture or pollutants, or alternatively, the leakage current between the terminals provided to the semiconductor chip, the electrical short circuit, and the electrical open circuit of the terminals can be solved. In addition, when the signal transmission function is dominant, the noise problem can be solved. Thus, the circuit board having the above-mentioned features of the present invention can maintain the stable function of IT equipment or household appliances, so that the entire product and the circuit board to which the present invention is applied can achieve functional unification or technical interlocking with each other.

[0211] When the circuit board having the above-mentioned features of the present invention is used in a transportation device such as a vehicle, the problem of signal distortion transmitted to the transportation device can be solved, or alternatively, the safety of the transportation device can be further improved by externally safely protecting the semiconductor chip controlling the transportation device and solving the problem of leakage current or electrical short circuit between terminals provided to the semiconductor chip or electrical open circuit of the terminals. Therefore, the transportation device and the circuit board applying the present invention can achieve functional integrity or technical interlocking with each other.

[0212] The characteristics, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, a person skilled in the art to which the embodiments belong may even combine or modify the characteristics, structures, and effects shown in each embodiment relative to other embodiments. Therefore, it should be understood that the contents related to such combinations and such modifications are included in the scope of the embodiments.

[0213] The above description focuses on the embodiments, but it is merely illustrative and does not limit the embodiments. It will be appreciated by those skilled in the art that various modifications and applications not shown above are possible without departing from the basic features of the embodiments. For example, each component specifically indicated in the embodiments may be modified and implemented. In addition, it should be understood that the differences associated with these changes and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: an insulating layer; and an electrode portion disposed in the insulating layer, wherein the electrode portion includes: a first electrode; a second electrode disposed on the first electrode; and a first via electrode and a second via electrode disposed between the first electrode and the second electrode, wherein the first via electrode is connected to the first electrode and the second electrode, and wherein the length of the second via electrode in the vertical direction is less than the length of the first via electrode in the vertical direction.

2. The circuit board according to claim 1, wherein the second via electrode is connected to the second electrode.

3. The circuit board according to claim 1, wherein the second via electrode is spaced apart from the first via electrode in the horizontal direction.

4. The circuit board according to claim 1, wherein the second via electrode extends from the second electrode toward the first electrode.

5. The circuit board according to claim 1, wherein the upper surface of the second via electrode is in the same plane as the upper surface of the first via electrode, and wherein the lower surface of the second via electrode is positioned higher than the lower surface of the first via electrode.

6. The circuit board according to claim 1, wherein the length of the second via electrode in the vertical direction satisfies the range of 30% to 70% of the length of the first via electrode in the vertical direction.

7. The circuit board according to claim 1, wherein the width of the second via electrode in the horizontal direction is less than the width of the first via electrode in the horizontal direction.

8. The circuit board according to any one of claims 1 to 7, wherein the second via electrode has a slope in the horizontal direction such that the width gradually changes as the second via electrode moves away from the second electrode.

9. The circuit board according to claim 8, wherein the first via electrode has a slope in the horizontal direction such that the width gradually changes from the second electrode toward the first electrode.

10. The circuit board according to claim 9, wherein the slope of the second via electrode is the same as the slope of the first via electrode.

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