Characterization tablet as well as preparation method, application and application method thereof

Abstract

The invention relates to a characterization tablet as well as a preparation method, application and an application method thereof. The characterization sheet comprises a silicon substrate, the first surface of the silicon substrate is sequentially provided with an A area, a B area, a C area and a D area in the extension direction, and the A area is of a planar structure; the B region is of a planar structure, and a first tunneling oxide layer, a first doped polycrystalline silicon layer and a first glass layer are sequentially stacked in the B region; the C region is a heavily doped region; the D region is of a suede structure, and a third tunneling oxide layer, a third doped polycrystalline silicon layer and a third glass layer are sequentially stacked in the D region. The characterization piece has the A area, the B area, the C area and the D area which have different structures at the same time, in the process of detecting the crystalline silicon cell technology, the characterization piece and a production line product are put into a to-be-detected working procedure, and an abnormal working procedure is analyzed and determined according to a test result difference value. Furthermore, the characterization sheet can obviously shorten the positioning time of failure analysis and abnormal procedures, and improve the production efficiency and the high-quality product rate.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, in particular to a characterization wafer and a preparation method, application and application method thereof. Background Art

[0002] Currently, the mainstream crystalline silicon cells mainly include all-aluminum back surface field cells (BSF cells), passivated emitter and rear cells (PERC cells), tunnel oxide passivated contact solar cells (TOPCon cells), interdigitated back contact cells (IBC cells) and heterojunction cells (HJT cells). When preparing these mainstream cells, one or more of the processes such as texturing, cleaning, diffusion, etching, SE laser doping, oxidation, annealing, de-bumping, back coating, front coating, screen printing and sintering are included.

[0003] Due to the lengthening of the process and the increase in the number of processes of the current crystalline silicon cells, it has become increasingly difficult to perform failure analysis on crystalline silicon cells and locate abnormal processes. Moreover, the hourly production capacity of crystalline silicon cells is also increasing. Therefore, how to quickly and accurately lock abnormal processes and give solutions, maintain the stability of the production line, and improve the battery efficiency and the high-quality product rate are problems that need to be solved urgently in the prior art. Summary of the Invention

[0004] Based on this, in view of the above problems, it is necessary to provide a characterization wafer and a preparation method, application and application method thereof. Using the characterization wafer of the present invention to detect a single process of a crystalline silicon cell can directly determine whether there is an abnormality in this process, significantly shorten the time for failure analysis and the location of abnormal processes, and improve production efficiency and the high-quality product rate.

[0005] According to a first aspect of the present invention, there is provided a characterization wafer for detecting a single process of a crystalline silicon cell, including a silicon substrate, and an A area, a B area, a C area and a D area are sequentially provided on a first surface of the silicon substrate in an extending direction;

[0006] Wherein, the A area has a planar structure;

[0007] The B area has a planar structure, and a first tunnel oxide layer, a first doped polysilicon layer and a first glass layer are sequentially stacked on the B area;

[0008] The C area is a heavily doped area;

[0009] The D area has a textured structure, and a third tunnel oxide layer, a third doped polysilicon layer and a third glass layer are sequentially stacked on the D area.

[0010] In one embodiment, the heavily doped area is formed by SE on a textured structure with a second tunnel oxide layer, a second doped polysilicon layer and a second glass layer sequentially stacked thereon.

[0011] In one embodiment, the characterization sheet further satisfies at least one of the following conditions:

[0012] (1) The thickness of the first tunneling oxide layer is 0.5 nm to 2.5 nm;

[0013] (2) The thickness of the second tunneling oxide layer is 0.5 nm to 2.5 nm;

[0014] (3) The thickness of the third tunneling oxide layer is 0.5 nm to 2.5 nm;

[0015] (4) The thickness of the first doped polysilicon layer is 50 nm to 300 nm;

[0016] (5) The thickness of the second doped polysilicon layer is 50 nm to 300 nm;

[0017] (6) The thickness of the third doped polysilicon layer is 50 nm to 300 nm.

[0018] In one embodiment, the characterization sheet further satisfies at least one of the following conditions:

[0019] (1) The first doped polysilicon layer is selected from the N-Poly layer, and the first glass layer is selected from the PSG layer;

[0020] Or, the first doped polysilicon layer is selected from the P-Poly layer, and the first glass layer is selected from the BSG layer;

[0021] (2) The second doped polysilicon layer is selected from the N-Poly layer, and the second glass layer is selected from the PSG layer;

[0022] Or, the second doped polysilicon layer is selected from the P-Poly layer, and the second glass layer is selected from the BSG layer;

[0023] (3) The third doped polysilicon layer is selected from the N-Poly layer, and the third glass layer is selected from the PSG layer;

[0024] Or, the third doped polysilicon layer is selected from the P-Poly layer, and the third glass layer is selected from the BSG layer;

[0025] (4) The doping concentration of the first doped polysilicon layer is 2×10 19 ~4×10 20 atoms / cm 3 ;

[0026] (5) The doping concentration of the second doped polysilicon layer is 2×10 19 ~4×10 20 atoms / cm 3 ;

[0027] (6) The doping concentration of the third doped polysilicon layer is 2×10 19 ~4×10 20 atoms / cm 3 。

[0028] In one embodiment, the sizes of the A area, B area, C area and D area are all greater than 5 cm×5 cm.

[0029] In one embodiment, a fourth tunneling oxide layer, a fourth doped polysilicon layer and a fourth glass layer are sequentially stacked on the second surface opposite to the first surface of the silicon substrate.

[0030] According to the second aspect of the present invention, there is provided a method for preparing a characterization wafer for detecting the process of a crystalline silicon cell, including the following steps:

[0031] Provide a silicon substrate, divide the first surface of the silicon substrate into an A area, a B area, a C area and a D area in the extension direction in sequence, and prepare a protective layer on the first surface of the silicon substrate;

[0032] Remove the protective layers of the C area and D area of the silicon substrate and perform texturing to form a textured surface structure in the C area and D area, and then remove the protective layers of the A area and B area of the silicon substrate;

[0033] Deposit a tunneling oxide layer and a polysilicon layer on the first surface of the silicon substrate in sequence, and dope the polysilicon layer to form a doped polysilicon layer and form a glass layer on the surface of the doped polysilicon layer;

[0034] Perform SE treatment on the C area of the silicon substrate to form a heavily doped area;

[0035] Remove the glass layer, doped polysilicon layer and tunneling oxide layer of the A area of the silicon substrate.

[0036] In one embodiment, a tunneling oxide layer and a polysilicon layer are sequentially deposited on the second surface opposite to the first surface of the silicon substrate, and the polysilicon layer is doped to form a doped polysilicon layer and form a glass layer on the surface of the doped polysilicon layer.

[0037] According to the third aspect of the present invention, there is provided an application of a characterization wafer in detecting a single process of a crystalline silicon cell.

[0038] According to the fourth aspect of the present invention, there is provided an application method of a characterization wafer in detecting a single process of a crystalline silicon cell. The application method includes: putting the characterization wafer and the production line product into the production of the process to be measured, respectively detecting the characterization wafer and the production line product and obtaining the difference in the detection results, and judging whether the process to be measured is abnormal by analyzing the difference in the detection results.

[0039] On the surface of the above-mentioned characterization wafer, there are regions A, B, C, and D with different structures simultaneously. During the process of detecting a single process of a crystalline silicon cell, the characterization wafer and the normal products on the production line are simultaneously subjected to the process to be measured. After the process is completed, tests such as the texture size, reflectivity, sheet resistance, photoluminescence, electroluminescence, open-circuit voltage, leakage current, or line resistance are performed on the characterization wafer and the normal products on the production line. The abnormal process is determined by analyzing the difference in the test results. Furthermore, the characterization wafer of the present invention can significantly shorten the time for failure analysis and the positioning of abnormal processes, improving production efficiency and the yield of high-quality products. Brief Description of the Drawings

[0040] Figure 1 It is a schematic structural diagram of the characterization wafer of the present invention;

[0041] Figure 2 It is a process flow chart for the preparation of the characterization wafer of the present invention.

[0042] In the figure: 1, silicon substrate; 2, heavily doped region; 3, texture structure; 4, protective layer; 5, polysilicon layer; 10, tunneling oxide layer; 20, doped polysilicon layer; 30, glass layer; 101, first tunneling oxide layer; 102, second tunneling oxide layer; 103, third tunneling oxide layer; 104, fourth tunneling oxide layer; 201, first doped polysilicon layer; 202, second doped polysilicon layer; 203, third doped polysilicon layer; 204, fourth doped polysilicon layer; 301, first glass layer; 302, second glass layer; 303, third glass layer; 304, fourth glass layer. Detailed Embodiments

[0043] To facilitate the understanding of the present invention, the present invention will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present invention. The terms used in the description of the present invention in this specification are only for the purpose of describing specific embodiments or examples and are not intended to limit the present invention.

[0045] In the present invention, when it comes to numerical ranges, unless otherwise specified, the above numerical ranges are considered continuous and include the minimum and maximum values of the range, as well as each value between such minimum and maximum values. Further, when the range refers to integers, it includes each integer between the minimum and maximum values of the range. In addition, when multiple ranges are provided to describe features or characteristics, these ranges can be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all sub-ranges subsumed therein.

[0046] According to a first aspect of the present invention, there is provided a characterization wafer for detecting a single process of a crystalline silicon cell, such as Figure 1 as shown, the characterization wafer includes a silicon substrate 1, and an A region, a B region, a C region, and a D region are sequentially provided on a first surface of the silicon substrate 1 in an extending direction;

[0047] wherein, the A region of the silicon substrate 1 is a planar structure;

[0048] the B region is a planar structure, and a first tunneling oxide layer 101, a first doped polysilicon layer 201, and a first glass layer 301 are sequentially stacked on the B region;

[0049] the C region is a heavily doped region 2;

[0050] the D region is a textured structure 3, and a third tunneling oxide layer 103, a third doped polysilicon layer 203, and a third glass layer 303 are sequentially stacked on the D region.

[0051] On the surface of the characterization wafer provided by the present invention, there are simultaneously regions A, B, C, and D with different structures. During the process of detecting a single process of a crystalline silicon cell, the characterization wafer and the normal products on the production line are simultaneously subjected to the process to be measured. After the process is completed, the characterization wafer and the normal products on the production line are tested for parameters such as textured size, reflectivity, sheet resistance, photoluminescence, electroluminescence, open circuit voltage, leakage current, or line resistance. The abnormal process is determined by analyzing the difference in the test results. Furthermore, the characterization wafer of the present invention can significantly shorten the time for failure analysis and the positioning of abnormal processes, and improve production efficiency and the yield of high-quality products.

[0052] The heavily doped region 2 in the present invention can be directly laser-processed on the textured structure through laser selective doping technology to form a heavily doped region 2 of P++ or N++.

[0053] In one embodiment, the heavily doped region 2 can also be formed by sequentially stacking a second tunneling oxide layer, a second doped polysilicon layer, and a second glass layer on the textured structure and then performing SE.

[0054] In one embodiment, the thickness of the first tunneling oxide layer 101 is 0.5 nm to 2.5 nm, the thickness of the first doped polysilicon layer 201 is 50 nm to 300 nm, and the doping concentration of the first doped polysilicon layer 201 is 2×10 19 atoms / cm 3 ~4×10 20 atoms / cm 3 ; when the first doped polysilicon layer 201 is selected from the N-Poly layer, the first glass layer 301 is selected from the PSG layer; when the first doped polysilicon layer 201 is selected from the P-Poly layer, the first glass layer 301 is selected from the BSG layer.

[0055] In one embodiment, the thickness of the second tunneling oxide layer is 0.5 nm to 2.5 nm, the thickness of the second doped polysilicon layer is 50 nm to 300 nm, and the doping concentration of the second doped polysilicon layer is 2×10 19 atoms / cm 3 ~4×10 20 atoms / cm 3 ; when the second doped polysilicon layer is selected from the N-Poly layer, the second glass layer is selected from the PSG layer; when the second doped polysilicon layer is selected from the P-Poly layer, the second glass layer is selected from the BSG layer.

[0056] In one embodiment, the thickness of the third tunneling oxide layer 103 is 0.5 nm to 2.5 nm, the thickness of the third doped polysilicon layer 203 is 50 nm to 300 nm, and the doping concentration of the third doped polysilicon layer 203 is 2×10 19 atoms / cm 3 ~4×10 20 atoms / cm 3 ; when the third doped polysilicon layer 203 is selected from the N-Poly layer, the third glass layer 303 is selected from the PSG layer; when the third doped polysilicon layer 203 is selected from the P-Poly layer, the third glass layer 303 is selected from the BSG layer.

[0057] The thicknesses of the first tunneling oxide layer 101, the second tunneling oxide layer, and the third tunneling oxide layer 103 in the present invention may be the same or different. Preferably, the thicknesses of the first tunneling oxide layer 101, the second tunneling oxide layer, and the third tunneling oxide layer 103 are the same; the thicknesses of the first doped polysilicon layer 201, the second doped polysilicon layer, and the third doped polysilicon layer 203 may be the same or different. Preferably, the thicknesses of the first doped polysilicon layer 201, the second doped polysilicon layer, and the third doped polysilicon layer 203 are the same; the thicknesses of the first glass layer 301, the second glass layer, and the third glass layer 303 may be the same or different. Preferably, the thicknesses of the first glass layer 301, the second glass layer, and the third glass layer 303 are the same.

[0058] The doping concentrations of the first doped polysilicon layer 201, the second doped polysilicon layer, and the third doped polysilicon layer 203 in the present invention may be the same or different. Preferably, the doping concentrations of the first doped polysilicon layer 201, the second doped polysilicon layer, and the third doped polysilicon layer 203 are the same.

[0059] In one embodiment, the silicon substrate 1 is selected from a P-type silicon wafer or an N-type silicon wafer.

[0060] In one embodiment, the sizes of the A area, B area, C area, and D area are all greater than 5 cm × 5 cm, which is more convenient for the measuring device to measure each area of the characterization wafer.

[0061] In one embodiment, a fourth tunneling oxide layer 104, a fourth doped polysilicon layer 204, and a fourth glass layer 304 are further stacked in sequence on the second surface opposite to the first surface of the silicon substrate 1. By passivating both sides of the silicon substrate 1, it is more beneficial for the long-term storage of the characterization wafer.

[0062] The thicknesses of the fourth tunneling oxide layer 104, the first tunneling oxide layer 101, the second tunneling oxide layer, and the third tunneling oxide layer 103 in the present invention may be the same or different. Preferably, the thicknesses of the fourth tunneling oxide layer 104, the first tunneling oxide layer 101, the second tunneling oxide layer, and the third tunneling oxide layer 103 are the same; the thicknesses of the fourth doped polysilicon layer 204, the first doped polysilicon layer 201, the second doped polysilicon layer, and the third doped polysilicon layer 203 may be the same or different. Preferably, the thicknesses of the fourth doped polysilicon layer 204, the first doped polysilicon layer 201, the second doped polysilicon layer, and the third doped polysilicon layer 203 are the same; the thicknesses of the fourth glass layer 304, the first glass layer 301, the second glass layer, and the third glass layer 302 may be the same or different. Preferably, the thicknesses of the fourth glass layer 304, the first glass layer 301, the second glass layer, and the third glass layer 302 are the same.

[0063] The doping concentrations of the fourth doped polysilicon layer 204, the first doped polysilicon layer 201, the second doped polysilicon layer, and the third doped polysilicon layer 203 in the present invention may be the same or different. Preferably, the doping concentrations of the fourth doped polysilicon layer 204, the first doped polysilicon layer 201, the second doped polysilicon layer, and the third doped polysilicon layer 203 are the same.

[0064] In one embodiment, the second surface of the silicon substrate 1 includes an E region and an F region. The E region is a textured surface 3, and the F region is a planar structure. By providing the same structure as the D region in the E region of the second surface opposite to the first surface, the process effect of this structure can be determined by testing the results of i-Voc and PL after passivating this symmetric structure.

[0065] In another embodiment, the second surface of the silicon substrate 1 of the present invention includes an E region, an F region, and a G region. The E region is opposite to the D region of the first surface and has the same structure as the D region. The F region has the same structure as the B region of the first surface. The G region is opposite to the A region of the first surface and has the same structure as the A region, and all are the surfaces of the bare silicon substrate.

[0066] According to the second aspect of the present invention, a method for preparing a characterization wafer is provided. The process flow chart is as Figure 2 shown, and includes the following steps:

[0067] S1. Provide a silicon substrate 1, divide the first surface of the silicon substrate 1 into regions A, B, C, and D in the extension direction in sequence, and prepare a protective layer 4 on the first surface of the silicon substrate 1;

[0068] S2. Remove the protective layer 4 in regions C and D of the silicon substrate 1 and perform texturing to form a textured surface 3 in regions C and D, and then remove the protective layer 4 in regions A and B of the silicon substrate;

[0069] S3. Deposit a tunneling oxide layer 10 and a polysilicon layer 5 on the first surface of the silicon substrate 1 in sequence, and dope the polysilicon layer 5 to form a doped polysilicon layer 20 and form a glass layer 30 on the surface of the doped polysilicon layer 20;

[0070] S4. Perform SE treatment on region C of the silicon substrate 1 to form a heavily doped region 2;

[0071] S5. Remove the glass layer 30, the doped polysilicon layer 20, and the tunneling oxide layer 10 in region A of the silicon substrate.

[0072] In one embodiment, the protective layer 4 in step S1 may form a silicon dioxide layer on the first surface of the silicon substrate 1 by means of oxidation gettering. It not only does not introduce new impurities, but also can remove the original surface impurities of the silicon substrate 1, improving the quality of the characterization wafer.

[0073] In one embodiment, the flow rate of oxygen for oxidation gettering is 3000 sccm to 5000 sccm. Specifically, the oxidation gettering can be carried out in a closed quartz furnace tube.

[0074] In one embodiment, the silicon substrate 1 can be polished on both sides before the oxidation gettering to improve the quality of the characterization wafer.

[0075] In one embodiment, in step S2, the protective layers 4 in the C area and D area of the silicon substrate 1 can be removed by picosecond laser. Among them, the conditions for laser removal are: the power is greater than 37 W, and the output spot size is 50 μm to 300 μm. Since the picosecond laser has a high power, a short action time and will not damage the silicon substrate 1, a picosecond laser is selected to remove the protective layers 4 in the C area and D area.

[0076] In one embodiment, the alkali solution used in the texturing process is selected from sodium hydroxide solution or potassium hydroxide solution.

[0077] It should be noted that an oxide layer protection additive is also contained in the texturing solution during the texturing process, so a textured surface structure 3 is only formed in the C area and D area where the protective layer 4 is removed. Specifically, the oxide layer protection additive is selected from additives of the Shichuang TS55 series or the Topband EP12 series.

[0078] In one embodiment, the textured silicon substrate 1 is sequentially subjected to alkali washing, acid washing and water washing to remove the protective layers 4 in the A area and B area of the substrate silicon 1, so that the silicon surface of the silicon substrate 1 is exposed. Specifically, the solution for alkali washing is a mixed solution of sodium hydroxide and hydrogen peroxide, and the solution for acid washing is a mixed solution of hydrogen fluoride and hydrogen chloride.

[0079] In one embodiment, the tunneling oxide layer 10 and the polysilicon layer 5 in step S3 can be prepared by the LPCVD process.

[0080] In one embodiment, the doped polysilicon layer 20 in step S3 can be doped by high-temperature diffusion. Specifically, the doping method is phosphorus doping or boron doping, and a PSG layer or a BSG layer is spontaneously formed on the surface of the doped polysilicon layer 20.

[0081] After the steps S1 to S3 are completed for the silicon substrate 1 of the present invention, a first tunneling oxide layer 101, a first doped polysilicon layer 201, and a first glass layer 301 are sequentially stacked in the B region of the silicon substrate 1. A second tunneling oxide layer 102, a second doped polysilicon layer 202, and a second glass layer 302 are sequentially stacked on the textured structure 3 in the C region of the silicon substrate 1. A third tunneling oxide layer 103, a third doped polysilicon layer 203, and a third glass layer 303 are sequentially stacked on the textured structure 3 in the D region of the silicon substrate 1.

[0082] In one embodiment, in step S4, the heavily doped region 2 is processed by a nanosecond laser to dope phosphorus atoms or boron atoms into the polysilicon doped layer 20, the tunneling oxide layer 10, and the silicon substrate 1.

[0083] In one embodiment, in step S5, a picosecond laser can be used to remove the glass layer 30, the doped polysilicon layer 20, and the tunneling oxide layer 10 in the A region, exposing the silicon surface of the silicon substrate 1.

[0084] In the present invention, the preparation of the protective layer, the preparation of the tunneling oxide layer, the preparation of the polysilicon layer, and the preparation of the doped polysilicon layer can all be performed on both sides to obtain a silicon substrate with double-sided passivation, which is more conducive to the long-term storage of the characterization wafer. At the same time, the preparation method of the characterization wafer of the present invention is simple and can be mass-produced.

[0085] In one embodiment, the preparation method further includes: sequentially depositing a tunneling oxide layer 10 and a polysilicon layer 5 on the second surface of the silicon substrate 1, doping the polysilicon layer 5 to form a doped polysilicon layer 20, and forming a glass layer 30 on the surface of the doped polysilicon layer 20. The second surface of the silicon substrate 1 is sequentially stacked with a fourth tunneling oxide layer 104, a fourth doped polysilicon layer 204, and a fourth glass layer 304.

[0086] In the present invention, the preparation of the tunneling oxide layer 10, the doped polysilicon layer 20, and the glass layer 30 sequentially stacked on the second surface can be performed simultaneously with the preparation of the tunneling oxide layer 10, the doped polysilicon layer 20, and the glass layer 30 on the first surface, or can be performed on the second surface after the structures required on the first surface are prepared. Preferably, the preparation of the structures required on the second surface is performed simultaneously with the preparation of the structures required on the first surface.

[0087] When the structures required on the second surface are prepared simultaneously with the first surface, the preparation method is as follows:

[0088] In step S1, a protective layer 4 is synchronously prepared on the second surface of the silicon substrate 1;

[0089] In step S2, the protective layer 4 in the E region of the silicon substrate is synchronously removed and textured to form a textured structure 3 in the E region, and then the protective layer 4 in the remaining regions is removed;

[0090] In step S3, a tunneling oxide layer 10 and a polysilicon layer 5 are synchronously deposited on the second surface of the silicon substrate 1, and the polysilicon layer 5 is doped to form a doped polysilicon layer 20 and a glass layer 30 is formed on the surface of the doped polysilicon layer 20.

[0091] When the second surface sequentially includes an E region, an F region, and a G region in the extending direction, in step S5, the glass layer 30, the doped polysilicon layer 20, and the tunneling oxide layer 10 in the G region of the silicon substrate are synchronously removed.

[0092] According to a third aspect of the present invention, there is provided an application of a characterization wafer in detecting a single process of a crystalline silicon cell.

[0093] According to a fourth aspect of the present invention, there is provided an application method of a characterization wafer in detecting a single process of a crystalline silicon cell. The application method includes: putting the characterization wafer and the production line products into the process to be measured for production, respectively detecting the characterization wafer and the production line products and obtaining the difference in the detection results, and judging whether the process to be measured is abnormal by analyzing the difference in the detection results.

[0094] In an embodiment, the difference in the detection results is selected from at least one of the difference in the texture size, the difference in the reflectivity, the difference in the sheet resistance, the difference in the electroluminescence (EL difference), the difference in the photoluminescence (PL difference), the difference in the open circuit voltage, the difference in the leakage current, and the difference in the line resistance.

[0095] The detection method provided by the present invention can accurately and quickly lock the abnormal process and improve the production efficiency.

[0096] Hereinafter, the characterization wafer, its preparation method, application, and application method will be further described through the following specific examples.

[0097] Example 1

[0098] A P-type silicon wafer with a resistivity of 1.0 Ω·cm and a size of M10 is used. In a Kun Sheng trough polishing machine, it is sequentially pre-cleaned with a mixed solution containing hydrogen peroxide and sodium hydroxide, and then alkali-polished in a sodium hydroxide solution at 70 °C with a concentration of 1.5 wt%. After alkali polishing, it is sequentially washed with water and HF, and after a slow lift and drying process, a double-sided polished P-type silicon wafer is obtained.

[0099] The double-sided polished P-type silicon wafer is placed in a sealed quartz diffusion tube, and at a temperature of 850 °C, oxygen with a flow rate of 5000 sccm is continuously introduced for 20 min for oxidation gettering, and a silicon dioxide protective layer is prepared on both sides of the double-sided polished P-type silicon wafer.

[0100] Use the Dier picosecond laser with a power of 40W, set the laser spot as a square spot with a size of 110μm, and perform laser treatment on areas C, D, and E of the P-type silicon wafer. In the areas treated by laser, the silicon dioxide protective layer is sublimated and removed under the high temperature of the laser.

[0101] Place the P-type silicon wafer after local laser treatment into a trough texturing machine, and texture it at 75°C for 400s. The mass fraction of NaOH in the texturing trough is 1.2%, and the protection texturing additive Tuobang EP21 is added, with the mass fraction of the additive in the trough being 0.35%. After texturing, uniform textured surfaces are formed in areas C, D, and E of the P-type silicon wafer.

[0102] After the textured P-type silicon wafer passes through an alkali washing trough containing sodium hydroxide and hydrogen peroxide, a pickling trough containing hydrogen fluoride and hydrogen chloride, and a water washing trough in sequence, and then is dried, the silicon dioxide protective layers in areas A, B, and F of the P-type silicon wafer are removed.

[0103] Use the LPCVD process to sequentially form a tunneling oxide layer and a polysilicon layer on the surface of the P-type silicon wafer. The thickness of the tunneling oxide layer is 1nm, and the thickness of the polysilicon layer is 150nm.

[0104] Place the passivated P-type silicon wafer into a high-temperature diffusion furnace. At 875°C and a pressure of 200mbar, introduce 3000sccm of oxygen, 800sccm of nitrogen, and phosphorus oxychloride gas, and diffuse for 2200s to convert the polysilicon layer into an N-Poly layer with a doping concentration of 8×10 19 atoms / cm 3 and form a PSG layer on the surface of the N-Poly layer.

[0105] Use a nanosecond laser with a laser power of 30W and a single laser spot of 115μm to perform SE heavy doping on area C of the silicon substrate, so as to form a heavily doped area in area C of the silicon substrate.

[0106] In area A, use a picosecond laser with a power of 66W and a spot diameter of 150μm to remove the PSG layer, N-Poly layer, and tunneling oxide layer in area A of the silicon substrate to obtain a characterization wafer.

[0107] Example 2

[0108] The difference between Example 2 and Example 1 is that the P-type silicon wafer is replaced with an N-type silicon wafer, and the diffusion method is boron diffusion to form a BSG layer.

[0109] Examples 3 to 5 illustrate the application of the characterization wafer in the detection of single processes of crystalline silicon cells.

[0110] Example 3

[0111] The 10 characterization wafers prepared in Example 1 and the silicon wafers of the production line were put into a tank-type alkali polishing machine. The alkali polishing tank contained sodium hydroxide and oxide layer protection additives to polish the A area of ​​the silicon substrate. The remaining areas did not participate in the reaction because they contained PSG layer protection.

[0112] The characterization films were divided into two groups. The first group selected 5 characterization films to directly perform iVoc testing. The second group selected 5 characterization films and the silicon wafers polished by the production line to perform double-sided AlO testing at the same time. x and SiN x After passivation, the samples were sintered in a sintering furnace set at 700°C to 780°C, and the iVoc data were tested, as shown in Table 1.

[0113] Table 1

[0114]

[0115] According to the data comparison in Table 1, the iVoc value of area A of the characterization wafer of the second group, after the same polishing, passivation and sintering process as the production line, is not much different from that of the silicon wafer of the production line. The area A of the characterization wafer is slightly higher by 3mV. This is because the characterization wafer substrate was pre-made with high-temperature gettering, and the silicon substrate material has relatively few impurities.

[0116] At the same time, the B, C and D areas of the first and second groups were compared. Whether it was the suede structure passivation, suede doping or polished substrate passivation structure, AlO x +SiN x After passivation, iVoc increases after high-temperature sintering. This shows that the characterization sheet is not contaminated and no contamination is introduced to the surface, so the hydrogen in AlOx+SiNx can still passivate the matrix and bring about an increase in iVoc.

[0117] The second group of characterization slices, region B, is based on the polished substrate, and has a passivation structure of N-Poly and double-sided AlOx+SiNx, with the highest iVoc level, which is also in line with expectations. Because the double-sided polished substrate has fewer composite centers, in the absence of pollution, the iVoc after passivation is better than that of the velvet region D. Through Example 3, it can be clearly determined that there is no pollution problem in the alkali polishing process.

[0118] Example 4

[0119] The 10 characterization wafers prepared in Example 1 and the silicon wafers of the production line were put into a tank-type alkali polishing machine. The alkali polishing tank contained sodium hydroxide and oxide layer protection additives to polish the A area of ​​the silicon substrate. The remaining areas did not participate in the reaction because they contained PSG layer protection.

[0120] The characterization pieces were divided into two parts, 5 of which were used in the LPCVD and diffusion processes, using the mass production process of the production line and double-sided P-Poly passivation. This group was recorded as the "verification group".

[0121] Another 5 wafers are not subjected to other treatments and are recorded as the "characterization wafer comparison group".

[0122] The data of PL and iVoc tests on the "verification group" and the "characterization wafer comparison group" are shown in Table 2;

[0123] Table 2

[0124] Characterization chip comparison group D B A PL luminance 1680 1711 100 iVoc 739 mV 740 335 mV Verification group D B A PL luminance 1550 1632 1330 iVoc 726 mV 736 722 mV

[0125] From the data comparison in Table 2, for the "characterization wafer comparison group" directly tested for iVoc and PL, both the iVoc value and the PL brightness in the D area and B area are significantly better than those in the A area and D area of the "verification group".

[0126] The passivation structures of the A area of the verification group, the B area of the characterization wafer comparison group, and the B area of the experimental group are the same. Only the passivation is carried out at different times, and there are obvious differences in iVoc, indicating that there is a risk of low efficiency in the P-Poly process during this mass production.

[0127] Example 5

[0128] Characterize and compare the damage of the front and back passivation and selective laser implantation processes of the TOPCon cell.

[0129] Take 10 characterization wafers prepared in Example 2 and perform the texturing process together with the N-type silicon wafers of the TOPCon product. The texturing tank contains the texturing additive Tuobang-EP21 that protects the oxide layer. After passing through the texturing machine, due to the lack of oxide layer protection in the A area, a double-sided textured substrate will be obtained after texturing. The structures in the remaining areas will not be affected;

[0130] At the same time, take the semi-finished products in the mass production process of each process on the TOPCon production line and perform the following treatments:

[0131] For N-type silicon wafers, 10 wafers after double-sided texturing are marked as the "texturing group";

[0132] For N-type silicon wafers, after double-sided polishing on the alkaline polishing machine, perform double-sided LPCVD tunneling oxide layer SiO x and poly deposition, double-sided phosphorus diffusion, and are marked as the "N-Poly group";

[0133] For 10 silicon wafers after texturing and boron diffusion processes, perform SE after boron diffusion. SE laser is implanted in a 7 cm × 7 cm square area on the boron diffusion surface, and then perform double-sided HF cleaning to remove BSG, and are marked as the "SE group";

[0134] Unify the characterization wafers and the semi-finished products of each process prepared above to perform double-sided AlO x and double-sided SiN x passivation, where AlO x, SiN x Use mass-produced machines and processes. After passing through the sintering furnace, the sintering conditions are the same as those of the mass-produced TOPCon cell process.

[0135] Test the iVoc of all groups and calculate the average value, as shown in Table 3;

[0136] Table 3

[0137]

[0138] According to the data analysis in Table 3, the iVoc of the TOPCon texturing group has little difference from the A and D areas of the characterization wafer, indicating that after double-sided texturing of the substrate, whether it is for the passivation of the double-sided SiO x +N-Poly TOPCon structure, or for the passivation of AlO x +SiN x , the passivation levels are basically the same, indicating that there is no pollution problem on the surface after TOPCon texturing. It can be considered that there is no abnormality in the TOPCon texturing process.

[0139] The passivation of the N-Poly group is also basically consistent with the iVoc level of the B area of the characterization wafer, indicating that under the same passivation structure, the tunneling oxide layer, poly structure, and phosphorus doping prepared by the LPCVD and phosphorus diffusion processes in the production line do not fluctuate much, and the mass production level is stable.

[0140] For the SE group, the iVoc is only 702 mV, which is significantly lower compared to the C area of the characterization wafer. There may be a problem of excessive laser damage in boron diffusion SE, and the cause needs to be investigated.

[0141] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0142] The above-described embodiments only represent several implementation manners of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent should be subject to the appended claims.

Claims

1. A characterization wafer for detecting a single process of a crystalline silicon cell, characterized in that, it includes a silicon substrate, and on the first surface of the silicon substrate, there are successively arranged an A area, a B area, a C area and a D area in the extension direction; wherein, the A area is a planar structure; the B area is a planar structure, and on the B area, there are successively stacked a first tunneling oxide layer, a first doped polysilicon layer and a first glass layer; the C area is a heavily doped area; the D area is a textured structure, and on the D area, there are successively stacked a third tunneling oxide layer, a third doped polysilicon layer and a third glass layer.

2. The characterization wafer according to claim 1, characterized in that, the heavily doped area is formed by performing SE on a second tunneling oxide layer, a second doped polysilicon layer and a second glass layer that are successively stacked on the textured structure.

3. The characterization wafer according to claim 2, characterized in that, the characterization wafer further satisfies at least one of the following conditions: (1) The thickness of the first tunneling oxide layer is 0.5 nm to 2.5 nm; (2) The thickness of the second tunneling oxide layer is 0.5 nm to 2.5 nm; (3) The thickness of the third tunneling oxide layer is 0.5 nm to 2.5 nm; (4) The thickness of the first doped polysilicon layer is 50 nm to 300 nm; (5) The thickness of the second doped polysilicon layer is 50 nm to 300 nm; (6) The thickness of the third doped polysilicon layer is 50 nm to 300 nm.

4. The characterization wafer according to claim 2, characterized in that, the characterization wafer further satisfies at least one of the following conditions: (1) The first doped polysilicon layer is selected from the N-Poly layer, and the first glass layer is selected from the PSG layer; Or, the first doped polysilicon layer is selected from the P-Poly layer, and the first glass layer is selected from the BSG layer; (2) The second doped polysilicon layer is selected from the N-Poly layer, and the second glass layer is selected from the PSG layer; Or, the second doped polysilicon layer is selected from the P-Poly layer, and the second glass layer is selected from the BSG layer; (3) The third doped polysilicon layer is selected from the N-Poly layer, and the third glass layer is selected from the PSG layer; Or, the third doped polysilicon layer is selected from the P-Poly layer, and the third glass layer is selected from the BSG layer; (4) The doping concentration of the first doped polysilicon layer is 2×10 19 ~4×10 20 atoms / cm 3 ; (5) The doping concentration of the second doped polysilicon layer is 2×10 19 ~4×10 20 atoms / cm 3 ; (6) The doping concentration of the third doped polysilicon layer is 2×10 19 ~4×10 20 atoms / cm 3 .

5. The characterization wafer according to claim 1, characterized in that, the sizes of the A area, the B area, the C area and the D area are all greater than 5 cm × 5 cm.

6. The characterization wafer according to claim 1, characterized in that, on the second surface opposite to the first surface of the silicon substrate, there are also successively stacked a fourth tunneling oxide layer, a fourth doped polysilicon layer and a fourth glass layer.

7. A preparation method of a characterization wafer, characterized in that, it includes the following steps: providing a silicon substrate, dividing the first surface of the silicon substrate into an A area, a B area, a C area and a D area successively in the extension direction, and preparing a protective layer on the first surface of the silicon substrate; removing the protective layers of the C area and the D area of the silicon substrate and performing texturing to form a textured structure in the C area and the D area, and then removing the protective layers of the A area and the B area of the silicon substrate; A tunneling oxide layer and a polysilicon layer are sequentially deposited on the first surface of the silicon substrate, and the polysilicon layer is doped to form a doped polysilicon layer and a glass layer is formed on the surface of the doped polysilicon layer; SE treatment is performed on the C region of the silicon substrate to form a heavily doped region; The glass layer, the doped polysilicon layer, and the tunneling oxide layer in the A region of the silicon substrate are removed.

8. The method for preparing a characterization wafer according to claim 7, wherein, the preparation method further includes: sequentially depositing a tunneling oxide layer and a polysilicon layer on the second surface opposite to the first surface of the silicon substrate, and doping the polysilicon layer to form a doped polysilicon layer and a glass layer is formed on the surface of the doped polysilicon layer.

9. An application of a characterization wafer according to any one of claims 1 to 6 in detecting a single process of a crystalline silicon cell.

10. A method for applying a characterization wafer according to any one of claims 1 to 6 in detecting a single process of a crystalline silicon cell, wherein, the application method includes: putting the characterization wafer according to any one of claims 1 to 6 and the production line products into the production of the process to be measured, respectively detecting the characterization wafer and the production line products and obtaining the difference of the detection results, and judging whether the process to be measured is abnormal by analyzing the difference of the detection results.

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