Rapid current sampling circuit

Abstract

The invention provides a current sampling circuit which comprises a sampling tube, an error amplifier, a sampling hold circuit, a first transistor, a second transistor and a third transistor. The sampling tube and the first transistor are connected in series, when the sampling tube is disconnected, the first transistor and the second transistor establish feedback loops with the error amplifier respectively, when the sampling tube is connected, the loop of the second transistor and the error amplifier is disconnected, and the first transistor and the error amplifier form a feedback loop. The loop of the error amplifier is established when the sampling tube is disconnected, so that when the sampling tube is conducted again, the loop does not need to be established again, and the current sampling speed is greatly improved. Meanwhile, the circuit can realize peak value sampling, valley value sampling, mean value sampling or current sampling in a certain period of time of the inductive current, and the circuit is simple, flexible and easy to realize.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technologies, and more particularly, to a fast current sampling circuit applied to a switching converter. Background Art

[0002] Switching converters are widely used in various industrial and consumer electronic devices. In a switching converter, the on and off states of switching elements can be controlled by different control methods, so as to convert the input voltage received by the switching converter into an appropriate output voltage.

[0003] In some control circuits, it is necessary to sample the current of the circuit for further control of the circuit. Generally, a sampling circuit contains one or more poles, which will result in a relatively slow response speed during the sampling establishment process. There is a need to propose a current sampling circuit with a faster response speed. Summary of the Invention

[0004] The object of the present invention is to provide a fast current sampling circuit to solve the technical problem of slow response speed in the related art.

[0005] To achieve the above object, according to an embodiment of the present disclosure, a current sampling circuit is provided and applied to a switching converter. The switching converter includes a high-side switch transistor, a low-side switch transistor, and an inductor. The common terminal of the high-side switch transistor and the low-side switch transistor serves as a switching node. The current sampling circuit includes: a sampling transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the sampling transistor being coupled to the switching node, and the control terminal of the sampling transistor receiving a sampling control signal; an error amplifier having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the error amplifier being coupled to the first terminal of the sampling transistor, and the error amplifier amplifying the difference between the voltages on its first and second input terminals to output an error signal at its output terminal; a sample-and-hold circuit for holding the value of the error signal and generating a hold voltage; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor receiving a first voltage, the second terminal of the first transistor being coupled to the first input terminal of the error amplifier, and the control terminal of the first transistor being coupled to the output terminal of the error amplifier; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor receiving a first voltage, the control terminal of the second transistor being coupled to the output terminal of the error amplifier through the sample-and-hold circuit, and the second terminal of the second transistor being coupled to the second input terminal of the error amplifier through a first switch transistor; a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor receiving a first voltage, the control terminal of the third transistor being coupled to the control terminal of the second transistor, and the second terminal of the third transistor serving as the output terminal of the sampling circuit to output a current sampling signal; wherein, when the sampling transistor is turned off, the first switch transistor is turned on, the first input terminal of the error amplifier is coupled to a second voltage through a first resistor, and the second input terminal of the error amplifier is coupled to the second voltage through a second resistor; when the sampling transistor is turned on, the first switch transistor is turned off, the first input terminal of the error amplifier is disconnected from the first resistor, and the second input terminal of the error amplifier is disconnected from the second resistor and coupled to a third voltage. Through the above technical solution, rapid sampling of the current can be achieved. At the same time, sampling of a specific value of the inductor current or current values within a continuous period of time can be flexibly realized. The circuit is simple and easy to implement. Other features and advantages of the present invention will be described in detail in the following detailed implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification. Together with the following detailed implementation, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the accompanying drawings:

[0007] Figure 1 Shown is a current sampling circuit according to an embodiment of the present invention;

[0008] Figure 2 Shown is a switching converter with a current sampling circuit according to an embodiment of the present invention. DETAILED IMPLEMENTATION MODE

[0009] Next, specific embodiments of the present invention will be described non - restrictively in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only for the purpose of illustration and explanation of the present disclosure, and are not used to limit the present disclosure. The reference to "one embodiment" or "an embodiment" throughout the specification means that the specific features, structures, or characteristics described in connection with that embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment" or "in an embodiment" that appear throughout the specification do not necessarily all refer to the same embodiment. The terms "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. The verbs "comprise" and "have" are used as open limitations in this text, which neither exclude nor require the existence of unrecited features. Unless otherwise clearly stated, the features recited in the dependent claims can be freely combined with each other. Elements defined by the use of "a" or "an" (i.e., the singular form) throughout the document do not exclude the possibility of multiple such elements. Further, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Unless otherwise specified, the term "connected" is used to specify a direct electrical connection between circuit elements, while the term "coupled" is used to specify an electrical connection between circuit elements that can be direct or can be via one or more other elements. In contrast, when an element is said to be "directly connected to" or "directly coupled to" another element, there is no intermediate element. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0010] Figure 1 Shown is a current sampling circuit according to an embodiment of the present invention. This current sampling circuit can be applied to a switching converter. A switching converter generally includes a power switch and an inductor. By controlling the on - off switching of the power switch, energy storage and release are performed in the inductor, thereby achieving power transmission. Generally, the power switch includes a high - side switch tube and a low - side switch tube. The common node of the high - side switch tube and the low - side switch tube is marked as the switch node SW. One end of the inductor is coupled to this switch node. By sampling the current flowing through the high - side switch tube or the low - side switch tube, the inductor current can be obtained. This current sampling circuit is coupled to one end of the switch node SW and can sample the current flowing through the high - side switch tube or the low - side switch tube in the switching converter.

[0011] As Figure 1 shown, the current sampling circuit includes a sampling tube Msen, an error amplifier EA, a sample - and - hold circuit 10, a first transistor M1, a second transistor M2, a third transistor M3, and a first switch tube S1.

[0012] As Figure 1As shown, the sampling tube Msen has a first end, a second end, and a control end. The second end of the sampling tube Msen is coupled to the switch node SW, and the control end of the sampling tube Msen receives a sampling control signal EN-sen.

[0013] The error amplifier EA has a first input end, a second input end, and an output end. The first input end of the error amplifier EA is coupled to the first end of the sampling tube Msen, and the error amplifier EA amplifies the difference between the voltages on its first end and second end to output an error signal Vea at its output end.

[0014] The sample and hold circuit 10 holds the value of the error signal Vea and generates a hold voltage Vh. The hold voltage Vh is used to characterize the current value flowing through the sampling tube Msen. In one embodiment, the hold voltage is a specific value used to represent the peak value, valley value, or any specific current value of the current flowing through the sampling tube Msen. In another embodiment, the hold voltage Vh is a continuously varying value representing the current flowing through the sampling tube Msen over a period of time. The sample and hold circuit 10 can flexibly set the value of the hold voltage Vh according to the specific topology of the switching converter or the current to be sampled.

[0015] The first transistor M1 has a first end, a second end, and a control end. The first end of the first transistor M1 receives a first voltage V1, the second end of the first transistor M1 is coupled to the first input end of the error amplifier EA, and the control end of the first transistor M1 is coupled to the output end of the error amplifier EA.

[0016] The second transistor M2 has a first end, a second end, and a control end. The first end of the second transistor M2 receives a first voltage, the control end of the second transistor M2 is coupled to the output end of the error amplifier EA through the sample and hold circuit 10, and the second end of the second transistor M2 is coupled to the second input end of the error amplifier EA through a first switch tube.

[0017] The third transistor M3 has a first end, a second end, and a control end. The first end of the third transistor M3 receives a first voltage V1, the control end of the third transistor M3 is coupled to the control end of the second transistor M2, and the second end of the third transistor M3 outputs a current sampling signal ICS as the output of the sampling circuit 10.

[0018] When the sampling tube Msen is disconnected, the first switching tube S1 is turned on. The first input terminal of the error amplifier EA is coupled to the second voltage V2 through the first resistor, and the second input terminal of the error amplifier EA is coupled to the second voltage V2 through the second resistor. At the same time, the hold voltage Vh is maintained at the value at the moment when its sampling tube Msen switches from on to off. At this time, the first transistor M1 forms a loop through the first input terminal of the error amplifier EA and the error amplifier EA. The second transistor M2 forms a loop with the error amplifier EA through the first switching tube S1 and the second input terminal of the error amplifier EA, and two equal voltage values are established at the first input terminal and the second input terminal of the error amplifier EA respectively. At this time, the value of the error signal Vea will be adjusted to be equal to the value of the hold voltage Vh. The hold voltage Vh, as the voltage on the control terminal of the third transistor M3, will control the third transistor M3 to generate a current sampling signal Ics with a corresponding value at its second terminal. The current sampling signal Ics will change with the change of the hold voltage Vh.

[0019] When the sampling tube Msen is turned on, the first switching tube S1 is disconnected, and the second terminal of the second transistor M2 floats (disconnected from the second input terminal of the error amplifier EA). At the same time, the second input terminal of the error amplifier EA is coupled to the third voltage V3. At this time, the first transistor M1, the sampling tube Msen, and the error amplifier EA form a loop. The current Isen flowing through the first transistor M1 and the sampling tube Msen is proportional to the current flowing through the inductor, and the proportionality coefficient is the ratio of the on-resistance of the sampling tube Msen to the on-resistance of the corresponding power switch (high-side switch or low-side switch). At the same time, the sample and hold circuit 10 will generate the hold voltage Vh according to the error signal Vea. In one embodiment, if the sample and hold circuit 10 generates the hold voltage Vh at a certain specific current (such as peak value, valley value or average value, etc.) moment of the sampling tube Msen, then the hold voltage Vh represents the current flowing through the sampling tube Msen at that specific moment. Therefore, the current sampling signal Ics generated by the hold voltage Vh controlling the third transistor M3 at its second terminal can represent the current flowing through the sampling tube Msen at that specific moment. In another embodiment, the hold voltage Vh generated by the sample and hold circuit 10 is a continuously changing value, which can change according to the change of the current flowing through the sampling tube Msen. Therefore, the current sampling signal Ics generated by the hold voltage Vh controlling the third transistor M3 at its second terminal also changes, and can represent the current flowing through the sampling tube Msen during a period of time (for example, during the on period of the sampling tube Msen).

[0020] Since the feedback loop of the error amplifier EA has been established when the sampling tube Msen is disconnected, and the value of the error signal Vea has been adjusted to be equal to the value of the holding voltage Vh, when the sampling tube Msen is turned on again, there is no need to re - establish the feedback loop of the error amplifier EA, and the current sampling speed will be greatly improved. At the same time, by flexibly setting the sampling and holding time of the error signal Vea in the sample - and - hold circuit 10, peak sampling, valley sampling, average sampling of the inductor current, or current sampling for a period of time can be achieved.

[0021] It should be noted that the forms of the first resistor and the second resistor are not fixed. In Figure 1 the illustrated embodiment, since it is shown that the first input terminal and the second input terminal of the error amplifier EA are clamped to a voltage value through the second switching tube S2 and the third switching tube S3, in some embodiments, if the on - state voltage drop values of the second switching tube S2 and the third switching tube S3 meet the requirements for loop establishment, their respective on - state resistances can be used as the first resistor and the second resistor respectively. In other embodiments, for example, in Figure 2 the illustrated embodiment, two resistors R1 and R2 can also be separately introduced as the first resistor and the second resistor respectively. In one embodiment, the second switching tube S2 and the third switching tube S3 are complementary to the sampling tube Msen in conduction, that is: when the sampling tube Msen is on, the second switching tube S2 and the third switching tube S3 are off; when the sampling tube Msen is off, the second switching tube S2 and the third switching tube S3 are on. In one embodiment, the values of the resistors R1 and R2 are equal.

[0022] In one embodiment, the access of the third voltage V3 can be controlled by introducing a fourth switching tube S4 into the above - mentioned current sampling circuit. Specifically, the fourth switching tube S4 is coupled between the second input terminal of the error amplifier EA and the third voltage V3, and the fourth switching tube S4 is turned on synchronously with the sampling tube Msen. In one embodiment, the first switching tube S1, the second switching tube S2, and the third switching tube S3 are controlled by the inverted signal EN - sen - b of the sampling control signal, and the fourth switching tube S4 is controlled by the sampling control signal EN - sen.

[0023] In one embodiment, the first switching tube S1, the second switching tube S2, the third switching tube S3, and the fourth switching tube S4 are all transistors. In one embodiment, the first transistor M1, the second transistor M2, the third transistor M3, the first switching tube S1, the second switching tube S2, the third switching tube S3, and the fourth switching tube S4 include any suitable controllable semiconductor devices, such as metal - semiconductor field - effect transistors (MOSFETs). In one embodiment, its first terminal is the source of the MOSFET, the second terminal is the drain of the MOSFET, and the control terminal is the gate of the MOSFET.

[0024] In one embodiment, the current sampling circuit further includes a capacitor C0. The capacitor C0 is used to compensate the loop, so that the voltage on the control terminal of the first transistor M1 changes slowly, and the loop is more stable.

[0025] Further, in one embodiment, the specific topology of the first voltage V1, the second voltage V2, the third voltage V3 and the switched converter selected or the current to be determined sampled is related to the type of transistor selected. Next, the circuit schematic diagram of a specific embodiment will be shown in Figure 2 the following.

[0026] As Figure 2 shown, the switching circuit 20 in the switched converter is shown as a buck topology structure formed by connecting a high-side switch HS, a low-side switch LS, an inductor L and a filter capacitor. The high-side switch HS and the low-side switch LS are serially coupled between the input terminal of the switching circuit 20 and the reference ground. The common node of the high-side switch HS and the low-side switch LS is marked as the switching node SW. The inductor L is coupled between the switching node SW and the output terminal of the switching circuit 20. The filter capacitor is coupled between the output terminal and the reference ground. The control signal HS-on of the high-side switch is used to control the on and off times of the high-side switch HS, and the control signal LS-on of the low-side switch is used to control the on and off times of the low-side switch LS. Generally, in the non-discontinuous mode, the control signal HS-on of the high-side switch and the control signal LS-on of the low-side switch are logically complementary signals. By controlling the on and off switching of the high-side switch HS and the low-side switch LS, the input voltage signal VIN is converted into the output voltage signal VOUT. Those of ordinary skill in the art can understand that the embodiments disclosed in the present invention are not limited to being applied in the switched converter with a buck topology, and can also be applied in the switched converters with other topologies, such as a boost switched converter, etc.

[0027] In Figure 2 the embodiment shown, the sampling circuit is shown as sampling the current flowing through the low-side switch LS in the sampling switching circuit 20. Therefore, the sampling control signal EN-sen can be the control signal LS-on of the low-side switch. In actual design, there is a certain time difference between the sampling control signal EN-sen and the control signal LS-on of the low-side switch, ensuring that the sampling switch Msen conducts after the low-side switch LS conducts. In addition, since the current flowing through the low-side switch LS is sampled, the first voltage V1 can be the supply voltage VCC inside the sampling circuit, and the second voltage V2 and the third voltage V3 are both at the reference ground potential. Usually, the supply voltage VCC is generated by the input voltage VIN.

[0028] In Figure 2In the illustrated embodiment, the first transistor M1, the second transistor M2, and the third transistor M3 are shown as P-type MOSFETs, and the high-side switch HS, the low-side switch LS, and the sampling transistor Msen are shown as N-type MOSFETs. The first voltage V1, the second voltage V2, the third voltage V3, and the types of all transistors can be flexibly set according to different application scenarios. For example, when the sampling circuit needs to sample the current flowing through the high-side switch HS in the switching circuit 20, the first transistor M1, the second transistor M2, and the third transistor M3 can be selected as N-type MOSFETs, the first voltage V1 is set to the reference ground, and the second voltage V2 and the third voltage V3 are set to the input voltage VIN of the switching converter. Similarly, in a BOOST switching converter, if it is necessary to collect the current of the high-side switch in the BOOST switching converter, the first voltage V1 can be set to the reference ground, and the second voltage V2 and the third voltage V3 can be set to the output voltage VOUT of the switching converter.

[0029] Continuing to refer to Figure 2 , in Figure 2 the illustrated embodiment, the circuit structure of a sample-and-hold circuit 10 is specifically illustrated. The sample-and-hold circuit 10 is shown as including a pulse signal generator, a transmission gate 101, and a first capacitor C1.

[0030] The pulse signal generator receives a sampling control signal EN-sen and generates a pulse signal on-pls at a specific moment according to the sampling control signal EN-sen. The pulse signal generator can generate the pulse signal on-pls at the rising edge of the sampling control signal EN-sen, or at the falling edge of the sampling control signal EN-sen, or at other selected appropriate moments. In one embodiment, the pulse signal on-pls is a narrow pulse signal with a certain fixed pulse width, generally dozens of ns. The transmission gate 101 has a first end, a second end, a first control end, and a second control end. The first end of the transmission gate 101 is coupled to the output end of the error amplifier EA, the second end of the transmission gate is coupled to the control end of the second transistor M2, the first control end of the transmission gate 101 receives the pulse signal on-pls, and the second control end of the transmission gate 101 receives the inverted signal on-pls-b of the pulse signal on-pls. The first capacitor C1 is coupled between the first end and the control end of the first transistor M1.

[0031] In one embodiment, when the low-side switch LS is conducting, the pulse signal on-pls turns on the transmission gate 101 during its effective pulse width, samples and holds the value of the error signal Vea at this time on the first capacitor C1, and then the transmission gate 101 is turned off. At this time, the value on the capacitor C1 can represent the peak value of the current flowing through the low-side switch LS.

[0032] In another embodiment, when the low-side switch LS is turned off, the pulse signal on-pls turns on the transmission gate 101 during its effective pulse width, samples and holds the value of the error signal Vea at this time onto the first capacitor C1, and then the transmission gate 101 is turned off. At this time, the value on the capacitor C1 can represent the valley value of the current flowing through the low-side switch LS.

[0033] In yet another embodiment, the sample-and-hold circuit 10 may omit the pulse signal generator and only include the transmission gate 101 and the first capacitor C1. The first capacitor C1 is still coupled between the first end and the control end of the first transistor M1. The first end of the transmission gate 101 is coupled to the output end of the error amplifier EA, the second end of the transmission gate 101 is coupled to the control end of the second transistor M2, the first control end of the transmission gate 101 no longer receives the pulse signal on-pls, but directly receives the sampling control signal EN-sen, and the second control end of the transmission gate 101 receives the inverted signal EN-sen-b of the sampling control signal EN-sen. At this time, during the conduction of the sampling transistor Msen, the transmission gate 101 remains on, samples and holds the value of the error signal Vea onto the first capacitor C1. Since the error signal Vea changes with the current flowing through the sampling transistor Msen, the held voltage Vh is also a continuously changing value, and the current sampling signal Ics generated at the second end of the third transistor M3 represents the current flowing through during the conduction of the sampling transistor Msen.

[0034] The preferred embodiments of the present disclosure have been described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure. Additionally, it should be noted that in the above specific embodiments, the various specific technical features described can be combined in any suitable manner without conflict. To avoid unnecessary repetition, the present disclosure does not separately describe various possible combination methods. Furthermore, any combination can be made between different embodiments of the present disclosure as long as it does not violate the idea of the present disclosure, and it should equally be regarded as the content disclosed by the present disclosure.

Claims

1. A current sampling circuit, applied to a switching converter, wherein the switching converter comprises a high-side switch tube, a low-side switch tube and an inductor, wherein a common end of the high-side switch tube and the low-side switch tube serves as a switch node, and wherein: The current sampling circuit comprises: The sampling tube has a first end, a second end and a control end, the second end of the sampling tube is coupled to the switch node, and the control end of the sampling tube receives a sampling control signal; An error amplifier having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the error amplifier is coupled to the first terminal of the sampling tube, and the error amplifier amplifies the difference between the voltages on the first terminal and the second terminal thereof to output an error signal at its output terminal; The sample-and-hold circuit holds the value of the error signal and generates a holding voltage; A first transistor having a first terminal, a second terminal and a control terminal, the first terminal of the first transistor receiving a first voltage, the second terminal of the first transistor coupled to a first input terminal of an error amplifier, and the control terminal of the first transistor coupled to an output terminal of the error amplifier; A second transistor has a first end, a second end and a control end, the first end of the second transistor receives a first voltage, the control end of the second transistor is coupled to the output end of the error amplifier through a sampling and holding circuit, and the second end of the second transistor is coupled to the second input end of the error amplifier through a first switch tube; The third transistor has a first end, a second end and a control end. The first end of the third transistor receives the first voltage. The control end of the third transistor is coupled to the control end of the second transistor. The second end of the third transistor serves as the output end of the sampling circuit to output a current sampling signal. When the sampling tube is disconnected, the first switch tube is turned on, and the first input terminal of the error amplifier is also coupled to the second voltage through the first resistor, and the second input terminal of the error amplifier is also coupled to the second voltage through the second resistor; When the sampling tube is turned on, the first switch tube is turned off, the first input terminal of the error amplifier is disconnected from the first resistor, and the second input terminal of the error amplifier is disconnected from the second resistor and coupled to the third voltage.

2. The current sampling circuit according to claim 1, characterized in that: Further including: A second switch tube is coupled between the first input terminal of the error amplifier and the second voltage, wherein the first resistor comprises an on-resistance of the second switch tube after being turned on; A third switch tube is coupled between the second input terminal of the error amplifier and the second voltage, wherein the second resistor includes an on-resistance of the third switch tube after being turned on; a fourth switch tube, coupled between the second input terminal of the error amplifier and the third voltage; The second switch tube and the third switch tube are complementarily turned on with the sampling tube, and the fourth switch tube is turned on synchronously with the sampling tube.

3. The current sampling circuit according to claim 1, characterized in that: Further including: A second switch tube, wherein the second switch tube and the first resistor are connected in series between the first input terminal of the error amplifier and the second voltage; A third switch tube, wherein the third switch tube and the second resistor are connected in series between the second input terminal of the error amplifier and the second voltage; a fourth switch tube, coupled between the second input terminal of the error amplifier and the third voltage; The second switch tube and the third switch tube are complementarily turned on with the sampling tube, and the fourth switch tube is turned on synchronously with the sampling tube.

4. The current sampling circuit according to claim 1, characterized in that: When the sampled inductor current is the current flowing through the low-side switch tube, the first voltage includes the supply voltage, the second voltage and the third voltage include the reference ground, and the sampling control signal includes the control signal of the low-side switch tube.

5. The current sampling circuit according to claim 1, characterized in that: When the sampled inductor current is the current flowing through the high-side switch tube, the first voltage includes the reference ground, the second voltage and the third voltage include the input voltage of the switching converter, and the sampled control signal includes the control signal of the high-side switch tube.

6. The current sampling circuit according to claim 1, characterized in that: The first resistor and the second resistor have the same resistance value.

7. The current sampling circuit according to claim 1, characterized in that: The held voltage represents a peak value, a valley value or any specific current value of the current flowing through the sampling tube.

8. The current sampling circuit according to claim 1, characterized in that: The holding voltage is a continuously changing value, representing the current flowing through the sampling tube over a period of time.

9. The current sampling circuit according to claim 1, characterized in that: The sample and hold circuit includes: A transmission gate having a first end, a second end, a first control end, and a second control end, wherein the first end of the transmission gate is coupled to the output end of the error amplifier, the second end of the transmission gate is coupled to the control end of the second transistor, the first control end of the transmission gate receives a sampling control signal, and the second control end of the transmission gate 101 receives an inverted signal of the sampling control signal; The first capacitor is coupled between the first terminal and the control terminal of the first transistor.

10. The current sampling circuit according to claim 1, characterized in that: The sample and hold circuit includes: A pulse signal generator receives a sampling control signal and generates a pulse signal at a specific time according to the sampling control signal; A transmission gate having a first end, a second end, a first control end, and a second control end, wherein the first end of the transmission gate is coupled to the output end of the error amplifier, the second end of the transmission gate is coupled to the control end of the second transistor, the first control end of the transmission gate receives a pulse signal, and the second control end of the transmission gate 101 receives an inverted signal of the pulse signal; The first capacitor is coupled between the first terminal and the control terminal of the first transistor.

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